Semiconductor structure, forming method thereof and packaging structure
By forming a seed layer and a sacrificial layer on the substrate structure, the problems of pitting and poor contact in metal interconnect structures are solved, thereby improving the performance of semiconductor structures and packaging yield.
Patent Information
- Application Number
- CN202410627862.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-11-21
AI Technical Summary
In the existing technology, the yield and performance of metal interconnect structures need to be improved, especially in the later stages of the process, where the reduction in the linewidth of the metal interconnect structure leads to pitting and poor contact of the interconnect layer.
By forming a seed layer and a sacrificial layer on the substrate structure, the sacrificial layer is removed after forming the via structure, and then an interconnect layer is formed on top of the via structure. The seed layer is used as the growth base, avoiding additional planarization processes and improving the surface flatness of the via structure.
It reduces the probability of surface etch pits in via structures, improves the surface flatness of interconnect layers and the performance of semiconductor structures, reduces surface etch pits and bubble defects on bonding pads, and improves the yield of packaging structures.
Smart Images
Figure CN120998875A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure, a method for forming the semiconductor structure, and a packaging structure. Background Technology
[0002] In recent years, with the development of integrated circuit technology, the integration level of integrated circuits and semiconductor technology have made great progress. In semiconductor manufacturing processes, as the size of integrated circuits continues to shrink, the linewidth of the metal interconnect structure in the back-end of line (BEOL) process is also continuously decreasing.
[0003] The formation of metal interconnect structures in the back-end process typically includes the formation of via structures and metal interconnect layers, but the yield and performance of metal interconnect structures currently need to be improved. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure, a method for forming the same, and a packaging structure, which is beneficial to further improve the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate structure; forming a seed layer on top of the substrate structure; forming a sacrificial layer on top of the substrate structure, wherein a first opening is formed in the sacrificial layer exposing the top of the seed layer; forming a via structure on the seed layer in the first opening; removing the sacrificial layer after forming the via structure; forming a first dielectric layer covering the substrate structure and the via structure after removing the sacrificial layer; and forming an interconnect layer in the first dielectric layer above the top of the via structure, wherein at least a portion of the interconnect layer is connected to the top of the corresponding via structure.
[0006] Accordingly, embodiments of the present invention provide a semiconductor structure, including: a substrate structure; via structures disposed discretely on the top of the substrate structure; a seed layer located only between the bottom of each via structure and the substrate structure; a first dielectric layer located on the top of the substrate structure, the first dielectric layer covering the sidewalls of the via structures and the sidewalls of the seed layer, and the top of the first dielectric layer being higher than the top of the via structures; and an interconnect layer located in the first dielectric layer above the top of the via structures, at least a portion of the interconnect layer being connected to the top of the corresponding via structure.
[0007] Accordingly, embodiments of the present invention provide a packaging structure, including: a first wafer and a second wafer stacked and bonded together, wherein one or both of the first wafer and the second wafer adopt a semiconductor structure according to any embodiment of the present invention, and the interconnect layer is a bonding pad; wherein the bonding pads of the first wafer and the bonding pads of the second wafer are disposed opposite to each other and in contact with each other.
[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0009] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate structure; forming a seed layer on top of the substrate structure; forming a sacrificial layer on top of the substrate structure, wherein a first opening is formed in the sacrificial layer exposing the top of the seed layer; forming a via structure on the seed layer in the first opening; removing the sacrificial layer after forming the via structure; forming a first dielectric layer covering the substrate structure and the via structure after removing the sacrificial layer; and forming an interconnect layer in the first dielectric layer above the top of the via structure, wherein at least a portion of the interconnect layer is connected to the top of the corresponding via structure. In this invention, by first forming a seed layer and a sacrificial layer with a first opening, and then forming the via structure in the first opening, compared with the conventional single damask process for forming via structures, the via structure, under the constraint of the sacrificial layer, can use the seed layer as a growth base to form the via structure from bottom to top, without the need for additional planarization processes. This reduces the probability of erosion on the surface of the via structure, which is beneficial for providing a flat surface for the formation of the interconnect layer, thereby improving the surface flatness of the interconnect layer and enhancing the performance of the semiconductor structure.
[0010] This invention provides a semiconductor structure, including: a substrate structure; via structures discretely disposed on the top of the substrate structure; a seed layer located only between the bottom of each via structure and the substrate structure; a first dielectric layer located on top of the substrate structure, the first dielectric layer covering the sidewalls of the via structures and the sidewalls of the seed layer, and the top of the first dielectric layer being higher than the top of the via structures; and an interconnect layer located in the first dielectric layer above the top of the via structures, at least a portion of the interconnect layer being connected to the top of the corresponding via structure. In this invention, since the seed layer is located only between the bottom of each via structure and the substrate structure, the formed seed layer is a planar structure, thereby increasing the area of the seed layer. This increases the surface area of the via structures, which in turn improves the surface flatness of the via structures, and consequently improves the surface flatness of the interconnect layer, thus enhancing the performance of the semiconductor structure.
[0011] This invention provides a packaging structure including: a first wafer and a second wafer stacked and bonded together. One or both of the first wafer and the second wafer employ a semiconductor structure according to any embodiment of this invention, and the interconnect layer is a bonding pad. The bonding pads of the first wafer and the second wafer are disposed opposite to each other and in contact. At least one of the first wafer and the second wafer has a bonding pad with higher surface flatness, resulting in a lower probability of pit formation on the bonding pad surface. Therefore, during the process of forming the interconnect bonding pad on top of the via structure, the probability of pit formation on the interconnect bonding pad surface is reduced, thereby reducing the probability of bubble defects between the bonding pads of the first wafer and the second wafer. This allows for good contact between the bonding pads of the first wafer and the second wafer, thereby improving the yield of the packaging structure. Attached Figure Description
[0012] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0013] Figures 7 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;
[0014] Figure 22 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
[0015] Figure 23 This is a schematic diagram of an embodiment of the packaging structure of the present invention. Detailed Implementation
[0016] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one method for forming a semiconductor structure as an example. Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0017] refer to Figure 1 A substrate 10 is provided, on which a first dielectric layer 11 is formed, and a first opening 12 is formed in the first dielectric layer 11.
[0018] refer to Figure 2 A through-hole structure material layer 13A is formed in the first opening 12 and on the top of the first dielectric layer 11 on the side of the first opening 12.
[0019] refer to Figure 3 The via structure material layer 13A above the top of the first dielectric layer 11 is planarized, and the remaining via structure material layer 13A located in the first opening 12 is used as via structure 13.
[0020] refer to Figure 4 A second dielectric layer 14 is formed on top of the first dielectric layer 11 and the through-hole structure 13, and a second opening 15 is formed in the second dielectric layer 14.
[0021] refer to Figure 5 An interconnect material layer 16A is formed in the second opening 15 and on top of the second dielectric layer 14 on the side of the second opening 15.
[0022] refer to Figure 6 The interconnect material layer 16A above the top of the second dielectric layer 14 is planarized, and the remaining interconnect material layer 16A located in the second opening 15 serves as the interconnect layer 16.
[0023] Specifically, the via structure 13 and the interconnect layer 16 constitute an interconnect structure (not shown).
[0024] Research has revealed that two planarization processes are required during the formation of the interconnect structure. For example... Figure 3 As shown, during the planarization process of the through-hole material layer 13A at the top of the first dielectric layer 11, due to the influence of different pattern densities, pitting is easily observed on the top surface of the through-hole structure 13 in the first opening 12; for example... Figure 6 As shown, during the planarization process of the interconnect material layer 16A on top of the second dielectric layer 14, due to the transmissivity of the film layer, the area of the etch pits on the top of the interconnect layer 16 in the second opening 15 is larger and the depth of the etch pits is deeper. Correspondingly, in the subsequent bonding process of the semiconductor structure formed by this process, the risk of gaps appearing between the interconnect layers 16 of the bonded semiconductor structure is increased, resulting in poor contact between the interconnect layers 16 of the semiconductor structure, thereby affecting the packaging reliability and packaging yield of the semiconductor structure.
[0025] Improving the uniformity of the pattern density of the via structure 13 helps to mitigate the pitting phenomenon on the top surface of the via structure 13. However, since the via structure 13 penetrates the bottom surface of the first dielectric layer 11, if a pseudo-gate via structure is set in the first dielectric layer 11, undesirable short-circuit problems may occur. Therefore, it is usually difficult to fabricate a corresponding pseudo-gate via structure for the via structure 13.
[0026] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate structure; forming a seed layer on top of the substrate structure; forming a sacrificial layer on top of the substrate structure, wherein a first opening is formed in the sacrificial layer to expose the top of the seed layer; forming a via structure on the seed layer in the first opening; removing the sacrificial layer after forming the via structure; forming a first dielectric layer covering the substrate structure and the via structure after removing the sacrificial layer; and forming an interconnect layer in the first dielectric layer above the top of the via structure, wherein at least a portion of the interconnect layer is connected to the top of the corresponding via structure.
[0027] In the scheme disclosed in the embodiments of the present invention, by first forming a seed layer and a sacrificial layer with a first opening, and then forming a via structure in the first opening, compared with the traditional method of forming via structure by single damask process, the via structure, under the constraint of the sacrificial layer, can use the seed layer as the growth base to form the via structure from bottom to top, without the need for additional planarization process, thereby reducing the probability of pit formation on the surface of the via structure, which is beneficial to provide a flat surface for the formation of interconnect layer, thereby improving the surface flatness of interconnect layer and improving the performance of semiconductor structure.
[0028] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0029] Figures 7 to 21 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0030] refer to Figure 7 Provides a 500-meter base structure.
[0031] The substrate structure 500 is used to provide a process platform for forming semiconductor structures.
[0032] In this embodiment, in the step of providing the substrate structure 500, the substrate structure 500 includes a substrate (not shown), a second dielectric layer (not shown) located on the substrate, and a front interconnect structure (not shown) located in the second dielectric layer, wherein the second dielectric layer exposes the top surface of the front interconnect structure.
[0033] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.
[0034] The second dielectric layer is used to achieve electrical isolation between various devices or interconnect structures. For example, the devices can be MOS devices formed on the substrate, and the interconnect structures can include interconnect layers or via structures formed in later processes.
[0035] In this embodiment, the material of the second dielectric layer is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6).
[0036] Front-end interconnect structures are used to electrically connect to specific devices within or on the substrate, thereby bringing out the electrical properties of each device or enabling electrical connections between devices.
[0037] It should be noted that the interconnect structure formed by the back-end process usually includes interconnect layers, and the number of interconnect layers is multi-layered, with the multi-layered interconnect layers located at different thicknesses of the second dielectric layer.
[0038] As an example, the front-end interconnect structure is the topmost interconnect layer in the back-end process.
[0039] In other embodiments, the front-end interconnect structure may also be an interconnect layer of a certain layer in the back-end process.
[0040] refer to Figure 8 A seed layer 501 is formed on top of the substrate structure 500.
[0041] The seed layer 501 provides a growth basis for the subsequent formation of the through-hole structure and provides a uniform starting surface, which helps to reduce the probability of defects such as voids and cracks in the through-hole structure, thereby improving the quality and reliability of the through-hole structure.
[0042] In this embodiment, during the step of forming the seed layer on top of the substrate structure 500, the seed layer 501 covers the entire top of the substrate structure 500.
[0043] Specifically, since the seed layer 501 covers the entire top of the substrate structure 500, there is no need to pattern the seed layer 501, reducing the complexity of the process for forming the seed layer 501. Secondly, the fact that the seed layer 501 covers the entire top of the substrate structure 500 also helps to increase the process window for forming the first opening, thereby increasing the surface area of the bottom of the through-hole structure, which in turn helps to improve the surface flatness of the through-hole structure and thus improves the quality of the formed through-hole structure.
[0044] In other embodiments, the seed layers may also be separately disposed on top of the substrate structure. In other words, the seed layers are disposed at the locations where the through-hole structure is subsequently formed, thereby eliminating the step of removing the seed layers on the sides of the through-hole structure and thus avoiding the impact of the step of removing the seed layers on the through-hole structure.
[0045] In this embodiment, in the step of forming a seed layer 501 on top of the substrate structure 500, the seed layer 501 is located at least above the top surface of the front interconnect structure.
[0046] Specifically, the seed layer 501 is located at least above the top surface of the previous interconnect structure, so that the subsequently formed via structure can be electrically connected to the corresponding previous interconnect structure.
[0047] In this embodiment, in the step of forming a seed layer 501 on top of the substrate structure 500, the material of the seed layer 501 includes tantalum nitride.
[0048] Specifically, tantalum nitride facilitates the accurate deposition of the plating solution of the through-hole material at the corresponding location in the subsequent electroplating process, and forms a continuous through-hole structure without pores or voids.
[0049] refer to Figures 9 to 10 A sacrificial layer 502 is formed on top of the substrate structure 500, and a first opening 510 is formed in the sacrificial layer 502 to expose the top of the seed layer 501.
[0050] The sacrificial layer 502 is used to control the growth direction of the subsequently formed through-hole structure, so that the through-hole structure can be formed in the first opening 510.
[0051] The first opening 510 is used to provide space for the subsequently formed through-hole structure.
[0052] Specifically, the step of forming a sacrificial layer on top of the seed layer includes: (Refer to...) Figure 9 A sacrificial material layer 502A is formed on top of the substrate structure 500, covering the seed layer 501; Reference Figure 10 The sacrificial material layer 502A is graphically represented, and a first opening 510 is formed in the sacrificial material layer 502A to expose the top of the seed layer 501, with the remaining sacrificial material layer 502A serving as the sacrificial layer 502.
[0053] A first opening 510 is formed in the sacrificial layer 502 to expose the top of the seed layer 501, so that the subsequently formed through-hole structure can be formed from bottom to top with the seed layer 501 as the growth base under the constraint of the sacrificial layer 502, without the need for additional planarization process, thereby reducing the probability of pitting on the surface of the through-hole structure.
[0054] It should be noted that since the seed layer 501 covers the entire top of the substrate structure 500, the bottom surface of the first opening 510 is the surface of the seed layer 501, which significantly reduces the difficulty of aligning the first opening 510 and the seed layer 501, and also helps to ensure that the subsequently formed through-hole structures are all located on the seed layer 501.
[0055] In this embodiment, the sacrificial material layer 502A is a photolithographic material.
[0056] Specifically, a photolithographic material is used as the sacrificial material layer 502A. The sacrificial material layer 502A can be patterned by photolithography, without the need for an additional etching process to form a first opening 510 in the sacrificial material layer 502A that exposes the top of the seed layer 501, thereby simplifying the process flow and avoiding etching damage to the seed layer 501.
[0057] Specifically, the sacrificial material layer 502A is made of photoresist. Photoresist is easy to remove, thereby reducing process complexity and improving production efficiency. Furthermore, it helps to reduce damage to the via structure during the removal of the sacrificial layer 502.
[0058] In this embodiment, the process of forming a sacrificial material layer 502A covering the seed layer 501 on top of the substrate structure 500 includes a spin coating process.
[0059] Specifically, the spin coating process can uniformly coat liquid or thin film materials onto the substrate structure 500, ensuring a consistent coating thickness. It can coat a large area of the substrate structure 500 in a short time, improving productivity. Furthermore, the thickness of the resulting coating can be controlled by adjusting the spin coating process parameters. Therefore, a sacrificial material layer 502A with uniform thickness can be obtained.
[0060] In this embodiment, the step of patterning the sacrificial material layer 502A includes: exposing the sacrificial material layer 502A and developing the exposed sacrificial material layer 502A to form a first opening 510 in the sacrificial material layer 502A.
[0061] Specifically, exposure and development are common semiconductor processes, which have advantages such as low process cost and high production efficiency.
[0062] In this embodiment, the first opening 510 is formed above the top of the corresponding front layer interconnect structure.
[0063] It should be noted that the first opening 510 is formed above the top of the corresponding front layer interconnect structure, so that the sacrificial layer 502 and the seed layer 501 can form a space to accommodate the via structure, thereby ensuring that the via structure can be electrically connected to the corresponding front layer interconnect structure.
[0064] It should also be noted that, in other embodiments, in the step of forming a seed layer on top of the substrate structure, the seed layer is disposed separately on top of the substrate structure, and correspondingly, in the step of forming a sacrificial layer on top of the substrate structure, the first opening exposes the top of the corresponding seed layer.
[0065] refer to Figure 11 A through-hole structure 503 is formed on the seed layer 501 in the first opening 510.
[0066] The via structure 503 is used to connect the interconnect layer and the front interconnect structure, thereby realizing the electrical connection between the interconnect layer and the internal circuitry of the semiconductor structure.
[0067] In this embodiment, the material of the through-hole structure 503 includes copper. Copper has good electrical conductivity and low resistance, which is beneficial for obtaining a through-hole structure 503 with good conductivity.
[0068] In other embodiments, the material of the through-hole structure may also include suitable conductive materials such as aluminum.
[0069] In this embodiment, in the step of forming a through-hole structure 503 on the seed layer 501 in the first opening 510, the top of the through-hole structure 503 is lower than or flush with the top surface of the sacrificial layer 502.
[0070] Specifically, the top of the via structure 503 is lower than or flush with the top surface of the sacrificial layer 502, so that the via structure 503 can be formed from bottom to top with the seed layer 501 as the growth base under the constraint of the sacrificial layer 502, without the need for additional planarization process, thereby reducing the probability of pitting on the surface of the via structure 503, which is beneficial to provide a flat surface for the formation of the interconnect layer, thereby improving the surface flatness of the interconnect layer and improving the performance of the semiconductor structure.
[0071] In one embodiment, the top of the through-hole structure 503 is lower than the top surface of the sacrificial layer 502 to ensure that the through-hole structures 503 at each location are formed only in the first opening 510.
[0072] In this embodiment, the process of forming a through-hole structure 503 on the seed layer 501 of the first opening 510 includes an electroplating process.
[0073] Specifically, the electroplating process can enhance the bonding force between the formed through-hole structure 503 and the seed layer 501, improve the adhesion of the through-hole structure 503, and at the same time, the through-hole structure 503 formed by the electroplating process has high conductivity, thereby improving the performance of the semiconductor structure.
[0074] refer to Figure 12 After forming the through-hole structure 503, the sacrificial layer 502 is removed.
[0075] Specifically, after forming the through-hole structure 503, the sacrificial layer 502 is removed, thereby providing a process basis for the subsequent formation of the first dielectric layer.
[0076] In this embodiment, the process for removing the sacrificial layer 502 includes a wet process.
[0077] Specifically, the wet process has the characteristic of isotropic etching, which is beneficial to remove the sacrificial layer 502 cleanly. Moreover, the wet process is easy to obtain a large etching selectivity, which helps to reduce damage to other film layers (e.g., via structure 503) during the removal of the sacrificial layer 502.
[0078] In this embodiment, the sacrificial layer 502 is made of photoresist, and therefore a wet photoresist removal method is used to remove the sacrificial layer 502. In other embodiments, an ashing process can also be used to remove the sacrificial layer.
[0079] refer to Figure 13 After removing the sacrificial layer 502, the process further includes removing the seed layer 501 on the side of the through-hole structure 503.
[0080] Specifically, removing the seed layer 501 on the side of the through-hole structure 503 helps prevent communication between the through-hole structures 503, thereby reducing leakage current.
[0081] In this embodiment, the process of removing the seed layer 501 on the side of the through-hole structure 503 includes a dry etching process.
[0082] Specifically, the dry etching process has good selectivity, which can etch the material of the seed layer 501 while reducing damage to other material films (e.g., via structure 503). At the same time, the dry etching process can precisely control the etching rate, thereby accurately removing the seed layer 501.
[0083] In addition, the dry etching process has the characteristics of anisotropic etching, which is conducive to obtaining a better profile after etching, thereby improving the contact effect between the through-hole structure 503 and the seed layer 501 at its bottom.
[0084] refer to Figure 14After removing the sacrificial layer 502, the method further includes forming a protective layer 504 on the top and sidewalls of the through-hole structure 503.
[0085] Specifically, the protective layer 504 is used to protect the via structure 503, prevent the via structure 503 from being exposed to air, thereby reducing the probability of the via structure 503 being oxidized. At the same time, it can also be used to define the etching stop position of the first dielectric layer.
[0086] In this embodiment, the thickness of the protective layer 504 should not be too large or too small. If the thickness of the protective layer 504 is too large, it will generate significant stress on the subsequently formed first dielectric layer, thereby affecting the performance of the semiconductor structure. If the thickness of the protective layer 504 is too small, it will be less effective in reducing the probability of oxidation of the via structure 503. Therefore, in this embodiment, the thickness of the protective layer 504 is [not specified in the original text]. to
[0087] In this embodiment, the material of the protective layer 504 includes silicon nitride or tetraethyl orthosilicate.
[0088] Specifically, silicon nitride or tetraethyl orthosilicate are common semiconductor materials, thus being compatible with existing process technologies and having the advantage of low process costs.
[0089] The process of forming a protective layer 504 on the top and sidewalls of the through-hole structure 503 includes atomic layer deposition or chemical vapor deposition.
[0090] Specifically, the atomic layer deposition process or chemical vapor deposition process has good coverage, which helps to reduce the probability of defects such as voids in the protective layer 504, thereby improving the quality and insulation performance of the protective layer 504 and thus improving the performance of the semiconductor structure.
[0091] refer to Figures 15-16 After removing the sacrificial layer 502, a first dielectric layer 505 is formed covering the substrate structure 500 and the via structure 503.
[0092] The first dielectric layer 505 is used to provide a process basis for setting up interconnect layers, and also to provide electrical isolation between adjacent interconnect layers, reducing the risk of leakage between adjacent interconnect layers.
[0093] In this embodiment, the first dielectric layer 505 is made of an insulating material, including tetraethoxysilane. In other embodiments, the material of the first dielectric layer may also include one or more of silicon oxide, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.
[0094] Specifically, the step of forming a first dielectric layer 505 covering the substrate structure 500 and the via structure 503 includes: referencing Figure 15 A dielectric material layer 505A is formed covering the substrate structure 500 and the through-hole structure 503; Reference Figure 16 The first dielectric material layer 505A is planarized to form a first dielectric layer 505 with a flat surface.
[0095] It should be noted that the first dielectric material layer 505A undergoes planarization, that is, a portion of the first dielectric material layer 505A is removed. On the one hand, this ensures that the thickness of the first dielectric layer 505 meets the process requirements, saving process time in subsequent processes and thus improving the production efficiency of the semiconductor structure. On the other hand, it improves the surface flatness of the first dielectric layer 505, providing a smoother process foundation for subsequent processes, which is beneficial to improving the quality of the semiconductor structure.
[0096] In this embodiment, in step 505 of forming a first dielectric layer covering the substrate structure 500 and the through-hole structure 503, the first dielectric layer 505 covers the protective layer 504.
[0097] Specifically, the first dielectric layer 505 covers the protective layer 504. In the subsequent process of forming interconnect openings in the first dielectric layer 505, the protective layer 504 can be used to define the etching stop position of the first dielectric layer 505. At the same time, the protective layer 504 can also facilitate the electrical isolation between the pseudo bonding pads formed in the first dielectric layer 505 and the previous interconnect structure.
[0098] refer to Figures 17 to 21 An interconnect layer 506 is formed in the first dielectric layer 505 above the top of the via structure 503, and at least a portion of the interconnect layer 506 is connected to the top of the corresponding via structure 503.
[0099] Interconnect layer 506 is used to make electrical connections with via structure 503.
[0100] Correspondingly, the via structure 503 is located between the interconnect layer 506 and the front interconnect structure, and connects the interconnect layer 506 and the front interconnect structure, thereby realizing the electrical connection between the interconnect layer 506 and the internal circuit of the semiconductor structure.
[0101] It should be noted that in this embodiment, the seed layer 501 is a planar structure, resulting in a larger surface area for the via structure 503. This is beneficial for further improving the surface flatness of the via structure 503, thereby improving the surface flatness of the interconnect layer 506. Moreover, with the projected area of the seed layer 501 on the surface of the substrate structure 500 remaining unchanged, compared with the U-shaped seed layer, the planar structure of the seed layer 501 results in a larger surface area for the via structure 503. This correspondingly improves the contact effect between the via structure 503 and the interconnect layer 506, as well as the contact effect between the via structure 503 and the previous interconnect structure. Consequently, it helps to reduce the resistance of the via structure 503, the contact resistance between the via structure 503 and the interconnect layer 506, and the contact resistance between the via structure 503 and the previous interconnect structure, thereby improving the electrical performance of the semiconductor structure.
[0102] The remaining interconnect layer 506, which is laterally isolated from the via structure 503, is used as a dummy interconnect layer.
[0103] It should be noted that the pseudo interconnect layer is used to increase the total number of interconnect layers 506, so as to improve the uniformity of the distribution and pattern density of interconnect layers 506, thereby helping to improve the flatness of the top surface of interconnect layers 506.
[0104] In one embodiment, in the step of forming an interconnect layer 506 in the first dielectric layer 505 above the top of the via structure 503, the interconnect layer 506 is a bonding pad 509.
[0105] Specifically, in the subsequent bonding process of semiconductor structures, the bonding pad 509 is used to achieve metal bonding between different semiconductor structures in order to improve the bonding strength.
[0106] In this embodiment, the bonding pad 509 is made of one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is beneficial for obtaining better conductivity.
[0107] In this embodiment, the bonding pad 509 includes a dummy bonding pad (not shown) and an interconnect bonding pad 507. The remaining interconnect layer 506, which is laterally isolated from the via structure 503, serves as the dummy interconnect bonding pad.
[0108] Part of the interconnect layer 506 is connected to the top of the corresponding via structure 503 and serves as an interconnect bonding pad 507, while the remaining interconnect layer 506 is laterally isolated from the via structure 503 as a pseudo bonding pad.
[0109] Specifically, the interconnect bonding pads 507 are connected to the top of the corresponding via structures 503, thereby enabling each interconnect bonding pad 507 to achieve electrical connection with a specific front-layer interconnect structure through the corresponding via structure 503.
[0110] It should be noted that in this embodiment, the interconnect bonding pad 507 and the pseudo bonding pad are formed in the same step, which improves the overall distribution uniformity and pattern density consistency of the interconnect bonding pad 507 and the pseudo bonding pad, thereby improving the uniformity in the planarization process and further improving the flatness of the top surface of the interconnect bonding pad 507 and the pseudo bonding pad.
[0111] refer to Figure 17 Before forming the interconnect layer 506 in the first dielectric layer 505 above the top of the via structure 503, the method further includes forming a bonding dielectric layer 520 on top of the first dielectric layer 505.
[0112] Specifically, the bonding dielectric layer 520 is used to provide a smooth bonding surface for subsequent bonding processes, thereby improving bonding quality. At the same time, the bonding dielectric layer 520 can adjust the thermal expansion coefficient of the overall structure, thereby reducing the stress caused by temperature changes and improving the bonding yield.
[0113] In this embodiment, the bonding dielectric layer 520 is made of a dielectric material. Therefore, a hybrid bonding process is achieved through the bonding dielectric layer 520 and the bonding pad 509 to further improve the bonding yield.
[0114] In this embodiment, the material of the bonding dielectric layer 520 includes silicon carbide (SiCN).
[0115] In this embodiment, in the step of forming an interconnect layer 506 in the first dielectric layer 505 above the top of the via structure 503, the interconnect layer 506 is also formed in the bonding dielectric layer 520, and the top surface of the interconnect layer 506 is exposed by the bonding dielectric layer 520.
[0116] Specifically, the interconnect layer 506 penetrates the bonding dielectric layer 520 and the first dielectric layer 505 above the top of the via structure 503. The top surface of the interconnect layer 506 is exposed by the bonding dielectric layer 520, preparing for subsequent bonding of the semiconductor structure through the interconnect layer 506.
[0117] In this embodiment, the step of forming an interconnect layer 506 in the first dielectric layer 505 above the top of the via structure 503 includes: referencing Figures 18 to 19 An interconnect opening 511 is formed in the first dielectric layer 505 above the top of the via structure 503, at least partially exposing the top of the via structure 503; Reference Figure 20 An interconnect material layer 506A is filled into the interconnect opening 511; Reference Figure 21 The interconnect material layer 506A is planarized, and the interconnect material layer 506A outside the interconnect opening 511 is removed.
[0118] Interconnect opening 511 provides space for forming interconnect layer 506. Specifically, interconnect opening 511 extends through bonding dielectric layer 520 and first dielectric layer 505 above the top of via structure 503.
[0119] Specifically, the interconnect opening 511 exposes the top of the via structure 503, facilitating the contact between the interconnect layer 506 formed in the interconnect opening 511 and the top of the via structure 503, thereby achieving electrical connection between the front interconnect structure and the interconnect layer 506, and further achieving electrical connection of the internal circuit of the semiconductor structure.
[0120] It should be noted that planarizing the interconnect material layer 506A helps to improve the flatness of the top surface of the formed interconnect layer 506, so as to provide a process basis for subsequent bonding processes.
[0121] The step of forming the interconnect opening 511 in the first dielectric layer above the top of the via structure 503 includes: referencing Figure 18 Using the protective layer 504 located at the top of the through-hole structure as a stop layer, the first dielectric layer 505 is patterned to form an initial interconnect opening 512; Reference Figure 19 Remove the protective layer 504 at the bottom of the initial interconnect opening 512 to form the interconnect opening 511.
[0122] Specifically, the initial interconnect opening 512 is used to provide a process window for the subsequent formation of interconnect openings.
[0123] First, the protective layer 504 located at the top of the via structure is used as a stop layer, so that each initial interconnect opening 512 can penetrate the bonding dielectric layer 520 and the first dielectric layer 505 above the top of the via structure 503, thereby ensuring that each interconnect opening 511 can expose the corresponding via structure 503.
[0124] It should be noted that in this embodiment, after forming the via structure 503, a first dielectric layer 505 and an interconnect layer 506 are formed. Therefore, the interconnect layer 506 can adopt a single damask structure. Compared with the scheme of forming the interconnect layer and via structure through a double damask process, it is beneficial to improve the morphological quality of the interconnect layer 506, reduce the probability of the top size of the interconnect layer 506 being too large, and thus help to reduce the material diffusion problem of the interconnect layer 506.
[0125] Accordingly, embodiments of the present invention also provide a semiconductor structure. Figure 22 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
[0126] refer to Figure 22 The semiconductor structure includes: a substrate structure 100; via structures 101, discretely disposed on the top of the substrate structure 100; a seed layer 102, located only between the bottom of each via structure 101 and the substrate structure 100; a first dielectric layer 103, located on the top of the substrate structure 100, the first dielectric layer 103 covering the sidewalls of the via structures 101 and the sidewalls of the seed layer 102, and the top of the first dielectric layer 103 being higher than the top of the via structures 101; and an interconnect layer 104, located in the first dielectric layer 103 above the top of the via structures 101, at least a portion of the interconnect layer 104 being connected to the top of the corresponding via structure 101.
[0127] The substrate structure 100 is used to provide a process platform for forming semiconductor structures.
[0128] In this embodiment, the substrate structure 100 includes a substrate (not shown), a second dielectric layer (not shown) on the substrate, and a front interconnect structure (not shown) in the second dielectric layer, wherein the second dielectric layer exposes the top surface of the front interconnect structure.
[0129] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.
[0130] The second dielectric layer is used to achieve electrical isolation between various devices or interconnect structures. For example, the devices can be MOS devices formed on the substrate, and the interconnect structures can include interconnect layers or via structures formed in later processes.
[0131] In this embodiment, the material of the second dielectric layer is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6).
[0132] Front-end interconnect structures are used to electrically connect to specific devices within or on the substrate, thereby bringing out the electrical properties of each device or enabling electrical connections between devices.
[0133] It should be noted that the interconnect structure formed by the back-end process usually includes interconnect layers, and the number of interconnect layers is multi-layered, with the multi-layered interconnect layers located at different thicknesses of the second dielectric layer.
[0134] As an example, the front-end interconnect structure is the topmost interconnect layer in the back-end process.
[0135] In other embodiments, the front-end interconnect structure may also be an interconnect layer of a certain layer in the back-end process.
[0136] In this embodiment, the material of the front-layer interconnect structure is copper. In other embodiments, the material of the front-layer interconnect structure can also be other conductive materials, such as aluminum.
[0137] The via structure 101 is used to connect the interconnect layer 104 and the front interconnect structure, thereby realizing the electrical connection between the interconnect layer 104 and the internal circuitry of the semiconductor structure.
[0138] In this embodiment, the material of the through-hole structure 101 includes copper. Copper has good electrical conductivity and low resistance, which is beneficial for obtaining a through-hole structure 101 with good conductivity.
[0139] In other embodiments, the material of the through-hole structure may also include suitable conductive materials such as aluminum.
[0140] In this embodiment, the through-hole structure 101 is located above the top surface of the front interconnect structure and is electrically connected to the front interconnect structure.
[0141] Specifically, the reason why the via structure 101 is located above the top surface of the front interconnect structure and is electrically connected to the front interconnect structure is to bring out the front interconnect structure, thereby realizing the electrical connection between the front interconnect structure and the interconnect layer 104, and thus realizing the electrical connection of the internal circuit of the semiconductor structure.
[0142] The seed layer 102 provides a growth basis for the formation of the through-hole structure 101 and provides a uniform starting surface, which helps to reduce the probability of defects such as voids and cracks in the through-hole structure 101, thereby improving the quality and reliability of the through-hole structure 101.
[0143] In this embodiment, the seed layer 102 is located only between the bottom of each of the through-hole structures 101 and the base structure 100.
[0144] It should be noted that since the seed layer 102 is located only between the bottom of each via structure 101 and the substrate structure 100, the formed seed layer 102 is a planar structure, thereby increasing the area of the seed layer 102. This is beneficial to increasing the process window of the via structure 101, and correspondingly increasing the surface area of the via structure 101. This is beneficial to further improve the surface flatness of the via structure 101, thereby improving the surface flatness of the interconnect layer 104, and thus improving the performance of the semiconductor structure.
[0145] In this embodiment, the seed layer 102 is made of tantalum nitride.
[0146] Specifically, tantalum nitride facilitates the accurate deposition of the plating solution of the through-hole material at the corresponding location in the subsequent electroplating process, and forms a continuous through-hole structure without pores or voids.
[0147] The first dielectric layer 103 is used to provide a process basis for setting up the interconnect layer 104, and also to provide electrical isolation between adjacent interconnect layers 104, thereby reducing the risk of leakage between adjacent interconnect layers 104.
[0148] In this embodiment, the material of the first dielectric layer 103 is an insulating material, including tetraethoxysilane. In other embodiments, the material of the first dielectric layer may also include one or more of silicon oxide, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.
[0149] The interconnect layer 104 is used to make electrical connections with the through-hole structure 101.
[0150] Correspondingly, the via structure 101 is located between the interconnect layer 104 and the front interconnect structure, and connects the interconnect layer 104 and the front interconnect structure, thereby realizing the electrical connection between the interconnect layer 104 and the internal circuit of the semiconductor structure.
[0151] It should be noted that the seed layer 102 in this embodiment is a planar structure, thus the surface area of the via structure 101 is larger, which is beneficial to further improve the surface flatness of the via structure 101, thereby improving the surface flatness of the interconnect layer 104. Moreover, with the projected area of the seed layer 102 on the surface of the substrate structure 100 remaining unchanged, compared with the U-shaped seed layer, the planar structure of the seed layer 102 makes the surface area of the via structure 101 larger, which correspondingly improves the contact effect between the via structure 101 and the interconnect layer 104, as well as the contact effect between the via structure 101 and the previous interconnect structure. This is beneficial to reduce the resistance of the via structure 101, the contact resistance between the via structure 101 and the interconnect layer 104, and the contact resistance between the via structure 101 and the previous interconnect structure, thereby improving the electrical performance of the semiconductor structure.
[0152] In this embodiment, the interconnect layer 104 is made of copper. In other embodiments, the interconnect layer may be made of other conductive materials, such as aluminum.
[0153] The remaining interconnect layer 104, which is laterally isolated from the via structure 101, is used as a pseudo interconnect layer (not shown).
[0154] It should be noted that the pseudo interconnect layer is used to increase the total number of interconnect layers 104, so as to improve the uniformity of the distribution and pattern density of interconnect layers 104, thereby helping to improve the flatness of the top surface of interconnect layers 104.
[0155] In this embodiment, the interconnect layer 104 is a bonding pad 105.
[0156] Specifically, in the subsequent bonding process of semiconductor structures, bonding pad 105 is used to achieve metal bonding between different semiconductor structures in order to improve the bonding strength.
[0157] In this embodiment, the bonding pad 105 is made of one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is beneficial for obtaining better conductivity.
[0158] In this embodiment, the bonding pad 105 includes a pseudo bonding pad and an interconnect bonding pad 107. The remaining interconnect layer 104, which is laterally isolated from the via structure 101, serves as a pseudo interconnect bonding pad.
[0159] Part of the interconnect layer 104 is connected to the top of the corresponding via structure 101 and serves as an interconnect bonding pad 107, while the remaining interconnect layer 104 is laterally isolated from the via structure 101 as a pseudo interconnect pad.
[0160] It should be noted that the interconnect bonding pads 107 are connected to the top of the corresponding via structures 101, so that each interconnect bonding pad 107 can be electrically connected to a specific front-layer interconnect structure through the corresponding via structure 101.
[0161] In this embodiment, the semiconductor structure further includes a protective layer 108 located between the sidewall of the via structure 101 and the first dielectric layer 103, and exposing the top of the via structure 101.
[0162] Specifically, the protective layer 108 is used to protect the via structure 101, prevent the via structure 101 from being exposed to air, thereby reducing the probability of the via structure 101 being oxidized. At the same time, it can also be used to define the etching stop position of the first dielectric layer 103.
[0163] In this embodiment, the thickness of the protective layer 108 should not be too large or too small. If the thickness of the protective layer 108 is too large, it will generate significant stress on the subsequently formed first dielectric layer 103, thereby affecting the performance of the semiconductor structure. If the thickness of the protective layer 108 is too small, it may result in poor effectiveness in reducing the probability of oxidation of the via structure 101. Therefore, in this embodiment, the thickness of the protective layer 108 is... to
[0164] In this embodiment, the material of the protective layer 108 includes silicon nitride or tetraethyl orthosilicate.
[0165] Specifically, silicon nitride or tetraethyl orthosilicate are common semiconductor materials, thus being compatible with existing process technologies and having the advantage of low process costs.
[0166] In this embodiment, the semiconductor structure further includes: a bonding dielectric layer 120 located on top of the first dielectric layer 103; an interconnect layer 104 located above the top of the via structure 101 in the bonding dielectric layer 120 and the first dielectric layer 103, and the top surface of the interconnect layer 104 (i.e. the bonding pad 105) is exposed by the bonding dielectric layer 120.
[0167] Specifically, the bonding dielectric layer 120 is used to provide a smooth bonding surface for subsequent bonding processes, thereby improving the bonding quality. At the same time, the bonding dielectric layer 120 can adjust the thermal expansion coefficient of the overall structure, thereby reducing the stress caused by temperature changes and thus improving the bonding yield.
[0168] In this embodiment, the material of the bonding dielectric layer 120 is a dielectric material. Therefore, a hybrid bonding process is achieved through the bonding dielectric layer 120 and the bonding pad 105 to further improve the bonding yield.
[0169] In this embodiment, the material of the bonding dielectric layer 120 includes silicon carbide (SiCN).
[0170] In this embodiment, the top surface of the interconnect layer 104 is exposed by the bonding medium layer 120, in preparation for the subsequent bonding of the semiconductor structure through the interconnect layer 104.
[0171] It should be noted that the semiconductor structure of the embodiments of the present invention can be formed using any of the formation methods of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure of the embodiments of the present invention, please refer to the relevant content of the foregoing embodiments.
[0172] Accordingly, embodiments of the present invention also provide a packaging structure. Figure 23 This is a schematic diagram of an embodiment of the packaging structure of the present invention.
[0173] refer to Figure 23 A first wafer 200 and a second wafer 201 are stacked and bonded together. One or both of the first wafer 200 and the second wafer 201 adopt the semiconductor structure of any of the foregoing embodiments, and the interconnect layer 304 is a bonding pad 204. The bonding pads 204 of the first wafer 200 and the bonding pads 204 of the second wafer 201 are disposed opposite to each other and in contact.
[0174] It should be noted that at least one of the first wafer 200 and the second wafer 201 has a bonding pad 204 with higher surface flatness. The probability of pitting on the surface of the bonding pad 204 is relatively small. Therefore, in the process of forming the interconnect bonding pad 206 on the top of the via structure 301, the probability of pitting on the surface of the interconnect bonding pad 206 is reduced, thereby reducing the probability of bubble defects between the bonding pad 204 of the first wafer 200 and the bonding pad 204 of the second wafer 201. This allows the bonding pad 204 of the first wafer 200 and the bonding pad 204 of the second wafer 201 to achieve good contact, thereby improving the yield of the packaging structure.
[0175] It should also be noted that an annealing process is usually used during the bonding process, which causes the bonding pads 204 of the first wafer 200 and the second wafer 201 to expand, so as to connect the bonding pads 204 of the first wafer 200 and the second wafer 201.
[0176] Specifically, one or both of the first wafer 200 and the second wafer 201 include: a substrate structure 300; via structures 301, discretely disposed on the top of the substrate structure 300; a seed layer 302, located only between the bottom of each via structure 301 and the substrate structure 300; a first dielectric layer 303, located on the top of the substrate structure 300, the first dielectric layer 303 covering the sidewalls of the via structures 301 and the sidewalls of the seed layer 302, and the top of the first dielectric layer 303 being higher than the top of the via structures 301; and an interconnect layer 304, located in the first dielectric layer 303 above the top of the via structures 301, at least a portion of the interconnect layer 304 being connected to the top of the corresponding via structure 301, the interconnect layer 304 being a bonding pad 204; wherein the bonding pad 204 includes a dummy bonding pad (not shown) and an interconnect bonding pad 206.
[0177] In this embodiment, in order to further improve the yield of the packaging structure, both the first wafer 200 and the second wafer 201 adopt the semiconductor structure of any of the aforementioned embodiments.
[0178] The first wafer 200 and the second wafer 201 are used to implement wafer-level packaging of the packaging structure.
[0179] Specifically, the first wafer 200 and the second wafer 201 form facet contact with bonding pads 204 to achieve mutual bonding.
[0180] In this embodiment, the substrate structure 300 includes a substrate (not shown), a second dielectric layer (not shown) on the substrate, and a front interconnect structure (not shown) in the second dielectric layer, wherein the second dielectric layer exposes the top surface of the front interconnect structure.
[0181] In this embodiment, the pseudo bonding pads in the first wafer 200 do not achieve electrical connection with the front interconnect structure inside the first wafer 200, and the pseudo bonding pads in the second wafer 201 do not achieve electrical connection with the front interconnect structure inside the second wafer 201. By setting pseudo bonding pads, the number of bonding pads 204 is increased, thereby improving the uniformity of the distribution and the uniformity of the pattern density of the bonding pads 204.
[0182] Specifically, one or both of the first wafer 200 and the second wafer 201 adopt the semiconductor structure of this embodiment. For a detailed description of the substrate structure 300, via structure 301, seed layer 302, first dielectric layer 303 and interconnect layer 304 in the first wafer 200 and the second wafer 201, please refer to the corresponding descriptions in the foregoing embodiments, and will not be repeated here.
[0183] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Provide the base structure; A seed layer is formed on top of the substrate structure; A sacrificial layer is formed on top of the substrate structure, and a first opening is formed in the sacrificial layer to expose the top of the seed layer; A through-hole structure is formed on the seed layer in the first opening; After forming the through-hole structure, the sacrificial layer is removed; After removing the sacrificial layer, a first dielectric layer is formed covering the substrate structure and the via structure; An interconnect layer is formed in the first dielectric layer above the top of the via structure, and at least a portion of the interconnect layer is connected to the top of the corresponding via structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the seed layer on top of the substrate structure, the seed layer covers the entire top of the substrate structure; After removing the sacrificial layer, the method further includes: removing the seed layer on the side of the through-hole structure; or, In the step of forming a seed layer on top of the substrate structure, the seed layer is disposed separately on top of the substrate structure; In the step of forming a sacrificial layer on top of the substrate structure, the first opening exposes the top of the corresponding seed layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a sacrificial layer on top of the seed layer includes: forming a sacrificial material layer covering the seed layer on top of the substrate structure; The sacrificial material layer is graphically represented, and a first opening is formed in the sacrificial material layer to expose the top of the seed layer, with the remaining sacrificial material layer serving as the sacrificial layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The sacrificial material layer is a photolithographic material; The step of patterning the sacrificial material layer includes: exposing the sacrificial material layer and developing the exposed sacrificial material layer to form a first opening in the sacrificial material layer.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a through-hole structure on the seed layer in the first opening, the top of the through-hole structure is lower than or flush with the top surface of the sacrificial layer.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first dielectric layer covering the substrate structure and the via structure includes: forming a dielectric material layer covering the substrate structure and the via structure; The dielectric material layer is planarized to form a first dielectric layer with a flat surface.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming an interconnect layer in the first dielectric layer above the top of the via structure, a portion of the interconnect layer is connected to the top of the corresponding via structure, and the remaining interconnect layer is laterally isolated from the via structure.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate structure, the substrate structure includes a substrate, a second dielectric layer on the substrate, and a front interconnect structure located in the second dielectric layer, wherein the second dielectric layer exposes the top surface of the front interconnect structure; In the step of forming a seed layer on top of the substrate structure, the seed layer is located at least above the top surface of the front interconnect structure; In the step of forming an interconnect layer in the first dielectric layer above the top of the via structure, the interconnect layer is a bonding pad.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, Before forming an interconnect layer in the first dielectric layer above the top of the via structure, the method further includes: forming a bonding dielectric layer on top of the first dielectric layer; In the step of forming an interconnect layer in the first dielectric layer above the top of the via structure, the interconnect layer is also formed in the bonding dielectric layer, and the top surface of the interconnect layer is exposed by the bonding dielectric layer.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming an interconnect layer in the first dielectric layer above the top of the via structure includes: forming an interconnect opening in the first dielectric layer above the top of the via structure, wherein at least a portion of the interconnect opening exposes the top of the via structure; The interconnect openings are filled with interconnect material layers; The interconnect material layer is planarized to remove the interconnect material layer outside the interconnect opening.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After removing the sacrificial layer, the method further includes: forming a protective layer on the top and sidewalls of the through-hole structure; In the step of forming a first dielectric layer covering the substrate structure and the via structure, the first dielectric layer covers the protective layer; The step of forming an interconnect opening in the first dielectric layer above the top of the via structure includes: using a protective layer located at the top of the via structure as a stop layer, patterning the first dielectric layer to form an initial interconnect opening; and removing the protective layer at the bottom of the initial interconnect opening to form an interconnect opening.
12. The method for forming a semiconductor structure according to any one of claims 1 to 11, characterized in that, In the step of forming a sacrificial layer on top of the substrate structure, the material of the sacrificial layer includes photoresist.
13. The method for forming a semiconductor structure according to any one of claims 1 to 11, characterized in that, The process of forming a through-hole structure on the seed layer of the first opening includes an electroplating process.
14. A semiconductor structure, characterized in that, include: Substrate structure; Through-hole structures are separately disposed on the top of the base structure; The seed layer is located only between the bottom of each of the through-hole structures and the base structure; A first dielectric layer is located on top of the substrate structure. The first dielectric layer covers the sidewalls of the through-hole structure and the sidewalls of the seed layer, and the top of the first dielectric layer is higher than the top of the through-hole structure. An interconnect layer is located in the first dielectric layer above the top of the via structure, and at least a portion of the interconnect layer is connected to the top of the corresponding via structure.
15. The semiconductor structure as described in claim 14, characterized in that, Some of the interconnect layers are connected to the top of the corresponding via structure, while the remaining interconnect layers are laterally isolated from the via structure.
16. The semiconductor structure as claimed in claim 14, characterized in that, The interconnect layer is a bonding pad.
17. The semiconductor structure as claimed in claim 14, characterized in that, The semiconductor structure further includes a protective layer located between the sidewall of the via structure and the first dielectric layer, and exposing the top of the via structure.
18. The semiconductor structure as claimed in claim 17, characterized in that, The protective layer is made of silicon nitride or tetraethyl orthosilicate.
19. The semiconductor structure according to any one of claims 14 to 18, characterized in that, The substrate structure includes a substrate, a second dielectric layer on the substrate, and a front interconnect structure located in the second dielectric layer, wherein the second dielectric layer exposes the top surface of the front interconnect structure; The via structure is located above the top surface of the front interconnect structure and is electrically connected to the front interconnect structure.
20. A packaging structure, characterized in that, include: A first wafer and a second wafer are stacked and bonded, one or both of the first wafer and the second wafer comprising a semiconductor structure as described in any one of claims 14 to 19, and the interconnect layer is a bonding pad; wherein the bonding pads of the first wafer and the bonding pads of the second wafer are disposed opposite to each other and in contact.