Semiconductor structure, semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor structure, a semiconductor device and a forming method of the semiconductor structure and the semiconductor device. A first trench group located in the substrate; the first groove group comprises a first groove; and a communication groove portion communicating the adjacent first grooves. The semiconductor device comprises a first trench group located in a substrate; the first groove group comprises a first groove; a communication groove portion communicating the adjacent first grooves; the second groove groups are located in the substrate, the second groove groups and the first groove groups are arranged in an array, and the second groove groups are separated by the first groove groups; and the capacitor stacking body is stacked on the first groove group, the second groove group and the communicating groove part, and the capacitor stacking body continuously extends to the side walls and the bottom surfaces of the first groove group, the second groove group and the communicating groove part. According to the semiconductor structure and the semiconductor device, the communicating groove part, the first groove group and the second groove group are arranged in an array, so that the overall structure stress of the substrate is small, the surface flatness is good, and the warping degree is small.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a semiconductor device and a forming method thereof. BACKGROUND

[0002] An interposer is a medium for transferring signals of chips and modules in 2.5D and 3D semiconductor packaging, and can realize interconnection between chips and interconnection with a packaging substrate. A silicon interposer (Si interposer) can realize high-density I / O requirements due to its high fine-pitch wiring capability and through silicon via (TSV) interconnection capability, and plays an important role in 2.5D and 3D semiconductor packaging.

[0003] In order to meet the requirements of high computing power and high speed, a large number of silicon capacitors are usually designed in the Si interposer, which play an important role in power and signal integrity, and ensure the power stability or high-frequency impedance characteristics of the device. SUMMARY

[0004] Therefore, in view of the above problems, the present application provides a semiconductor structure and a semiconductor device and a forming method thereof.

[0005] The present application provides a semiconductor structure, comprising: a substrate; a first trench group located in the substrate; at least two first trench groups arranged along a second direction X'; the first trench group comprises a first trench; a communication trench part for communicating the first trenches located on a third direction Y; and the second direction X' and the third direction Y have an included angle.

[0006] The semiconductor structure described above can ensure that the substrate has small structural stress, small warping degree and good surface flatness due to the presence of the communication trench part.

[0007] The present application provides a semiconductor structure, further comprising: a second trench group located in the substrate, and a plurality of second trench groups arranged along a first direction X; wherein the second trench group and the first trench group are arrayed, and two second trench groups along the first direction X are separated by the first trench group; the first direction X, the second direction X' and the third direction Y are located in the same plane, the first direction X is perpendicular to the third direction Y, the second direction X' intersects the first direction X and the third direction Y, and the included angle between the second direction X' and the third direction Y is an acute angle.

[0008] The semiconductor structure described above further reduces the overall structural stress of the substrate, and has smaller overall warping degree and better surface flatness due to the arrayed arrangement of the first trench group and the second trench group.

[0009] In one of the embodiments, the first trenches extend along a third direction Y, and the second trench group includes second trenches extending along a first direction X.

[0010] In one of the embodiments, the number of the first trenches in each first trench group is N, and the communication trench part includes communication trenches, the number of which is greater than or equal to N / 2. In this way, the substrate has smaller structure stress and higher reliability.

[0011] In one of the embodiments, the communication trenches extend along a third direction Y, and the communication trenches, and the first trenches adjacent to the communication trenches along the upper and lower directions of the third direction Y, are collinearly aligned.

[0012] In one of the embodiments, the number ratio of the first trench group and the second trench group is close to 1.

[0013] In one of the embodiments, along the third direction Y, the second trench group includes side surfaces located at the edges thereof, and the first trench group includes a plurality of end surfaces located at the ends of the first trenches; the side surfaces and the end surfaces are flush along the first direction X.

[0014] In one of the embodiments, along the third direction Y, there is a first gap between two adjacent second trench groups; along the first direction X, there is a second gap between the first trench group and the adjacent second trench group; the size of the first gap is greater than the size of the second gap.

[0015] The disclosure provides a semiconductor structure, further comprising: an extension trench part connected to the first trench group, the extension trench part including extension trenches extending along a third direction Y, the extension trenches being in communication with the first trenches and collinearly aligned along the third direction Y.

[0016] The above semiconductor structure, due to the presence of the extension trench part, increases the proportion of the trenches in the substrate, increases the specific surface area of the trench structure in the substrate, and increases the capacitance density of the silicon capacitor in the substrate.

[0017] In one of the embodiments, the top and bottom of the first trench have a first width and a second width respectively, the top and bottom of the second trench have a third width and a fourth width respectively, the first width and the second width are substantially the same, and the third width and the fourth width are substantially the same. The structure that the width of the top and bottom of the trench is substantially the same makes the continuity of the capacitor material good, the thickness uniformity good, the capacitance density of the silicon capacitor high, and the leakage current small.

[0018] In one of the embodiments, the first width and the third width are in the range of 0.3-1.6um.

[0019] In one of the embodiments, the first trench has a first depth, and the second trench has a third depth, the first depth being greater than the third depth.

[0020] The present disclosure also provides a semiconductor device, comprising: a substrate;

[0021] a first trench group is located in the substrate; at least two groups of the first trench group are arranged along a second direction X'; the first trench group comprises a plurality of first trenches; a communication trench part is arranged to communicate the first trenches located in a third direction Y; a second trench group is located in the substrate, and a plurality of second trench groups are arranged along a first direction X; wherein the second trench group and the first trench group are arranged in an array, and two second trench groups are separated by the first trench group in the first direction X; a capacitor stack is stacked on the first trench group, the second trench group and the communication trench part, wherein the capacitor stack continuously extends to the sidewalls and the bottom surface of the first trench group, the second trench group and the communication trench part; the first direction X, the second direction X' and the third direction Y are located in the same plane, the first direction X is perpendicular to the third direction Y, the second direction X' intersects the first direction X and the third direction Y, and the angle between the second direction X' and the third direction Y is an acute angle.

[0022] In one of the embodiments, the capacitor stack has a protrusion at the position where the sidewall and the bottom surface intersect. The protrusion is arranged to make the thickness of the capacitor stack at this position more continuous and uniform, and thus the leakage current of the silicon capacitor is smaller.

[0023] In one of the embodiments, the semiconductor device further comprises a first contact plug, the capacitor stack comprises an upper electrode and a lower electrode, and a plurality of first contact plugs are located in the edge region of the substrate, and the edge region has only one of the upper electrode or the lower electrode.

[0024] In one of the embodiments, the semiconductor device further comprises a second contact plug, wherein along the third direction, there is a first gap between two adjacent second trench groups; along the third direction, there is a third gap between an adjacent first trench group and a second trench group; and the second contact plug is located on the first gap and the third gap. By arranging the second contact plug at the positions of the first gap and the third gap, more and shorter conductive paths are additionally provided, the resistance of the interconnection structure is reduced, and the equivalent resistance of the entire silicon capacitor is reduced.

[0025] The present disclosure also provides a method for forming a semiconductor device, comprising: providing a substrate; forming a first trench group, a second trench group and a communication trench part in the substrate; and forming a capacitor stack stacked on the first trench group, the second trench group and the communication trench part, wherein the capacitor stack continuously extends to the sidewalls and the bottom surface of the first trench group, the second trench group and the communication trench part.

[0026] In one of the embodiments, when the first trench group, the second trench group and the communication trench part are formed in the substrate, a virtual trench is further formed on the outer edge of the substrate. The virtual trench can avoid the problem of uneven width of the formed trenches.

[0027] In one embodiment, the capacitor stack forms a protrusion at the intersection of the sidewall and the bottom surface.

[0028] In one embodiment, the capacitor stack is formed by forming an upper electrode, a dielectric layer, and a lower electrode, the lower electrode continuously extending to cover the surface of the substrate, and the upper electrode and the dielectric layer discontinuously extending to cover the surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1A 、 Figure 1B , Figures 2-5 is a top view of a semiconductor structure of the present disclosure.

[0030] Figure 6 is a sectional view of a semiconductor structure of the present disclosure.

[0031] Figure 7 is a sectional view of a semiconductor structure of the present disclosure. Figure 8 is a sectional view of a semiconductor device of the present disclosure.

[0032] Figures 9A-9E is a top view of a semiconductor device of the present disclosure.

[0033] Figures 10A-10D is a sectional view of a semiconductor device of the present disclosure.

[0034] In the figure: 1 - substrate; 2 - first group of trenches; 20 - first trench; 201 - sidewall; 202 - bottom surface; 3 - communicating trench part; 30 - communicating trench; 31 - second initial metal column; 4 - second group of trenches; 40 - second trench; 5 - extended trench part; 50 - extended trench; 61 - first gap; 62 - second gap; 63 - third gap; 71 - lower electrode; 72 - upper electrode; 721 - supplementary electrode; 81 - dielectric layer; 90 - first contact plug; 91 - second contact plug; 100 - insulating layer; 200 - sacrificial layer; 300 - mask layer; 400 - dummy trench. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present application, a more complete description of the present application will be given below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this description, the singular forms "a", "an" and "the" include plural references, unless the context clearly dictates otherwise.

[0037] In the description of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the method or position shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0038] The main function of the silicon capacitor decoupling capacitor is to reduce noise and decoupling, so the larger the capacitance value density of the silicon capacitor is required, and the smaller the equivalent resistance and leakage current of the interconnection structure are required, and at the same time, the overall structure of the Si interposer is required to have good reliability, high surface flatness and small warpage.

[0039] Based on this, the semiconductor structure of the technical scheme of the present application is described in detail below in combination with the drawings and specific embodiments.

[0040] Reference Figure 1A 、 Figure 1B The present application provides a semiconductor structure, comprising: a substrate 1; a first trench group 2 located in the substrate 1; at least two first trench groups 2 arranged along a second direction X'; the first trench group 2 comprises a plurality of first trenches 20; a communication trench part 3 communicating the first trenches 20 located on the third direction Y.

[0041] The substrate 1 can include but is not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate, when the substrate 1 is a single crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a doped silicon substrate, further, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The substrate 1 can include but is not limited to an organic substrate, a glass substrate, a ceramic substrate, a metal substrate.

[0042] The semiconductor structure includes at least two first trench groups 2, the two first trench groups 2 are arranged in a staggered manner, the staggered arrangement is parallel to the second direction X', referring to Figure 1A 、 Figure 1BThe shown top view of the semiconductor structure, the connecting line of the features at the same position on two first trench groups 2 is parallel to the second direction X'. As an example, the connecting line of the center point O of one first trench group 2 and the center point O' of another first trench group 2 is parallel to the second direction X', where the center points O and O' can be fictitious points and can not belong to the structural features on the first trench group 2; or the connecting line of the corner point A of one first trench group 2 and the corner point B of another first trench group 2 is parallel to the second direction X'.

[0043] Here, for the sake of clarity and simplicity of description, as shown in FIG. 1, Figure 1B As shown, the first direction X, the second direction X' and the third direction Y are defined in the same plane, the first direction X and the third direction Y are perpendicular, the second direction X' intersects the first direction X and the third direction Y, and the angle θ between the second direction X' and the third direction Y is an acute angle.

[0044] The first trench group 2 includes a plurality of first trenches 20, and as an example, the first trench 20 is a rectangular trench, and the plurality of first trenches 20 of each first trench group 2 are parallel to each other, and each first trench 20 extends along the third direction Y. The shape and extension direction of the first trench 20 can also be other embodiments, such as the shape of the first trench 20 is a circular arc trench (not shown in the figure), which is not limited here.

[0045] The rectangular trench required by the present disclosure can be a standard right-angled rectangle, or a rounded rectangle (the rectangular end or right-angled position is a circular arc), or even approximately elliptical, and the rectangular shape does not limit the trench, such as the rectangular trench extending along the third direction Y can be the center line of the trench extending along the third direction.

[0046] The semiconductor structure further includes a communication trench part 3, and the communication trench part 3 communicates the first trenches 20 located adjacent in the third direction Y. Because the at least two first trench groups 2 are staggered, there are up and down adjacent first trenches along the third direction Y at the position where the two first trench groups 2 are close. The communication trench part 3 includes a plurality of communication trenches 30, and the plurality of communication trenches 30 communicate the up and down adjacent first trenches 20 along the third direction Y.

[0047] The existence of the communication trench part 3 and the communication trench 30 can ensure that the structure stress of the substrate 1 is small and the reliability is high, especially the warping of the substrate 1 in the direction perpendicular to the third direction Y is small, the surface flatness of the substrate 1 is good, and the metal interconnection structure in the substrate 1 is reliable, and further the interconnection reliability of the substrate 1 and the chip or module or other substrate package is ensured.

[0048] Each of the communication trenches 30 extends along the third direction Y, as an example, when each of the first trenches 20 extends along the third direction Y, the communication trench 30, together with the two first trenches 20 adjacent to it along the third direction Y, are in line and in line alignment.

[0049] In one embodiment, the number of the first trenches 20 in each of the first trench groups 2 is N, and the number of the communication trenches 30 in each of the communication trench groups 3 is M, where the included angle θ between the second direction X' and the third direction Y is an acute angle including zero, and when the included angle θ is zero, the number M of the communication trenches 30 is equal to the number N of the first trenches 20. At this time, the two first trench groups 2 adjacent along the third direction Y are completely connected by the communication trench group 3.

[0050] In other embodiments, the number M of the communication trenches 30 is at least a natural number 1, that is, there is at least one communication trench 30 connecting the two first trench groups 2 adjacent along the third direction Y. In order to make the structure stress of the substrate 1 smaller and the reliability higher, in the preferred embodiments, the number M of the communication trenches 30 is greater than or equal to N / 2.

[0051] As an example, FIG. 1 only shows the two first trench groups 2 adjacent along the third direction Y and the corresponding communication trench group 3 and its communication trenches 30, the first trenches 20 extend along the third direction Y, the communication trenches 30 extend along the third direction Y, the first trenches 20 and the communication trenches 30 in line and in line alignment are rectangular trenches, and the number M of the communication trenches 30 is equal to half of the number N of the first trenches 20. However, this example does not constitute a specific implementation limitation.

[0052] Reference Figure 2 The semiconductor structure provided by the present disclosure further comprises: a second trench group 4 located in the substrate 1, and a plurality of second trench groups 4 are arranged along the first direction X; wherein the second trench group 4 and the first trench group 2 are arrayed, and the two second trench groups 4 arranged along the first direction X are separated by the first trench group 2, or the two first trench groups 2 adjacent along the first direction X are separated by the second trench group 4, and the first trench group 2 and the second trench group 4 are arranged in a vertical and horizontal staggered manner. In this embodiment, the arrangement mode of the plurality of first trench groups 2 is set according to any embodiment of the semiconductor structure in FIG. 1, which will not be repeated here.

[0053] In another embodiment, further comprising: a plurality of second trench groups 4 arranged along the second direction X' to form a second trench group array. Referring to the embodiment shown in FIG. 1, the plurality of first trench groups 2 are arranged along the second direction X' to form a first trench group array. The first trench group array and the second trench group array are arranged along the first direction X with an interval, and two second trench group arrays arranged along the first direction X are separated by a first trench group array, or alternatively, two first trench groups 2 arranged along the first direction X are separated by a second trench group 4, and the first trench groups 2 and the second trench groups 4 are arranged in a staggered manner.

[0054] In both embodiments, at least some of the first trenches 20 in the first trench group 2 are connected to each other through the communication trench portion 3, and the first trench groups 2 and the second trench groups 4 are arranged in a staggered manner, which further ensures that the overall structural stress of the substrate 1 is small, and in particular, the warping of the substrate 1 in the direction perpendicular to the first direction X is also reduced, and the overall warping of the substrate 1 is smaller, and the surface flatness is better.

[0055] As a preferred embodiment, the ratio of the number of the first trench groups 2 to the number of the second trench groups 4 in the substrate 1 is close to 1, the first trench groups 2 and the second trench groups 4 are arranged in a staggered manner, and at least some of the first trenches 20 in the first trench group 2 are connected to each other through the communication trench portion 3. The ratio close to 1 can further reduce the overall structural stress of the substrate 1, and ensure the surface flatness and warping of the substrate 1.

[0056] Continuing to refer to Figure 2 , the second trench group 4 includes a plurality of second trenches 40. As an example, the second trench 40 is a rectangular trench, and the plurality of second trenches 40 in each second trench group 4 are parallel to each other, and each second trench 40 extends along the first direction X. The shape and extension direction of the second trench 40 can also be other embodiments, such as a circular arc-shaped trench or a wavy line trench (not shown in the figure). It can be understood that Figure 2 only a preferred example is given, and the implementation is not specifically limited.

[0057] Referring to Figure 3 , in the third direction Y, there is a first gap 61 between adjacent second trench groups 4, and the size is D1 as shown in the figure; along the first direction X, there is a second gap 62 between adjacent second trench groups 4 and the first trench group 2, and the size is D2 as shown in the figure; the size D1 of the first gap 61 is greater than the size D2 of the second gap 62. As an example, as Figure 3As shown, the second grooves 40 are rectangular grooves, the multiple second grooves 40 of each second groove group 4 are parallel to each other, and each second groove 40 extends along the first direction X. At this time, the size of the first gap 61 between the adjacent second groove groups 4 is unique, and is equal in the third direction Y, that is, the two second grooves 40 of the adjacent second groove groups 4 in the adjacent positions are parallel. For the shape and extension direction of the second grooves 40, other embodiments are possible, such as the second grooves 40 being circular arc grooves or wavy line grooves (not shown in the figure), at this time, the size of the first gap 61 between the adjacent second groove groups 4 is not unique, and can not be equal in the third direction Y.

[0058] In the present embodiment, the size D1 of the first gap 61 is greater than the size D2 of the second gap 62, but it should be understood that the second gap 62 does not limit the first gap 61, that is, the space of the first gap 61 is greater than that of the second gap 62, and it is more convenient and has greater freedom to subsequently arrange other interconnection structures in the position of the first gap 61, such as the arrangement and size of the interconnection structures. Those skilled in the art should understand that other interconnection structures can also be arranged in the space of the second gap 62, and the present embodiment does not constitute a limitation.

[0059] Continuing to refer to Figure 3 , the second grooves 40 are rectangular grooves, the multiple second grooves 40 of each second groove group 4 are parallel to each other, and each second groove 40 extends along the first direction X. In the third direction Y, the second groove group 4 includes a side surface located at the edge thereof, which appears as a side in the top view. Since the second grooves 40 are rectangular, the side is a straight line extending along the first direction X. In the third direction Y, there is a first gap 61 between the adjacent second groove groups 4, at this time, the size D1 of the first gap 61 between the adjacent second groove groups 4 is the same.

[0060] In the present embodiment, the end face of the first groove 20, and the end faces of the multiple first grooves 20 of each first groove group 2 are flush in the first direction X. For example, the end faces of the multiple upper ends of the first grooves 20 are flush, or the end faces of the multiple lower ends of the first grooves 20 are flush.

[0061] As an example, the first grooves 20 are rectangular grooves, the multiple first grooves 20 of each first groove group 2 are parallel to each other, and each first groove 20 extends along the third direction Y. The rectangular groove has a long side and a wide side, and the first grooves 20 located on the wide side have end faces, and the multiple end faces on the same side along the third direction Y are flush.

[0062] In the present embodiment, the side surface of the second trench group 4 is located at the edge of the second trench 40. Since the first trench 20 has a plurality of end surfaces which are flush in the third direction Y, the side surface and the plurality of end surfaces are also flush in the first direction X. In other words, along the third direction Y, there are the adjacent first trench group 2 and the second trench group 4, the first trench 20 has a plurality of end surfaces which are flush in the third direction Y, the second trench group 4 has a side surface located at the edge of the second trench 40, and the side surface and the end surfaces have a third gap 63 in the third direction Y, as shown in Figure 3 The size D1 of the first gap 61 is equal to the size D3 of the third gap 63. The third gap 63 provides more space for subsequent other interconnection structures. It can be understood that the size D1 of the first gap 61 can be equal to or not equal to the size D3 of the third gap 63, for example, D1 is greater than D3. Here, only a preferred example is given, and the implementation is not specifically limited.

[0063] Referring to Figure 4 , the semiconductor structure further comprises an extension trench part 5, the extension trench part 5 is arranged in the third gap 63, and the extension trench part 5 is connected with the first trench group 2, wherein the extension trench part 5 comprises a plurality of extension trenches 50, and the extension trenches 50 are in communication with the first trenches 20.

[0064] As an example, the first trench 20 is a rectangular trench, the plurality of first trenches 20 of each first trench group 2 are parallel to each other, and each first trench 20 extends in the third direction Y. The extension trench 50 is a rectangular trench, the plurality of extension trenches 50 of each extension trench part 5 are parallel to each other, and each extension trench 50 extends in the third direction Y. When the extension trench part 5 is connected with the first trench group 2, the corresponding extension trench 50 is in communication with the first trench 20, and the communicated extension trench 50 and the first trench 20 are aligned in the third direction Y.

[0065] The shape and extension direction of the first trench 20 and the extension trench 50 can also be other implementations, such as a circular arc trench or a wavy line trench (not shown in the figure). When the extension trench part 5 is connected with the first trench group 2, the corresponding extension trench 50 is connected with the first trench 20, and the two are in communication with each other at the connection. It can be understood that Figure 4 only a preferred example is given, and the implementation is not specifically limited.

[0066] In the embodiments of this disclosure, the presence of the connecting trench portion 3 and the extended trench portion 5 increases the proportion of space occupied by the trenches in the substrate 1 (or the interposer or Siinterposer), and increases the specific surface area of ​​the trench structure in the substrate 1 (the ratio of the sum of the surface areas of the trench sidewalls and the bottom to the sum of the trench volumes). This results in a greater capacitance density (capacitance per unit area as viewed from a top view) of the silicon capacitors fabricated in the substrate 1. It should be noted that the connecting trench portion 3 is connected to the first trench group 2, which firstly ensures lower structural stress in the substrate 1, and secondly increases the capacitance density of the silicon capacitors in the substrate 1.

[0067] In this embodiment, the extended trench portion 5 is connected to the first trench group 2. This is because the feature dimensions (such as length and width) of the extended trench portion 5 are typically small; if it were not connected to the first trench group 2, the manufacturing process would be more difficult. Therefore, the connection between the extended trench portion 5 and the first trench group 2 is merely a preferred example, and its implementation is not specifically limited. That is, the semiconductor structure includes the extended trench portion 5, which is located between adjacent first trench groups 2 and second trench groups 4 along the third direction Y. The extended trench portion 5 may or may not be connected to the first trench group 2.

[0068] In another embodiment, such as Figure 5 As shown, the extended groove portion 5 is provided at the third gap 63. There is a third gap 63 on each side adjacent to the first gap 61. The extended groove portion 5 can be provided at both of these third gaps 63, or it can be provided as shown in the figure. Figure 4 The example shown is only set at one of the third gaps 63; or it can be set according to actual needs, with the aim of increasing the capacitance density of silicon capacitors in substrate 1.

[0069] Figure 6 yes Figure 5 The image shows cross-sectional views of substrate 1 along the E-E', F-F', and G-G' directions. The E-E' direction cross-sectional view is a cross-section of the first trench group 2, the F-F' direction cross-sectional view is a cross-section of the second trench group 4, and the G-G' direction cross-sections from left to right are the extending trench portion 5, the connecting trench portion 3, and the extending trench portion 5. The E-E' direction cross-section is closer to the G-G' direction cross-section.

[0070] As an example, such as Figure 5 As shown, the top view of the extending trench 50, the connecting trench 30, the second trench 40, and the first trench 20 forms rectangular trenches, with the width of the rectangles being approximately the same. (Reference) Figure 6 Along the depth Z direction, the width of the top and bottom of each groove rectangle is approximately the same. Here, the positions of top and bottom are relative concepts, relative to the middle depth of each groove; their specific locations are not limited.

[0071] The substantially consistent or approximately equal of the present disclosure refers to both the same size and within a certain tolerance range, and the specific tolerance can be determined according to the actual processing requirements, and the tolerance range is substantially consistent.

[0072] As shown in Figure 6 , the top and bottom of the first groove 20 have a first width W1 and a second width W2, respectively, and the first width W1 and the second width W2 are substantially consistent. The top and bottom of the second groove 40 have a third width W3 and a fourth width W4, respectively, and the third width W3 and the fourth width W4 are substantially consistent. In this embodiment, the first width W1 and the third width W3 are also substantially consistent, and the first width and the third width are preferably in the range of 0.2-1.6um, which can be any size of 0.2um, 0.3um, 0.5um, 0.9um, 1.2um, 1.5um, 1.6um, of course, it can also be other ranges greater than 1.6um or less than 0.2um, and under the preferred conditions of the embodiment, the silicon capacitor with a capacitance value density of 0.2-1.6um is obtained.

[0073] In the present disclosure, the width of the top and bottom of the groove is substantially consistent, such structure is more conducive to the subsequent filling of the capacitor material, the filled capacitor material has good continuity and thickness consistency, the silicon capacitor has high capacitance value density and small leakage current.

[0074] Continuing to refer to Figure 6 , the depth of the embodiment is in the fourth direction Z direction.

[0075] In the E-E' direction cross-sectional view, the depths of the plurality of first grooves 20 of the first groove group 2 are different, wherein the first groove 20 has a first depth H1 near the position where the first groove 20 communicates with the extension groove part 5, and the first depths H1 of the plurality of first grooves 20 are substantially consistent; the first groove 20 has a second depth H2 near the position where the first groove 20 communicates with the connecting groove part 3, and the second depths H2 of the plurality of first grooves 20 are substantially consistent; and the second depth H2 is greater than the first depth H1.

[0076] In the F-F' direction cross-sectional view, the second grooves 40 of the second groove group 4 have a third depth H3, and the third depths H3 of the plurality of second grooves 40 are substantially consistent.

[0077] In the G-G' direction cross-sectional view, the fourth depths H4 of the plurality of connecting grooves 30 of the connecting groove part 3 are substantially consistent, and the fifth depths H5 of the plurality of extension grooves 50 of the extension groove part 5 are substantially consistent.

[0078] Among them, as Figure 6The middle dotted line indicates that the third depth H3 is the smallest; the first depth H1 and the fifth depth H5 are substantially the same, both of which are greater than the third depth H3; the second depth H2 and the fourth depth H4 are substantially the same, both of which are greater than the first depth H1.

[0079] In the present disclosure, the second groove group 4 (corresponding to the third depth H3), the extension groove part 5 (corresponding to H5), the first groove group 2 (corresponding to H1, H2), and the communication groove part 3 (corresponding to H4) are etched to form grooves, which can form a structure in which the depths of the second groove 40, the extension groove 50, the first groove 20, and the communication groove 30 increase in turn. It can be understood here that if there is no communication groove part 3 and extension groove part 5, the groove depths formed by synchronous etching of the second groove group 4 and the first groove group 2 will be substantially the same, but in the present embodiment, the presence of the communication groove part 3 and the extension groove part 5 makes the depth of the first groove group 2 increase more than before, thereby increasing the capacitance value density of the silicon capacitor.

[0080] The present disclosure also provides a semiconductor device, comprising: any of the semiconductor structures disclosed above; and a capacitor stack stacked in the semiconductor structure; wherein the capacitor stack continuously extends on the sidewalls and bottom surfaces of the first groove group 2, the communication groove part 3, the second groove group 4, and the extension groove part 5.

[0081] In one embodiment, the semiconductor structure comprises: a substrate 1; a first groove group 2 located in the substrate 1; at least two first groove groups 2 arranged along a second direction X'; the first groove group 2 comprises a plurality of first grooves 20; and a communication groove part 3 that communicates the first grooves 20 located adjacent to each other in a third direction Y.

[0082] In one embodiment, the semiconductor structure further comprises: a second groove group 4 located in the substrate 1, a plurality of second groove groups 4 arranged along a first direction X; wherein the second groove group 4 and the first groove group 2 are arranged in an array, and two second groove groups 4 arranged along the first direction X are separated by the first groove group 2.

[0083] In one embodiment, the semiconductor structure further comprises: an extension groove part 5 connected to the first groove group 2, wherein the extension groove part 5 comprises a plurality of extension grooves 50, and the extension grooves 50 communicate with the first grooves 20.

[0084] As an example, the capacitor stack can be a three-layer structure comprising a lower electrode layer, a dielectric layer, and an upper electrode layer, or a five-layer structure comprising electrode layer 1, dielectric layer 1, electrode layer 2, dielectric layer 2, and electrode layer 3, or a stacked structure with more than one layer. Each electrode layer can be a single or multiple sub-electrode layers, or a layered or composite structure composed of multiple identical or different sub-electrode layers. Each dielectric layer can be a single or multiple sub-dielectric layers, or a layered or composite structure composed of multiple identical or different sub-dielectric layers.

[0085] The electrode layer material can be a metal or a conductive non-metal, and the dielectric layer material can be an insulator or a semiconductor. For example, the electrode material can be one or more of tungsten, copper, aluminum, gold, silver, or titanium nitride and doped polycrystalline silicon, and the dielectric layer material can be one or more of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, lanthanum oxide, niobium oxide, etc.

[0086] refer to Figure 7 Select as Figure 6 Taking the first trenches 20 of the first trench group 2 in region T as an example, the capacitor stack extends continuously along the sidewalls and bottom surface of the first trenches 20. The capacitor stack includes a lower electrode 71, a dielectric layer 81, and an upper electrode 72. The lower electrode 71, dielectric layer 81, and upper electrode 72 sequentially and continuously cover the sidewalls and bottom surface of the first trenches 20. Each lower electrode 71, dielectric layer 81, and upper electrode 72 also continuously or discontinuously covers the top surface between the corresponding trenches. This top surface is on the surface of the substrate 1 in the top view. The capacitor stack shown only shows three layers: lower electrode 71, dielectric layer 81, and upper electrode 72. In practice, there can be more layers. For example, dielectric layers and electrode layers can be stacked on top of the lower electrode 71, dielectric layer 81, and upper electrode 72 to form a capacitor stack with five or more layers. The more layers, the greater the capacitance density, but the leakage current, process difficulty, and cost also increase accordingly. A controllable balance needs to be found, which is not limited here.

[0087] The upper and lower electrodes can be single-layer conductive material structures, multi-layer electrode structures made of the same or different conductive materials, or composite conductive material electrode structures made of different conductive materials; no limitation is imposed here. Similarly, the dielectric layer can be a single layer of material with a high dielectric constant (high k), a multi-layer dielectric layer structure made of the same or different dielectric materials, or a composite dielectric layer structure made of different dielectric materials; no limitation is imposed here.

[0088] Here, before the lower electrode 71 is set, at least one layer of insulating layer 100 is set on the side wall and bottom surface of the first trench 20 or the entire surface of the trench, for preventing metal diffusion or improving the leakage current of the trench side wall, the material of the insulating layer 100 can be one or more of silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, or one or more of tantalum, tantalum nitride, titanium nitride, tungsten nitride.

[0089] Here, the upper electrode 72 can be continuously covered along the side wall and bottom surface of the first trench 20 after the dielectric layer 81, and then the supplementary electrode layer 721 fills the remaining trench space of the first trench 20; or the upper electrode 72 can directly fill the first trench 20.

[0090] As shown in Figure 6 , Figure 7 , due to the structure that the width of the top and bottom of the trench is basically the same, when the capacitor stack continuously extends along the side wall and bottom surface of the first trench 20 (as an example), the material layers of the lower electrode 71, the dielectric layer 81, and the upper electrode 72 have good continuity, i.e., the layers of the capacitor stack continuously cover the side wall and bottom surface of the trench with few defects; the thickness uniformity of the layers of the capacitor stack at the top and bottom of the trench is good and can be basically the same; such a silicon capacitor has high capacitance density and small leakage current.

[0091] As an example, referring to Figure 8 , Figure 8 is an enlarged view of region I of Figure 7 , region I has a region Q at the position where the side wall 201 and the bottom surface 202 of the first trench 20 meet. As shown in Figure 8 , the lower electrode 71, the dielectric layer 81, and the upper electrode 72 have protrusions at the position of region Q, i.e., the layers of the capacitor stack are inwardly recessed toward the insulating layer 100 at the position of Q, as shown in the material layer of the lower electrode 71 has different widths at different positions of the first trench 20, the width of the material layer at the top and bottom of the trench is basically the same, while the width at the position of Q is increased. This embodiment takes the first trench 20 as an example for description, and protrusions can also be provided at the positions where the side wall and the bottom surface of other trenches of the semiconductor device meet. At these positions, the thickness of the layers of the capacitor stack can be discontinuous, and even have defects such as cracks and holes. By providing protrusions, the thickness continuity and uniformity of the capacitor stack at these positions are better, and thus the leakage current of the silicon capacitor is smaller.

[0092] Referring to Figures 9A-9B , the semiconductor device further includes: a plurality of first contact plugs 90, one end of each of the plurality of first contact plugs 90 is connected with the upper electrode 72 or the lower electrode 71, and the other end is connected with other conductive structures outside.

[0093] As shown in Figure 9A , Figure 9BAs shown, multiple first contact plugs 90 are distributed in the edge region of the substrate 1 (e.g., Figure 9A Regions P1 and P2 are shown in the diagram. In these regions, there are no trenches within the substrate 1, and the upper electrode 72 or lower electrode 71 may continuously or discontinuously cover these regions. For clarity, the upper electrode 72 is shown in a semi-transparent diagram. In region P2 of the substrate 1, only the lower electrode 71 is exposed, with no dielectric layer or upper electrode on it; while in region P1, there may only be the upper electrode 72 without a dielectric layer or lower electrode, or there may be both the upper electrode 72, the dielectric layer 81, and the lower electrode 72 (not shown in the diagram). In other regions of the substrate 1 besides regions P1 and P2, there are both the upper electrode 72, the dielectric layer 81, and the lower electrode 72. In regions P1 and P2, multiple first contact plugs 90 are electrically connected to the upper electrode 72 and the lower electrode 71, respectively. This is achieved by placing the first contact plugs 90 in the trenchless edge region of the substrate 1, directly exposing the upper electrode 72 or lower electrode 71 in the edge region, or having only one of the upper or lower electrodes in the edge region. The lower electrode 71 can be electrically connected to the first contact plug 90 without opening a window later. That is, there is no need to etch open the upper electrode or dielectric layer to form the window of the first contact plug 90. This avoids damage to the lower electrode caused by the inability to accurately stop on the lower electrode when opening the window. The process is simple and highly reliable.

[0094] As an example, when the lower electrode 71, dielectric layer 81, and upper electrode 72 continuously cover the top surface between the trenches and the surface of the substrate 1, all the first contact plugs 90 connected to the upper electrode 72 are vertically led out and connected to each other, and all the first contact plugs 90 connected to the lower electrode 71 are vertically led out and connected to each other, so that the silicon capacitor can reach its maximum capacitance.

[0095] In other embodiments, when the lower electrode 71, dielectric layer 81, and upper electrode 72 do not discontinuously cover the top surface between trenches and the surface of substrate 1, these first contact plugs 90 can be electrically connected in different ways to adjust the capacitance of each trench capacitor, or to form multiple trench capacitors in parallel or series connection.

[0096] In these embodiments, the capacitor stack only shows a lower electrode 71, a dielectric layer 81, and an upper electrode 72. If there are more layers in the capacitor stack, such as five, seven, or more, then multiple first contact plugs 90 are disposed in different areas, with one end connected to different electrode layers in the capacitor stack. Therefore, the examples do not constitute a limitation on the number of electrode layers in the capacitor stack or the connection positions of the first contact plugs 90.

[0097] refer to Figure 9CThe semiconductor device further comprises: a plurality of second contact plugs 91, one end of the plurality of second contact plugs 91 is connected with the upper electrode 72 or the lower electrode 71, and the other end is connected with other conductive structure outside.

[0098] As shown in Figure 3 , in this embodiment, there are first gaps 61 and third gaps 63 between the first groove group 2 and the second groove group 4.

[0099] As shown in Figure 9C , the plurality of second contact plugs 91 are uniformly distributed at the positions of the first gaps 61 and the third gaps 63, wherein the upper electrode 72 or the lower electrode 71 continuously or discontinuously covers the first gaps 61 and the third gaps 63. In order to electrically isolate the upper electrode 72 and the lower electrode 71, the positions of the first gaps 61 and the third gaps 63 here can have only the upper electrode 72 in some areas (such as the P3 area shown in Figure 9C ) and only the lower electrode 71 in some areas (such as the P4 area shown in Figure 9C ), and the plurality of second contact plugs 91 are respectively electrically connected with the upper electrode 72 and the lower electrode 71; in the P3 area, there are the dielectric layer 81 and the lower electrode 71 successively below the upper electrode 72, which are not shown in the figure. The connection relationship of the second contact plugs 91 at the positions of the first gaps 61 and the third gaps 63 with the upper electrode 72 or the lower electrode 71 here is only an example, such as the connection of the second contact plugs 91 in the P3 area with the upper electrode 72 and the connection of the second contact plugs 91 in the P4 area with the lower electrode 71, but it does not constitute a specific limitation, and those skilled in the art can flexibly set it according to actual needs.

[0100] As an example, all the second contact plugs 91 connected with the upper electrode 72 (such as the second contact plugs 91 in the P3 area shown in Figure 9C ) are vertically led out and connected together, and are connected with the first contact plug 90 in the P1 area; all the second contact plugs 91 connected with the lower electrode 71 (such as the second contact plugs 91 in the P4 area shown in Figure 9C ) are vertically led out and connected together, and are connected with the first contact plug 90 in the P2 area, so that the silicon capacitor can achieve the maximum capacitance.

[0101] By setting the second contact plugs 91 at the positions of the first gaps 61 and the third gaps 63, more and shorter conductive paths are additionally provided, the resistance of the interconnection structure is greatly reduced, the equivalent resistance of the entire silicon capacitor is reduced, and the leakage current is reduced.

[0102] Similarly, there are embodiments, such as Figure 4 , there are first gaps 61 and third gaps 63 between the first groove group 2 and the second groove group 4; or as shown in Figure 5 , there are first gaps 61 between the first groove group 2 and the second groove group 4. Figure 9D , Figure 9EIn the embodiment, the second contact plugs 91 are evenly distributed in the positions of the first gaps 61 and the first gaps 63, wherein the upper electrodes 72 or the lower electrodes 71 continuously or discontinuously cover these areas. When the third gap 63 is provided with the extended groove portion 5, the second contact plug 91 can not be provided above the third gap 63, because a window of the upper electrode 72 and the dielectric layer 81 can be needed to be opened at this time. Alternatively, the second contact plug 91 can be provided only in the position of the third gap 63 provided with the extended groove portion 5, and the second contact plug 91 is connected with the upper electrode (not shown in the figure), so that the opening of the window of the upper electrode 72 and the dielectric layer 81 is not involved.

[0103] The disclosure also provides a method for forming a semiconductor device, comprising: providing a substrate 1; forming a first groove group 2, a second groove group 4 and a communication groove portion 3 in the substrate 1; forming a capacitor stack, the capacitor stack being stacked on the first groove group 2, the second groove group 4 and the communication groove portion 3, wherein the capacitor stack continuously extends on the sidewalls 201 and the bottom surface 202 of the first groove group 2, the second groove group 4 and the communication groove portion 3.

[0104] In the embodiment, at least two first groove groups 2 are arranged along a second direction; the first groove group 2 comprises a first groove 20; the communication groove portion 3 communicates the first grooves 20 located in a third direction; a plurality of second groove groups 4 are arranged along a first direction; wherein the second groove group 4 and the first groove group 2 are arranged in an array, and two second groove groups 4 are separated by the first groove group 2 in the first direction; the first direction, the second direction and the third direction are located in the same plane, the first direction and the third direction are perpendicular, the second direction intersects the first direction and the third direction, and the angle between the second direction and the third direction is an acute angle.

[0105] The method comprises the following steps:

[0106] Step 1: providing a substrate 1.

[0107] The provided substrate 1 has opposite front and back surfaces, which are parallel to each other. The back surface of the substrate 1 can have a circuit structure, which can include but is not limited to a device layer, a metal interconnection layer, a dielectric layer, etc.

[0108] Step 2: forming a first groove group 2, a second groove group 4 and a communication groove portion 3 on the front surface of the substrate 1.

[0109] This step comprises: Figures 10A-10DAs shown, first, a certain thickness of the sacrificial layer 200 and a certain thickness of the mask layer 300 are formed on the surface of the substrate 1 in sequence; then, part of the mask layer 300 is removed by lithography to form the mask layer 300 after lithography, with the top view of the first groove group 2, the second groove group 4 and the communication groove part 3 as a pattern; then, the sacrificial layer 200 is etched to the surface of the substrate 1 by taking the mask layer 300 as a template; finally, the mask layer 300 is removed, and part of the material of the substrate 1 is removed by etching downward to form the first groove group 2, the second groove group 4 and the communication groove part 3, taking the sacrificial layer 200 as a template.

[0110] In other embodiments, the method further comprises forming an extension groove part 5, and the extension groove part 5, the first groove group 2, the second groove group 4 and the communication groove part 3 are formed simultaneously.

[0111] In the method, removing part of the mask layer 300 further comprises patterning and lithographing the mask layer 300 with a certain width of the edge of the substrate 1 as a pattern. Finally, as shown in Figure 10D In the method of forming the substrate 1 including the first groove group 2, the second groove group 4 and the communication groove part 3, the outer edge of the substrate 1 has a virtual groove 400. The virtual groove 400 is used to balance the problem of slow etching rate of the first groove group 2 and the second groove group 4 located at the edge of the substrate 1 during etching, so as to avoid the problem of uneven width of the formed grooves.

[0112] In the method, as shown in Figure 10D In the method, after the material of part of the substrate 1 is removed by etching downward taking the sacrificial layer 200 as a template, the sacrificial layer 200 is left with a certain thickness, which is smaller than the initial thickness of the sacrificial layer 200. The sacrificial layer 200 left with a certain thickness can prevent the risk of collapse of the sidewall between grooves due to the long length of the grooves when forming the rectangular grooves.

[0113] In the method, the method of removing part of the material of the substrate 1 includes but is not limited to laser etching, mechanical etching, chemical etching, or includes but is not limited to wet etching, dry etching, BOSCH etching, wherein the BOSCH etching is more likely to form a groove with a vertical sidewall.

[0114] The formation of the first groove group 2, the second groove group 4 and the communication groove part 3 can be synchronous etching or asynchronous etching. The synchronous etching refers to that the patterns of the first groove group 2, the second groove group 4 and the communication groove part 3 in the sacrificial layer 200 are all formed and the surface of the substrate 1 is exposed, and then the same etching process parameters are used, such as Bosch etching, in which the process parameters are the same at different positions of the substrate 1, including etching gas concentration, plasma concentration and speed, etc. In laser etching, the process parameters are the same at different positions of the substrate 1, such as that the laser is perpendicular to the material surface of the substrate 1, the laser energy and time are the same, etc. In synchronous etching, if the size characteristics of each structure are the same, such as that the diameters of multiple circular holes are the same or the length and width characteristics (or length multiplied by width) of a rectangle are the same from the top view, the depths of the grooves etched in the same time can be the same. However, in the embodiment, because the communication groove part 3 connects the adjacent first groove group 2, the depths of the grooves formed after the synchronous etching of the first groove group 2 and the second groove group 4 can be different, such as Figure 6 schematically.

[0115] The respective grooves of the first groove group 2, the second groove group 4, the communication groove part 3 and the extension groove part 5 have corresponding sidewalls 201 and bottom surfaces 202 of the same or similar structures, and the widths of the sidewalls 201 at different depth positions can be basically consistent; the bottom surface 202 can be a horizontal bottom surface or a circular arc bottom surface that is downwardly recessed, such as Figure 8 schematically.

[0116] The material of the mask layer 300 includes but is not limited to one or a combination of polycrystalline silicon, photoresist, metal film and polyimide, etc.; and the material of the sacrificial layer 200 includes but is not limited to one or a combination of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride and silicon oxycarbide, etc.

[0117] Step 3: depositing a capacitor stack on the substrate 1, including: depositing the capacitor stack on the first groove group 2, the second groove group 4 and the communication groove part 3, wherein the capacitor stack continuously extends to the sidewalls 201 and the bottom surfaces 202 of the first groove group 2, the second groove group 4 and the communication groove part 3. The capacitor stack also covers the surface of the front surface of the substrate 1.

[0118] In other embodiments, the capacitor stack is also deposited in the extension groove part 5, and the capacitor stack continuously extends to the sidewalls 201 and the bottom surfaces 202 of the extension groove part 5.

[0119] Before depositing the capacitor stack, the method further includes: etching the sacrificial layer 200 to form the first groove group 2, the second groove group 4 and the communication groove part 3, and then depositing the mask layer 300 on the first groove group 2, the second groove group 4 and the communication groove part 3. Figure 7 , Figure 8As shown in the figure, an insulating layer 100 is deposited on the side wall 201 and bottom surface 202 of the first groove group 2, the second groove group 4 and the connecting groove part 3; or the insulating layer 100 is formed by oxidation, and the substrate 1 is located on the side wall 201 and bottom surface 202 of the first groove group 2, the second groove group 4 and the connecting groove part 3 to form an insulating layer 100 with a certain thickness.

[0120] As shown in the figure, the side wall 201 and bottom surface 202 of each groove of the first groove group 2, the second groove group 4 and the connecting groove part 3 have a protrusion at the intersection of the side wall 201 and bottom surface 202, i.e. the insulating layer 100 is inwardly recessed towards the substrate 1 at the intersection, as shown in the figure. Figure 8 As another embodiment, the inward recess is formed before the formation of the insulating layer 100, i.e. the side wall 201 and bottom surface 202 of each groove of the first groove group 2, the second groove group 4 and the connecting groove part 3 have a feature of being inwardly recessed towards the substrate 1 at the intersection of the side wall 201 and bottom surface 202, i.e. the groove is inwardly recessed at the intersection (not shown in the figure). The protrusion can be obtained by adjusting the last etching parameter or several etching parameters, such as extending the time of the last etching or several etchings to increase the scallop shape, and multiple scallop shapes constitute the inward recess of the groove.

[0121] As shown in the figure, the side wall 201 and bottom surface 202 of each groove of the first groove group 2, the second groove group 4 and the connecting groove part 3 have a protrusion at the intersection of the side wall 201 and bottom surface 202, i.e. the insulating layer 100 is inwardly recessed towards the substrate 1 at the intersection, as shown in the figure. Figure 8 As shown in the figure, the side wall 201 and bottom surface 202 of each groove of the first groove group 2, the second groove group 4 and the connecting groove part 3 have a protrusion at the intersection of the side wall 201 and bottom surface 202, i.e. the insulating layer 100 is inwardly recessed towards the substrate 1 at the intersection, as shown in the figure.

[0122] As shown in the figure, the side wall 201 and bottom surface 202 of each groove of the first groove group 2, the second groove group 4 and the connecting groove part 3 have a protrusion at the intersection of the side wall 201 and bottom surface 202, i.e. the insulating layer 100 is inwardly recessed towards the substrate 1 at the intersection, as shown in the figure. Figures 9A-9E As shown in the figure, the side wall 201 and bottom surface 202 of each groove of the first groove group 2, the second groove group 4 and the connecting groove part 3 have a protrusion at the intersection of the side wall 201 and bottom surface 202, i.e. the insulating layer 100 is inwardly recessed towards the substrate 1 at the intersection, as shown in the figure.

[0123] Step 4: forming the first contact plug 90 and the second contact plug 91, including: forming the first contact plug 90 and the second contact plug 91 on the exposed area of the lower electrode 71 by the dielectric layer 81, and forming the first contact plug 90 and the second contact plug 91 on the surface of the upper electrode 72, such as Figures 9A-9E schematically.

[0124] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present disclosure.

[0125] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The first trench group is located within the substrate; At least two of the first trench groups are arranged along the second direction; The first trench group includes a first trench; The connecting trench section connects to the first trench located on the third side and adjacent upwards; The second direction forms an angle with the third direction.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A second trench group is located within the substrate, and a plurality of second trench groups are arranged along a first direction; The second trench group and the first trench group are arranged in an array, and in the first direction, the two second trench groups are separated by the first trench group. The first direction, the second direction, and the third direction are located in the same plane. The first direction and the third direction are perpendicular. The second direction intersects the first direction and the third direction. The angle between the second direction and the third direction is an acute angle.

3. The semiconductor structure according to claim 2, characterized in that, The first trench extends along a third direction, and the second trench group includes a second trench that extends along a first direction.

4. The semiconductor structure according to claim 1, characterized in that, include: The number of first trenches in each first trench group is N, and the connecting trench portion includes connecting trenches, the number of which is greater than or equal to N / 2.

5. The semiconductor structure according to claim 4, characterized in that, The connecting trench extends along a third direction, and the connecting trench and the first trench that is adjacent to the connecting trench above and below along the third direction are collinearly aligned.

6. The semiconductor structure according to claim 2, characterized in that, The ratio of the number of the first trench group to the number of the second trench group is close to 1.

7. The semiconductor structure according to claim 2, characterized in that, Along a third direction, the second trench group includes a side surface located at its edge, and the first trench group includes a plurality of end faces located at the ends of the first trench; the side surface and the end faces are flush with each other along a first direction.

8. The semiconductor structure according to claim 2, characterized in that, Along a third direction, there is a first gap between two adjacent second groove groups; along a first direction, there is a second gap between adjacent second groove groups and the first groove group; the size of the first gap is larger than the size of the second gap.

9. The semiconductor structure according to claim 8, characterized in that, It also includes an extended groove portion connected to the first groove group, the extended groove portion including an extended groove extending in a third direction, the extended groove communicating with the first groove and collinearly aligned in the third direction.

10. The semiconductor structure according to claim 3, characterized in that, The first groove has a first width and a second width at its top and bottom, respectively, and the second groove has a third width and a fourth width at its top and bottom, respectively. The first width and the second width are substantially the same, and the third width and the fourth width are substantially the same.

11. The semiconductor structure according to claim 10, characterized in that, The first width and the third width are between 0.2 and 1.6 μm.

12. The semiconductor structure according to claim 2, characterized in that, The first trench has a first depth, and the second trench has a third depth, wherein the first depth is greater than the third depth.

13. A semiconductor device, characterized in that, include: Substrate; A first trench group is located within the substrate; at least two groups of the first trench groups are arranged along a second direction; The first trench group includes a first trench; The connecting trench section connects to the first trench located on the third side and adjacent upwards; A second trench group is located within the substrate, and a plurality of second trench groups are arranged along a first direction; wherein, the second trench groups and the first trench groups are arranged in an array, and two second trench groups are separated by the first trench groups in the first direction; A capacitor stack is stacked on the first trench group, the second trench group and the connecting trench portion, wherein the capacitor stack extends continuously on the sidewalls and bottom surface of the first trench group, the second trench group and the connecting trench portion; The first direction, the second direction, and the third direction are located in the same plane. The first direction and the third direction are perpendicular. The second direction intersects the first direction and the third direction. The angle between the second direction and the third direction is an acute angle.

14. The semiconductor device according to claim 13, characterized in that, The capacitor stack has a protrusion at the intersection of the sidewall and the bottom surface.

15. The semiconductor device according to claim 13, characterized in that, It also includes first contact plugs, the capacitor stack includes an upper electrode and a lower electrode, and a plurality of first contact plugs are located in the edge region of the substrate, the edge region having only one of the upper electrode or the lower electrode.

16. The semiconductor device according to claim 13, characterized in that, It also includes a second contact plug, wherein, along a third direction, there is a first gap between two adjacent second groove groups; along a third direction, there is a third gap between adjacent first groove groups and second groove groups; the second contact plug is located on the first gap and the third gap.

17. A method for forming a semiconductor device, characterized in that, include: Provide substrate; A first trench group, a second trench group, and a connecting trench portion are formed within the substrate; A capacitor stack is formed on the first trench group, the second trench group and the connecting trench portion, wherein the capacitor stack extends continuously on the sidewalls and bottom surface of the first trench group, the second trench group and the connecting trench portion.

18. The method for forming a semiconductor device according to claim 17, characterized in that, When forming the first trench group, the second trench group, and the connecting trench portion in the substrate, a virtual trench is also formed at the outer edge of the substrate.

19. The method for forming a semiconductor device according to claim 17, characterized in that, At the intersection of the sidewall and the bottom surface, the capacitor stack forms a protrusion.

20. The method for forming a semiconductor device according to claim 17, characterized in that, The process of forming a capacitor stack also includes forming an upper electrode, a dielectric layer, and a lower electrode. The lower electrode extends continuously to cover the surface of the substrate, while the upper electrode and the dielectric layer extend discontinuously to cover the surface of the substrate.

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