Semiconductor structure and manufacturing method thereof
By introducing a copper germanium layer between the substrate via and the barrier layer, the contamination problem caused by component diffusion in the substrate via is solved, achieving a more effective protection effect.
Patent Information
- Application Number
- CN202510219048.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-20
- Filing Date
- 2025-02-26
- Publication Date
- 2025-11-21
AI Technical Summary
In the substrate perforation process, the barrier layer at the top corner of the deep hole is thin, which causes the substrate perforation components to diffuse and cause contamination.
A copper germanium layer is introduced between the substrate via and the barrier layer. Near the corner of the via, a copper layer is formed to connect to the second side of the copper germanium layer to prevent component diffusion.
It effectively prevents contamination caused by the diffusion of components through substrate perforations, and enhances the protective effect of the barrier layer.
Smart Images
Figure CN120998902A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor structure and a method of manufacturing the same, and more particularly to a semiconductor structure including a through-substrate via (TSV) and a method of manufacturing the same. BACKGROUND
[0002] In a process of forming a through-substrate via, a hole is first formed in a substrate, and then a dielectric liner, a barrier layer and a through-substrate via are formed in the hole. The dielectric liner is between the through-substrate via and the substrate. The barrier layer is between the through-substrate via and the dielectric liner. Since the hole for accommodating the through-substrate via is deep, in order to increase the thickness of the barrier layer at the bottom of the hole, alternating current (AC) power is increased to increase the hole-filling capability of the barrier layer. In this way, the thickness of the barrier layer formed at the top corner of the hole is thin, so the composition of the through-substrate via easily diffuses through the barrier layer at the top corner of the hole, causing contamination. SUMMARY
[0003] The present application provides a semiconductor structure and a method of manufacturing the same, which can prevent contamination caused by diffusion of the composition of a through-substrate via.
[0004] The present application provides a semiconductor structure including a substrate, a dielectric liner, a through-substrate via, a barrier layer, a copper germanide (Cu3Ge) layer and a copper layer. The substrate includes a first surface and a second surface opposite to each other. The substrate has a hole therein. The dielectric liner is on a sidewall of the hole. The through-substrate via is in the hole. The dielectric liner is between the through-substrate via and the substrate. The barrier layer is between the through-substrate via and the dielectric liner. The copper germanide layer is between the through-substrate via and the barrier layer. The copper germanide layer is adjacent to the first surface and adjacent to a corner of the hole. The copper layer is between the through-substrate via and the barrier layer. The copper layer is connected to the copper germanide layer and adjacent to the second surface.
[0005] The present application provides a method of manufacturing a semiconductor structure, which can include the following steps. A substrate is provided. The substrate includes a first surface and a second surface opposite to each other. A hole is formed in the substrate. A dielectric liner is formed on a sidewall of the hole. A through-substrate via is formed in the hole. The dielectric liner is between the through-substrate via and the substrate. A barrier layer is formed between the through-substrate via and the dielectric liner. A copper germanide layer is formed between the through-substrate via and the barrier layer. The copper germanide layer is adjacent to the first surface and adjacent to a corner of the hole. A first copper layer is formed between the through-substrate via and the barrier layer. The first copper layer is connected to the copper germanide layer and adjacent to the second surface.
[0006] In order to make the above features and advantages of the present application more apparent, the following detailed description of the preferred embodiments will be made with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figures 1A-1J This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0008] Explanation of icon numbers:
[0009] 10: Semiconductor Structure
[0010] 100: Substrate
[0011] 102: Dielectric layer
[0012] 104: Dielectric backing material layer
[0013] 104a: Dielectric sheath
[0014] 106: Barrier Material Layer
[0015] 106a: Barrier layer
[0016] 108, 116: Copper material layers
[0017] 116a: Copper layer
[0018] 110: Fill layer
[0019] 112: Copper germanide layer
[0020] 114: Copper oxide layer
[0021] 118: Substrate perforation material layer
[0022] 118a: Substrate via
[0023] C1: Corner
[0024] HP1: Hydrogen plasma treatment
[0025] IP1: Ion implantation process
[0026] OP1: Oxygen Plasma Process
[0027] P1: Part 1
[0028] P2: Part Two
[0029] S1: First Page
[0030] S2: Second side
[0031] SW1: Sidewall
[0032] T1: Hole Detailed Implementation
[0033] Reference will now be made in detail to the exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0034] Figures 1A-1J A cross-sectional view of a manufacturing process of a semiconductor structure according to some embodiments of the application.
[0035] Referring to Figure 1A , a substrate 100 is provided. The substrate 100 includes a first side S1 and a second side S2 opposite to each other. In one embodiment, the first side S1 can be a front side of the substrate 100, and the second side S2 can be a back side of the substrate 100. In one embodiment, the substrate 100 can be a semiconductor substrate, such as a silicon substrate. Further, although not shown in the figures, there can be desired features (e.g., semiconductor devices, dielectric layers, and / or interconnect structures) on and / or in the substrate 100, the description of which is omitted herein.
[0036] Next, a dielectric layer 102 can be formed on the first side S1. In one embodiment, the material of the dielectric layer 102 is, for example, silicon nitride. In one embodiment, the method of forming the dielectric layer 102 is, for example, chemical vapor deposition.
[0037] Referring to Figure 1B , a hole T1 is formed in the substrate 100. The hole T1 can pass through the dielectric layer 102. In one embodiment, the hole T1 can be a deep hole. In one embodiment, the hole T1 can be formed by patterning the dielectric layer 102 and the substrate 100 through a lithography process and an etching process.
[0038] Referring to Figure 1C , a dielectric liner layer 104 can be conformally formed in the hole T1. In one embodiment, the dielectric liner layer 104 can also be formed on the dielectric layer 102. In one embodiment, the material of the dielectric liner layer 104 is, for example, silicon oxide. In one embodiment, the method of forming the dielectric liner layer 104 includes atomic layer deposition.
[0039] Next, a barrier material layer 106 can be conformally formed on the dielectric liner layer 104. The barrier material layer 106 can be a single layer structure or a multi-layer structure. In one embodiment, the material of the barrier material layer 106 is, for example, tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In one embodiment, the method of forming the barrier material layer 106 is, for example, physical vapor deposition or chemical vapor deposition.
[0040] Then, a copper material layer 108 may be conformally formed in the aperture T1. In one embodiment, the copper material layer 108 may be conformally formed on the barrier material layer 106. In one embodiment, the material of the copper material layer 108 is, for example, copper. In one embodiment, the copper material layer 108 may be formed by, for example, physical vapor deposition or chemical vapor deposition.
[0041] Please refer to Figure 1D A filling layer 110 can be formed in the hole T1. The filling layer 110 can cover the first portion P1 of the copper material layer 108 in the hole T1 and expose the second portion P2 of the copper material layer 108 in the hole T1. The second portion P2 of the copper material layer 108 can be located above the first portion P1 of the copper material layer 108. In one embodiment, the material of the filling layer 110 is, for example, spin-on carbon (SOC). In one embodiment, the filling layer 110 is formed by, for example, spin coating.
[0042] Please refer to Figure 1E An ion implantation process IP1 can be performed on the second portion P2 of the copper material layer 108 to form a copper germanide layer 112. The copper germanide layer 112 can be used as a barrier layer. In one embodiment, the germanium content in the copper germanide layer 112 can be from 0.1 atomic percent (at.%) to 50 atomic percent. In another embodiment, the germanium content in the copper germanide layer 112 can be from 15 atomic percent to 35 atomic percent. In one embodiment, the dopant used in the ion implantation process IP1 may include germanium.
[0043] Please refer to Figure 1F The filler layer 110 can be removed using the oxygen plasma process OP1. The first portion P1 of the copper material layer 108 is oxidized into a copper oxide layer (CuO2) 114 in the oxygen plasma process OP1.
[0044] Please refer to Figure 1G The copper oxide layer 114 can be reduced using hydrogen plasma treatment HP1 to form a copper material layer 116. The copper material layer 116 can be used as a seed layer. Furthermore, hydrogen plasma treatment HP1 can be used to remove residues left by the oxygen plasma process OP1. In one embodiment, the material of the copper material layer 116 is, for example, copper.
[0045] Please refer to Figure 1H A substrate through-hole material layer 118 can be formed on the substrate 100. The substrate through-hole material layer 118 can fill the holes T1. In one embodiment, the material of the substrate through-hole material layer 118 may include copper. In one embodiment, the substrate through-hole material layer 118 is formed by, for example, electrochemical plating (ECP).
[0046] Please refer to Figure 1I The substrate through-hole material layer 118 located outside the hole T1 can be removed to form a substrate through-hole 118a. Thus, a substrate through-hole 118a filling the hole T1 can be formed. The substrate through-hole 118a is located on the copper material layer 116 and the copper germanide layer 112. In one embodiment, the material of the substrate through-hole 118a is, for example, copper. In one embodiment, the method for removing the substrate through-hole material layer 118 located outside the hole T1 is, for example, chemical mechanical polishing. For example, the dielectric layer 102 can be used as a polishing termination layer to remove part of the substrate through-hole material layer 118, part of the copper germanide layer 112, part of the barrier material layer 106, and part of the dielectric substrate material layer 104 to form the substrate through-hole 118a.
[0047] Please refer to Figure 1J A thinning process can be performed on the second surface S2 of the substrate 100 to remove a portion of the substrate 100, a portion of the dielectric substrate layer 104, a portion of the barrier material layer 106, and a portion of the copper material layer 116, thereby forming a dielectric substrate 104a, a barrier layer 106a, and a copper layer 116a, and exposing a substrate via 118a. Thus, a dielectric substrate 104a can be formed on the sidewall SW1 of the via T1, a substrate via 118a can be formed in the via T1, a barrier layer 106a can be formed between the substrate via 118a and the dielectric substrate 104a, a copper germanate layer 112 can be formed between the substrate via 118a and the barrier layer 106a, and a copper layer 116a can be formed between the substrate via 118a and the barrier layer 106a. The via T1 can penetrate the substrate 100. The substrate via 118a can penetrate the substrate 100. In one embodiment, the material of the dielectric substrate 104a is, for example, silicon oxide. In one embodiment, the material of the barrier layer 106a is, for example, tantalum, tantalum nitride, or a combination thereof.
[0048] The following is through Figure 1J The semiconductor structure 10 in the above embodiments will be explained here. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.
[0049] Please refer to Figure 1J, the semiconductor structure 10 includes a substrate 100, a dielectric liner 104a, a substrate via 118a, a barrier layer 106a, a germanium copper layer 112, and a copper layer 116a. The substrate 100 includes a first surface S1 and a second surface S2 opposite to each other. The substrate 100 has a hole T1 therein. The dielectric liner 104a is located on a sidewall SW1 of the hole T1. The substrate via 118a is located in the hole T1. The dielectric liner 104a is located between the substrate via 118a and the substrate 100. The barrier layer 106a is located between the substrate via 118a and the dielectric liner 104a. The germanium copper layer 112 is located between the substrate via 118a and the barrier layer 106a. The germanium copper layer 112 is adjacent to the first surface S1 and adjacent to a corner C1 of the hole T1. The copper layer 116a is located between the substrate via 118a and the barrier layer 106a. The copper layer 116a is connected to the germanium copper layer 112 and adjacent to the second surface S2. In an embodiment, the semiconductor structure 10 can further include a dielectric layer 102. The dielectric layer 102 is located on the first surface S1. The hole T1 can pass through the dielectric layer 102.
[0050] Furthermore, the details of each component in the semiconductor structure 10 (e.g., materials and forming methods, etc.) have been described in the above embodiments, and will not be described here.
[0051] Based on the above embodiments, in the semiconductor structure 10 and the manufacturing method thereof, the germanium copper layer 112 is located between the substrate via 118a and the barrier layer 106a, and the germanium copper layer 112 is adjacent to the first surface S1 and adjacent to the corner C1 of the hole T1. Since the germanium copper layer 112 can block the diffusion of the components of the substrate via 118a, even if the barrier layer 106a adjacent to the top corner (e.g., the corner C1) of the hole T1 is thinned, the pollution caused by the diffusion of the components of the substrate via 118a can be prevented.
[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit it. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements to some or all of the technical features. Such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor structure, comprising: a substrate including a first side and a second side opposite to each other, wherein the substrate has a hole therein; a dielectric liner on a sidewall of the hole; a substrate via in the hole, wherein the dielectric liner is between the substrate via and the substrate; a barrier layer between the substrate via and the dielectric liner; a germanium copper layer between the substrate via and the barrier layer, wherein the germanium copper layer is adjacent to the first side and adjacent to a corner of the hole; and a copper layer between the substrate via and the barrier layer, wherein the copper layer is connected to the germanium copper layer and adjacent to the second side.
2. The semiconductor structure of claim 1, wherein a germanium content in the germanium copper layer is 0.1 atomic percent to 50 atomic percent.
3. The semiconductor structure of claim 1, wherein a germanium content in the germanium copper layer is 15 atomic percent to 35 atomic percent.
4. The semiconductor structure of claim 1, wherein the hole penetrates through the substrate.
5. The semiconductor structure of claim 1, wherein a material of the dielectric liner includes silicon oxide.
6. The semiconductor structure of claim 1, wherein the substrate via penetrates through the substrate.
7. The semiconductor structure of claim 1, wherein a material of the substrate via includes copper.
8. The semiconductor structure of claim 1, wherein a material of the barrier layer includes tantalum, tantalum nitride, or a combination thereof.
9. The semiconductor structure of claim 1, further comprising: a dielectric layer on the first side, wherein the hole penetrates through the dielectric layer.
10. The semiconductor structure of claim 9, wherein a material of the dielectric layer includes silicon nitride.
11. A method of fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate includes a first side and a second side opposite to each other; forming a hole in the substrate; forming a dielectric liner on a sidewall of the hole; forming a substrate via in the hole, wherein the dielectric liner is between the substrate via and the substrate; forming a barrier layer between the substrate via and the dielectric liner; forming a germanium copper layer between the substrate via and the barrier layer, wherein the germanium copper layer is adjacent to the first side and adjacent to a corner of the hole; and forming a first copper layer between the substrate via and the barrier layer, wherein the first copper layer is connected to the germanium copper layer and adjacent to the second side.
12. The method of fabricating a semiconductor structure of claim 11, wherein the forming of the germanium copper layer and the first copper layer includes: forming a first copper material layer conformally in the hole; forming a fill layer in the hole, wherein the fill layer covers a first portion of the first copper material layer and exposes a second portion of the first copper material layer; performing an ion implantation process on the second portion of the first copper material layer to form the germanium copper layer; removing the fill layer using an oxygen plasma process, wherein the first portion of the first copper material layer is oxidized to a copper oxide layer in the oxygen plasma process; reducing the copper oxide layer using a hydrogen plasma process to form a second copper material layer; forming a substrate via that fills the hole, wherein the substrate via is located on the second copper material layer and the copper germanide layer; and performing a thinning process on the second side of the substrate to remove portions of the substrate and portions of the second copper material layer to form the first copper layer and expose the substrate via.
13. The method of claim 12, wherein the method of forming the first copper material layer comprises a physical vapor deposition or a chemical vapor deposition.
14. The method of claim 12, wherein the material of the fill layer comprises spin-on carbon.
15. The method of claim 12, wherein the dopant used in the ion implantation process comprises germanium.
16. The method of claim 11, wherein the method of forming the dielectric liner and the barrier layer comprises: forming a layer of dielectric liner material conformally in the hole; forming a layer of barrier material conformally on the layer of dielectric liner material; and performing a thinning process on the second side of the substrate to remove portions of the substrate, portions of the layer of dielectric liner material, and portions of the layer of barrier material to form the dielectric liner and the barrier layer.
17. The method of claim 16, wherein the method of forming the layer of barrier material comprises a physical vapor deposition or a chemical vapor deposition.
18. The method of claim 11, wherein the method of forming the substrate via comprises: forming a layer of substrate via material on the substrate, wherein the layer of substrate via material fills the hole; and removing the layer of substrate via material located outside of the hole to form the substrate via.
19. The method of claim 18, wherein the method of removing the layer of substrate via material located outside of the hole comprises a chemical mechanical polishing.
20. The method of claim 11, further comprising: forming a dielectric layer on the first side, wherein the hole passes through the dielectric layer.