Ultra-wideband multilayer vertical interconnection structure applied to SiP packaging

By employing glass via technology and an optimized multilayer vertical interconnect structure, the problems of high TSV process cost and high electrical loss are solved, achieving low-loss and high-efficiency RF front-end integration, which is suitable for ultra-wideband system-in-package.

CN120998911APending Publication Date: 2025-11-21THE 54TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
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Patent Information

Application Number
CN202511063369.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-31
Publication Date
2025-11-21

AI Technical Summary

Technical Problem

The TSV process is expensive due to its small wafer size and complex manufacturing process, and silicon substrates have significant electrical losses in RF front-end applications, making it difficult to meet the requirements of high-density integration.

Method used

Using through-glass via (TGV) technology, an ultra-wideband multilayer vertical interconnect structure suitable for SiP packaging is designed. Combining cavity structure, high and low impedance line structure and coaxial structure, the parameters are optimized to reduce insertion loss and improve return loss.

Benefits of technology

It achieves high-density integration with low loss and low cost, is suitable for DC-30GHz system-in-package, reduces insertion loss by 0.14dB, and improves return loss by 20dB.

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Abstract

The invention belongs to the technical field of radio frequency front ends, and particularly relates to an ultra-wideband multilayer vertical interconnection structure applied to SiP packaging. According to the structure, a novel TGV technology is utilized, a cavity is embedded below an interlayer cpwg, and meanwhile, a high-low impedance line structure is inserted, so that insertion loss is reduced, and return loss is improved. The structure is simulated and optimized by using HFSS software. An excellent result is obtained through simulation, the insertion loss is smaller than-0.16 dB in the full frequency band from 0.1 GHz to 30 GHz, the return loss is lower than-30 dB, and the return loss is about-40 dB in the full frequency band from 2 GHz to 24 GHz. Meanwhile, the impedance of the two ports is 50 ohms, and the antenna can be well matched with various radio frequency devices. The test result shows that the coplanar waveguide-quasi-coaxial-interlayer coplanar waveguide structure has excellent transmission performance in a broadband, and can be applied to more and more three-dimensional connection designs of sip system-in-package.
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Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of radio frequency front end, and particularly relates to an ultra-wideband multilayer vertical interconnection structure applied to SiP system level packaging. BACKGROUND

[0002] The main challenges of the TSV technology are high cost due to small wafer size and complex manufacturing process, and significant electrical loss related to silicon. The semiconductor and semi-insulating properties of silicon make it difficult to use silicon substrates in increasingly demanding radio frequency front end applications. To solve these problems, Georgia Institute of Technology proposes and proves the use of glass as a dielectric layer instead of a silicon dielectric layer, which has ultra-low loss, silicon-matched coefficient of thermal expansion (CTE), smooth surface, large panel processability and excellent dimensional stability. Electrically, glass is different from silicon because glass is essentially an insulating material, while silicon is a semiconductor material.

[0003] To adapt to the miniaturized system level packaging (SiP) technology, the application designs a vertical interconnection structure suitable for high-density integration, which adopts the emerging glass via (TGV) technology. Compared with the TSV technology, the TGV process flow is simpler, and there is no need to deposit an insulating layer on the surface of the substrate and the inner wall of the TGV; glass has excellent electrical resistance, heat resistance and chemical resistance, has high transparency and surface smoothness, and has been used in many consumer and industrial products. Its coefficient of thermal expansion is similar to that of a silicon wafer, and its electrical properties are better than those of a silicon wafer. Glass is lower in cost than silicon, has better mechanical stability and lower warpage, so it has higher productivity and yield. Glass has high insulation performance, low loss factor and low dielectric loss, and its dielectric constant is only about 1 / 3 of that of silicon material. This greatly reduces the substrate loss and parasitic effects, and has lower loss at the same line width, and is easier to miniaturize. SUMMARY

[0004] Therefore, the application is applied to the three-dimensional connection design of SiP system level packaging, supported by the TGV technology, and cavity structures, high-low impedance line structures and coaxial structures are added, and parameters are optimized and internal impedance matching is adjusted to reduce insertion loss and improve return loss.

[0005] To achieve the above purpose, the technical scheme adopted by the application is as follows:

[0006] The ultra-wideband multilayer vertical interconnection structure applied to SiP packaging comprises six layers of glass substrates which are sequentially stacked from top to bottom; the upper surface of each glass substrate is provided with a metal layer;

[0007] The center of the metal layer on the upper surface of the first to fifth glass substrates is etched with a circular hollow; on the upper surface of the first glass substrate, a first circular patch and a first rectangular patch are further provided; the metal layer is etched with a first rectangular gap, which extends from the circular hollow to the outer edge; the first circular patch and the first rectangular patch are located in the region where the circular hollow and the first rectangular gap are connected;

[0008] On the upper surface of the fourth glass substrate, a second rectangular patch and a third rectangular patch structure are further provided; the metal layer is etched with a second rectangular gap, the width of the second rectangular gap is the same as the diameter of the circular hollow, and the second rectangular gap extends from the circular hollow to the outer edge; the extension direction of the second rectangular gap is perpendicular to the extension direction of the first rectangular gap; the second rectangular patch and the third rectangular patch are located in the region where the circular hollow and the second rectangular gap are connected;

[0009] The outer side of the region where the circular hollow and the first rectangular gap of the metal layer of the first glass substrate are connected is provided with a plurality of first shielding columns, the first shielding columns penetrate the first glass substrate and the second glass substrate, and the two ends of the first shielding columns are respectively connected to the metal layer on the upper surface of the first glass substrate and the metal layer on the upper surface of the third glass substrate;

[0010] The outer side of the circular hollow of the metal layer of the fourth glass substrate is provided with a plurality of second shielding columns, and the outer side of the second rectangular gap is provided with a third shielding column, wherein the second shielding columns penetrate the third glass substrate, and the two ends of the second shielding columns are respectively connected to the metal layer of the third glass substrate and the metal layer of the fourth glass substrate, and the third shielding column penetrates the fourth glass substrate, and the two ends of the third shielding column are respectively connected to the metal layer of the fourth glass substrate and the metal layer of the fifth glass substrate;

[0011] The second circular patch and the third circular patch are respectively arranged at the circular hollow of the second glass substrate and the circular hollow of the third glass substrate; a central metal column penetrates and connects the first circular patch, the second circular patch, the third circular patch, and the second rectangular patch, and is connected to the metal layer of the fifth glass substrate.

[0012] Further, the first circular patch coincides with the center of the circular hollow; the first rectangular patch is connected to the first circular patch, and extends from the circular patch along the first rectangular gap to the outer edge.

[0013] Further, the inner end of the second rectangular patch is semicircular, the other end is connected to the third rectangular patch, and the width of the second rectangular patch is greater than the width of the third rectangular patch; the semicircular shape of the inner end of the second rectangular patch is concentric with the circular hollow, and the third rectangular patch extends along the second rectangular gap to the outer edge.

[0014] Further, the central metal column is concentric with the circular hollow.

[0015] Further, the first shielding column is provided with 17 columns, of which 9 columns are located on the circular hollow outer side, 6 columns are located on the first rectangular gap outer side, and two columns are shared by the circular hollow and the first rectangular gap.

[0016] Further, the second shielding column is provided with 7 columns, and the third shielding column is provided with 10 columns.

[0017] Further, the lower surface of the sixth glass substrate is provided with a metal floor.

[0018] Further, the fourth glass substrate is provided with a cylindrical air cavity, the height of the cylindrical air cavity is the same as the height of the fourth glass substrate, and the cylindrical air cavity is coaxial with the central metal column.

[0019] The beneficial effects produced by the above-mentioned optimization technical scheme are:

[0020] 1. The application designs an ultra-wideband cpwg-to-cpwg three-dimensional vertical interconnection coaxial structure, which can be used for DC-30GHz system-level packaging (SiP) applications.

[0021] 2. The application supports TGV technology, adds cavity structure, high-low impedance line structure, coaxial structure, optimizes parameters, adjusts internal impedance matching, reduces insertion loss, and improves return loss. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is the total view of the model.

[0023] Figure 2 is the front view of the model.

[0024] Figure 3 is the top view of the top structure.

[0025] Figure 4 is the top view of the interlayer structure.

[0026] Figure 5 is the sectional view of the model.

[0027] Figure 6 is the equivalent circuit model diagram.

[0028] Figure 7 is the comparison diagram before and after the insertion loss optimization.

[0029] Figure 8 is the comparison diagram before and after the return loss optimization.

[0030] In the figure: 1, the first layer of glass substrate, 2, the second layer of glass substrate, 3, the third layer of glass substrate, 4, the fourth layer of glass substrate, 5, the fifth layer of glass substrate, 6, the sixth layer of glass substrate, 1.1, the first metal layer, 2.1, the second metal layer, 3.1, the third metal layer, 4.1, the fourth metal layer, 5.1, the fifth metal layer, 6.1, the sixth metal layer, 1.2, the first circular patch, 1.3, the first rectangular patch, 4.2, the second rectangular patch, 4.3, the third rectangular patch. 11, the first shielding column, 12, the second shielding column, 13, the center metal column, 14, the third shielding column, 15, the air cavity. DETAILED DESCRIPTION

[0031] The application will be further described in detail below with reference to the accompanying drawings.

[0032] Reference Figures 1 to 8 Ultra-wideband multilayer vertical interconnection structure applied to SiP package,

[0033] Ultra-wideband multilayer vertical interconnection structure applied to SiP package, comprising 6 layers of glass substrates stacked from top to bottom; the upper surface of each layer of glass substrate is provided with a metal layer;

[0034] The center of the metal layer on the upper surface of the first to fifth layers of glass substrates is etched with a circular hollow; on the upper surface of the first layer of glass substrate, a first circular patch and a first rectangular patch are further provided; the metal layer is etched with a first rectangular gap, and the first rectangular gap extends from the circular hollow to the outer edge; the first circular patch and the first rectangular patch are located in the region where the circular hollow and the first rectangular gap are connected;

[0035] On the upper surface of the fourth layer of glass substrate, a second rectangular patch and a third rectangular patch structure are further provided; the metal layer is etched with a second rectangular gap, and the width of the second rectangular gap is the same as the diameter of the circular hollow, and the second rectangular gap extends from the circular hollow to the outer edge; the extension direction of the second rectangular gap is perpendicular to the extension direction of the first rectangular gap; the second rectangular patch and the third rectangular patch are located in the region where the circular hollow and the second rectangular gap are connected;

[0036] A plurality of first shielding columns are provided on the outer side of the region where the circular hollow and the first rectangular gap of the metal layer of the first layer of glass substrate are connected, the first shielding columns penetrate the first layer of glass substrate and the second layer of glass substrate, and the two ends of the first shielding columns are connected to the metal layer on the upper surface of the first layer of glass substrate and the metal layer on the upper surface of the third layer of glass substrate, respectively;

[0037] The outer side of the circular hollow of the fourth layer of glass substrate metal layer is provided with a plurality of second shielding columns, and the outer side of the second rectangular gap is provided with third shielding columns, wherein the second shielding columns penetrate through the third layer of glass substrate, and the two ends thereof are connected with the metal layer of the third layer of glass substrate and the metal layer of the fourth layer of glass substrate respectively, and the third shielding columns penetrate through the fourth layer of glass substrate, and the two ends thereof are connected with the metal layer of the fourth layer of glass substrate and the metal layer of the fifth layer of glass substrate respectively.

[0038] The circular hollow of the second layer of glass substrate and the circular hollow of the third layer of glass substrate are respectively provided with second circular patches and third circular patches; and the central metal column penetrates through and connects the first circular patch, the second circular patch, the third circular patch and the second rectangular patch, and is connected with the metal layer of the fifth layer of glass substrate.

[0039] Further, the first circular patch is coincident with the center of the circular hollow; the first rectangular patch is connected with the first circular patch, and extends from the circular patch along the first rectangular gap to the outer edge.

[0040] Further, the inner end of the second rectangular patch is semicircular, and the other end is connected with the third rectangular patch, and the width of the second rectangular patch is greater than that of the third rectangular patch; the semicircular shape of the inner end of the second rectangular patch is concentric with the circular hollow thereof, and the third rectangular patch extends along the second rectangular gap to the outer edge.

[0041] Further, the central metal column is concentric with the circular hollow.

[0042] Further, the first shielding column is provided with 17 columns, of which 9 columns are located on the outer side of the circular hollow, 6 columns are located on the outer side of the first rectangular gap, and two columns are shared by the circular hollow and the first rectangular gap.

[0043] Further, the second shielding column is provided with 7 columns, and the third shielding column is provided with 10 columns.

[0044] Further, the lower surface of the sixth layer of glass substrate is provided with a metal floor.

[0045] Further, the fourth layer of glass substrate is internally provided with a cylindrical air cavity, the height of the cylindrical air cavity is the same as that of the fourth layer of glass substrate, and the cylindrical air cavity is coaxial with the central metal column.

[0046] The following is a specific description of the principles:

[0047] Reference Figure 1The center of the metal layer on the upper surface of the first to fifth glass substrates is etched with a circular hollow, and a circular patch is arranged at the metal hollow, a center metal column penetrates through the circular patch to form a signal through hole, 12 ground shielding columns are designed around the signal through hole to simulate a coaxial structure. To prevent the signal line from being connected to the shielding column to cause short circuit, the shielding columns of this layer are appropriately reduced; for example, in this embodiment, there are 11 shielding columns in the first glass substrate and 7 shielding columns in the fourth glass substrate. The capacitance effect between the signal column (center metal column) and the shielding column is used to increase ΔC, and these shielding columns can also prevent signal radiation and avoid parasitic mode excitation due to the approximate structure size and wavelength at a high frequency.

[0048] When the signal through hole passes through the metal layer, the matching pad (circular patch) and the ground reverse pad (circular hollow) structure are increased to shorten the distance to the ground and enhance the reflow current at this position. When the reflow currents of the two structures are equal, the transition performance of the multilayer circuit signal reaches the best;

[0049] By changing the spacing dx between the shielding column and the signal column (center metal column), the signal pad (circular patch) radius, and the reverse pad radius (circular hollow), the characteristic impedance of the vertical through hole structure is adjusted to match the front and rear impedances, reduce the insertion loss and return loss of the overall line. When simulating and optimizing, attention should be paid to the matching problem of the coaxial structure of the metal layer and the dielectric layer. The characteristic impedance of the coaxial structure of the metal layer is determined by the matching pad (circular patch) radius rp and the reverse pad radius (circular hollow) rp0. Adjust dr until the impedances of the two vertical structures match, and the transition performance reaches the best. The spacing dx between the shielding column and the signal column (center metal column) mainly determines the impedance of the dielectric layer coaxial structure and can reduce signal radiation. The difference between the matching pad (circular patch) and the reverse pad radius (circular hollow) should be appropriately reduced, and the spacing dx between the shielding column and the signal column should be as small as possible to optimize the return loss. After comprehensive optimization, rp = 180 um, rp0 = 325 um, and dx = 430 um.

[0050] The interlayer CPWG structure is adopted, and there are equidistant large-area grounds above and below the signal line, and the glass substrate AF32 is filled as the dielectric in the middle, that is, the glass substrate AF32 is arranged between the rectangular patch and the metal layer on the upper surface of the first glass substrate. The signal line is in a G-S-G structure, and the distance between the ground and the signal is w. This CPWG cross-section structure is surrounded by ground on four sides, and the structure is more similar to a coaxial line, and the impedance transition of the coaxial structure is smoother; the 50-ohm impedance parameters of this structure are simulated in HFSS. Finally, the line width and the spacing of the interlayer CPWG are obtained, which corresponds to the top view of the interlayer structure, the line width dw_btw = 280 um, and the spacing between the two ground planes dw_btw_gap = 630 um.

[0051] Because the vertical interconnection structure will have a strong capacitive effect on the directly below, an air cavity is added below the connection between the coaxial-like structure and the interlayer CPWG, that is, the height of the cavity is the same as the height of the fourth glass substrate, and the cavity is coaxial with the central metal column.

[0052] The air cavity structure added below the vertical interconnection structure can effectively reduce the strong capacitive effect, but changes the interlayer CPWG structure and affects the impedance continuity before and after. To prevent the return loss from deteriorating, a high-low impedance line structure is added at this position, and the width of this section of line is appropriately increased to compensate for the decrease in parasitic capacitance caused by the removal of the lower metal.

[0053] Because the vertical interconnection structure needs to be connected to the interlayer CPWG on one side, the number of shielding columns at this position is 6, which is quite different from the number of shielding columns in the other two layers, which will cause impedance mismatch and deteriorate the return loss. Therefore, in addition to adjusting the high-low impedance line width, the third and fourth interlayer shielding column spacing is also appropriately reduced to compensate for the decrease in parasitic capacitance caused by the reduction in shielding columns, so that the impedance before and after this section is matched.

[0054] After applying all the new structures, the proposed structure is simulated and optimized in the frequency range of 100 MHz to 30 GHz using HFSS simulation software.

[0055] The optimized vertical interconnection structure has an insertion loss S21 of less than -0.16 dB at 30 GHz, which is 0.14 dB better than the original structure. The return loss S11 is less than -32 dB at 30 GHz, and is about -40 dB from 2 GHz to 24 GHz, which is an average improvement of 20 dB compared to the original structure.

Claims

1. An ultra-wideband multilayer vertical interconnect structure for SiP packaging, characterized by, The glass substrate includes six layers stacked from top to bottom; each layer of glass substrate is provided with a metal layer on the upper surface; The center of the metal layer on the upper surface of the first to fifth layer of glass substrate is etched with a circular hollow; the first circular patch and the first rectangular patch are arranged on the upper surface of the first layer of glass substrate; the metal layer is etched with a first rectangular gap, which extends from the circular hollow to the outer edge; the first circular patch and the first rectangular patch are located in the region where the circular hollow and the first rectangular gap are connected; The second rectangular patch and the third rectangular patch structure are arranged on the upper surface of the fourth layer of glass substrate; the metal layer is etched with a second rectangular gap, the width of the second rectangular gap is the same as the diameter of the circular hollow, and the second rectangular gap extends from the circular hollow to the outer edge; the extension direction of the second rectangular gap is perpendicular to the extension direction of the first rectangular gap; the second rectangular patch and the third rectangular patch are located in the region where the circular hollow and the second rectangular gap are connected; The outer side of the region where the circular hollow and the first rectangular gap of the metal layer of the first layer of glass substrate are connected is provided with a plurality of first shielding columns, the first shielding columns penetrate the first layer of glass substrate and the second layer of glass substrate, and the two ends of the first shielding columns are respectively connected with the metal layer on the upper surface of the first layer of glass substrate and the metal layer on the upper surface of the third layer of glass substrate; The outer side of the circular hollow of the metal layer of the fourth layer of glass substrate is provided with a plurality of second shielding columns, and the outer side of the second rectangular gap is provided with a third shielding column, wherein the second shielding column penetrates the third layer of glass substrate, and the two ends of the second shielding column are respectively connected with the metal layer of the third layer of glass substrate and the metal layer of the fourth layer of glass substrate; the third shielding column penetrates the fourth layer of glass substrate, and the two ends of the third shielding column are respectively connected with the metal layer of the fourth layer of glass substrate and the metal layer of the fifth layer of glass substrate; The circular hollow of the second layer of glass substrate and the circular hollow of the third layer of glass substrate are respectively provided with a second circular patch and a third circular patch; a central metal column penetrates and connects the first circular patch, the second circular patch, the third circular patch and the second rectangular patch, and is connected with the metal layer of the fifth layer of glass substrate.

2. The ultra-wideband multilayer vertical interconnect structure for SiP package of claim 1, wherein, The center of the first circular patch coincides with the center of the circular hollow; the first rectangular patch is connected with the first circular patch, and extends from the circular patch along the first rectangular gap to the outer edge.

3. The ultra-wideband multilayer vertical interconnect structure for SiP packaging of claim 1, wherein, The inner end of the second rectangular patch is semicircular, the other end is connected with the third rectangular patch, and the width of the second rectangular patch is greater than the width of the third rectangular patch; the semicircle of the inner end of the second rectangular patch is concentric with the circular hollow, and the third rectangular patch extends along the second rectangular gap to the outer edge.

4. The ultra-wideband multilayer vertical interconnect structure for SiP package of claim 1, wherein, The central metal column is concentric with the circular hollow.

5. The ultra-wideband multilayer vertical interconnect structure for SiP packaging of claim 1, wherein, The first shielding column is provided with 17 columns, of which 9 columns are located on the outer side of the circular hollow, 6 columns are located on the outer side of the first rectangular gap, and two columns are shared by the circular hollow and the first rectangular gap.

6. The ultra-wideband multilayer vertical interconnect structure for SiP packaging of claim 1, wherein, The second shielding column is provided with 7 columns, and the third shielding column is provided with 10 columns.

7. The ultra-wideband multilayer vertical interconnect structure for SiP packaging of claim 1, wherein, The lower surface of the sixth layer of glass substrate is provided with a metal floor.

8. The ultra-wideband multilayer vertical interconnect structure for SiP packaging of claim 1, wherein, The fourth layer of glass substrate is provided with a cylindrical air cavity, the height of the cylindrical air cavity is the same as the height of the fourth layer of glass substrate, and the cylindrical air cavity is coaxial with the central metal column.