Semiconductor packaging structure and semiconductor structure

Abstract

The invention relates to the technical field of semiconductor technologies, in particular to a semiconductor packaging structure and a semiconductor structure. The semiconductor packaging structure at least comprises a flange layer and a ceramic substrate layer which are stacked in sequence, wherein a first metallization layer is formed on a contact interface of the flange layer and the ceramic substrate layer; the surface of the ceramic substrate layer is used for connecting a chip to be packaged, and a second metallization layer is formed on a contact interface between the chip to be packaged and the ceramic substrate layer; the second metallization layer comprises a source electrode, a drain electrode and a grid electrode which are mutually independent; and isolation regions are arranged among the source electrode, the drain electrode and the grid electrode. The semiconductor packaging structure is excellent in heat conduction performance, resistant to high pressure and high temperature, small in thermal stress, wide in application range, long in service life, lower in cost and higher in reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor process technology, and more specifically, to a semiconductor packaging structure and a semiconductor structure. Background Technology

[0002] Packaging is one of the most important processes in high-power semiconductor device manufacturing, and the quality of the packaging process directly affects the product yield. Traditional device packaging mainly includes two types: metal packaging and plastic packaging.

[0003] Metal packaging is widely used due to the high thermal conductivity of metal materials, such as copper, which can quickly conduct heat from the chip. However, metal packaging has significant drawbacks. On the one hand, metal materials are expensive, with special alloys being particularly costly, significantly increasing packaging costs. On the other hand, metal processing is difficult, requiring high-precision equipment and complex processes, reducing production efficiency and further increasing costs. Furthermore, while metal packaging offers heat dissipation advantages, the mismatch between the thermal expansion coefficient and the chip can easily lead to thermal stress, affecting chip reliability. In the chip bonding process, voids in the bonding layer severely impact heat conduction, increasing thermal resistance. Existing heat dissipation structures are poorly designed, with single heat dissipation paths and high contact thermal resistance, making it difficult to meet the heat dissipation requirements of high-power chips. Plastic packaging materials are low-cost and mainly used in some cost-sensitive low-to-mid-range products, but plastic's heat dissipation performance is far inferior to metals and ceramics. Its low thermal conductivity prevents rapid heat transfer from the chip, resulting in poor heat dissipation and excessively high chip operating temperatures, affecting performance and lifespan. Moreover, plastic has poor hermeticity, making it difficult to isolate external moisture, dust, and other contaminants, unsuitable for high-power devices operating in harsh environments.

[0004] Traditional hollow-shell packages, when used for special circuit packaging such as half-bridge packages, cannot achieve electrical isolation and proper circuit connections due to structural limitations. Existing packages also suffer from low internal space utilization, hindering the effective integration of multiple components and failing to meet the miniaturization and integration trends in electronic products. Furthermore, the high dielectric loss of molding compounds can impair the efficient release of RF performance in radio frequency and microwave bands. Therefore, a semiconductor packaging method that balances cost and performance is urgently needed. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a semiconductor packaging structure and a semiconductor structure.

[0006] A first aspect of the embodiments of this application provides a semiconductor package structure, comprising at least:

[0007] A flange layer and a ceramic substrate layer are stacked sequentially; wherein: the contact interface between the flange layer and the ceramic substrate layer forms a first metallization layer;

[0008] The surface of the ceramic substrate layer is used to connect the chip to be packaged, and the contact interface between the chip to be packaged and the ceramic substrate layer forms a second metallization layer.

[0009] The second metallization layer includes an independent source, drain, and gate; an isolation region is provided between the source, the drain, and the gate.

[0010] In one optional embodiment of this application, the drain and the gate extend to the outer edges of both sides of the ceramic substrate layer and protrude.

[0011] In one optional embodiment of this application, the drain and the gate are made of Kovar alloy; and / or, the drain and the gate are brazed to the surface of a ceramic substrate layer.

[0012] In one optional embodiment of this application, the second metallization layer includes at least: a first metallization region for connecting the metal to be encapsulated and the remaining second metallization region; the material of the first metallization region is aluminum nitride; and / or, the material of the second metallization region is aluminum oxide.

[0013] In one optional embodiment of this application, the chip to be packaged is bonded to the first metallization region by a sintering silver process.

[0014] In one optional embodiment of this application, the material of the first metallized region is aluminum nitride;

[0015] The first metallized region is a co-fired metallized region, and the co-fired material is a tungsten-nickel alloy.

[0016] In one optional embodiment of this application, the thickness of the first metallized region is no greater than 0.6 mm.

[0017] In one optional embodiment of this application, the thickness of the tungsten metal layer in the tungsten-nickel alloy is 15-25 μm; the thickness of the nickel metal layer in the tungsten-nickel alloy is not less than 2.5 μm.

[0018] In an optional embodiment of this application, the above-described semiconductor packaging structure further includes:

[0019] A ceramic cover plate having a cavity is disposed on the surface of the second metallization layer, and the chip to be packaged is packaged in the cavity.

[0020] In one optional embodiment of this application, the ceramic cover plate is bonded to the surface of the second metallization layer by a semi-solid adhesive.

[0021] In an optional embodiment of this application, the above-described semiconductor packaging structure further includes:

[0022] A lead frame is disposed on the surface of the second metal layer, and the lead frame is electrically connected to the chip to be packaged, as well as the source and gate, through leads.

[0023] In one optional embodiment of this application, the lead frame is made of Kovar alloy.

[0024] A second aspect of this application provides a semiconductor structure comprising at least:

[0025] Semiconductor packaging structures as described in any of the preceding items;

[0026] A chip to be packaged, wherein the chip to be packaged is disposed on the surface of the second metallization layer of the semiconductor package structure.

[0027] The semiconductor packaging structure provided in this application embodiment comprises a flange layer and a ceramic substrate layer stacked sequentially. A first metallization layer is formed at the contact interface between the flange layer and the ceramic substrate layer. A second metallization layer is formed at the contact interface between the chip to be packaged and the ceramic substrate layer. The second metallization layer includes an independent source, drain, and gate electrode. An isolation region is provided between the source, drain, and gate electrode. Firstly, the ceramic substrate layer has excellent thermal conductivity (up to 200 W / mK), far exceeding that of organic substrates, etc. Secondly, the ceramic substrate layer has high resistivity (>10). 14 The ceramic substrate layer (Ω·cm) can withstand high voltage, preventing device leakage. Thirdly, the ceramic substrate layer is close to the chip material (such as Si or GaAs), which greatly reduces failures caused by thermal stress. Fourthly, the ceramic substrate layer can withstand temperatures above 500℃ (organic substrates are typically <200℃), making it suitable for high-temperature processes (such as eutectic bonding). Fifthly, the ceramic substrate layer is corrosion-resistant, oxidation-resistant, and has a long lifespan, significantly improving the device's lifespan. Sixthly, it eliminates the high material costs and complex processes required for metal packaging, thereby reducing production costs. Furthermore, to ensure better connection between the ceramic substrate and flange layer and the chip to be packaged, a first metallization layer and a second metallization layer are respectively provided on both sides of the ceramic substrate layer, thereby achieving normal circuit conduction and ensuring stable electrical performance of the device. In summary, this application provides a semiconductor packaging structure with excellent thermal conductivity, high voltage and high temperature resistance, low thermal stress, wide applicability, long lifespan, lower cost, and higher reliability. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this application;

[0030] Figure 2 This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this application;

[0031] Figure 3 This is a schematic diagram of the semiconductor packaging structure provided in an embodiment of this application.

[0032] in:

[0033] 10. Semiconductor packaging structure; 100. Flange layer; 200. Ceramic substrate layer; 300. First metallization layer; 400. Second metallization layer; 410. Source; 420. Drain; 430. Gate; 500. Ceramic cover plate; 20. Chip to be packaged. Detailed Implementation

[0034] In the process of developing this application, the applicant discovered that there is an urgent need for a semiconductor packaging method that combines cost and performance.

[0035] To address the aforementioned problems, this application provides a semiconductor packaging structure and a semiconductor structure. To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, through embodiments and in conjunction with the accompanying drawings, provides a semiconductor packaging structure and a semiconductor structure of this application. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0036] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). It should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used solely for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0037] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0038] Please see Figure 1 This application provides a semiconductor package structure 10, which includes at least:

[0039] A flange layer 100 and a ceramic substrate layer 200 are stacked sequentially; wherein: the contact interface between the flange layer 100 and the ceramic substrate layer 200 forms a first metallization layer 300.

[0040] The surface of the ceramic substrate layer 200 is used to connect the chip to be packaged 20, and the contact interface between the chip to be packaged 20 and the ceramic substrate layer 200 forms a second metallization layer 400.

[0041] The second metallization layer 400 includes an independent source 410, a drain 420, and a gate 430; an isolation region is provided between the source 410, the drain 420, and the gate 430.

[0042] In this embodiment, the flange layer 100 refers to a metal base or frame in the semiconductor packaging structure 10 used for mechanical support, heat dissipation, or electrical connection. It provides a stable mounting platform for chip packaging. Simultaneously, during the operation of power devices, a large amount of heat is generated, and the flange layer 100, as part of a heat sink, conducts heat to an external heat sink or PCB, providing a heat dissipation path. It also provides grounding and shielding functions for RF chips, reducing signal interference. The flange layer 100 in this embodiment can be made of metals such as copper and aluminum, or alloys, and can be formed through stamping / etching, electroplating, welding / bonding, etc.

[0043] The ceramic substrate layer 200 in this embodiment can be made of alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), silicon nitride (Si3N4), LTCC / HTCC (low-temperature / high-temperature co-fired ceramic), etc. This embodiment does not impose specific limitations and can be flexibly selected according to actual conditions. The ceramic substrate layer 200 has excellent thermal conductivity, insulation, mechanical strength, and thermal stability, which can greatly improve the device performance of the semiconductor packaging structure 10.

[0044] The chip 20 to be packaged in this embodiment can be a power device or a radio frequency device. This embodiment does not impose specific limitations and can be flexibly set according to the actual situation.

[0045] This embodiment includes at least two metallization layers: a first metallization layer 300 and a second metallization layer 400. The first metallization layer 300 is formed at the contact interface between the flange layer 100 and the ceramic substrate layer 200, serving to connect the flange layer 100 and the ceramic substrate layer 200; otherwise, the ceramic and flange cannot be welded. The material of the first metallization layer 300 can be a tungsten-nickel alloy, and the thickness of the first metallization layer 300 can be approximately 0.15 mm. The second metallization layer 400 is formed at the contact interface between the chip to be packaged 20 and the ceramic substrate layer 200, serving to connect the chip to be packaged 20 and the ceramic substrate layer 200. Similarly, the ceramic and chip cannot be welded together. The material of the second metallization layer 400 can also be a tungsten-nickel alloy, and the thickness of the second metallization layer 400 can be approximately 0.15 mm.

[0046] The material of the isolation region can be ceramic or insulating, and this application embodiment does not impose a specific limitation, but can be flexibly adjusted according to the actual situation. The lateral width of the isolation region can be greater than 0.5 mm, and the longitudinal depth of the isolation region can be the same as the height of the source 410, the drain 420 and the gate 430, so as to achieve better isolation.

[0047] The semiconductor packaging structure 10 provided in this application embodiment includes a flange layer 100 and a ceramic substrate layer 200 stacked sequentially. A first metallization layer 300 is formed at the contact interface between the flange layer 100 and the ceramic substrate layer 200. A second metallization layer 400 is formed at the contact interface between the chip to be packaged 20 and the ceramic substrate layer 200. The second metallization layer 400 includes an independent source 410, a drain 420, and a gate 430. An isolation region is provided between the source 410, the drain 420, and the gate 430. Firstly, the ceramic substrate layer 200 has excellent thermal conductivity (up to 200 W / mK), far exceeding that of organic substrates, etc. Secondly, the ceramic substrate layer 200 has high resistivity (>10). 14The ceramic substrate layer 200 has excellent thermal conductivity (Ω·cm), can withstand high voltage, and avoids device leakage. Thirdly, the ceramic substrate layer 200 is close to the chip material (such as Si or GaAs), which can greatly reduce failures caused by thermal stress. Fourthly, the ceramic substrate layer 200 can withstand temperatures above 500℃ (organic substrates are usually <200℃), making it suitable for high-temperature processes (such as eutectic bonding). Fifthly, the ceramic substrate layer 200 is corrosion-resistant, oxidation-resistant, and has a long lifespan, which can greatly improve the lifespan of the device. Sixthly, it eliminates the high material costs and complex processes required for metal packaging, thereby reducing production costs. Furthermore, in order to better connect the ceramic substrate and flange layer 100 with the chip 20 to be packaged, a first metallization layer 300 and a second metallization layer 400 are respectively provided on both sides of the ceramic substrate layer 200, thereby achieving normal circuit conduction and ensuring stable electrical performance of the device. In summary, this application provides a semiconductor packaging structure 10 with excellent thermal conductivity, high voltage and high temperature resistance, low thermal stress, wide applicability, long lifespan, lower cost, and higher reliability.

[0048] Please continue reading Figure 1 and Figure 2 In one optional embodiment of this application, the lateral width of the second metallization layer 400 is greater than the lateral width of the ceramic substrate layer 200. The lateral width of the second metallization layer 400 refers to the width including the source 410, drain 420, and gate 430, as well as the width of all isolation regions, and does not refer to the width of the exposed second metallization layer 400 or its cumulative width. The drain 420 and the gate 430 extend to the outer edges of both sides of the ceramic substrate layer 200 and protrude, that is, extend to the outside of the cavity of the ceramic cover plate 500. The source 410 is connected to the flange through the first metallization layer 300 and the second metallization layer 400 on both sides of the ceramic substrate layer 200, and the drain 420 and the gate 430 are obtained by fins extending from both sides of the second metallization layer 400. The shape of the fin can be any shape such as rectangular or circular. The drain 420 and the gate 430 are distributed on both sides of the second metallization layer 400 through the fin. In an optional embodiment, side arm metallization layers (not shown in the figure) are also distributed on both sides of the second metallization layer 400, that is, the two fins and the two side arm metallization layers are distributed at a 90° interval on the outer periphery of the source 410.

[0049] In one optional embodiment of this application, the drain 420 and the gate 430 are made of Kovar alloy;

[0050] Kovar is a nickel-cobalt-iron alloy, with a composition such as 29% Ni, 17% Co, and 54% Fe. Its coefficient of thermal expansion is 4.5–5.5 × 10⁻⁶ / ℃ (20–400℃), which is perfectly matched with glass (such as borosilicates) and ceramics (Al₂O₃, AlN), significantly reducing thermal stress cracking. Its thermal conductivity of 17–18 W / m·K balances heat dissipation and thermal expansion. Its mechanical strength includes a tensile strength ≥ 517 MPa and a yield strength ≥ 345 MPa, providing structural support and making it suitable for high-reliability packaging.

[0051] The source electrode 410 is itself part of the second metallization layer 400. After the fins and flange layer 100 are completed, before connecting the chip to be packaged 20 and the ceramic cover plate 500, the entire structure can be electroplated to achieve preliminary overall packaging. The plating structure can be Ni / NiCo / Au, with Au purity >99.9%; plating thickness: 2.5um≤Ni+NiCo≤11.0um, Ni≥0.5um, NiCo≥2um (Co: 20%-40%wt); Au: ≥0.50um.

[0052] In one optional embodiment of this application, the drain 420 and the gate 430 are brazed to the surface of the ceramic substrate layer 200.

[0053] Brazing is a process that joins materials by melting a filler metal (brazing filler metal). The filler metal has a lower melting point than the substrate and fills the gap between the joints through capillary action, forming a high-strength, highly airtight permanent connection. Brazing can be performed in medium-high temperature environments (450℃~1200℃), offering excellent airtightness and preventing the substrate from easily melting. Therefore, in this embodiment, the drain 420 and the gate 430 are brazed onto the surface of the ceramic substrate layer 200 to reduce process conditions and manufacturing costs.

[0054] In one optional embodiment of this application, the second metallization layer 400 includes at least: a first metallization region for connecting the metal to be encapsulated and the remaining second metallization region; the material of the first metallization region is aluminum nitride; and / or, the material of the second metallization region is aluminum oxide.

[0055] Alumina is low in cost and has a mature manufacturing process. While its thermal conductivity is moderate (20–30 W / mK), its relatively low cost makes it the preferred material for the second metallization region to reduce the overall cost of the packaging structure. Aluminum nitride has excellent thermal conductivity (150–200 W / mK) and its coefficient of thermal expansion matches that of silicon, significantly reducing thermal stress in the device. Its metallization void ratio is approximately 5%. Therefore, aluminum nitride is chosen as the first metallization region at the chip bonding location to improve the overall performance of the chip 20 to be packaged. This results in a structure where aluminum oxide forms the sidewalls and aluminum nitride forms the bonding carrier region for the chip 20 to be packaged. The second metallization region on the side is connected to the bottom flange layer 100 for grounding.

[0056] In one optional embodiment of this application, the chip to be packaged 20 is bonded to the first metallization region by a sintering silver process.

[0057] Sintered silver is a bonding technology that uses high temperature or pressure to drive the solid-phase diffusion of silver particles (nano / micron scale) to form a dense structure. It has advantages such as high thermal conductivity, high melting point, and low thermal resistance, and can achieve sintering at a lower stability level to avoid damaging the performance of the chip to be packaged 20.

[0058] In one optional embodiment of this application, the first metallized region is a co-fired metallized region, and the co-fired material is a tungsten-nickel alloy.

[0059] In one optional embodiment of this application, the thickness of the first metallized region is no greater than 0.6 mm.

[0060] In one optional embodiment of this application, the thickness of the tungsten metal layer in the tungsten-nickel alloy is 15-25 μm; the thickness of the nickel metal layer in the tungsten-nickel alloy is not less than 2.5 μm.

[0061] If the metallization region is too thin, it is easy to generate voids, which will affect the conductivity of the device. However, if the metallization region is too thick, it will affect the heat dissipation system. Therefore, in the embodiments of this application, the thickness of the first metallization region is no more than 0.6 mm, so as to balance heat dissipation and conductivity, thereby providing a semiconductor packaging structure 10 with better overall performance.

[0062] Please continue reading Figure 1 In an optional embodiment of this application, the above-mentioned semiconductor packaging structure 10 further includes: a ceramic cover plate 500, wherein:

[0063] The ceramic cover plate 500 has a cavity disposed on the surface of the second metallization layer 400, and the chip to be packaged 20 is packaged in the cavity.

[0064] In one optional embodiment of this application, the ceramic cover plate 500 is bonded to the surface of the second metallization layer 400 by a semi-solid adhesive.

[0065] Semi-solid adhesives, such as B-stage adhesives, and ceramic cover plates, such as ACC ceramics (Aluminum Carbon Composite Ceramic, an aluminum-carbon composite ceramic material, is made by combining aluminum (Al) with carbon-based materials (such as graphite and carbon fiber), combining the advantages of metal thermal conductivity and toughness with ceramic high temperature resistance and low expansion characteristics) as sealing materials, have good adhesion and airtightness, enabling the cavity to reach a quasi-airtight level, thereby improving the overall sealing and encapsulation effect.

[0066] Please see Figure 2 and Figure 3 In an optional embodiment of this application, the semiconductor package structure 10 further includes a lead frame. Wherein:

[0067] The lead frame is disposed on the surface of the second metal layer, and the lead frame is electrically connected to the chip to be packaged 20, the source 410, and the gate 430 via leads. The lead frame can be any shape, such as rectangular, and is not limited in this embodiment. The drain 420 is connected through the bottom flange layer 100 and the side arm metallization layers located on both sides of the second metallization layer 400. The chip to be packaged 20 is connected to the bottom first metallization layer 300 via a sintered silver patch, and the drain 420 is led out from the upper side fin. The source 410 is wired to the second metallization layer 400 connected to the surface of the ceramic substrate layer 200 and connected to the bottom flange layer 100 via the side arm metallization layers. The gate 430 is wired to the lower fin.

[0068] In one optional embodiment of this application, the lead frame is made of Kovar alloy, such as 4J42 Kovar alloy, which has good conductivity and mechanical strength, thereby improving the electrical conductivity of the device.

[0069] To further illustrate the packaging effect of the semiconductor packaging structure 10 provided in this application, the following embodiments provide parameter comparison data between this application and conventional packaging:

[0070]

[0071] Therefore, it can be seen that the semiconductor packaging structure 10 provided in this application embodiment has a packaging effect that is far superior to traditional packaging.

[0072] One embodiment of this application provides a semiconductor structure, comprising at least:

[0073] Semiconductor packaging structure 10 as described in any of the preceding items;

[0074] The chip to be packaged 20 is disposed on the surface of the second metallization layer 400 of the semiconductor packaging structure 10.

[0075] The beneficial effects of the semiconductor packaging structure 10 have been described in detail in the above embodiments and will not be repeated here. In summary, the embodiments of this application provide a semiconductor structure with excellent thermal conductivity, high pressure and high temperature resistance, low thermal stress, wide applicability, long service life, lower cost, and higher reliability.

[0076] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that, At least including: A flange layer and a ceramic substrate layer are stacked sequentially; wherein: the contact interface between the flange layer and the ceramic substrate layer forms a first metallization layer; The surface of the ceramic substrate layer is used to connect the chip to be packaged, and the contact interface between the chip to be packaged and the ceramic substrate layer forms a second metallization layer. The second metallization layer includes an independent source, drain, and gate; an isolation region is provided between the source, the drain, and the gate.

2. The semiconductor packaging structure according to claim 1, characterized in that, The drain and the gate extend to the outer edges of both sides of the ceramic substrate layer and protrude.

3. The semiconductor packaging structure according to claim 1, characterized in that, The drain and the gate are made of Kovar alloy; and / or, the drain and the gate are brazed to the surface of a ceramic substrate layer.

4. The semiconductor packaging structure according to claim 1, characterized in that, The second metallization layer includes at least: a first metallization region for connecting the metal to be encapsulated and the remaining second metallization region; the material of the first metallization region is aluminum nitride; and / or, the material of the second metallization region is aluminum oxide.

5. The semiconductor packaging structure according to claim 4, characterized in that, The chip to be packaged is bonded to the first metallized region using a sintering silver process.

6. The semiconductor packaging structure according to claim 4, characterized in that, The material of the first metallized region is aluminum nitride; The first metallized region is a co-fired metallized region, and the co-fired material is a tungsten-nickel alloy.

7. The semiconductor packaging structure according to claim 4, characterized in that, The thickness of the first metallized region is no greater than 0.6 mm.

8. The semiconductor packaging structure according to claim 4, characterized in that, The thickness of the tungsten metal layer in the tungsten-nickel alloy is 15-25 μm; the thickness of the nickel metal layer in the tungsten-nickel alloy is not less than 2.5 μm.

9. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A ceramic cover plate having a cavity is disposed on the surface of the second metallization layer, and the chip to be packaged is packaged in the cavity.

10. The semiconductor packaging structure according to claim 9, characterized in that, The ceramic cover plate is bonded to the surface of the second metallized layer using semi-solid adhesive.

11. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A lead frame is disposed on the surface of the second metal layer, and the lead frame is electrically connected to the chip to be packaged, as well as the source and gate, through leads.

12. The semiconductor packaging structure according to claim 11, characterized in that, The lead frame is made of Kovar alloy.

13. A semiconductor structure, characterized in that, At least including: The semiconductor packaging structure as described in any one of claims 1-12; A chip to be packaged, wherein the chip to be packaged is disposed on the surface of the second metallization layer of the semiconductor package structure.

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