Test element set and use method thereof
By designing test element groups containing probe pads and contact areas on the wafer scribe line and using through-hole connections, the problem of probe pads extending beyond the scribe line is solved. This enables efficient layout of test element groups on the reduced scribe line, saving photomask and scribe line space and supporting denser semiconductor element layout.
Patent Information
- Application Number
- CN202411255174.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-20
- Filing Date
- 2024-09-09
- Publication Date
- 2025-11-21
AI Technical Summary
Existing technologies struggle to provide test element groups on reduced scribe lines, especially since the probe pads for dual-row test element groups cannot be reduced, causing probe pads in metal-oxide-semiconductor field-effect transistors to extend beyond the scribe line area and contact the wafer.
The test component group design includes first, second, and third probe pads and upper and lower rows of contact areas. By retaining the layout of double rows of contact areas and single rows of probe pads, the probe pads are connected by through holes, thereby reducing the number of probe pads. Through holes are formed by photomask to detect the upper and lower wafers.
It enables efficient placement of test component groups on reduced scribe lines, saving photomask and scribe line space, ensuring that probe pads do not exceed the scribe line area, and supporting denser semiconductor component placement.
Smart Images
Figure CN120998914A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a test element group and a method of using the same. BACKGROUND
[0002] Integrated circuit wafers have been widely used in today's electronic products. As technology advances, the width and spacing of metal wiring layers providing equal potential contact in the integrated circuit are becoming smaller and smaller to allow the wafers to have more dense semiconductor elements. In order to provide more wafers on a wafer, one of the methods is to reduce the scribe lane. However, the test element group needs to occupy a certain position of the scribe lane, and it is difficult to reduce the size of the scribe lane.
[0003] Therefore, how to provide a test element group on a reduced scribe lane is necessary to be improved in the prior art. SUMMARY
[0004] An embodiment of the present invention provides a test element group on a scribe lane of a wafer, the test element group comprising: a first probe pad, at least one second probe pad, at least one third probe pad, at least one upper row of contact regions, and at least one lower row of contact regions. The first probe pad, the at least one second probe pad, and the at least one third probe pad are sequentially arranged. The at least one upper row of contact regions is between the at least one second probe pad and the at least one third probe pad. The at least one lower row of contact regions is between the at least one second probe pad and the at least one third probe pad relative to the at least one upper row of contact regions. Wherein when the at least one upper row of contact regions is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the at least one lower row of contact regions is insulated from the first probe pad, the at least one second probe pad, and the at least one third probe pad; or wherein when the at least one lower row of contact regions is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the at least one upper row of contact regions is insulated from the first probe pad, the at least one second probe pad, and the at least one third probe pad.
[0005] In some embodiments, the at least one upper row of contact regions comprises three of the plurality of vias corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
[0006] In some embodiments, when the at least one upper row of contact regions is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the three of the plurality of vias are electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
[0007] In some embodiments, the at least one lower row of contact regions comprises three of the plurality of vias corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
[0008] In some embodiments, when the at least one upper contact region is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, three of the plurality of through holes are respectively electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad.
[0009] In some embodiments, the number of the at least one second probe pad is two second probe pads; the number of the at least one third probe pad is two third probe pads; each of the two second probe pads is sequentially staggered with each of the two third probe pads.
[0010] In some embodiments, the number of the at least one upper contact region is three upper contact regions; and the number of the at least one lower contact region is three lower contact regions; wherein each of the three upper contact regions is located between an adjacent one of the two second probe pads and an adjacent one of the two third probe pads, and each of the three lower contact regions is located between an adjacent one of the two second probe pads and an adjacent one of the two third probe pads.
[0011] In some embodiments, the first probe pad is a gate probe pad, the at least one second probe pad is at least one drain probe pad, and the at least one third probe pad is at least one source probe pad.
[0012] In some embodiments, the width of the test element group is less than or equal to the width of the scribe lane, which is 50 micrometers to 60 micrometers.
[0013] In some embodiments, the test element group further comprises a substrate, a plurality of metal layers, a top layer, and a plurality of through holes. The plurality of metal layers is above the substrate. The top layer is above the plurality of metal layers, and the top layer comprises a first probe pad, at least one second probe pad, and at least one third probe pad. The plurality of through holes is connected to at least one of the plurality of metal layers. Wherein the at least one upper contact region comprises three of the plurality of through holes corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
[0014] In some embodiments, the at least one lower contact region comprises three of the plurality of through holes corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
[0015] In some embodiments, the plurality of metal layers comprises an active layer and a gate electrode layer above the active layer; wherein the wafer further comprises an insulating layer disposed between the active layer and the gate electrode layer.
[0016] Another embodiment of the present application provides a method of testing a wafer using a test element group, comprising: providing a test element group as previously described; providing a first mask to form three of the plurality of vias in at least one upper row of contact areas, and the three of the plurality of vias are electrically connected to a first probe pad, at least one second probe pad, and at least one third probe pad, respectively; and detecting an upper wafer by contacting the three of the plurality of vias in at least one upper row of contact areas, the first probe pad, the at least one second probe pad, and the at least one third probe pad with a detection device.
[0017] In some embodiments, the method of testing a wafer using a test element group further comprises providing a second mask to enclose the three of the plurality of vias in at least one upper row of contact areas, and form three of the plurality of vias in at least one lower row of contact areas, and the three of the plurality of vias in at least one lower row of contact areas are electrically connected to a first probe pad, at least one second probe pad, and at least one third probe pad, respectively; and detecting a lower wafer by contacting the three of the plurality of vias in at least one lower row of contact areas, the first probe pad, the at least one second probe pad, and the at least one third probe pad with a detection device.
[0018] In some embodiments, the first probe pad is a gate probe pad, the at least one second probe pad is at least one drain probe pad, and the at least one third probe pad is at least one source probe pad. BRIEF DESCRIPTION OF DRAWINGS
[0019] Various aspects of the application will become more apparent by a consideration of the detailed description and drawings. It is noted that the various features might not be drawn to scale in the attached drawings. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. So that the above and other objects, features, and advantages of the present application can be clearly understood, the following description should be read with reference to the accompanying drawings wherein:
[0020] Figure 1 A top view of a wafer containing a test element group illustrating some embodiments of the present application.
[0021] Figure 2 A top view of a wafer containing a test element group illustrating some embodiments of the present application. Figure 1 A magnified view of the M region of
[0022] Figure 3 A magnified view of the M region of Figure 2 A magnified view of the M region of
[0023] Figure 4 A schematic diagram illustrating testing of an upper wafer by electrically connecting upper row contact areas of some embodiments of the present application.
[0024] Figure 5 A schematic diagram illustrating testing of an upper wafer by electrically connecting upper row contact areas of some embodiments of the present application. Figure 4Cross-sectional view of line AA'.
[0025] Figure 6 Schematic diagram of testing the underlying wafer by electrically connecting the underlying contact region. DETAILED DESCRIPTION
[0026] In order to make the description of the present application more complete and perfect, the following describes the illustrative description for the implementation state and specific examples of the present application, but this is not the only form of implementation or use of the specific examples of the present application. The embodiments disclosed below can be combined with each other or replaced in a beneficial case, and other embodiments can be added in an embodiment without further description or illustration. In the following description, many specific details will be described in detail to enable the reader to fully understand the following embodiments. However, the embodiments of the present application can also be practiced without such specific details.
[0027] In addition, spatial relative terms, such as "lower", "upper", and the like, can be used for ease of description to describe one element or feature's relative positioning as to other elements or features with respect to the figures. These spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0028] In this document, unless the context clearly requires otherwise, "a", "an", and "the" can be used generically to refer to one or more, and each of these terms is used in the sense of "one or more" unless otherwise stated. It will be further understood that the use of the terms "includes", "including", "has", "having", "comprises" and / or "comprising", or the like, in this document, means "including one or more of the features, elements, integers, steps, operations, elements, and / or components so described and / or one or more such items so described, and that the singular encompasses the plural or vice versa, unless otherwise stated.
[0029] Further, when a number or a numerical range is described as "about", "approximately", and the like, the term is intended to encompass numbers that are within a reasonable range given the nature of the characteristics associated with the number, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number, the number or numerical range encompasses a reasonable range including the described number, such as within + / - 10% of the described number. Further, the present application can refer to numbers and / or letters repeatedly in various instances. This repetition is for simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.
[0030] The reduction of scribe line width is generally to divide more dies on a wafer in future technology nodes. That is, another meaning of continuing Moore's Law of "increasing gross die". However, when the scribe line width shrinks, it will affect the size of objects on the scribe line, such as cut marks, test element groups (TEGs) or test keys, film thickness measurements, etc. The main challenge is the double-row test element group commonly used in the metal-oxide-semiconductor field-effect transistor (MOSFET) series, because the probe pad cannot be shrunk, and when the scribe line shrinks, the probe pad will exceed the scribe line area and contact the die area.
[0031] The present application keeps the contact area positions of all model MOSFET test element groups as the original double-row contact area and single-row probe pad to reduce the scribe line width. Therefore, the original metal wiring of the double-row test element group is kept, but the contact point falls on the probe pad of the single-row test element group.
[0032] The following lists several embodiments and experimental examples to more fully describe the test element group of the present application and its method of use, which are only for illustrative purposes and are not intended to limit the present application. The protection scope of the present application is defined by the appended claims.
[0033] Please refer to Figure 1 , Figure 1 The wafer containing the test element group of some embodiments of the present application is shown in a top view. The wafer 10 includes a plurality of dies 11 and a plurality of scribe lines 12. The wafer 10 includes semiconductor material, including but not limited to silicon dies, III_V dies, silicon-on-insulator (SOI) dies, silicon-on-sapphire (SOS) dies, and / or another material dies.
[0034] Various circuit devices can be mounted in the plurality of dies 11. For example, resistors, inductors, capacitors, diodes, transistors, etc. can be mounted in the plurality of dies 11. The dies 11 include, but are not limited to, rectangles, such as squares. The dies 11 can extend to each edge of the wafer 10 and can define partial dies. The number of dies 11 can be greater than, equal to, or less than Figure 1 the number shown.
[0035] A scribe line 12 is defined as the area between one wafer 11 and another wafer 11 on wafer 10. A scribe line 12 may be or corresponds to an area that is cut after the processing of wafer 10 is completed to separate multiple wafers 11.
[0036] Please see Figure 1 and Figure 2 , Figure 2 for Figure 1 An enlarged view of region M. The test element group 100 may include a pattern implemented to measure actual characteristics of a semiconductor or wafer. When the test element group 100 is mounted on a scribe line 12, the test element group 100 may be disposed on at least two adjacent wafers 11 on wafer 10. The width W1 of the test element group 100 is less than or equal to the width W2 of the scribe line 12, and the width W2 is 50 micrometers (μm) to 60 micrometers. In some embodiments, the width W2 of the plurality of scribe lines 12 is less than 70 micrometers, less than 60 micrometers, or less than 50 micrometers.
[0037] Please see Figure 3 , Figure 3 for Figure 2 An enlarged view. The test element group 100 includes a first probe pad 110, at least one second probe pad 120, at least one third probe pad 130, at least one upper row contact region 140, and at least one lower row contact region 150. The first probe pad 110, at least one second probe pad 120, and at least one third probe pad 130 are arranged sequentially. In some embodiments, the first probe pad 110 is a gate probe pad, the at least one second probe pad 120 is at least one drain probe pad, and the at least one third probe pad 130 is at least one source probe pad.
[0038] In some embodiments, the number of at least one second probe pad 120 is two; the number of at least one third probe pad 130 is two; each of the two second probe pads 120 and each of the two third probe pads 130 are arranged alternately in sequence. In some embodiments, the number of at least one upper row contact area 140 is three; and the number of at least one lower row contact area 150 is three. Each of the three upper row contact areas 140 is located between an adjacent pair of two second probe pads 120 and an adjacent pair of two third probe pads 130, and each of the three lower row contact areas 150 is located between an adjacent pair of two second probe pads 120 and an adjacent pair of two third probe pads 130.
[0039] Please see Figure 4 , Figure 4To illustrate the testing of the upper wafer through the electrical connection of the upper row of contact regions in some embodiments of the present application. At least one upper row of contact regions 140 is located between at least one second probe pad 120 and at least one third probe pad 130. In some embodiments, at least one upper row of contact regions 140 includes three of the plurality of vias 142 corresponding to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, respectively. In some embodiments, when at least one upper row of contact regions 140 is electrically connected to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, the three vias 142 are electrically connected to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, respectively. In turn, at least one lower row of contact regions 150 is insulated from the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130.
[0040] Referring to Figure 4 and Figure 5 , Figure 5 for Figure 4 a cross-sectional view of line AA'. Figure 5 is an embodiment, the metal traces can be any known traces and are not limited to Figure 5 . The test element group 100 also includes a substrate 210, a plurality of metal layers 220, a top layer 230, and the plurality of vias 142. The plurality of metal layers 220 is above the substrate 210. The top layer 230 is above the plurality of metal layers 220, and the top layer 230 includes the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130. The plurality of vias 142 (or vias 152 as shown in Figure 6 ) connects at least one of the plurality of metal layers 220. In some embodiments, at least one upper row of contact regions 140 includes three of the plurality of vias 142 corresponding to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, respectively. In some embodiments, at least one lower row of contact regions 150 includes three of the plurality of vias 152 corresponding to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, respectively. In some embodiments, the plurality of metal layers 220 includes, but is not limited to, two layers, three layers, four layers, five layers, six layers, or seven layers, and the plurality of vias is connected to which layer directly or indirectly depends on the testing needs.
[0041] In some embodiments, the plurality of metal layers 220 includes an active layer 222 and a gate electrode layer 224 over the active layer 222. The wafer 10 further includes an insulating layer 240 disposed between the active layer 222 and the gate electrode layer 224. In some embodiments, the active layer 222 includes a source 222A and a drain 222B, the at least one second probe pad 120 is electrically connected to the source 222A through one of the plurality of vias 142, and the at least one third probe pad 130 is electrically connected to the drain 222B through another one of the plurality of vias 142.
[0042] Referring to Figure 6 , Figure 6 FIG. 4 illustrates a schematic diagram of testing an underlying wafer through electrically connecting lower row contact regions, according to some embodiments of the present disclosure. At least one lower row contact region 150 is opposite to the at least one upper row contact region 140, and the at least one lower row contact region 150 is located between the at least one second probe pad 120 and the at least one third probe pad 130. In some embodiments, the at least one lower row contact region 150 includes three of the plurality of vias 152 corresponding to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, respectively. In some embodiments, when the at least one lower row contact region 150 is electrically connected to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, the three vias 152 are electrically connected to the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130, respectively. In turn, the at least one upper row contact region 140 is insulated from the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130.
[0043] While the following describes certain operations or steps in a series, the order of the operations or steps is not to be construed as a limitation of the disclosure. For example, certain operations or steps can be performed in different order or concurrently with other steps. In addition, not all illustrated operations, steps, and / or features can be required to implement an embodiment of the present disclosure. Further, each of the operations or steps described herein can include sub-steps or actions.
[0044] Referring back to Figure 4The present invention provides a method of using a test element group 100, comprising: providing the test element group 100 as described above; providing a first photomask to form three of a plurality of vias 142 in at least one upper row contact area 140, wherein the three of the plurality of vias 142 are electrically connected to a first probe pad 110, at least one second probe pad 120, and at least one third probe pad 130, respectively; and using a detection device to detect an upper wafer 11A by contacting the three of the plurality of vias 142 in the at least one upper row contact area 140, the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130. In some embodiments, the detection device includes, but is not limited to, a probe card. The metal traces of the original dual-row test element group are retained, but the contact points fall on the probe pads of a single-row test element group. Therefore, if it is necessary to measure other row contact areas of the test element group, there is no need to tap out all layers of the photomask. Simply change the contact location to other row contact areas of the test element group, since the corresponding metal wiring has been prepared and retained.
[0045] Please see the return Figure 6 The present invention provides a method for using the test element assembly 100, which further includes providing a second photomask to close three through holes 142 (e.g., in an upper row of contact areas 140) in at least one upper row of contact areas 140. Figure 4 As shown), three of the multiple vias 152 are formed in at least one lower row of contact areas 150, and the three vias 152 in the at least one lower row of contact areas 150 are electrically connected to the first probe pad 110, at least one second probe pad 120, and at least one third probe pad 130, respectively; and the detection device detects the underlying wafer 11B by contacting the three vias 152, the first probe pad 110, the at least one second probe pad 120, and the at least one third probe pad 130 in the at least one lower row of contact areas 150. By retaining the double row of contact areas and the double row of metal traces of the test element group, different rows of contact areas can be selected for measurement, which can save a lot of photomask and scribe space, thereby making effective use of the scribe.
[0046] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0047] [Symbol Explanation]
[0048] 10: Wafers
[0049] 11: Chips
[0050] 11A: Upper chip
[0051] 11B: lower wafer
[0052] 12: scribe lane
[0053] 100: test element group
[0054] 110: first probe pad
[0055] 120: second probe pad
[0056] 130: third probe pad
[0057] 140: upper row of contact areas
[0058] 142: via
[0059] 150: lower row of contact areas
[0060] 152: via
[0061] 210: substrate
[0062] 220: metal layer
[0063] 222: active layer
[0064] 222A: source
[0065] 222B: drain
[0066] 224: gate electrode layer
[0067] 230: top layer
[0068] 240: insulating layer
[0069] AA': line
[0070] M: region
[0071] W1, W2: width
Claims
1. A test element group located in a scribe line on a wafer, characterized in that, The test element group includes: First probe pad; At least one second probe pad; At least one third probe pad; the first probe pad, the at least one second probe pad, and the at least one third probe pad are arranged in sequence; At least one upper row of contact areas is located between the at least one second probe pad and the at least one third probe pad; and At least one lower row of contact areas is relative to the at least one upper row of contact areas, and the at least one lower row of contact areas is located between the at least one second probe pad and the at least one third probe pad; Wherein, when the at least one upper row of contact areas is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the at least one lower row of contact areas is insulated from the first probe pad, the at least one second probe pad, and the at least one third probe pad; or Wherein, when the at least one lower row of contact areas is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the at least one upper row of contact areas is insulated from the first probe pad, the at least one second probe pad, and the at least one third probe pad.
2. The test element assembly according to claim 1, wherein the at least one upper row contact area includes three of a plurality of through holes corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
3. The test element assembly according to claim 2, wherein when the at least one upper row of contact areas is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the three of the plurality of through holes are respectively electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad.
4. The test element assembly according to claim 1, wherein the at least one row of contact areas includes three of a plurality of through holes corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
5. The test element assembly according to claim 4, wherein when the at least one row of contact areas is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the three of the plurality of through holes are respectively electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad.
6. The test element assembly according to claim 1, wherein The number of the at least one second probe pad is two second probe pads; The number of the at least one third probe pad is two third probe pads; Each of the two second probe pads and each of the two third probe pads are arranged alternately in sequence.
7. The test element assembly according to claim 6, wherein The number of the at least one upper row contact area is three upper row contact areas; and The number of at least one lower row contact areas is three lower row contact areas; Each of the three upper contact areas is located between an adjacent one of the two second probe pads and an adjacent one of the two third probe pads. Each of the three lower contact areas is located between an adjacent one of the two second probe pads and an adjacent one of the two third probe pads.
8. The test element group according to claim 6, wherein the first probe pad is a gate probe pad, the at least one second probe pad is at least one drain probe pad, and the at least one third probe pad is at least one source probe pad.
9. The test element group according to claim 1, wherein the width of the test element group is less than or equal to the width of the scribe line, which is 50 micrometers to 60 micrometers.
10. The test element assembly according to claim 1, wherein, Also includes: substrate; Multiple metal layers are located above the substrate; The top layer is located above the plurality of metal layers, and the top layer includes the first probe pad, the at least one second probe pad, and the at least one third probe pad; and Multiple through-holes are connected to at least one of the multiple metal layers; The at least one upper row of contact areas includes three of the plurality of through holes that correspond to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
11. The test element assembly of claim 10, wherein the at least one row of contact areas includes three of the plurality of through holes corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively.
12. The test element group of claim 10, wherein the plurality of metal layers includes an active layer and a gate electrode layer above the active layer; The wafer further includes an insulating layer disposed between the active layer and the gate electrode layer.
13. A method for using a test element set, characterized in that, Include: Provide the test element set according to claim 1; A first photomask is provided to form three of a plurality of vias in the at least one upper row of contact areas, and the three of the plurality of vias are respectively electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad; and The testing device detects the upper wafer by contacting the three of the plurality of vias in the at least one upper row of contact areas, the first probe pad, the at least one second probe pad, and the at least one third probe pad.
14. The method according to claim 13, wherein, Also includes: A second photomask is provided to enclose the plurality of vias in the at least one upper row of contact areas, and three of the vias are formed in the at least one lower row of contact areas and electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively; and The detection device detects the underlying wafer by contacting three of the plurality of through holes in the at least one row of contact areas, the first probe pad, the at least one second probe pad, and the at least one third probe pad.
15. The method of claim 13, wherein the first probe pad is a gate probe pad, the at least one second probe pad is at least one drain probe pad, and the at least one third probe pad is at least one source probe pad.