Low-power-consumption active equalization circuit and control method thereof

Abstract

The invention provides a low-power-consumption active equalization circuit and a control method thereof, and belongs to the technical field of battery management. The invention provides a low-power-consumption active equalization circuit and a control method thereof, the low-power-consumption active equalization circuit comprises n battery units, an active equalization circuit, a differential voltage acquisition circuit, a voltage difference comparison circuit, a phase-shift PWM generation circuit and a switching tube driving circuit, the active equalization circuit comprises n phase-shift full-bridge circuits, n single-phase transformers and n current-limiting resistors, a single battery unit is connected to the primary side of a single-phase transformer through a phase-shifted full-bridge circuit, and the secondary side of the transformer is connected in series with a current-limiting resistor to form a single equalization unit. The secondary side of the transformer is connected in parallel with the secondary sides of other equalization unit transformers through current-limiting resistors. According to the invention, energy balance can be carried out on a plurality of battery units connected in series at the same time, and the battery units comprise but are not limited to battery monomers, battery modules and battery clusters. When the voltage difference of any two battery units exceeds a set voltage difference threshold value, the active equalization circuit can quickly perform energy equalization, the equalization topology structure and the driving control method are simple, the active equalization topology based on the phase-shifted full-bridge converter can realize soft switching, the voltage and current change rate when the switch is switched on and switched off is effectively reduced, and the switching efficiency is improved. And the switching loss is reduced, and the method is suitable for balancing among battery modules or clusters in large-scale energy storage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, and discloses a low-power active balancing circuit and a control method thereof. BACKGROUND

[0002] At present, the new energy industry is a key development field in China and all countries in the world. Under this background, the global energy storage market also shows explosive growth. As the main core power source of new energy systems and energy storage systems, lithium ion batteries have become a common energy storage solution due to their high efficiency, high energy density, long cycle life and other advantages. However, due to the small differences in manufacturing processes, the inconsistency of material properties, the uneven temperature distribution, and the changes in the use environment, there are inevitably inconsistencies in capacity, internal resistance, voltage and other aspects among lithium ion battery monomers. Such inconsistencies can lead to problems such as reduced energy utilization rate, overcharging or overdischarging of single batteries during charging and discharging, thereby accelerating the performance degradation of the battery pack, shortening its service life, and even causing serious safety hazards such as battery thermal runaway, deformation or explosion. Therefore, it is necessary to balance the single batteries in the battery pack to effectively reduce the voltage differences among different single batteries in use.

[0003] However, in large-scale energy storage systems, in order to meet the demand for high voltage and high power output, a multi-level architecture of "single module-cluster" is usually adopted. Specifically, multiple single batteries are connected in series to form a module, multiple modules are connected in series to form a battery cluster, and finally multiple battery clusters are connected in parallel to form a complete energy storage system. Although this architecture meets the demand for high voltage and large capacity, it also brings more complex balancing management challenges.

[0004] Existing module or cluster level balancing technologies still face many challenges. On the one hand, the problem of switching loss caused by high power balancing is prominent; on the other hand, the complex balancing topology increases the difficulty of system control. The introduction of soft switching power conversion technology provides a new idea to solve these problems. By using soft switching topologies such as resonant converters, switching loss can be significantly reduced, and balancing efficiency can be improved. Applying soft switching technology to the battery active balancing system is expected to improve balancing efficiency while reducing switching loss, thereby further improving the overall performance of the battery cluster.

[0005] Therefore, it is necessary to further improve the active balancing battery balancing topology to improve balancing speed, simplify control strategy, and adapt to the balancing needs of large-scale battery packs. SUMMARY

[0006] In order to solve the problems existing in the prior art, the present application provides a low-power active balancing circuit and a control method thereof, comprising: n battery units, an active balancing circuit, a differential voltage acquisition circuit, a differential voltage comparison circuit, a phase-shifted PWM generation circuit and a switch tube driving circuit.

[0007] Among them, the battery unit includes, but is not limited to, battery cell, battery pack and battery cluster, and n battery units are connected in series;

[0008] The active balancing circuit includes n phase-shifting full-bridge circuits, n single-phase transformers, and n current-limiting resistors. Each battery cell is connected to the primary side of the single-phase transformer via a phase-shifting full-bridge circuit, and the secondary side of the transformer is connected in series with a current-limiting resistor to form a single balancing unit.

[0009] Among them, a single equalization unit includes battery unit U inn Input capacitor C n5 N-type MOSFET Q n1 N-type MOSFET Q n2 N-type MOSFET Q n3 N-type MOSFET Q n4 Parasitic junction capacitance C n1 Parasitic junction capacitance C n2 Parasitic junction capacitance C n3 Parasitic junction capacitance C n4 Primary-side DC blocking capacitor C n6 Single-phase transformer T n and current-limiting resistor R n ;

[0010] Among them, the four parasitic junction capacitances are connected in parallel across the four N-type MOSFETs, and the switching transistor, the reverse diode, and the junction capacitance are connected in parallel.

[0011] In this context, the number of turns on the primary side of each single-phase transformer is represented by n1, and the number of turns on the secondary side is represented by n2. The turns ratio of the single-phase transformer is n1:n2. In the topology described above, the turns ratio of the transformer is 1:1, and the secondary side and the primary side have the same polarity.

[0012] Furthermore, the primary side of the transformer, with the same name terminal connected to the primary side DC blocking capacitor C, n6 With N-type MOSFET Q n1 Source, N-type MOSFET Q n3 The drains are connected, and the primary side of the transformer with the opposite polarity is connected to the Q-type N-type MOSFET. n2 Source, N-type MOSFET Q n4 Drain connected; N-type MOSFET S n1 Source and N-type MOSFET Q n3 Drain connected, N-type MOSFET Q n2 Source and N-type MOSFET Q n4 Drain connected, N-type MOSFET Q n1 Drain, N-type MOSFET Q n2Drain and DC input power supply U inn Positive, input capacitor C n5 The upper end is connected, and the N-type MOSFET tube Q n3 Source, N-type MOSFET tube Q n4 Source and DC input power supply U inn Negative, input capacitor C n5 The lower end is connected; one end of the secondary side of the transformer passes through the current limiting resistor R n Parallel with the transformer secondary side of other balancing units, the other end of the transformer secondary side is grounded.

[0013] Further, the N-type MOSFET tube Q n1 And the N-type MOSFET tube Q n3 Alternately, the N-type MOSFET tube Q n3 More than the N-type MOSFET tube Q n1 Lag 180° conduction, there is a dead zone between the conduction of the two groups of N-type MOSFET tubes; the N-type MOSFET tube Q n2 And the N-type MOSFET tube Q n4 Alternately, the N-type MOSFET tube Q n2 More than the N-type MOSFET tube Q n4 Lag 180° conduction, there is a dead zone between the conduction of the two groups of N-type MOSFET tubes; the N-type MOSFET tube Q n4 Lag the N-type MOSFET tube Q n1 One phase conduction, the N-type MOSFET tube Q n2 Also lag the N-type MOSFET tube Q n3 One phase conduction.

[0014] The differential voltage acquisition circuit comprises n INA105 differential amplifiers connected in parallel across each battery unit; the positive input end is connected to the positive electrode of the battery unit, the negative input end is connected to the negative electrode of the battery unit, and the output end is connected to the differential comparison circuit.

[0015] The differential pressure comparison circuit comprises 2n diodes, a PNP transistor, an LM358 operational amplifier, an LM393 comparator, an NPN transistor and five resistors. The n voltage signals output by the differential voltage acquisition circuit are respectively connected with the anodes of n first diodes, and the cathodes of the n first diodes are connected in parallel and then connected to the positive input end of a set of operational amplifiers of the operational amplifier LM358; the n voltage signals output by the differential voltage acquisition circuit are respectively connected with the cathodes of n second diodes, and the anodes of the n second diodes are connected in parallel and then connected to the emitter of the PNP transistor, the collector of the PNP transistor is connected with the resistor R3 and grounded, and is also connected to the negative input end of a set of operational amplifiers of the operational amplifier LM358, the differential operational amplifier generates a differential pressure signal through comparison and connects the positive input end of the LM393 comparator, the negative input end of the LM393 comparator is connected with a preset threshold, and the output end is connected in series with the current-limiting resistor R4 and connected to the base of the NPN transistor, the collector of the NPN transistor is connected with the pull-up resistor R5 and connected to V CC , and the collector output enables the signal.

[0016] The phase-shifted PWM generation circuit comprises an LM555 timer, two 74HC123 monostable flip-flops, two 74HC14 Schmitt triggers, two NOT gates, seven AND gates, seven capacitors, seven resistors and a sliding resistor.

[0017] Further, the LM555 timer circuit generates a reference PWM signal with a certain frequency and duty ratio through the parameter configuration of the resistors R2 and R3 and the capacitor C2; the reference PWM signal is shaped by the 74HC14 Schmitt trigger U2 to output a PWM1 signal, the resistor R4 and the capacitor C3 are connected in series to form a first RC delay circuit, and the output signal is obtained through the 74HC14 Schmitt trigger U2; the resistor R5 and the capacitor C4 are connected in series to form a second RC delay circuit, the output signal is shaped by the 74HC14 Schmitt trigger U2, and the signal is output through the NOT gate U3 and input into the input end 1 of the AND gate U4; the input end 2 of the AND gate U4 is connected with the signal A, and the output of the AND gate U4 is a PWM3 signal which is complementary to the PWM1 signal and has a dead zone.

[0018] Further, the sliding resistor R6 and the capacitor C5 are connected in series to form a phase-shifted adjustable RC delay circuit, the phase shift is realized by adjusting the resistance value of R6 to 0-180°, the PWM1 signal is phase-shifted through the phase-shifted circuit, and the phase-shifted PWM4 signal is obtained by shaping the PWM1 signal through the 74HC14 Schmitt trigger U5; the resistor R7 and the capacitor C6 are connected in series to form a third RC delay circuit, the resistor R8 and the capacitor C7 are connected in series to form a fourth RC delay circuit, and the PWM4 signal is obtained through the third and fourth RC delay circuits, the 74HC14 Schmitt trigger U5, the NOT gate U6 and the AND gate U7, which is complementary to the PWM4 signal and has a dead zone.

[0019] Furthermore, the autonomous equalization enable signal and equalization on enable signal output from the differential pressure comparator are input to AND gate U8, outputting an enable signal; the enable signals are respectively connected to AND gates U9 and U1. 10 U 11 U 12 The input terminals of AND gates U9 and U 10 U 11 U 12 The other input terminal is connected to PWM1, PWM2, PWM3, and PWM4 signals respectively, and the output is the switch drive signal for enabling control.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] Compared to traditional active balancing topologies, this invention can simultaneously perform energy balancing on multiple battery cells connected in series. Battery cells include, but are not limited to, individual battery cells, battery modules, and battery clusters. This invention enables the control signal generator to operate based on the voltage difference. In the balancing enabled state, when the voltage difference between any two battery cells exceeds a threshold, the active balancing circuit can quickly perform energy balancing, allowing current to flow from the higher-voltage battery cell to the lower-voltage battery cell. This increases the voltage of the lower-voltage battery cell and decreases the voltage of the higher-voltage battery cell, ensuring that the voltages across all battery cells are consistent. Energy flows from the high-voltage end to the low-voltage end, effectively reducing system energy loss and eliminating the potential risks caused by inconsistent energy levels among battery cells during energy storage system operation. The topology is based on a phase-shifting full-bridge converter, with each battery cell connected in series. The primary side of the transformer connects to the corresponding terminal via a primary-side DC blocking capacitor C. n6 With N-type MOSFET Q n1 The source of the N-type MOSFET Q n3 The drains are connected, and the primary side of the transformer with the opposite polarity is connected to the Q-type N-type MOSFET. n2 Source, N-type MOSFET Q n4 Drain connected; N-type MOSFET Q n1 Source and N-type MOSFET Q n3 Drain connected, N-type MOSFET Q n2 Source and N-type MOSFET Q n4 Drain connected, N-type MOSFET Q n1 and N-type MOSFET Q n3 The series connection forms the advanced bridge arm and the N-type MOSFET Q. n2 and N-type MOSFET Q n4 The series-connected lag bridge arms are connected in parallel, and one end of the transformer secondary side is connected through a current-limiting resistor R. n The transformer secondary is connected in parallel with other equalization units, and the other end of the transformer secondary is grounded. A phase-shifted full-bridge control method is adopted, utilizing the parasitic junction capacitance C.n1 , C n3 or C n2 , C n4 The resonant inductor L is multiplexed with the primary winding of the transformer m The soft switch is connected at both ends of the switch tube, and zero voltage switching can be realized in the voltage balance transfer process, so that zero voltage turn-off and zero current conduction of the switch tube can be realized, and the switching loss is effectively reduced.

[0022] The phase-shifted full-bridge circuit converts the battery unit U inn into a bipolar square wave with a conversion amplitude of ±V inn , and the transformer is isolated to the secondary side, and the transformer is connected in parallel to form a multi-source circuit, and according to Kirchhoff's law, the multi-path voltage balance is realized autonomously, and then the transformer feeds back the balanced energy to the primary side, thereby realizing energy balance between each battery unit, and the control is simple. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0024] Figure 1 A low-power active balancing circuit and a control method thereof provided by the first embodiment of the present disclosure are shown in the structural diagram;

[0025] Figure 2 The differential pressure comparison circuit schematic diagram of a low-power active balancing circuit and a control method thereof provided by the second embodiment of the present disclosure is shown in the structural diagram;

[0026] Figure 3 The active balancing circuit schematic diagram of a low-power active balancing circuit and a control method thereof provided by the third embodiment of the present disclosure is shown in the structural diagram;

[0027] Figure 4 The phase-shifted PWM generation circuit schematic diagram of a low-power active balancing circuit and a control method thereof provided by the fourth embodiment of the present disclosure is shown in the structural diagram;

[0028] Figure 5 The phase-shifted PWM signal schematic diagram of a low-power active balancing circuit and a control method thereof provided by the fifth embodiment of the present disclosure is shown in the structural diagram;

[0029] Figure 6 The key waveform schematic diagram of a low-power active balancing circuit and a control method thereof provided by the sixth embodiment of the present disclosure is shown in the structural diagram;

[0030] Figure 7 A low-power active balancing circuit and a control method thereof according to an embodiment of the present disclosure are provided in FIG. 1. FIG. 1 is a schematic diagram of a main working mode of the low-power active balancing circuit and the control method thereof according to the embodiment of the present disclosure running in an active balancing mode for half a switching period.

[0031] Figure 8 A low-power active balancing circuit and a control method thereof according to an embodiment of the present disclosure are provided in FIG. 1. FIG. 1 is a schematic diagram of a main working mode of the low-power active balancing circuit and the control method thereof according to the embodiment of the present disclosure running in an active balancing mode for half a switching period. DETAILED DESCRIPTION

[0032] Embodiments of the present application will be described in more detail by referring to the drawings. Although certain embodiments of the present application are shown in the drawings, it is understood that the present application can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein, but rather these embodiments are provided so as to more completely and thoroughly understand the present application. It is understood that the drawings and embodiments of the present application are for exemplary purposes only and are not intended to limit the scope of protection of the present application.

[0033] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0034] Reference Figure 1 A low-power active balancing circuit and a control method thereof according to an embodiment of the present disclosure are provided in FIG. 1. FIG. 1 is a schematic diagram of a main working mode of the low-power active balancing circuit and the control method thereof according to the embodiment of the present disclosure running in an active balancing mode for half a switching period.

[0035] The battery unit includes, but is not limited to, a battery monomer, a battery module, and a battery cluster, and the n battery units are connected in series.

[0036] Further, when the balancing mode is turned on, the differential voltage acquisition circuit acquires the voltage across each battery unit in the battery unit group, the differential voltage comparison circuit selects the maximum voltage and the minimum voltage, calculates the maximum differential voltage of the system, compares the maximum differential voltage with the set threshold differential voltage, and outputs an active balancing enable signal according to the differential voltage comparison result. The enable signal controls the output of the PWM control signal in the phase-shifted PWM generation circuit, and the four groups of phase-shifted PWM signals control the turn-on and turn-off of the switching tubes in the active balancing circuit through the switching tube driving circuit. The active balancing circuit balances the voltage across each battery unit, and the differential voltage acquisition circuit acquires the voltage across each battery unit in the battery unit group to the differential voltage comparison circuit, and so on.

[0037] Further, when the system maximum pressure difference is less than the set threshold pressure difference, the pressure difference comparison circuit outputs a low level active balancing enable signal, or the manual shutdown balancing mode input low level balancing start enable signal, the phase shift PWM generation circuit stops outputting the PWM control signal, and the active balancing circuit stops working.

[0038] Reference Figure 2 The second embodiment of the present disclosure provides a pressure difference comparison circuit schematic diagram of a low-power active balancing circuit and a control method thereof, according to the low-power active balancing circuit and the control method thereof in claim 1, the pressure difference comparison circuit comprises 2n diodes, a PNP transistor, an LM358 operational amplifier, an LM393 comparator, an NPN transistor, and five resistors, and can be specifically divided into a highest voltage selection circuit, a lowest voltage selection circuit, a pressure difference calculation circuit, and a pressure difference comparison circuit.

[0039] The n voltage signals output by the differential voltage acquisition circuit are respectively connected with anodes of n first diodes, cathodes of the n first diodes are connected in parallel, a highest voltage selection circuit is formed, and the highest voltage signal in the battery unit output by the parallel cathode is connected to the positive input end of a group of operational amplifiers of the operational amplifier LM358; the n voltage signals output by the differential voltage acquisition circuit are respectively connected with cathodes of n second diodes, the anodes of the n second diodes are connected in parallel and connected with the emitter of the PNP transistor, the collector of the PNP transistor is connected with the resistor R3 and grounded, a lowest voltage selection circuit is formed, the lowest voltage in the battery unit output by the collector of the PNP transistor is connected to the negative input end of a group of operational amplifiers of the operational amplifier LM358, the maximum pressure difference signal generated by the differential operational amplifier through comparison is connected to the positive input end of the LM393 comparator, the negative input end of the LM393 comparator is connected with a preset threshold, the output end is connected in series with the current limiting resistor R4 and connected to the base of the NPN transistor, the collector of the NPN transistor is connected to V CC At the same time, the collector outputs an enable signal, when the maximum pressure difference in the system is greater than the threshold voltage of the start balancing mode, the collector outputs a high level enable signal, otherwise, a low level enable signal is output.

[0040] Reference Figure 3 The third embodiment of the present disclosure provides an active balancing circuit schematic diagram of a low-power active balancing circuit and a control method thereof, which comprises n phase shift full bridge circuits, n single-phase transformers, and n current limiting resistors, wherein: a single battery unit is connected to the primary side of the single-phase transformer through the phase shift full bridge circuit, and the secondary side of the transformer is connected in series with the current limiting resistor, to form a single balancing unit.

[0041] The battery unit can include a battery monomer, a battery pack, and a battery cluster, and the N battery units are connected in series.

[0042] Wherein, the number of turns of each single-phase transformer primary winding is represented by n1, and the number of turns of secondary winding is represented by n2, the turns ratio of single-phase transformer is n1:n2, the turns ratio of transformer in the topology is 1:1, and the polarity of secondary winding is the same as that of primary winding.

[0043] Wherein, the single equalization unit comprises a battery unit U inn , an input capacitor C n5 , an N-type MOSFET tube Q n1 , an N-type MOSFET tube Q n2 , an N-type MOSFET tube Q n3 , an N-type MOSFET tube Q n4 , a parasitic junction capacitor C n1 , a parasitic junction capacitor C n2 , a parasitic junction capacitor C n3 , a parasitic junction capacitor C n4 , a primary winding direct-current blocking capacitor C n6 , a single-phase transformer T n , and a current-limiting resistor R n .

[0044] Wherein, the four parasitic junction capacitors are connected in parallel across the four N-type MOSFET tubes, and the switch tube, the reverse diode, and the junction capacitor are connected in parallel.

[0045] Further, the same-named end of the transformer primary winding is connected to the source of the N-type MOSFET tube S n6 , the drain of the N-type MOSFET tube S n1 , and the anode of the primary winding direct-current blocking capacitor C n3 ; the different-named end of the transformer primary winding is connected to the source of the N-type MOSFET tube S n2 , the drain of the N-type MOSFET tube S n4 , and the anode of the primary winding direct-current blocking capacitor C n1 ; the source of the N-type MOSFET tube S n3 is connected to the drain of the N-type MOSFET tube S n2 ; the source of the N-type MOSFET tube S n4 is connected to the drain of the N-type MOSFET tube S n1 ; the drain of the N-type MOSFET tube S n2 is connected to the positive electrode of the battery unit U inn ; the upper end of the input capacitor C n5 is connected to the source of the N-type MOSFET tube S n3 ; the source of the N-type MOSFET tube S n4 is connected to the negative electrode of the battery unit U inn ; the lower end of the input capacitor C n5 is connected to the drain of the N-type MOSFET tube S n ; one end of the transformer secondary winding is connected in parallel with the transformer secondary winding of other equalization units through the current-limiting resistor R ; and the other end of the transformer secondary winding is grounded.

[0046] Reference Figure 4 The fourth embodiment of the present disclosure provides a phase-shift PWM generation circuit schematic diagram of a low-power active equalization circuit and a control method thereof, which comprises an LM555 timer, two 74HC123 monostable flip-flops, two 74HC14 Schmitt triggers, two NOT gates, seven AND gates, seven capacitors, seven resistors, and a sliding rheostat.

[0047] The LM555 timer circuit generates a reference PWM signal with a certain frequency and duty cycle through the parameter configuration of resistors R2 and R3 and capacitor C2; the reference PWM signal is shaped by the 74HC14 Schmitt trigger U2 to output a PWM1 signal, the resistor R4 and the capacitor C3 are connected in series to form a first RC delay circuit, and the output signal is obtained through the 74HC14 Schmitt trigger U2; the resistor R5 and the capacitor C4 are connected in series to form a second RC delay circuit, and the output signal is shaped by the 74HC14 Schmitt trigger U2 and output through the NOT gate U3 and input end 1 of the AND gate U4; the input end 2 of the AND gate U4 is connected to the signal A, and the output of the AND gate U4 is a PWM3 signal which is complementary to the PWM1 signal and has a dead zone.

[0048] The sliding rheostat R6 and the capacitor C5 are connected in series to form a phase-shift adjustable RC delay circuit, and the phase shift of 0-180° is realized by adjusting the resistance value of R6; the PWM1 signal is phase-shifted through the phase-shift circuit and shaped by the 74HC14 Schmitt trigger U5 to obtain a phase-shifted PWM4 signal; the resistor R7 and the capacitor C6 are connected in series to form a third RC delay circuit, and the resistor R8 and the capacitor C7 are connected in series to form a fourth RC delay circuit; the PWM4 signal passes through the third and fourth RC delay circuits, the 74HC14 Schmitt trigger U5, the NOT gate U6, and the AND gate U7 to obtain a PWM2 signal which is complementary to the PWM4 signal and has a dead zone.

[0049] The differential pressure comparison circuit outputs an autonomous equalization enable signal and an equalization start enable signal which are input into the AND gate U8, and an enable signal is output; the enable signal is input into the input end of the AND gates U9, U 10 , U 11 , U 12 , and the other input end of the AND gates U9, U 10 , U 11 , U 12 is connected to the PWM1, PWM2, PWM3, and PWM4 signals respectively, and the switch tube driving signal controlled by the enable signal is output; when the enable signal is at a high level, the driving signal is normally output to the switch tube driving circuit.

[0050] In the equalization mode open state, when the system maximum pressure difference does not exceed the threshold, the autonomous equalization enable signal output by the pressure difference comparison circuit is low, and the enable signal output by the AND gate is also low, so that the phase-shifted PWM signal is not output; on the contrary, when the system maximum pressure difference does not exceed the threshold, the autonomous equalization enable signal output by the pressure difference comparison circuit is high, and the enable signal output by the AND gate is also high, so that the phase-shifted PWM signal is normally output to the switch tube driving circuit. When the equalization mode is not open, the phase-shifted PWM signal is not output.

[0051] Reference Figure 5 The fifth embodiment of the present disclosure provides a control pulse signal schematic diagram of a low-power active equalization circuit and a control method thereof, which includes: PWM1 signal, PWM2 signal, PWM3 signal and PWM4 signal, four groups of PWM driving control signals have the same duty cycle, PWM3 signal lags PWM1 signal by 180 degrees, and there is a dead zone between the two groups of signals; PWM2 signal lags PWM4 signal by 180 degrees, and there is a dead zone between the two groups of signals; PWM1 signal is phase-shifted by an angle δ to obtain PWM4 signal, PWM3 signal is phase-shifted by an angle δ to obtain PWM2 signal, and the phase-shift angle δ is adjustable. PWM1 signal controls N-type MOSFET tube Q n1 , PWM2 signal controls N-type MOSFET tube Q n2 , PWM3 signal controls N-type MOSFET tube Q n3 , and PWM4 signal controls N-type MOSFET tube Q n4 .

[0052] Reference Figure 6 The sixth embodiment of the present disclosure provides a key waveform schematic diagram of a low-power active equalization circuit and a control method thereof running in an active equalization mode, which includes: the waveform of the primary side current i p and the voltage v AB between points A and B, that is, the waveform of the transformer primary side voltage.

[0053] Reference Figure 7 The seventh embodiment of the present disclosure provides a main working mode schematic diagram of a low-power active equalization circuit and a control method thereof running in an active equalization mode for half a switching period, which includes:

[0054] Mode 0, t0 moment: before t0 moment, switch tubes Q n1 and Q n4 are turned on. The transformer primary side current i pn flows through the positive electrode of the power supply, switch tube Q n1 , primary side DC blocking capacitor C n6 , transformer primary side winding and switch tube Q n4 , and finally returns to the negative electrode of the power supply. For a single equalization module, the secondary side current loop is: the positive end of the secondary side winding, through the load Rn The circuit returns to the negative terminal of the secondary winding, which is then grounded. Since the transformer turns ratio is 1:1, the secondary voltage remains equal to the primary voltage throughout this process. The voltage between points A and B, i.e., the primary voltage, can be expressed as: v AB =+v inn .

[0055] The rise in the primary current of a transformer is mainly determined by the transformer's leakage inductance and magnetizing inductance. In Q... n1 and Q n4 During conduction, the primary voltage is applied across the inductor. According to the inductor characteristics:

[0056]

[0057] The rate of change of the primary current is a positive constant, therefore the primary current i pn The waveform rises approximately linearly.

[0058] Mode 1 [t0, t1]: Q at time t0 n1 When turned off, the primary current i of the transformer pn From the switching transistor Q n1 The transfer to the parasitic junction capacitance C n1 and C n3 In the branch, give C n1 Charging, while simultaneously supplying C n3 Discharge, thus the parasitic junction capacitance C n1 and C n3 The voltage is:

[0059]

[0060]

[0061] Due to the parasitic junction capacitance C n1 The function of the switching transistor Q n1 The voltage across the terminals rises slowly, at which point the switching transistor Q... n1 Zero-voltage turn-off. During this period, the voltage between points A and B is equal to the parasitic junction capacitance C. n3 The voltage across the terminals, as C n3 Discharge, the voltage across its terminals changes from +V inn The value drops to 0. This is due to the switching transistor Q. n1 When turned off, the primary current i pn Unable to pass Q n1 The current can only flow through the parasitic parameters of the transformer. The primary voltage of the transformer is the voltage between points A and B. When the primary voltage of the transformer decreases, the current in the primary winding of the transformer decreases. p / dt is negative, primary current i pn Decrease. Parasitic junction capacitance C n3 When the voltage across the transistor drops to zero, the switching transistor Q... n3 anti-parallel diode Dn3 Natural conduction, thus ending the switch mode 1.

[0062] Mode 2 [t1, t2]: at time t1, the parasitic junction capacitor C n3 The voltage across the switch tube Q n3 The anti-parallel diode D n3 Conducts naturally. D n3 After conduction, the switch tube Q n3 is turned on. Although the Q n3 is turned on at this time, the Q n3 does not have current flowing through it, i pn flows through D n3 . Since Q n3 is turned on when D n3 is conducting, the parasitic junction capacitor C n3 of the switch tube Q n3 at this time has its voltage across it dropped to zero, i.e. the voltage across the switch tube Q n3 is zero, so the switch tube Q n3 is turned on with zero voltage. During the period from t1 to t2, the primary current loop does not flow through the power supply, and the loop is unloaded, and points A and B are both approximately grounded, so the primary voltage v AB is always zero, and the primary current is also approximately constant.

[0063] Mode 3 [t2, t3]: at time t2, the switch tube Q n4 is turned off, and the transformer primary current i pn is transferred from the switch tube Q n4 to the parasitic junction capacitor C n2 and the C n4 branch, charging C n4 and discharging C n2 at the same time. At this time, point A is approximately grounded, and the voltage at point B is equal to the voltage across the parasitic junction capacitor C n4 , and the primary voltage, i.e. the voltage between points A and B, is v AB =-v cn4 at this time. The polarity of the transformer primary voltage v AB changes from zero to negative, and the potential of the transformer secondary winding becomes lower positive and higher negative.

[0064] As the primary current charges C n4 , the transformer primary voltage v AB rises in the opposite direction. The voltage across the switch tube Q n4 is equal to the voltage across the parasitic junction capacitor C n4 , and since C n2 and C n4 exist, the switch tube Q n4 is turned off with zero voltage. As in mode 1, the transformer primary voltage v ABThe di / dt in the primary winding of the transformer is negative p , so the primary current i pn drops.

[0065] At time t3, when the voltage across C n4 rises to V inn , D n2 naturally turns on, ending this switching mode.

[0066] Mode 4 [t3, t4]: At time t3, D n2 naturally turns on, clamping the voltage across Q n2 to zero potential. At this time, Q n2 can be turned on. At this time, there is no charging and discharging activity in the primary circuit, so the primary voltage v AB is always -V inn , and the voltage across D n2 and Q n2 is zero, so Q n2 is turned on with zero voltage. Although Q n2 is turned on at this time, Q n2 does not flow through the primary current i pn , i pn flows through the anti-parallel diode D n2 , and the current of the excitation inductance and the resonant inductance is fed back to the power supply. The direction of the feedback current generated in the primary winding is opposite to the direction of the primary current, so the primary current i pn drops in this period.

[0067] At time t4, the primary current i pn drops to zero, and D n2 and D n3 naturally turn off, and Q n2 and Q n3 will flow through the current.

[0068] Mode 5 [t4, t5]: At time t4, the primary current i pn passes through zero from positive to negative, and at this time Q n2 and Q n3 provide a path for i pn . The primary current i pn of the transformer flows through the switch Q n2 , the primary winding of the transformer, the DC blocking capacitor C n6 , and the switch Q n3 , and finally returns to the negative terminal of the power supply. At this time, the voltage between points A and B, i.e., the primary voltage, can be represented as: v AB = -v innSimilar to mode 1, the rate of change of the primary current during this period is a negative constant; therefore, the primary current i pn It increases approximately linearly in the negative direction.

[0069] At time t5, the switching transistor Q n3 When turned off, the equalization topology begins the operation of the other half of the cycle, which is similar to the half cycle described above, except that the direction of the primary current and the polarity of the primary voltage are opposite to those of the first half cycle.

[0070] The above-described switching mode 1 demonstrates that the low-power active equalization circuit described in this example switches transistor Q at time t0. n1 When turned off, the drain-source voltage U of the switching transistor dsn1 With the parasitic junction capacitance C of the switching transistor n1 During charging, the voltage increases slowly from zero without any sudden changes, thus achieving zero-voltage turn-off of the switching transistor.

[0071] The aforementioned switching mode 3 demonstrates that the low-power active equalization circuit described in the example switches transistor Q at time t2. n4 When turned off, the drain-source voltage U of the switching transistor dsn4 With the parasitic junction capacitance C of the switching transistor n4 During charging, the voltage increases slowly from zero without any sudden changes, thus achieving zero-voltage turn-off of the switching transistor.

[0072] The above-described switching mode 2 demonstrates that the low-power active equalization circuit described in the example switches transistor Q at time t1. n3 On, Q n3 It was activated, but Q n3 No current flows through i pn By D n3 Flow. At this time, the switching transistor Q... n3 parasitic junction capacitance C n3 The voltage across the two terminals has dropped to zero, i.e., the voltage across the switching transistor Q has dropped to zero. n3 With the voltage across the terminals at zero, the switching transistor Q is achieved. n3 Zero voltage conduction.

[0073] The above-described switching mode 4 demonstrates that the low-power active equalization circuit described in the example switches transistor Q at time t3. n2 On, Q n2 It was activated, but Q n2 No current flows through i pn By D n2 Circulation, will switch transistor Q n2 The voltage is clamped to zero potential. At this time, D n2 The voltage across the terminals, i.e., Q n2 The voltage across the two terminals is 0, thus achieving the switching of transistor Q. n2Zero-voltage turn-on of the switch tube and zero-voltage turn-off, which embody the low-power active balancing circuit and the control method thereof according to the present example, realize soft switching, and effectively reduce switching loss.

[0074] Reference Figure 8 The low-power active balancing circuit and the control method thereof according to the present example eight provide a schematic diagram of balancing effect when the low-power active balancing circuit and the control method thereof according to the present example run in an active balancing mode.

[0075] In the low-power active balancing circuit according to the present example, a battery unit U inn is converted into a bipolar square wave with a conversion amplitude of ±V inn , voltage size is determined through transformer isolation on the secondary side, the transformer secondary side voltage can be regarded as a secondary side power supply, each secondary side power supply and load are connected in parallel through an energy storage bus, and can be equivalent to a multi-source circuit, the equivalent power supply on the secondary side actively charges and discharges to realize energy balancing according to Kirchhoff's law, and the feedback of the completed balancing is fed back to the DC input source through a single-phase transformer, thereby realizing fast and accurate balancing of multiple battery units.

[0076] The low-power active balancing circuit and the control method thereof according to the present example are characterized in that the low-power active balancing circuit is controlled by four groups of phase-shifted full-bridge PWM signals, four switch tubes of two bridge arms of the phase-shifted full-bridge circuit are alternately turned on, the battery balancing topology retains the basic structure of the phase-shifted full-bridge converter, a soft switching composed of a parasitic junction capacitor and a transformer excitation inductance is connected across the switch tubes, zero-voltage turn-on and zero-voltage turn-off are realized, and switching loss is effectively reduced.

[0077] In the low-power active balancing circuit and the control method thereof according to the present example, in addition to balancing between battery monomers, it is also applicable to balancing between battery modules or clusters in other large-scale energy storage. Simulation results verify that the low-power active balancing circuit and the control method thereof according to the present example can quickly and accurately balance multiple battery units, the balancing effect is rapid, the control logic is simple, and it is a low-power and efficient active balancing topology and control method.

Claims

1. A low-power active equalization circuit and its control method, characterized in that, include: n battery cells, active equalization circuit, differential voltage acquisition circuit, differential voltage comparison circuit, phase-shifted PWM generation circuit, and switching transistor drive circuit; The battery unit includes, but is not limited to, individual battery cells, battery packs, and battery clusters, with n battery units connected in series. The active balancing circuit includes n phase-shifting full-bridge circuits, n single-phase transformers, and n current-limiting resistors. Each battery cell is connected to the primary side of the single-phase transformer via a phase-shifting full-bridge circuit, and the secondary side of the transformer is connected in series with a current-limiting resistor to form a single balancing unit.

2. The low-power active equalization circuit and its control method according to claim 1, characterized in that... The number of turns on the primary side of the single-phase transformer is represented by n1, and the number of turns on the secondary side is represented by n2. The turns ratio of the single-phase transformer is n1:n2. The turns ratio of the transformer in the topology is 1:1, and the secondary side and the primary side have the same polarity.

3. The low-power active equalization circuit and its control method according to claim 1, characterized in that... The single equalization unit includes battery unit U inn Input capacitor C n5 N-type MOSFET Q n1 N-type MOSFET Q n2 N-type MOSFET Q n3 N-type MOSFET Q n4 Parasitic junction capacitance C n1 Parasitic junction capacitance C n2 Parasitic junction capacitance C n3 Parasitic junction capacitance C n4 Primary-side DC blocking capacitor C n6 Single-phase transformer T n and current-limiting resistor R n .

4. The low-power active equalization circuit and its control method according to claim 1, characterized in that, The primary side of the transformer is connected to the same-name terminal via the primary side DC blocking capacitor C. n6 With N-type MOSFET Q n1 Source, N-type MOSFET Q n3 The drains are connected, and the non-transformer terminal of the transformer primary side is connected to the N-type MOSFET Q. n2 Source, N-type MOSFET Q n4 Drain connected; N-type MOSFET Q n1 Source and N-type MOSFET Q n3 The drains are connected to form the leading bridge arm branch, and the N-type MOSFET S... n2 Source and N-type MOSFET S n4 The drains are connected to form a hysteresis bridge arm circuit, and the N-type MOSFET S... n1 Drain, N-type MOSFET S n2 Drain and battery cell U inn Positive terminal, input capacitor C n5 The upper end is connected to the N-type MOSFET S. n3 Source, N-type MOSFET S n4 Source electrode and battery cell U inn Negative terminal, input capacitor C n5 Connected at the bottom; The transformer secondary side is connected to the same-name terminal via a current-limiting resistor R. n It is connected in parallel with the secondary side of other equalization unit transformers, and the opposite-name terminal of the transformer secondary side is grounded.

5. A low-power active equalization circuit according to claim 4, characterized in that, N-type MOSFET S n1 and N-type MOSFET S n3 The N-type MOSFET is turned on alternately, and the source is closed. n3 Compared to N-type MOSFETs S n1 There is a 180° hysteresis turn-on, and a dead zone exists between the two sets of N-type MOSFETs; N-type MOSFET S n2 and N-type MOSFET S n4 The N-type MOSFET is turned on alternately, and the source is closed. n2 Compared to N-type MOSFETs S n4 There is a 180° hysteresis turn-on, and a dead zone exists between the two sets of N-type MOSFETs; N-type MOSFET S n4 Hysteresis N-type MOSFET S n1 One phase is turned on, and the N-type MOSFET S n2 Hysteresis N-type MOSFET S n3 One phase is conducting.

6. The low-power active equalization circuit and its control method according to claim 1, characterized in that... The differential voltage acquisition circuit includes n INA105 differential amplifiers, which are connected in parallel across each battery cell. The positive input terminal is connected to the positive terminal of the battery cell, the negative input terminal is connected to the negative terminal of the battery cell, and the output terminal is connected to the differential voltage comparison circuit.

7. A low-power active equalization circuit and its control method according to claim 1, wherein the differential voltage comparison circuit comprises 2n diodes, one PNP transistor, one LM358 operational amplifier, one LM393 comparator, one NPN transistor, and five resistors. The n voltage signals output from the differential voltage acquisition circuit are respectively connected to the anodes of the n first diodes, and the cathodes of the n first diodes are connected in parallel to the positive input terminal of a group of operational amplifiers of the LM358; the n voltage signals output from the differential voltage acquisition circuit are respectively connected to the cathodes of the n second diodes, and the anodes of the n second diodes are connected in parallel to the emitter of the PNP transistor. The collector of the PNP transistor is connected to ground via resistor R3 and simultaneously connected to the negative input terminal of a group of operational amplifiers of the LM358. The differential operational amplifier generates a differential voltage signal through comparison and connects it to the positive input terminal of the LM393 comparator. The negative input terminal of the LM393 comparator is connected to a preset threshold. The output terminal is connected to the base of the NPN transistor via a series current-limiting resistor R4, and the collector of the NPN transistor is connected to V through a pull-up resistor R5. CC At the same time, the collector outputs an autonomous equalization enable signal.

8. The low-power active equalization circuit and its control method according to claim 1, wherein the phase-shifted PWM generating circuit includes an LM555 timer, two 74HC123 monostable multivibrators, two 74HC14 Schmitt triggers, two NOT gates, seven AND gates, seven capacitors, seven resistors, and a sliding rheostat. The LM555 timer circuit generates a reference PWM signal with a certain frequency and duty cycle through the parameter configuration of resistors R2 and R3 and capacitor C2. The reference PWM signal is shaped by a 74HC14 Schmitt trigger U2 to output the PWM1 signal. Resistor R4 and capacitor C3 are connected in series to form the first RC delay circuit, and the output is passed through the 74HC14 Schmitt trigger U2 to obtain signal A. Resistor R5 and capacitor C4 are connected in series to form the second RC delay circuit. The output signal is shaped by a 74HC14 Schmitt trigger U2, and the output is connected to input terminal 1 of AND gate U4 through NOT gate U3. Input terminal 2 of AND gate U4 is connected to signal A. The output of AND gate U4 is the PWM3 signal, which is complementary to PWM1 and has a dead time. A sliding rheostat R6 and a capacitor C5 are connected in series to form a phase-shift adjustable RC delay circuit. The phase shift from 0 to 180° is achieved by adjusting the resistance value of R6. The PWM1 signal is phase-shifted by the phase-shifting circuit and then shaped by the 74HC14 Schmitt trigger U5 to obtain the phase-shifted PWM4 signal. The resistor R7 and the capacitor C6 are connected in series to form the third RC delay circuit, and the resistor R8 and the capacitor C7 are connected in series to form the fourth RC delay circuit. The PWM4 signal is passed through the third and fourth RC delay circuits, the 74HC14 Schmitt trigger U5, the NOT gate U6, and the AND gate U7 to obtain the PWM2 signal, which is complementary to PWM4 and has a dead time. The autonomous equalization enable signal and equalization on enable signal output from the differential pressure comparator are input to AND gate U8, which outputs an enable signal; the enable signals are then connected to AND gates U9 and U1 respectively. 10 U 11 U 12 The input terminals of AND gates U9 and U 10 U 11 U 12 The other input terminal is connected to PWM1, PWM2, PWM3, and PWM4 signals respectively, and the output is the switch drive signal for enabling control.

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