Current correction circuit and method for motor driving and driving circuit

Abstract

The invention provides a current correction circuit and method for motor driving and a motor driving circuit. The current correction circuit comprises a preprocessing circuit, an integral judgment circuit and a pulse shielding circuit. The pre-processing circuit replaces a first type of pulse of which the pulse width is smaller than the pulse width of the minimum conduction time signal in the PWM1 with the pulse of the minimum conduction time signal to generate PWM2. The integral judgment circuit integrates the width of the first type of pulse to generate an integral voltage, and compares the integral voltage with a threshold voltage to generate a shielding enable signal. When the integral voltage is smaller than the threshold voltage, the pulse shielding circuit shields the pulse of which the pulse width is equal to the fixed minimum pulse width in the PWM2 so as to generate PWM3. By shielding part of the pulses with the fixed minimum pulse width, the current of the motor can be further reduced, the current waveform is improved, the current distortion degree and harmonic pollution are reduced, and the performance of the motor at different driving speeds can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of motor control, and in particular to a current correction circuit, a method and a driving circuit for motor driving. BACKGROUND

[0002] A brushless DC motor (BLDC) is a kind of DC motor that uses electronic commutation instead of mechanical brushes and commutators. Compared with traditional brush motors, it has the advantages of high efficiency, long service life, low noise, less maintenance, etc., and is widely used in unmanned aerial vehicles, electric vehicles, industrial automation, household appliances and other fields.

[0003] The brushless DC motor adjusts the duty cycle of the pulse width modulation signal (PWM) to control the input voltage, thereby achieving the adjustment of the motor speed. Generally, the motor has good linearity when running at high speed, but when the motor speed is very low, the motor current cannot be further reduced due to the influence of the minimum conduction time inside the driver. Especially in a sinusoidal brushless motor, the current waveform will be distorted at low speed, thereby generating additional noise and unnecessary harmonic interference. SUMMARY

[0004] The purpose of the present application is to provide a current correction circuit, a method and a motor driving circuit for motor driving to meet the optimal performance requirements of the motor at different driving speeds.

[0005] The present application provides a current correction circuit for motor driving, comprising: a preprocessing circuit receiving a minimum conduction time signal and a first pulse width modulation signal, and replacing the first type of pulse in the first pulse width modulation signal with a pulse of the minimum conduction time signal to generate a second pulse width modulation signal, wherein the period of the minimum conduction time signal is equal to the period of the first pulse width modulation signal, and the pulse of the minimum conduction time signal has a fixed minimum pulse width; an integral judgment circuit receiving the first pulse width modulation signal, when the first type of pulse in the first pulse width modulation signal arrives, the integral judgment circuit integrates the width of the first type of pulse to generate an integral voltage, and compares the integral voltage with a threshold voltage to generate a shielding enable signal; a pulse shielding circuit receiving the second pulse width modulation signal and the shielding enable signal, wherein when the integral voltage is less than the threshold voltage, the pulse shielding circuit shields the pulse in the second pulse width modulation signal with a pulse width equal to the fixed minimum pulse width to generate a third pulse width modulation signal, and the third pulse width modulation signal is used to control the speed of the motor. The motor driving circuit provided by the application comprises a power switch unit with a plurality of power switch tubes; the current correction circuit as described above is used to generate a third pulse width modulation signal; the logic driving circuit is used to receive the third pulse width modulation signal and generate a switch driving signal according to the third pulse width modulation signal, the switch driving signal is used to drive the turn-on and turn-off of each power switch tube and control the turn-on time and turn-off time of each power switch tube to adjust the motor rotating speed.

[0006] The current correction method for motor driving provided by the application comprises: replacing the first type of pulse with the pulse width smaller than the pulse width of the minimum turn-on time signal in the first pulse width modulation signal with the pulse of the minimum turn-on time signal to generate a second pulse width modulation signal, wherein the period of the minimum turn-on time signal is equal to the period of the first pulse width modulation signal and the pulse of the minimum turn-on time signal has a fixed minimum pulse width; when the first type of pulse in the first pulse width modulation signal arrives, the width of the first type of pulse is integrated to generate an integrated voltage; the size of the integrated voltage and the threshold voltage is judged; when the integrated voltage is smaller than the threshold voltage, the pulse with the pulse width equal to the fixed minimum pulse width in the second pulse width modulation signal is shielded to generate a third pulse width modulation signal, wherein the third pulse width modulation signal is used to control the rotating speed of the motor.

[0007] The current correction circuit, method and motor driving circuit for motor driving provided by the application can further reduce the motor current, improve the current waveform, reduce the current distortion at low speed of the motor and reduce the harmonic pollution, which is beneficial to improve the performance of the motor at different driving speeds. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0009] Figure 1 The figure shows a schematic diagram of a direct current brushless motor (BLDC) system according to an embodiment of the present application.

[0010] Figure 2 The circuit schematic diagram of the pulse width modulation signal generation circuit 40 according to an embodiment of the present application.

[0011] Figure 3 The figure shows a schematic diagram of a direct current brushless motor (BLDC) system according to an embodiment of the present application. Figure 1 and Figure 2 The waveform timing diagram of some parameters in the above-mentioned embodiments.

[0012] Figure 4 A circuit schematic diagram of a modulation circuit 41 according to an embodiment of the application is shown.

[0013] Figure 5 A detailed circuit schematic diagram of a current correction circuit 10 according to an embodiment of the application is shown.

[0014] Figure 6 A detailed circuit schematic diagram of a current correction circuit 10 according to an embodiment of the application is shown. Figure 5 A waveform timing diagram of the current correction circuit related parameters is shown.

[0015] Figure 7 A flowchart of a method of driving a brushless DC motor according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0016] The specific embodiments of the present application will now be described with reference to the drawings. The description of "one embodiment" or "an embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. The use of the terms "including," "containing," or "comprising" means that the feature, structure, or characteristic being described is included, but not that any feature, structure, or characteristic not specifically described is excluded. The use of the terms "first," "second," "third," etc. means the different claimed embodiments, not that the embodiments so designated are preferred or that there can be only one of each. The use of the term "or" in the claims means "and / or" unless specifically stated otherwise. The use of the term "about" means that the value modified by the term "about" can vary by up to 10% of the stated value. The use of the term "one" means "at least one" unless specifically stated otherwise. The use of the term "plurality" means "two or more" unless specifically stated otherwise. The use of the term "another" means "at least one" unless specifically stated otherwise. The use of the term "comprising" means "including, but not limited to" unless specifically stated otherwise. The use of the term "coupled" means that two or more elements are in some way currently directly or indirectly connected physically or logically, and the connection can be through one or more additional elements. The use of the term "connected" means that two or more elements are in some way currently directly connected physically or logically, and the connection can be through one or more additional elements. The use of the term "directly connected" means that two or more elements are in some way currently directly connected physically or logically, and the connection can not be through one or more additional elements. The use of the term "logic signal" means a signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state). The high and low states of different logic signals of the same electronic circuit can be different. In particular, the high and low states of a logic signal can correspond to voltages or currents that can not be completely constant in the high or low state.

[0017] Figure 1 A schematic diagram of a brushless DC motor (BLDC) system according to an embodiment of the application is shown. The motor system includes a current correction circuit 10, a logic drive circuit 20, a power switch unit 50, and a motor 60.

[0018] AsFigure 1 As shown, the current correction circuit 10 is configured to receive and process the first pulse width modulation signal PWM1, and then deliver a third pulse width modulation signal PWM3 to the logic drive circuit 20. The logic drive circuit 20 is configured to generate corresponding drive signals DRV according to the third pulse width modulation signal PWM3, to drive the on and off of each power switch in the power switch unit 50, and to control the on and off time of each power switch, to regulate the current flowing through the motor 60, and thus to control the rotation speed of the motor 60.

[0019] In Figure 1 In the embodiment shown, for the sake of simplicity and clarity, the motor system is shown as a single-phase motor system, and thus the power switch unit 50 is shown as a H-bridge topology composed of four power switches (S1, S2, S3, S4), which are controlled by four drive signals (DRV1, DRV2, DRV3, DRV4) output by the logic drive circuit 20. However, in other embodiments of the present application, the power switch unit 50 can also be in other circuit topologies. For example, in a three-phase motor system, the power switch unit 50 includes a 6-phase full-bridge topology composed of six power switches, and the power switch unit 50 will also include three output terminals for connecting the three-phase motor. At the same time, the logic drive circuit 20 will also output six drive signals to control the corresponding power switches.

[0020] In addition, in the embodiment of the three-phase motor, the first pulse width modulation signal PWM1 will also include three-phase pulse width modulation signals, which are staggered by 120° in turn, and each phase pulse width modulation signal is corrected by a current correction circuit 10, and then the three corrected pulse width modulation signals are sent to the logic drive circuit to generate the final drive signals.

[0021] In one embodiment, the first pulse width modulation signal PWM1 can be provided by an external microprocessor (MCU). In one embodiment, the first pulse width modulation signal PWM1 is generated by a pulse width modulation signal generation circuit according to a Hall signal, wherein the Hall signal is generated by a Hall sensor and is used to represent the motor commutation information. For example, Figure 2 According to an embodiment of the present application, a specific circuit schematic diagram of the pulse width modulation signal generation circuit 40 for generating the first pulse width modulation signal PWM1 is shown.

[0022] As Figure 2 As shown, the pulse width modulation signal generation circuit 40 includes a modulation circuit 41, a triangular wave generator 42, and a voltage comparator 43.

[0023] The modulation circuit 41 receives the Hall signal Hlogic and modulates the Hall signal Hlogic into a variable voltage signal Vmod of a desired waveform. InFigure 2 In the illustrated embodiment, the Hall signal Hlogic is generated by the Hall sensor 30. The Hall sensor 30 can be used to monitor the number of rotations of the motor 60 during its rotation. Typically, the Hall sensor 30 outputs the Hall signal Hlogic, and the interval between two adjacent single pulses of the Hall signal Hlogic characterizes the Hall cycle of the motor. It can be understood that the Hall cycle refers to the time it takes for the motor rotor to rotate through two different magnetic poles. The Hall cycle is related to the number of magnetic pole pairs of the motor rotor. For example, if the motor rotor has one pair of magnetic poles, the Hall cycle is the time it takes for the rotor to rotate one revolution; conversely, if the motor rotor has three pairs of magnetic poles, the Hall cycle is the time it takes for the rotor to rotate one-third of a revolution. In one embodiment, the Hall signal Hlogic is a high / low logic level signal, and the time between one high level and one low level constitutes one Hall cycle. In some embodiments, the Hall signal Hlogic can also be an analog voltage signal, the value of which varies, and a single pulse is generated at corresponding moments of two identical voltage values, with the time between the two identical voltage values ​​constituting one Hall cycle.

[0024] The triangular wave generator 42 is used to generate a triangular wave signal with a fixed period. The period of the triangular wave signal is much shorter than the period of the Hall signal Hlogic.

[0025] The voltage comparator 43 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the voltage comparator 43 receives a triangular wave signal, and the second input terminal of the voltage comparator 43 receives a variable voltage signal Vmod. The voltage comparator 43 compares the variable voltage signal Vmod with the triangular wave signal and outputs a first pulse width modulation signal PWM1 at the output terminal.

[0026] See also Figure 1 ,exist Figure 1 In the illustrated embodiment, the logic drive circuit 20 generates a corresponding drive signal DRV based on the third pulse width modulation signal PWM3. In some embodiments, for example, when the system is a single-phase BLDC and the first pulse width modulation signal PWM1 is generated by the pulse width modulation signal generation circuit based on the Hall signal Hlogic, the logic drive circuit 20 will also receive the Hall signal Hlogic and control the current direction through the Hall signal Hlogic.

[0027] Figure 3 The illustration shows an embodiment of the present invention. Figure 1 and Figure 2 Waveform timing diagrams of some parameters in the middle section. Figure 3 The diagram, from top to bottom, illustrates the waveforms of the Hall signal Hlogic, the variable voltage signal Vmod, and the output voltages OUT1 and OUT2. Because... Figure 1The diagram illustrates a single-phase BLDC converter. Therefore, the modulation circuit 41 modulates the Hall signal Hlogic into a variable voltage signal Vmod with a sinusoidal half-wave shape. After comparing the variable voltage signal Vmod with a high-frequency triangular wave signal, a first pulse width modulation signal PWM1 is generated.

[0028] It is understandable that in a three-phase motor application, the modulation circuit 41 can modulate the three-phase Hall signal Hlogic into a three-phase saddle wave form of a variable voltage signal Vmod, and then compare the variable voltage signal Vmod with a high-frequency triangular wave signal to generate three first pulse width modulation signals required to control the three-phase motor.

[0029] In one embodiment, the modulation circuit 41 may be derived from... Figure 4 The circuit implementation in [the context]. For example... Figure 4 As shown, the modulation circuit 41 includes a phase-shift signal generation circuit 411 and a resistor module 412.

[0030] The phase-shifting signal generation circuit 411 receives the Hall signal Hlogic, which represents the commutation information of the motor, and performs frequency division and phase shifting on the Hall signal Hlogic to generate the K-channel switch control signal Gate. <j>, j = 1, 2, … K, where K is an integer greater than or equal to 2. In an embodiment, the greater the value of K, the smoother the curve of the equivalent resistance of the resistance module 442.

[0031] The resistance module 442 includes K resistive elements and K electronic switches. The K resistive elements are connected in series between the current source Ibias and the reference ground in turn. The K electronic switches correspond to the K resistive elements and the K switch control signals one by one, each electronic switch has a first end, a second end and a control end, the first end of each electronic switch is coupled with one end of the corresponding resistive element in turn, the second end of each electronic switch is connected to the reference ground, and the control end of each electronic switch receives the K switch control signals Gate <j>, j = 1, 2, …K, the switch control signal is used to control the electronic switch to be on or off, thereby changing the resistance value of the resistance module. The current source Ibias provides current to flow through the resistance module 442, generating a variable voltage signal Vmod. The above-mentioned resistive elements can be implemented by resistors, and the resistances of the K resistive elements can be the same or different.

[0032] In the embodiment shown in FIG. 4, when the switch control signal controls the corresponding electronic switch to be on, the corresponding resistive element of the electronic switch is short-circuited, thereby changing the resistance value of the resistance module 442. It should be noted that Figure 4 Figure 4 The connection mode of the K resistive elements and the K electronic switches in the resistance module 442 is only illustrated according to one embodiment, Figure 4 The illustration does not constitute a limitation on the connection mode of the K resistive elements and the K electronic switches. For example, in other embodiments, each electronic switch can also be connected in parallel across the corresponding resistive element, and the equivalent resistance value of the resistance module 442 is changed by controlling the on and off of the electronic switch.

[0033] Figure 5 FIG. 5 shows a specific circuit schematic diagram of the current correction circuit 10 according to one embodiment of the present application. As shown in FIG. 5, Figure 5 The current correction circuit 10 includes a preprocessing circuit 11, an integral judgment circuit 12, and a pulse shielding circuit 13.

[0034] The preprocessing circuit 11 receives the minimum on-time signal Min-on and the first pulse width modulation signal PWM1, and replaces the first type of pulses in the first pulse width modulation signal PWM1 whose pulse width is smaller than the pulse width of the minimum on-time signal Min-on with the pulses of the minimum on-time signal Min-on to generate the second pulse width modulation signal PWM2. The period of the minimum on-time signal Min-on is equal to the period of the first pulse width modulation signal PWM1, and the pulses of the minimum on-time signal Min-on have a fixed minimum pulse width. In one embodiment, the fixed minimum pulse width of the minimum on-time signal Min-on is used to set the minimum on-time of the power switch, so as to ensure the reliable operation of the device and avoid abnormal output caused by too narrow pulses. The specific value of the fixed minimum pulse width is different according to different power switch devices selected in different application scenarios. In one embodiment, the preprocessing circuit 11 includes a logic gate circuit, which outputs the second pulse width modulation signal PWM2 by performing logic operation on the minimum on-time signal Min-on and the first pulse width modulation signal PWM1.

[0035] ​The integral judging circuit 12 receives the first pulse width modulation signal PWMl, and when a first type of pulse in the first pulse width modulation signal PWMl arrives, the integral judging circuit 12 integrates the width of the first type of pulse to generate an integral voltage, and compares the integral voltage with a threshold voltage to generate a shielding enable signal Vblock. That is, the integral judging circuit 12 integrates the width of a pulse with a fixed minimum pulse width smaller than the fixed minimum pulse width of the minimum on time signal Min-on in the first pulse width modulation signal PWMl. It should be noted that the width of only one first type of pulse in the first pulse width modulation signal PWMl is not integrated, but the width of multiple first type of pulses in the first pulse width modulation signal PWMl can be integrated. The integral voltage generated can represent the sum of the widths of all the integrated first type of pulses, i.e. the on time of the power switch to be shielded.

[0036] The pulse shielding circuit 13 receives the second pulse width modulation signal PWM2 and the shielding enable signal Vblock, and when the integral voltage is smaller than the threshold voltage, the pulse shielding circuit 13 shields the pulse with the fixed minimum pulse width in the second pulse width modulation signal PWM2 to generate a third pulse width modulation signal PWM3, which is used to control the rotating speed of the motor 60. In one embodiment, the pulse shielding circuit 13 includes a single-pole double-throw switch controlled by the shielding enable signal Vblock. When the shielding enable signal Vblock is invalid, the second pulse width modulation signal PWM2 is directly output as the third pulse width modulation signal PWM3; when the shielding enable signal Vblock is valid, the third pulse width modulation signal PWM3 is pulled to a reference ground. In one embodiment, the pulse shielding circuit 13 includes a logic gate circuit, and the third pulse width modulation signal PWM3 is output by performing logic operation on the second pulse width modulation signal PWM2 and the reference ground.

[0037] In one embodiment, the threshold voltage is positively correlated with the fixed minimum pulse width of the minimum on time signal Min-on. That is, the wider the fixed minimum pulse width of the minimum on time signal Min-on, the higher the threshold voltage can be set.

[0038] In Figure 5 In the embodiment shown, the present application further discloses a specific circuit example of the integral judging circuit 12, in which the integral judging circuit 12 further receives the third pulse width modulation signal PWM3. It can be understood that there are various forms of circuit structures to integrate the width of the first type of pulse in the first pulse width modulation signal PWMl and to compare the integral voltage with the threshold voltage, and in some embodiments, the third pulse width modulation signal PWM3 does not need to be introduced to realize the function of the integral judging circuit 12. The diagram shown here is only illustrative and does not limit the present application.

[0039] As Figure 5 As shown, the integral judgment circuit 12 is shown to include a first current source I1, a second current source I2, a first voltage source Vpre1, a second voltage source Vpre2, a first switch tube M1, a second switch tube M2, a third switch tube M3, an integral capacitor C1 and an integral comparator CA. The first switch tube M1 has a first end, a second end and a control end, the first end of the first switch tube M1 is coupled to the first current source I1, and the control end of the first switch tube M1 is coupled to the third pulse width modulation signal PWM3. The second switch tube M2 has a first end, a second end and a control end, the first end of the second switch tube M2 is pulled down to ground through the second current source I2, the second end of the second switch tube M2 is coupled to the second end of the first switch tube M1, and the control end of the second switch tube M2 is coupled to the first pulse width modulation signal PWM1. The integral capacitor C1 is coupled between the second end of the second switch tube M2 and a reference ground. The third switch tube M3 has a first end, a second end and a control end, the first end of the third switch tube M3 is coupled to the first voltage source Vpre1, the second end of the third switch tube is coupled to the second end of the second switch tube M2, and the control end of the third switch tube M3 is coupled to the enable signal EN. The integral comparator CA has a first end, a second end and a control end, the first end of the integral comparator CA is coupled to the second voltage source Vpre2, the second end of the integral comparator CA is coupled to the second end of the second switch tube M2, and the output end of the integral comparator CA outputs the shielded enable signal Vblock. Wherein, the above-mentioned threshold voltage is equal to the first voltage source Vpre1 minus the second voltage source Vpre2.

[0040] In one embodiment, the first voltage source Vpre1 is greater than the second voltage source Vpre2. In one embodiment, the first current source I1 is equal to the second current source I2.

[0041] Figure 6 According to an embodiment of the present application Figure 5 The waveform timing diagram of the current correction circuit related parameters. Figure 6 As shown, from top to bottom, the waveform of the third pulse width modulation signal PWM3 and the voltage signal VC1 on the integral capacitor C1 are shown. It should be noted that, in order to more clearly illustrate the principle of the present application and not to obscure the key points, only part of the pulses of the third pulse width modulation signal PWM3 (the pulses equal to the fixed minimum pulse width of the minimum on-time signal Min-on) are shown here, and the pulses of the second pulse width modulation signal PWM2 that are shielded in the third pulse width modulation signal PWM3 are shown with dashed lines. Next, the principle of the circuit correction circuit 10 will be described in combination with Figure 5 and Figure 6 The principle of the circuit correction circuit 10 will be described.

[0042] When the first pulse width modulated signal PWM1 is sent to the pre-processing circuit 11 for processing, the first type of pulse (pulse width less than the fixed minimum pulse width of the minimum on time signal Min-on) in the first pulse width modulated signal PWM1 will be replaced by the pulse of the minimum on time signal Min-on, thus generating the second pulse width modulated signal PWM2.

[0043] At the same time, the EN can be a single pulse signal, which turns on the third switch M3 for a single pulse time and then turns off, so that the voltage VC1 on the integration capacitor C1 is initialized to be equal to the first voltage source Vpre1. At this time, the voltage VC1 on the integration capacitor C1 is greater than the second voltage source Vpre2, and the shield enable signal Vblock output by the integration comparator CA is valid (high level), and the fixed minimum pulse width pulse in the second pulse width modulated signal PWM2 is shielded. At the same time, since the pulse is shielded, the first switch M1 is turned off by the third pulse width modulated signal PWM3, and the second switch M2 is turned on by the first pulse width modulated signal PWM1. During the effective pulse width of the first type of pulse in the first pulse width modulated signal PWM1, the integration capacitor C1 will be discharged through the second switch M2 and the second current source I2, and the voltage VC1 will decrease.

[0044] When the next pulse of the first pulse width modulated signal PWM1 is not the first type of pulse (pulse width greater than the fixed minimum pulse width of the minimum on time signal Min-on), the first switch M1 and the second switch M2 are both turned on, and since the first current source and the second current source are equal, the voltage VC1 on the integration capacitor C1 remains unchanged.

[0045] When the next pulse of the first pulse width modulated signal PWM1 is still the first type of pulse, if the voltage VC1 on the integration capacitor C1 has not decreased to the second voltage source Vpre2, the fixed minimum pulse width pulse in the second pulse width modulated signal PWM2 continues to be shielded, the first switch M1 continues to be turned off, and the second switch M2 is turned on. During the effective pulse width of the first type of pulse, the integration capacitor C1 will continue to be discharged through the second switch M2 and the second current source I2, and the voltage VC1 will continue to decrease.

[0046] The above process is repeated until the voltage VC1 on the integration capacitor C1 decreases to the second voltage source Vpre2, the shield enable signal Vblock output by the integration comparator CA is invalid (low level), and the next fixed minimum pulse width pulse in the second pulse width modulated signal PWM2 is no longer shielded, and the integration ends. In an embodiment, the value of the voltage VC1 decrease is the integration voltage. Figure 6 In the waveform diagram shown, the maximum value of the integration voltage in each shielding period is the difference between the voltage VC1 decreasing to the minimum value and the first voltage source Vpre1, for example, Figure 6 The threshold voltage Vth is the difference between the first voltage source Vpre1 and the second voltage source Vpre2.

[0047] When the first type pulse of the first pulse width modulation signal PWM1 comes again, if the voltage VC1 on the integration capacitor C1 has been lower than the second voltage source Vpre2, the mask enable signal Vblock output by the integration comparator CA is invalid (low level), and the first switch tube M1 and the second switch tube M2 are both turned on. Since the pulse width of the first type pulse of the first pulse width modulation signal PWM1 is smaller than the fixed minimum pulse width of the third pulse width modulation signal PWM3, the turn-on time of the first switch tube M1 is longer than that of the second switch tube M2, and the voltage VC1 on the integration capacitor C1 will rise.

[0048] In the above manner, the pulses with the fixed minimum pulse width in the second pulse width modulation signal PWM2 can be shielded, which can further reduce the motor current. Meanwhile, the current waveform is improved, the current waveform is closer to the expected waveform, the current distortion at low speed of the motor is reduced, the harmonic pollution is reduced, and the performance of the motor at different driving speeds is further improved. In addition, since the threshold voltage Vth is positively correlated with the fixed minimum pulse width, that is, the pulse width integral value of the shielded pulse is positively correlated with the fixed minimum pulse width, the third pulse width modulation signal PWM3 generated after correction can better reflect the control of the real turn-on time on the current. If the real turn-on time to be shielded is exactly set to be equal to the minimum turn-on time of the power switch represented by the fixed minimum pulse width, the energy input is exactly the real energy input demand.

[0049] Further, on the basis of the above embodiment, the embodiment of the present application further provides a current correction method of a direct-current brushless motor, as shown in the flow chart of a driving method of a direct-current brushless motor, the method comprises the following steps S1-S4. Figure 7 The flow chart of the driving method of the direct-current brushless motor, the method comprises the following steps S1-S4.

[0050] In step S1, the first type pulse with a pulse width smaller than the minimum turn-on time signal Min-on in the first pulse width modulation signal PWM1 is replaced by the pulse of the minimum turn-on time signal Min-on to generate the second pulse width modulation signal PWM2. The period of the minimum turn-on time signal Min-on is equal to that of the first pulse width modulation signal PWM1, and the pulse of the minimum turn-on time signal Min-on has a fixed minimum pulse width.

[0051] In step S2, when the first type pulse in the first pulse width modulation signal PWM1 comes, the width of the first type pulse is integrated to generate an integral voltage. In step S3, the integral voltage and the threshold voltage Vth are compared. Step S4, when the integral voltage is less than the threshold voltage Vth, the pulse with the fixed minimum pulse width in the second pulse width modulation signal PWM2 is shielded to generate the third pulse width modulation signal PWM3, wherein the third pulse width modulation signal PWM3 is used to control the rotating speed of the motor 60. It can be understood that when the integral voltage is greater than or equal to the threshold voltage Vth, the pulse with the fixed minimum pulse width in the second pulse width modulation signal PWM2 is no longer shielded.

[0052] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.< / j> < / j>

Claims

1. A current correction circuit for motor drive, characterized in that, The current correction circuit includes: The preprocessing circuit receives the minimum conduction time signal and the first pulse width modulation signal, and replaces the first type of pulses in the first pulse width modulation signal whose pulse width is smaller than that of the minimum conduction time signal with the pulses of the minimum conduction time signal to generate the second pulse width modulation signal. The period of the minimum conduction time signal is equal to the period of the first pulse width modulation signal, and the pulses of the minimum conduction time signal have a fixed minimum pulse width. The integral judgment circuit receives the first pulse width modulation signal. When the first type of pulse in the first pulse width modulation signal arrives, the integral judgment circuit integrates the width of the first type of pulse to generate an integral voltage, and compares the integral voltage with the threshold voltage to generate a shielding enable signal. The pulse shielding circuit receives a second pulse width modulation signal and a shielding enable signal. When the integrated voltage is less than the threshold voltage, the pulse shielding circuit will shield the pulses in the second pulse width modulation signal whose pulse width is equal to the fixed minimum pulse width to generate a third pulse width modulation signal. The third pulse width modulation signal is used to control the speed of the motor.

2. The current correction circuit according to claim 1, characterized in that, The threshold voltage is positively correlated with the fixed minimum pulse width.

3. The current correction circuit according to claim 1, characterized in that, The integration judgment circuit will also receive a third pulse width modulation signal, and the integration judgment circuit includes: First current source; Second current source; First voltage source; Second voltage source; The first switching transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first switching transistor is coupled to a first current source, and the control terminal of the first switching transistor is coupled to a third pulse width modulation signal. The second switch has a first terminal, a second terminal and a control terminal. The first terminal of the second switch is pulled down to ground through a second current source. The second terminal of the second switch is coupled to the second terminal of the first switch. The control terminal of the second switch is coupled to a first pulse width modulation signal. An integrating capacitor is coupled between the second terminal of the second switching transistor and the reference ground. The third switch has a first terminal, a second terminal and a control terminal. The first terminal of the third switch is coupled to a first voltage source, the second terminal of the third switch is coupled to the second terminal of the second switch, and the control terminal of the third switch is coupled to an enable signal. An integral comparator has a first terminal, a second terminal, and a control terminal. The first terminal of the integral comparator is coupled to a second voltage source, and the second terminal of the integral comparator is coupled to the second terminal of a second switching transistor. The output terminal of the integral comparator outputs a shielding enable signal. The threshold voltage is equal to the first voltage source minus the second voltage source.

4. The current correction circuit according to claim 3, characterized in that, The second current source is equal to the first voltage source.

5. The current correction circuit according to claim 1, characterized in that, The preprocessing circuit includes: The OR gate is used to perform a logical OR operation on the first pulse width modulation signal and the minimum on-time signal to generate the second pulse width modulation signal.

6. The current correction circuit according to claim 1, characterized in that, The first pulse width modulation signal is provided by an external MCU.

7. The current correction circuit according to claim 1, characterized in that, The first pulse width modulation signal is generated by the pulse width modulation signal generation circuit based on the Hall signal, wherein the Hall signal is generated by the Hall sensor and is used to characterize the motor commutation information.

8. The current correction circuit according to claim 7, characterized in that, The pulse width modulation signal generation circuit includes: The modulation circuit receives the Hall signal and modulates the Hall signal into a variable voltage signal with the desired waveform; A triangular wave generator, used to generate triangular wave signals with a fixed period; and A voltage comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the voltage comparator receives the triangular wave signal, the second input terminal of the voltage comparator receives the variable voltage signal, the voltage comparator compares the variable voltage signal with the triangular wave signal, and outputs a second pulse width modulation signal at the output terminal.

9. A drive circuit for an electric motor, characterized in that, include: A power switching unit, comprising multiple power switching transistors; The current correction circuit as described in any one of claims 1-8 is used to generate a third pulse width modulation signal; A logic driving circuit is used to receive the third pulse width modulation signal and generate a switch driving signal according to the third pulse width modulation signal. The switch driving signal is used to drive the turn-on and turn-off of each power switch and control the turn-on time and turn-off time of each power switch to adjust the motor speed.

10. A current correction method for motor drive, characterized in that, The current correction method includes: The first type of pulse with a pulse width smaller than that of the minimum conduction time signal in the first pulse width modulation signal is replaced with the pulse of the minimum conduction time signal to generate the second pulse width modulation signal. The period of the minimum conduction time signal is equal to the period of the first pulse width modulation signal, and the pulse of the minimum conduction time signal has a fixed minimum pulse width. When the first type of pulse in the first pulse width modulation signal arrives, the width of the first type of pulse is integrated to generate an integrated voltage; Determine the magnitude of the integral voltage and the threshold voltage; When the integral voltage is less than the threshold voltage, the pulses in the second pulse width modulation signal whose pulse width is equal to the fixed minimum pulse width are shielded to generate a third pulse width modulation signal, wherein the third pulse width modulation signal is used to control the speed of the motor.

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