Power control circuit and input / output circuitry

Abstract

This application discloses a power control circuit and an input / output circuit system. This circuit solves the leakage current problem caused by excessive gate-source voltage difference of PMOS transistors in the POC circuits of related technologies by employing the coordinated operation of multi-stage buck and multi-stage boost modules. The power control circuit of this application adopts a multi-stage buck and boost architecture, controlling the gate-source voltage difference of PMOS transistors through voltage stages, replacing the design of a large number of PMOS transistors connected in series in related technologies, thus reducing circuit area. The multi-stage boost module adopts a complementary MOS transistor structure (each stage includes a PMOS transistor and an NMOS transistor). The power control circuit of this application achieves step-by-step voltage control and supports configuration according to different application scenarios. An integrated Schmitt trigger filters power supply noise, and the trigger logic is matched with the number of stages of the multi-stage buck module to achieve signal transmission.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a power control circuit and an input / output circuit system. Background Technology

[0002] In integrated circuit design, input / output (I / O) circuits typically have two power domains: the chip's internal power domain (Core power domain) and the chip's external power domain (I / O power domain). Generally, the voltage of the Core power domain is lower than that of the I / O power domain. When the I / O circuit operates in output mode, logic signals generated by the Core power domain control the I / O power domain, ensuring that its output terminals (PADs) output the correct signals.

[0003] In conventional I / O circuit design, when the I / O power domain is powered on but the Core power domain is not, two main problems arise: First, the Core power domain cannot generate the correct logic signal, resulting in an uncertain output signal at the I / O circuit output terminal PAD; second, the driving MOS device connected to the PAD may be in an intermediate state, causing a large static current in the circuit. Summary of the Invention

[0004] The purpose of this application is to provide a power control circuit and an input / output circuit system to solve the problems of uncertain output signals and excessive static power consumption of IO circuits in related technologies.

[0005] According to a first aspect of this application, embodiments of this application provide a power control circuit, which includes:

[0006] A multi-stage buck module, each stage of which includes a diode, is used to gradually reduce the IO power domain voltage to an intermediate voltage that matches the Core power domain voltage.

[0007] A multi-stage boost module is coupled to the multi-stage buck module, and the multi-stage boost module is used to gradually restore the intermediate voltage to the IO power domain voltage;

[0008] A trigger module is provided, wherein the input terminal of the trigger module receives the output signal of the multi-stage boost module, and the output terminal of the trigger module generates a power state control signal based on the output signal. The power state control signal is used to control the output terminal of the output drive circuit to lock to a certain state when the Core power domain is not powered on, wherein the control input terminal of the output drive circuit is coupled to the output terminal of the power control circuit.

[0009] In some possible implementations, the number of stages of the multi-stage buck module is determined based on the difference between the IO power domain voltage and the Core power domain voltage.

[0010] In some possible implementations, the multi-stage buck module is formed by connecting the input and output terminals of each stage buck module in series. The input terminal of the first-stage buck module is coupled to the voltage terminal of the IO power domain. Each stage boost module includes an input terminal, an output terminal, a power terminal, and a ground terminal. The multi-stage boost module is formed by connecting the input and output terminals of adjacent boost modules in series. The power terminal of the first-stage boost module is coupled to the output terminal of the last-stage buck module. The input terminal of the first-stage boost module is coupled to the voltage of the Core power domain. The power terminal of the last-stage boost module is coupled to the input terminal of the first-stage buck module. The output terminal of the last-stage boost module is coupled to the input terminal of the trigger module. The power terminals of the intermediate boost modules are coupled to the coupling points of the two adjacent buck modules. The ground terminals of each boost module are coupled.

[0011] In some possible implementations, each boost module includes a PMOS transistor and a first NMOS transistor; the source of the PMOS transistor serves as the power supply terminal of the corresponding boost module, the gate of the PMOS transistor is coupled to the gate of the first NMOS transistor of the same stage as the input terminal of the corresponding boost module, the source of the first NMOS transistor serves as the ground terminal of the corresponding boost module and is coupled to ground potential, and the drain of the first NMOS transistor is coupled to the drain of the PMOS transistor to form the output terminal of the corresponding boost module.

[0012] In some possible implementations, each boost module further includes a second NMOS transistor, the gate of which is coupled to the input terminal of the corresponding stage, the drain of which is coupled to the source of the first NMOS transistor, and the source of which serves as the ground terminal of the corresponding boost module.

[0013] In some possible implementations, the voltage difference borne by each buck module is determined based on the ratio of the difference between the IO power domain voltage and the Core power domain voltage to the number of stages of the multi-stage buck module, in order to control the gate-source voltage difference of the PMOS transistor in the corresponding boost module.

[0014] In some possible implementations, the triggering logic of the trigger module is matched with the number of stages of the multi-stage buck module. When the number of stages of the multi-stage buck module is odd, the trigger module is configured with a positive trigger, and when the number of stages of the multi-stage buck module is even, the trigger module is configured with a negative trigger.

[0015] In some possible implementations, the power control circuit further includes: a protection module, the protection module including at least one resistor; when the protection module consists of multiple resistors, the multiple resistors are connected in series or in parallel, a first terminal of the protection module is coupled to the Core power domain voltage terminal, and a second terminal is coupled to the input terminal of the multi-stage boost module.

[0016] In some possible implementations, when the Core power domain is not powered on, the power state control signal is at a first logic level, used to lock the output terminal of the output drive circuit to a defined state; when the Core power domain is powered on, the power state control signal is at a second logic level, allowing the output drive circuit to operate normally; wherein, the first logic level is greater than or equal to a first threshold voltage, and the second logic level is less than or equal to a second threshold voltage.

[0017] According to a second aspect of this application, embodiments of this application provide an input / output circuit system, comprising:

[0018] The output drive circuit has a control input terminal and an output terminal;

[0019] As described in the embodiments of this application, the output terminal of the trigger module of the power control circuit is coupled to the control input terminal of the output drive circuit.

[0020] The power state control signal of the power control circuit is used to control the output drive circuit to lock the output terminal of the output drive circuit to a certain state when the Core power domain is not powered on and the IO power domain is powered on.

[0021] This application provides a power control circuit and input / output circuit system. This circuit, through the coordinated operation of multi-stage buck and boost modules, solves the leakage current problem caused by excessive gate-source voltage difference of PMOS transistors in related POC circuits, thereby reducing static power consumption. The circuit employs a multi-stage buck and boost architecture, controlling the gate-source voltage difference of PMOS transistors through voltage levels, replacing the complex structure of numerous PMOS transistors connected in series in related technologies, reducing circuit area. Furthermore, the matching design of step-by-step voltage division and boosting adapts to different voltage domain scenarios and supports customized configurations. In addition, the Schmitt trigger integrated in the power control circuit filters power supply noise, enhances signal stability, and adjusts the trigger logic according to the number of stages in the multi-stage buck module to adapt to different voltage difference environments. The protection module couples the Core power domain voltage terminal and the input terminal of the multi-stage boost module through resistors to suppress voltage transients, thereby improving the circuit's stability in complex power supply environments. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a circuit diagram of the power-on control circuit for related technologies.

[0024] Figure 2 for Figure 1 A schematic diagram showing the specific connection of the series PMOS transistors.

[0025] Figure 3 This is a circuit diagram of the power control circuit in one embodiment of this application.

[0026] Figure 4 This is a schematic diagram of an input / output circuit system in one embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] In integrated circuit design, input / output (I / O) circuits are typically configured with two power domains: an internal power domain (Core power domain) and an external power domain (I / O power domain). The voltage (VDD) of the Core power domain is typically lower than the voltage (VDDPST) of the I / O power domain. When the I / O circuit operates in output mode, its control logic is generated by the Core power domain, and the signal state of the output terminal (PAD) is controlled by the driver circuitry of the I / O power domain.

[0029] However, when the IO power domain is powered on but the Core power domain is not powered on, the Core power domain cannot provide an effective control signal, which leads to the following problems: on the one hand, the output terminal (PAD) of the IO circuit may be in a floating or intermediate level state, causing abnormal function of downstream circuits; on the other hand, the MOS device driving the PAD may be in a subthreshold conduction state (i.e., intermediate state), generating leakage current and causing a significant increase in power consumption.

[0030] To solve the above problems, the traditional solution uses a power-on control (POC) circuit 1', whose basic structure includes an inverter 10' and a Schmitt trigger 30' (see...). Figure 1Its working principle is as follows: When the Core power domain is not powered on (VDD=0, where 0 represents a logic low level), the POC output is high (POC=1), and the I / O circuit output is locked to a defined state (such as high configuration or fixed level); when the Core power domain is powered on (VDD=1, where 1 represents a logic high level), the POC output is low (POC=0), and the I / O circuit outputs a signal normally. It should be noted that the PMOS transistor in inverter 10'... Figure 1 Its detailed structure is not shown in detail, but is symbolically represented by a box.

[0031] However, traditional POC circuits have the following drawbacks: a large voltage difference between the Core power domain and the I / O power domain (e.g., VDD = 1.8V, VDDPST = 5V), preventing the PMOS transistor in inverter 10' from being completely turned off. Specifically, when VDD is high (here, 1.8V), the gate of the PMOS transistor is connected to VDD (1.8V), and the source is connected to VDDPST (5V), therefore the gate-source voltage V... GS =1.8V - 5V = -3.2V; because V GS = -3.2V is still less than the threshold voltage -0.7V, so the PMOS transistor cannot be completely turned off and remains conducting. At the same time, the NMOS transistor is also conducting because its gate voltage of 1.8V is greater than its threshold voltage, forming a leakage path from VDDPST to ground and generating high leakage current.

[0032] To mitigate leakage current issues, related technologies have proposed a solution involving connecting a large number of PMOS transistors in series, such as... Figure 1 As shown in module 11'. Figure 2 The specific structure of multiple PMOS transistors connected in series in module 11' is further illustrated in detail, where G represents the common gate of the series PMOS transistors, D represents the drain of the first PMOS transistor, S represents the source of the last PMOS transistor, and B represents the common substrate of the series PMOS transistors. Leakage current is reduced by increasing the equivalent resistance, for example, by connecting up to 100 PMOS transistors in series. However, this approach presents the following problems: hundreds of PMOS transistors in series occupy a large chip area, and the dense layout complicates the signal path; the accumulation of parasitic capacitance and resistance reduces circuit response speed and increases dynamic power consumption and signal delay; furthermore, manufacturing deviations can easily lead to uneven distribution of the threshold voltage of the series PMOS transistors, further exacerbating the risk of leakage.

[0033] To address the aforementioned issues, this application proposes an innovative power control circuit that solves the leakage current problem caused by the excessive gate-source voltage difference of the PMOS transistor through the coordinated operation of multi-stage buck and multi-stage boost modules, while also reducing circuit area overhead and power consumption.

[0034] like Figure 3 As shown, the power control circuit 1 of this application embodiment includes a multi-stage buck module 10, a multi-stage boost module 20, and a trigger module 30.

[0035] In this embodiment, the multi-stage buck module 10 is used to gradually reduce the IO power domain voltage to an intermediate voltage that matches the Core power domain voltage, and output it to the multi-stage boost module 20. The IO power domain voltage terminal is labeled VDDPST, and the Core power domain voltage terminal is labeled VDD, and the same applies below.

[0036] In this embodiment, the multi-stage buck module 10 may include multiple cascaded buck modules, each of which includes a diode. The number of stages in the multi-stage buck module 10 is determined based on the difference between the IO power domain voltage and the Core power domain voltage. The multi-stage buck module 10 is formed by connecting the input and output terminals of each stage of the buck module in series. The input terminal of the first-stage buck module is coupled to the IO power domain voltage terminal. The output terminal of each stage of the multi-stage buck module 10 serves as a different output terminal, outputting an intermediate voltage that has been stepped down by the corresponding number of stages.

[0037] Taking a configuration including a 3-stage buck module as an example, the multi-stage buck module 10 may include 3 buck modules connected in series. It should be noted that in this embodiment, the first-stage buck module corresponds to the first-stage buck module, the last-stage buck module corresponds to the third-stage buck module, and the intermediate-stage buck module corresponds to the second-stage buck module. The first-stage buck module includes diode D1, the second-stage buck module includes diode D2, and the third-stage buck module includes diode D3. The input terminal (anode of D1) of the first-stage buck module (i.e., the first-stage buck module) is coupled to the IO power domain voltage terminal VDDPST. The output terminal (cathode of D1) of the first-stage buck module is coupled to the input terminal (anode of D2) of the second-stage buck module (i.e., the intermediate-stage buck module), and the output terminal (cathode of D2) of the second-stage buck module is coupled to the input terminal (anode of D3) of the third-stage buck module (i.e., the last-stage buck module). The output terminals of each step-down module are as follows: the output terminal of the third-stage step-down module (i.e., the final-stage step-down module) (i.e., the cathode of D3) serves as the first output terminal P1; the output terminal of the second-stage step-down module (i.e., the intermediate-stage step-down module) (i.e., the cathode of D2) serves as the second output terminal P2; and the output terminal of the first-stage step-down module (i.e., the initial-stage step-down module) (i.e., the cathode of D1) serves as the third output terminal P3. The forward voltage drop of each diode (D1, D2, D3) is approximately 0.7V to 1V, and the voltage is gradually reduced through cascading.

[0038] The specific buck module stage configuration is as follows: The required number of stages is determined based on the difference between the IO power domain voltage and the Core power domain voltage. The voltage difference borne by each buck module (here, the diode in the buck module) is determined based on the ratio of the difference between the IO power domain voltage and the Core power domain voltage to the number of stages in the multi-stage buck module. This ensures that the output terminals of each buck module output corresponding intermediate voltages, thereby controlling the gate-source voltage difference of the PMOS transistor in the corresponding boost module. This reduces leakage current and lowers static power consumption when the Core power domain is powered on. In the first example, when VDDPST is 5V and VDD is 1.8V, the voltage difference is approximately 3.2V. In this case, the number of buck modules in the multi-stage buck module 10 is selected as 3 stages. In the second example, when VDDPST is 5V and VDD is 3.3V, the voltage difference is approximately 1.7V. In this case, the number of buck modules in the multi-stage buck module 10 is selected as 2 stages. In the third example scenario, when VDDPST is 1.8V and VDD is 1.2V, the voltage difference is approximately 0.6V. In this case, the number of stages in the multi-stage buck module 10 is selected as 1. Thus, by configuring an appropriate number of cascaded buck modules based on the voltage difference, a gradual reduction in voltage can be achieved, thereby resolving the leakage current problem caused by the excessive gate-source voltage difference of the PMOS transistor.

[0039] In this embodiment, the multi-stage boost module 20 is coupled to the multi-stage buck module 10. The multi-stage boost module 20 is used to gradually restore the intermediate voltage to the IO power domain voltage. Each boost module includes an input terminal, an output terminal, a power supply terminal, and a ground terminal. The multi-stage boost module 20 is formed by connecting the input and output terminals of adjacent boost modules in series. Specifically, the power supply terminal of the first-stage boost module is coupled to the output terminal of the last-stage buck module, the input terminal of the first-stage boost module is coupled to the Core power domain voltage, the power supply terminal of the last-stage boost module is coupled to the input terminal of the first-stage buck module, the output terminal of the last-stage boost module is coupled to the input terminal of the trigger module 30, the power supply terminals of the intermediate boost modules are coupled to the coupling points of the two adjacent buck modules, and the ground terminals of each boost module are coupled.

[0040] Taking a configuration that includes 4 boost modules and 3 buck modules as an example, it should be noted that in this embodiment, the first boost module corresponds to the first boost module, the last boost module corresponds to the fourth boost module, and the intermediate boost modules correspond to the second and third boost modules. The power supply terminal of the first-stage boost module 21 (i.e., the first-stage boost module) of the multi-stage boost module 20 is coupled to the first output terminal P1 of the multi-stage buck module 10, and the input terminal of the first-stage boost module 21 is coupled to the Core power domain voltage terminal VDD; the input terminal of the second-stage boost module 22 (i.e., one of the intermediate-stage boost modules) is coupled to the output terminal of the first-stage boost module 21, and the power supply terminal of the second-stage boost module 22 is coupled to the second output terminal P2 of the multi-stage buck module 10; the input terminal of the third-stage boost module 23 (i.e., one of the intermediate-stage boost modules) is coupled to the output terminal of the second-stage boost module 22, and the power supply terminal of the third-stage boost module 23 is coupled to the third output terminal P3 of the multi-stage buck module 10; the input terminal of the fourth-stage boost module 24 (i.e., the final-stage boost module) is coupled to the output terminal of the third-stage boost module 23, and the power supply terminal of the fourth-stage boost module 24 is coupled to the IO power domain voltage terminal VDDPST, thus realizing a one-to-one correspondence between each stage. The multi-stage boost module 20 includes multiple boost modules, with each boost module connected in sequence. By matching the voltage of the boost module with the corresponding buck module, the corresponding intermediate voltage is gradually restored to the IO power domain voltage.

[0041] In this embodiment, each boost module includes a PMOS transistor and a first NMOS transistor. The source of the PMOS transistor serves as the power supply terminal of the corresponding boost module, the gate of the PMOS transistor is coupled to the gate of the first NMOS transistor of the same stage to serve as the input terminal of the corresponding boost module, the source of the first NMOS transistor serves as the ground terminal of the corresponding boost module and is coupled to ground potential, and the drain of the first NMOS transistor is coupled to the drain of the PMOS transistor to form the output terminal of the corresponding boost module.

[0042] In some embodiments, each boost module further includes a second NMOS transistor, the gate of which is coupled to the input terminal of the corresponding stage, the drain of which is coupled to the source of the first NMOS transistor, and the source of which serves as the ground terminal of the corresponding boost module.

[0043] In this embodiment, in each stage of the multi-stage boost module 20, the driving voltage of the common gate of the PMOS and NMOS transistors is adjusted based on the output signal of the previous stage boost module to achieve voltage conversion and control.

[0044] In the above embodiments, the multi-stage buck module 10 and the multi-stage boost module 20 achieve the following technical effects through their collaborative design: On the one hand, the multi-stage buck module 10 adopts a series diode voltage divider design, which reduces the gate-source voltage difference of the PMOS transistors in the multi-stage boost module 20 when the Core power domain is powered on, thereby reducing leakage current and static power consumption; on the other hand, the collaborative architecture of the multi-stage buck module 10 and the multi-stage boost module 20, through voltage graded control, replaces the design of a large number of PMOS transistors in series in related technologies, reducing the circuit area. The multi-stage boost module 20 adopts a complementary MOS transistor structure (each boost module includes a PMOS transistor and a first NMOS transistor) to achieve the step-by-step voltage recovery function.

[0045] To better understand the structure of the multi-stage boost module 20 of this application, the specific connection relationships of each boost module are described in detail below. Each boost module includes a PMOS transistor, a first NMOS transistor, and a second NMOS transistor.

[0046] Specifically, the source of PMOS transistor MP1 in the first-stage boost module 21 serves as the power supply terminal of the first-stage boost module 21 and is coupled to the first output terminal P1 of the multi-stage buck module 10 to receive the bucked voltage signal. Simultaneously, its gate is coupled to the gate of the first NMOS transistor MN1 in the same stage, serving as the input terminal of the first-stage boost module 21. The drain of PMOS transistor MP1 is coupled to the drain of the first NMOS transistor MN1, forming the output terminal O1 of the first-stage boost module 21. The source of the first NMOS transistor MN1 is coupled to the drain of the second NMOS transistor MN2 in the same stage. The gate of the second NMOS transistor MN2 is coupled to the input terminal of the first-stage boost module 21, and the source of the second NMOS transistor MN2 serves as the ground terminal of the first-stage boost module 21 and is grounded.

[0047] In this embodiment, the second-stage boost module 22 follows a similar topology. The source of its PMOS transistor MP2 serves as the power supply terminal of the second-stage boost module 22, coupled to the second output terminal P2. Its gate is coupled to the gate of the first-stage NMOS transistor MN3, serving as the input terminal of the second-stage boost module 22. This input terminal receives the signal from the output terminal O1 of the first-stage boost module 21 as the drive voltage input. The drain is coupled to the drain of the first-stage NMOS transistor MN3, forming the output terminal O2 of the second-stage boost module 22. The source of the first NMOS transistor MN3 is coupled to the drain of the second-stage NMOS transistor MN4, and the gate of the second NMOS transistor MN4 is coupled to the input terminal of the second-stage boost module 22. The source of the second NMOS transistor MN4 serves as the ground terminal of the second-stage boost module 22 and is grounded.

[0048] In this embodiment, the third-stage boost module 23 follows a similar topology. The source of its PMOS transistor MP3 serves as the power supply terminal of the third-stage boost module 23, coupled to the third output terminal P3. Its gate is coupled to the gate of the first NMOS transistor MN5 in the same stage, serving as the input terminal of the third-stage boost module 23. This input terminal receives the signal from the output terminal O2 of the second-stage boost module 22 as the drive voltage input. The drain is coupled to the drain of the first NMOS transistor MN5 in the same stage, forming the output terminal O3 of the third-stage boost module 23. The source of the first NMOS transistor MN5 is coupled to the drain of the second NMOS transistor MN6 in the same stage. The gate of the second NMOS transistor MN6 is coupled to the input terminal of the third-stage boost module 23, and the source of the second NMOS transistor MN6 serves as the ground terminal of the third-stage boost module 23 and is grounded.

[0049] In this embodiment, the source of PMOS transistor MP4 in the fourth-stage boost module 24 serves as the power supply terminal of the fourth-stage boost module 24, coupled to the IO power domain voltage terminal VDDPST, providing the IO power domain voltage. The gate of PMOS transistor MP4 is coupled to the gate of the first NMOS transistor MN7, serving as the input terminal of the fourth-stage boost module 24 and receiving the output signal from the third-stage boost module 23. The drain of MP4 is coupled to the drain of the first NMOS transistor MN7, forming the output terminal O4 of the fourth-stage boost module 24. This output terminal O4 serves as the output terminal of the entire multi-stage boost module 20 and is directly connected to the input terminal Q of the trigger module 30. The source of the first NMOS transistor MN7 is coupled to the drain of the second NMOS transistor MN8 in the same stage. The gate of the second NMOS transistor MN8 is coupled to the input terminal of the fourth-stage boost module 24. The source of the second NMOS transistor MN8 serves as the ground terminal of the fourth-stage boost module 24 and is coupled to ground potential, completing the signal link of the entire multi-stage boost module 20.

[0050] It should be noted that, in some optional embodiments, each stage of the boost module may contain more than one PMOS transistor and NMOS transistor, and may include multiple parallel or series MOS transistors to meet the threshold requirements of the trigger module for the VDD identification voltage.

[0051] The input terminal Q of the trigger module 30 receives the output signal from the multi-stage boost module 20, and its output terminal O5 generates a power state control signal (i.e., a POC signal) based on this signal. It should be noted that in this document, the power state control signal refers to a control signal associated with the power state. The trigger module 30 includes a Schmitt trigger, whose power supply terminal is coupled to the I / O power domain voltage terminal. The Schmitt trigger is used to filter power supply noise and has anti-interference characteristics.

[0052] The triggering logic of trigger module 30 is matched with the number of stages of multi-stage buck module 10. When the number of stages of multi-stage buck module 10 is odd, trigger module 30 is configured as a positive trigger; when the number of stages of multi-stage buck module 10 is even, trigger module 30 is configured as a negative trigger. Figure 3 In the embodiment shown, the multi-stage buck module 10 has 3 stages, and the trigger module 30 is configured as a positive trigger.

[0053] In one embodiment, when the multi-stage buck module 10 is configured with an odd number of buck stages (i.e., an odd number of diodes), the trigger module 30 uses forward triggering logic. When the Core power domain is not powered on, the output power state control signal is at a first logic level, which locks the output drive circuit to a defined state (e.g., a high impedance state). The first logic level is greater than or equal to a first threshold voltage, i.e., the first logic level is high. When the multi-stage buck module 10 is configured with an even number of buck stages (i.e., an even number of diodes), the trigger module 30 uses reverse triggering logic, maintaining the same control effect.

[0054] After the Core power domain is powered on, the output power status control signal is at the second logic level (where the second logic level is less than or equal to the second threshold voltage, i.e., the second logic level is low), releasing the control and restoring the output drive circuit 2 to normal operating state. It should be noted that the control input terminal of the output drive circuit 2 is coupled to the output terminal of the power control circuit 1, such as... Figure 4 As shown, see the description below for details.

[0055] In such Figure 3 In the embodiment shown, the trigger module 30 adopts a Schmitt trigger structure, and the specific connection relationship is as follows.

[0056] Specifically, the source of PMOS transistor MP5 is coupled to the IO power supply voltage terminal VDDPST, providing a high-potential input. Its gate receives the final output signal from the multi-stage boost module 20, and its drain is coupled to the source of PMOS transistor MP6. The gate of PMOS transistor MP6 is coupled to the gates of PMOS transistor MP5, NMOS transistor MN9, and NMOS transistor MN10. The drains of PMOS transistor MP6 and NMOS transistor MN9 are coupled to form output terminal O5, generating a POC signal, which controls the output state of output drive circuit 2. Output terminal O5 is also coupled to the gates of PMOS transistor MP7 and NMOS transistor MN11, forming a feedback path.

[0057] Furthermore, the gate of NMOS transistor MN9 receives the same input signal as PMOS transistor MP5 to maintain logic consistency, and its source is coupled to the drain of NMOS transistor MN10. The gate of NMOS transistor MN10 is coupled together with the gates of PMOS transistors MP5 and MP6, and its source is grounded, forming a current pull-down path.

[0058] The circuit design also includes a supplementary control unit, comprising a PMOS transistor MP7 and an NMOS transistor MN11. The gate of PMOS transistor MP7 receives the POC signal from the drain of PMOS transistor MP6, its source is coupled to the source of PMOS transistor MP6, and its drain is coupled to ground. The gate of NMOS transistor MN11 is coupled to the gate of PMOS transistor MP7, receives the POC signal to achieve coordinated control, its drain is coupled to the IO power supply voltage VDDPST, and its source is coupled to the source of NMOS transistor MN9, together forming the circuit structure of a Schmitt trigger.

[0059] Continue reading Figure 3 As shown, the power control circuit 1 of this application includes a multi-stage buck module 10, a multi-stage boost module 20, and a trigger module 30, and also includes a protection module 40. The protection module 40 includes at least one resistor. In this embodiment, the protection module includes multiple resistors (R1, R2, R3) connected in parallel; however, in other embodiments, the multiple resistors may be connected in series. The first terminal of the protection module 40 is coupled to the Core power domain voltage terminal VDD, and the second terminal is coupled to the input terminal of the multi-stage boost module 20. The protection module 40 suppresses voltage transients and prevents damage to the MOSFET.

[0060] Based on the above structural design, researchers conducted a series of simulation experiments and performance evaluations. Regarding power consumption (using quiescent current as an indicator), when the Core power domain is powered on, the quiescent current of the circuit in this application is 19nA, while the quiescent current of related technologies with hundreds of PMOS transistors in series is 729nA, representing a current reduction of approximately 97%. This helps reduce chip energy consumption and improve thermal performance and battery life. In terms of circuit area, the circuit area of ​​this application is 200μm. 2 Compared to the 450μm of related technical solutions 2 The area is reduced by approximately 56%, which helps to improve chip integration and reduce manufacturing costs. In terms of electrical performance, the inversion voltage of the POC circuit in this application is 0.99V, which is close to the value of 1.02V in related technologies, meeting design standard requirements. Through optimized structure and Schmitt trigger design, the circuit in this application has anti-interference characteristics and signal stability.

[0061] like Figure 4As shown, this application also provides an input / output circuit system 100 (hereinafter referred to as the system), which includes an output drive circuit 2 and a power control circuit 1. The output drive circuit 2 has a control input terminal 21 and an output terminal 22, while the specific structure of the power control circuit 1 is as described above and will not be repeated here.

[0062] The output terminal O5 (i.e., the output POC signal) of the trigger module 30 of the power control circuit 1 is coupled to the control input terminal 21 of the output drive circuit 2. When the power state control signal (POC signal) of the power control circuit 1 is not powered on in the Core power domain and the IO power domain is powered on, it controls the output drive circuit 2 to lock the output terminal 22 to a certain state.

[0063] Specifically, the output drive circuit 2 is an interface circuit located between the IO power domain and the Core power domain, including an output stage circuit that drives the high and low level signals of the PAD terminal. In the input / output circuit system 100, when the system is in the power-on process, if the IO power domain powers on before the Core power domain, the power control circuit 1 generates a power state control signal (POC signal) through the coordinated operation of the multi-stage buck module 10 and the multi-stage boost module 20. This signal is transmitted to the control input terminal 21 of the output drive circuit 2 via the output terminal of the trigger module 30, locking the output terminal (i.e., the PAD terminal) 22 to a certain state (e.g., a high impedance state).

[0064] In this embodiment, the input / output circuit system 100 uses the power control circuit 1 to control the MOS device of the output drive circuit 2 to not be in the intermediate conduction state when the Core power domain is not powered on, by utilizing the cooperative operation of the multi-stage buck module 10 and the multi-stage boost module 20, thereby reducing leakage current and keeping the system 100 in a deterministic state.

[0065] In this embodiment, system 100 adapts to different voltage domain scenarios through a step-by-step voltage divider and boost matching design, supporting configuration according to application scenarios. This system employs a multi-stage buck and boost architecture, controlling the gate-source voltage difference of PMOS transistors through voltage gradation, replacing the design of a large number of PMOS transistors connected in series in related technologies, reducing circuit area, improving chip integration, and lowering the power consumption of portable electronic devices.

[0066] In this embodiment, the system reduces signal uncertainty during power-on by implementing lockout control on output terminal 22, enabling the system to operate stably under different power supply environments. System 100 is suitable for applications requiring high power consumption and stability, such as mobile communication devices, medical electronic products, and IoT terminal devices.

[0067] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0068] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power supply control circuit, characterized in that, include: A multi-stage buck module, each stage of which includes a diode, is used to gradually reduce the IO power domain voltage to an intermediate voltage that matches the Core power domain voltage. A multi-stage boost module is coupled to the multi-stage buck module, and the multi-stage boost module is used to gradually restore the intermediate voltage to the IO power domain voltage; A trigger module, wherein the input terminal of the trigger module receives the output signal of the multi-stage boost module, and the output terminal of the trigger module generates a power state control signal based on the output signal. The power state control signal is used to control the output terminal of the output drive circuit to lock to a certain state when the Core power domain is not powered on, wherein the control input terminal of the output drive circuit is coupled to the output terminal of the power control circuit. The multi-stage buck module is formed by connecting the input and output terminals of each stage buck module in series, and the input terminal of the first-stage buck module is coupled to the voltage terminal of the IO power domain. Each boost module includes an input terminal, an output terminal, a power supply terminal, and a ground terminal. The multi-stage boost modules are formed by connecting the input and output terminals of adjacent boost modules in series. The power supply terminal of the first-stage boost module is coupled to the output terminal of the last-stage buck module. The input terminal of the first-stage boost module is coupled to the Core power domain voltage. The power supply terminal of the last-stage boost module is coupled to the input terminal of the first-stage buck module. The output terminal of the last-stage boost module is coupled to the input terminal of the trigger module. The power supply terminals of the intermediate boost modules are coupled to the coupling points of the two adjacent buck modules. The ground terminals of each boost module are coupled.

2. The power control circuit as described in claim 1, characterized in that, The number of stages in the multi-stage buck module is determined based on the difference between the IO power domain voltage and the Core power domain voltage.

3. The power control circuit as described in claim 1, characterized in that, Each boost module includes a PMOS transistor and a first NMOS transistor; The source of the PMOS transistor serves as the power supply terminal of the corresponding boost module. The gate of the PMOS transistor is coupled to the gate of the first NMOS transistor of the same stage to serve as the input terminal of the corresponding boost module. The source of the first NMOS transistor serves as the ground terminal of the corresponding boost module and is coupled to ground potential. The drain of the first NMOS transistor is coupled to the drain of the PMOS transistor to form the output terminal of the corresponding boost module.

4. The power control circuit as described in claim 3, characterized in that, Each boost module also includes a second NMOS transistor. The gate of the second NMOS transistor is coupled to the input terminal of the corresponding stage, the drain of the second NMOS transistor is coupled to the source of the first NMOS transistor, and the source of the second NMOS transistor serves as the ground terminal of the corresponding boost module.

5. The power control circuit as described in claim 3, characterized in that, The voltage difference handled by each buck module is determined based on the ratio of the difference between the IO power domain voltage and the Core power domain voltage to the number of stages in the multi-stage buck module, in order to control the gate-source voltage difference of the PMOS transistor in the corresponding boost module.

6. The power control circuit as described in claim 1, characterized in that, The triggering logic of the trigger module is matched with the number of stages of the multi-stage buck module. When the number of stages of the multi-stage buck module is odd, the trigger module is configured with a positive trigger. When the number of stages of the multi-stage buck module is even, the trigger module is configured with a negative trigger.

7. The power control circuit as described in claim 1, characterized in that, Also includes: The protection module includes at least one resistor; When the protection module consists of multiple resistors, the multiple resistors are connected in series or in parallel. The first end of the protection module is coupled to the voltage terminal of the Core power domain, and the second end is coupled to the input terminal of the multi-stage boost module.

8. The power control circuit as described in claim 1, characterized in that, When the Core power domain is not powered on, the power state control signal is at a first logic level, used to lock the output terminal of the output drive circuit to a certain state; when the Core power domain is powered on, the power state control signal is at a second logic level, allowing the output drive circuit to operate normally; wherein, the first logic level is greater than or equal to the first threshold voltage, and the second logic level is less than or equal to the second threshold voltage.

9. An input / output circuit system, characterized in that, include: The output drive circuit has a control input terminal and an output terminal; The power control circuit according to any one of claims 1 to 8, wherein the output terminal of the trigger module of the power control circuit is coupled to the control input terminal of the output drive circuit; The power state control signal of the power control circuit is used to control the output drive circuit to lock the output terminal of the output drive circuit to a certain state when the Core power domain is not powered on and the IO power domain is powered on.

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