A network card adapter plate and a server system

Abstract

The application discloses a network card adapter plate and a server system, and relates to the technical field of computers.The network card adapter plate comprises a power connector, a plurality of node connectors, a power supply and timing signal processing module, and a plurality of network card connectors.The power connector is connected to a power board, the plurality of node connectors are respectively connected to different server nodes, and the plurality of network card connectors are respectively configured to connect different interfaces of network cards.The power supply and timing signal processing module comprises a power supply enable control unit, an electronic fuse, and a main power supply timing signal generation unit.The power supply enable control unit enables the electronic fuse to supply power to the network card when the hot insertion condition is met and no hot removal operation is performed.The power normal signal output end of the electronic fuse outputs an auxiliary power supply timing signal to the network card.The main power supply timing signal generation unit outputs a main power supply timing signal to the network card when receiving the network card power normal signal and no hot removal operation is performed.The application realizes the hot plug of the network card in a multi-node sharing environment.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to a network card adapter board and a server system. Background Technology

[0002] In related technologies, hot-swappable network interface cards (NICs) are mostly designed for single nodes, controlling power and signal timing through a complex programmable logic device (CPLD) or extender on a single server motherboard. This approach cannot adapt to scenarios where the NIC is connected to two independent nodes simultaneously. When performing a hot-swappable operation, the two nodes need to coordinate to synchronously establish or disconnect the link. However, related technologies lack hardware support for dual-node collaborative management, resulting in unreliable power-on and PCIe (Peripheral Component Interconnect Express) link establishment after hot-swapping, or data loss and device damage during hot-swapping.

[0003] Therefore, how to achieve hot-swapping of network cards in a multi-node shared environment is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a network card adapter board and a server system that enables hot-swapping of network cards in a multi-node shared environment.

[0005] To achieve the above objectives, the present invention provides a network interface card (NIC) adapter board, including a power connector, multiple node connectors, a power and timing signal processing module, and multiple NIC connectors. The power connector is connected to a power board, and the multiple node connectors are respectively connected to different server nodes. The multiple NIC connectors are respectively configured to connect to different interfaces of the NICs. The power and timing signal processing module is connected to the power connector, the multiple node connectors, and the multiple NIC connectors. The power and timing signal processing module includes a power enable control unit, an electronic fuse, and a main power timing signal generation unit. The power enable control unit is configured to enable the NIC to connect to different interfaces of the NICs when hot-insertion conditions are met and there is no hot-pull-out operation. During operation, the electronic fuse is enabled to supply power to the network card. The power input terminal of the electronic fuse is connected to the power connector, the power output terminal of the electronic fuse is connected to each network card connector, and the power normal signal output terminal of the electronic fuse is connected to the main network card connector to output an auxiliary power timing signal to the network card, controlling the auxiliary power of the network card to power on or off. After the auxiliary power is powered on, the network card returns a network card power normal signal through the main network card connector. The main power timing signal generation unit is configured to output a main power timing signal to the network card through the main network card connector when it receives the network card power normal signal and there is no hot-plugging operation, in order to control the main power of the network card to power on or off.

[0006] To achieve the above objectives, the present invention provides a server system, including a power supply board, multiple server nodes, and a network interface card (NIC) adapter board as described above. The power supply board supplies power to the NICs through the NIC adapter board, and the multiple server nodes are connected to the NICs through the NIC adapter board.

[0007] This invention constructs a switching control architecture, or network interface card (NIC) adapter board, independent of any single server node by setting up a power connector, multiple node connectors, multiple NIC connectors, and a power and timing signal processing module connecting the three. This allows power management and critical timing signals during hot-swapping to be centrally managed by a dedicated module on the adapter board, rather than relying on the independent control of any single node. During hot-swapping, the power and timing signal processing module actively controls the power supply sequence of the NIC, ensuring power-on timing conforms to the NIC specifications. During hot-swapping, it sequentially de-energizes and resets the NIC, preventing abnormal states. Since the power and timing signal processing module connects to multiple node connectors, it can send status indications to or receive feedback from each node before / after power-on, achieving synchronous coordination of link establishment and disconnection across multiple nodes. Therefore, this invention achieves hot-swapping of NICs in a multi-node shared environment. This invention also discloses a server system that achieves the same technical effects.

[0008] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the invention. Attached Figure Description

[0009] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a structural diagram of a network interface card (NIC) adapter board according to an exemplary embodiment.

[0011] Figure 2 This is a structural diagram of a server system according to an exemplary embodiment.

[0012] Figure 3 This is a structural diagram illustrating the hot-swappable implementation of a dual-node DSFF network card in one application embodiment of the present invention.

[0013] Figure 4 This is a circuit diagram illustrating the hot-swappable implementation of a dual-node DSFF network card in one application embodiment of the present invention.

[0014] Figure 5 This is a flowchart of a hot-insertion implementation method provided in an application embodiment of the present invention.

[0015] Figure 6 This is a flowchart of a hot-pull-out implementation method provided in an application embodiment of the present invention.

[0016] Explanation of reference numerals in the attached diagram: 10—Power supply board; 20—Server node; 30—Network card adapter board; 301—Power connector; 302—Node connector; 303—Power and timing signal processing module; 304—Network card connector; 40—Network card. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0018] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0019] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] This embodiment provides a network card adapter board, such as Figure 1 As shown, it includes a power connector 301, multiple node connectors 302, a power and timing signal processing module 303, and multiple network card connectors 304. The power connector 301 is connected to the power board, the multiple node connectors 302 are connected to different server nodes, the multiple network card connectors 304 are configured to connect to different interfaces of the network cards, and the power and timing signal processing module 303 is connected to the power connector 301, the multiple node connectors 302, and the multiple network card connectors 304.

[0021] The power supply and timing signal processing module 303 is configured to control the power-on of the network card and process the power-on timing signal according to the hot-insertion operation, or to control the power-off of the network card and process the power-off timing signal according to the hot-out operation.

[0022] In this embodiment, the network interface card (NIC) adapter board includes a power connector, multiple node connectors, a power and timing signal processing module, and multiple NIC connectors. The power connector connects to an external power board to obtain the standby power required by the system. The multiple node connectors connect to different server nodes to enable control signal and data communication with each node. The multiple NIC connectors connect to different interfaces on the NICs. The power and timing signal processing module, as the core control unit of the adapter board, is connected to the power connector, node connectors, and NIC connectors, and coordinates power management and timing control between multiple nodes and the NICs during hot-swapping operations.

[0023] During hot-insertion, when the network card is physically inserted and the hot-insertion button is triggered, the power and timing signal processing module detects the hot-insertion signal and the network card presence signal. It then controls the power circuit to power on the network card according to a preset timing sequence, sequentially enabling the auxiliary and main power enable signals, and managing the reset signals sent by each node. This ensures that the network card completes the power-on and link establishment process according to specifications in a multi-node environment. During hot-unplugging, the module receives the hot-unplugging signal, notifies each node to disconnect from the network card, and sequentially shuts down the main power, auxiliary power, and standby power according to the power-down sequence. Simultaneously, it controls the reset signal status to ensure the network card is safely powered down without affecting subsequent insertion.

[0024] The network interface card (NIC) adapter board in this embodiment supports shared access to the same NIC from multiple server nodes. Each node is independent of the others, and a failure of any node will not affect the normal connection between other nodes and the NIC. Hardware-implemented timing control and power management can adapt to the hot-swappable requirements of multi-node NICs of different specifications.

[0025] The power supply and timing signal processing module 303 includes a power enable control unit, an electronic fuse, and a main power supply timing signal generation unit.

[0026] The power enable control unit is configured to enable the electronic fuse to supply power to the network card when hot-insertion conditions are met and there is no hot-out operation.

[0027] The power input terminal of the electronic fuse is connected to the power connector, the power output terminal of the electronic fuse is connected to each network card connector, and the power normal signal output terminal of the electronic fuse is connected to the main network card connector to output an auxiliary power timing signal to the network card to control the auxiliary power of the network card to power on or off; wherein, after the auxiliary power is powered on, the network card returns a network card power normal signal through the main network card connector.

[0028] The main power timing signal generation unit is configured to output a main power timing signal to the network card through the main network card connector when it receives a normal power signal from the network card and there is no hot-plugging operation, so as to control the main power of the network card to be powered on or off.

[0029] To achieve independent and reliable control over the hot-plugging process of network interface cards (NICs), the power supply and timing signal processing module 303 adopts a phased and sequential power management architecture. The core of this module includes a power enable control unit, an electronic fuse, and a main power timing signal generation unit. The power enable control unit is responsible for the initial judgment of the hot-plugging operation and the initiation of basic power supply. It receives in real time the presence signal (PRSNTB#) from each NIC connector, the hot-plug signal generated by the hot-plugging operation, and the hot-pull-out signal generated by the hot-pull-out operation, and performs logical synthesis on these signals. Only when the NIC is physically in place, the user has performed a hot-plugging operation, and no hot-pull-out operation has been triggered, will the power enable control unit output a valid signal, thereby enabling the electronic fuse.

[0030] As a key actuator for power on / off switching, the electronic fuse's power input is connected to the power connector, obtaining power from an external power board (such as P12V_STBY or P3V3_STBY). When enabled, the electronic fuse outputs power to each network interface card (NIC) connector, providing basic power to the NICs. Simultaneously, the power good (PG) signal generated internally by the electronic fuse is directly used as the auxiliary power timing signal (AUX_PWR_EN) and transmitted to the NICs via the main NIC connector. Upon receiving this signal, the NIC begins powering on its internal auxiliary power domain. Once the auxiliary power stabilizes, the NIC returns a high-level valid NIC power good (NIC_PWR_GOOD) signal to the NIC adapter board via the main NIC connector, indicating that it is ready to proceed to the next stage.

[0031] The main power timing signal generation unit is responsible for the final main power control. After confirming that the network interface card (NIC) auxiliary power supply is ready (i.e., receiving the NIC_PWR_GOOD signal) and there is no hot-plugging operation, the main power timing signal generation unit outputs a valid main power timing signal (MAIN_PWR_EN), which is also sent to the NIC via the main NIC connector. The NIC initiates its main power domain power-on process based on this signal. In a hot-plugging scenario, this process is reversed: first, the main power timing signal is canceled; after the main power is turned off, the power enable control unit then turns off the electronic fuse, cutting off the basic power supply. This ensures that the entire power-on and power-off process strictly follows the specified timing sequence, avoiding hardware damage or data loss due to timing errors.

[0032] This invention constructs a switching control architecture, or network interface card (NIC) adapter board, independent of any single server node by setting up a power connector, multiple node connectors, multiple NIC connectors, and a power and timing signal processing module connecting the three. This allows power management and critical timing signals during hot-plugging to be centrally managed by a dedicated module on the adapter board, rather than relying on the independent control of any single node. During hot-plugging, the power and timing signal processing module actively controls the power supply sequence of the NIC, ensuring power-on timing conforms to the NIC specifications. During hot-plugging, it sequentially de-energizes and resets the NIC, preventing abnormal states. Since the power and timing signal processing module connects to multiple node connectors, it can send status indications to or receive feedback from each node before / after power-on, achieving synchronous coordination of link establishment and disconnection across multiple nodes. Therefore, this invention enables hot-plugging of NICs in a multi-node shared environment.

[0033] Based on the above embodiments, as a feasible implementation method, the power enable control unit includes: a first AND logic implementation unit, a first inverting line, a second AND logic implementation unit, and a second inverting line; the input terminal of the first AND logic implementation unit is connected to the presence signal output by each network card connector, and the output terminal of the first AND logic implementation unit is connected to the input terminal of the first inverting line; the input terminal of the second AND logic implementation unit is respectively connected to the hot-insertion signal generated by the hot-insertion operation, the output terminal of the first inverting line, and the output terminal of the second inverting line, and the output terminal of the second AND logic implementation unit is connected to the enable terminal of the electronic fuse; the input terminal of the second inverting line is connected to the hot-pull-out signal generated by the hot-pull-out operation; the main power timing signal generation unit includes a third AND logic implementation unit; the input terminal of the third AND logic implementation unit is respectively connected to the network card power normal signal and the output terminal of the second inverting line, and the output terminal of the third AND logic implementation unit is configured to output the main power timing signal to the network card through the main network card connector; wherein, the network card is configured to control the main power supply to power on or off according to the received main power timing signal.

[0034] In practical implementation, the AND logic implementation unit can be an AND gate circuit built with MOSFETs or an AND logic chip; no specific limitation is made here. The input terminal of the first AND logic implementation unit is connected to the presence signal (such as the PRSNTB# signal) output by each network card connector, which is used to comprehensively determine whether the network card is physically present on all interfaces; its output signal is inverted by the first inverting circuit to generate a high-level active network card presence status indication signal. The input terminal of the second AND logic implementation unit receives the hot-insertion signal generated by the hot-insertion operation, the network card presence status signal output by the first inverting circuit, and the hot-pull-out signal inverted by the second inverting circuit. The second AND logic implementation unit performs a logical AND operation on these three conditions, and its output is only valid when the hot-insertion is valid, the network card is present, and there is no hot-pull-out operation. This output signal directly controls the enable terminal of the electronic fuse (EFUSE).

[0035] The power input terminal of the electronic fuse connects to the power connector of the adapter board, obtaining standby power from it. When its enable terminal is active, the electronic fuse outputs power to each network card connector, providing basic power to the network cards. Simultaneously, the power normal signal (PG) generated by the electronic fuse is used as the auxiliary power timing signal (e.g., AUX_PWR_EN) for the network cards, and is output to the network cards through the main network card connector. Upon receiving a valid auxiliary power timing signal, the network card controls its internal auxiliary power supply to power on, and after power-on, returns a network card power normal signal (e.g., NIC_PWR_GOOD) to the adapter board through the main network card connector.

[0036] The normal power signal of the network card and the hot-pull signal (indicating no hot-pull status), inverted by the second inverting circuit, are input together to the third logic implementation unit. The output of this unit serves as the main power timing signal (e.g., MAIN_PWR_EN), which is sent to the network card through the main network card connector. The network card controls the power-on or power-off of its internal main power supply based on this main power timing signal. Through this hierarchical enabling method, the module strictly adheres to the power-on sequence of auxiliary power supply first, followed by main power supply, and the power-off sequence of disconnecting main power supply first, followed by auxiliary power supply, during hot-pull, thereby ensuring the safety and reliability of network card power management and providing crucial hardware protection for hot-plugging operations in multi-node environments.

[0037] As one possible implementation, the power enable control unit further includes a first delay line, and the output of the second inverting line is connected to the input of the second AND logic implementation unit through the first delay line.

[0038] The delay circuit can be a simple RC (resistor, capacitor) delay circuit, where the delay length is set by adjusting the values ​​of the resistor and capacitor. It can also be a more complex digital delay circuit, using a counter or register to achieve precise time control. In specific implementation, the hot-pull signal generated by the hot-pull operation is first input to the second inverting circuit for inversion. Its output signal is then connected to the newly added first delay circuit, and then via this delay circuit, it is connected to the input terminal of the second AND logic implementation unit.

[0039] When an operator triggers a hot-plug operation, the first delay line, after the hot-plug signal is inverted, delays for a period of time before transmitting this invalidated signal (indicating that the hot-plug action has begun) to the second AND logic implementation unit. This delay creates a critical time window: before the hot-plug command is issued but the network card's main power supply is immediately cut off, the system has sufficient time to prioritize the standard power-down process for both the main and auxiliary power supplies. Specifically, during this period, the hot-plug signal first pulls down the main power timing signal through the third AND logic implementation unit, powering down the network card's main power and notifying each node to disconnect the link. Only after the delay time set by the first delay line has elapsed will the second AND logic implementation unit output a low level due to the change in input conditions, thereby turning off the electronic fuse and cutting off the power supply to the network card. This "delayed power-off" mechanism implemented by the first delay line enforces the power-down sequence, effectively preventing data loss or hardware stress problems that may occur due to instantaneous power cut-off, thus making the power timing control of the entire hot-plug process more precise and reliable, fully complying with high-standard hot-plug specifications.

[0040] As one feasible implementation, the electronic fuse includes a first electronic fuse and a second electronic fuse. The power input terminal of the first electronic fuse is connected to a 12V power supply via a power connector, and the power input terminal of the second electronic fuse is connected to a 3.3V power supply via a power connector. The power and timing signal processing module further includes a fourth AND logic implementation unit. The input terminal of the fourth AND logic implementation unit is connected to the normal power signal output terminals of the first and second electronic fuses, respectively. The output terminal of the fourth AND logic implementation unit is configured to output auxiliary power timing signals to the network card via the main network card connector.

[0041] In practical implementation, the electronic fuses include a first electronic fuse and a second electronic fuse, each responsible for different voltage domains: the power input terminal of the first electronic fuse is connected to a 12V power supply via a power connector, dedicated to generating and managing the 12V standby power required by the network card (P12V_STBY_OCP); while the power input terminal of the second electronic fuse is connected to a 3.3V power supply, responsible for providing the 3.3V standby power (P3V3_STBY_OCP). The input terminals of the fourth AND logic implementation unit are connected to the power good (PG) output terminals of the first and second electronic fuses, respectively. This means that the fourth AND logic implementation unit will only output a high level when both the 12V and 3.3V standby power supplies are stably outputting and their respective electronic fuses report normal power. This output signal is directly configured as an auxiliary power timing signal (such as AUX_PWR_EN) sent to the network card via the main network card connector. This "dual confirmation" mechanism is crucial. It ensures that the auxiliary power supply inside the network card is only allowed to be powered on when both basic power supplies are fully ready. This strictly adheres to the integrity and safety requirements of power sequence, effectively preventing the risk of network card initialization failure or damage due to unstable single power supply, and further enhancing the robustness of hot-swapping operations in complex multi-node environments.

[0042] As a feasible implementation method, the main power timing signal generation unit further includes a second delay line, the output terminal of the third AND logic implementation unit is connected to the input terminal of the second delay line, the output terminal of the second delay line is connected to the main network card connector, and the third AND logic implementation unit is configured to output the main power timing signal to the network card through the main network card connector via the second delay line.

[0043] In practical implementation, the output of the third AND logic implementation unit is first connected to the input of the second delay line, and then finally connected to the main network card connector via the output of the second delay line. This means that the original main power timing signal generated by the third AND logic implementation unit must be delayed by a preset time through the second delay line before it can be output to the network card as a valid main power timing signal. When the auxiliary power supply of the network card completes power-on and returns a power normal signal, the third AND logic implementation unit will immediately respond and output a high level, but this signal must be delayed by the second delay line before it finally takes effect. That is, a controllable time interval is forcibly inserted before the main power is enabled. This delay ensures that the auxiliary power supply inside the network card has enough time to reach a fully stable state, power the core logic and complete the initial initialization before the main power is allowed to power on. In this way, the second delay line forcibly establishes a strict time sequence between the two critical events of auxiliary power supply readiness and main power supply startup, thereby reliably realizing the critical step required by the network card power timing specification of "starting the main power supply only after the auxiliary power supply is stable". This effectively prevents problems such as power surges, logic competition or initialization failures that may be caused by the main power supply starting too early, and ensures the reliability and stability of the network card hot-swapping process.

[0044] As a feasible implementation, the power and timing signal processing module also includes a bandwidth configuration signal processing unit. The bandwidth configuration signal processing unit is connected to the bandwidth allocation pin of the network card through each network card connector. The bandwidth configuration signal processing unit is configured to output a preset bandwidth configuration level signal to the network card to configure the network card in a mode where multiple server nodes share bandwidth.

[0045] In practical implementation, the bandwidth configuration signal processing unit is responsible for initializing and allocating the PCIe (Peripheral Component Interconnect Express) channel resources of the network card to adapt to multi-node shared application scenarios. The bandwidth configuration signal processing unit is physically connected to specific pins on the network card used for bandwidth allocation, namely the BIF (Bandwidth Indication Function) pins, through each network card connector. Its core function is to output a set of preset, fixed level signals to these pins. This set of preset level signals is equivalent to issuing explicit configuration instructions to the network card hardware, telling the network card how to allocate its internal PCIe channel resources. For example, in a typical dual-node scenario, this unit can divide the total bandwidth of the network card (e.g., 32 PCIe channels) into two independent x16 channel groups by configuring the level signals to a specific mode, and allocate them to two server nodes respectively, thereby achieving hard bandwidth partitioning and sharing. This configuration is completed at the initial power-on stage of the network card and before establishing a link with the nodes, ensuring that the network card can start in the correct hardware mode and laying the foundation for subsequent identification and access by multiple server nodes. Through this hardware-level static configuration method, the bandwidth configuration signal processing unit enables a single network card to be flexibly and reliably divided into multiple logical endpoints, which can be recognized and shared by multiple server nodes, thereby giving full play to the resource utilization and flexibility advantages of high-performance network cards in multi-node server architecture.

[0046] As a feasible implementation, the power supply and timing signal processing module also includes multiple bus switches. The first signal terminal of the bus switch is configured to receive a reset signal sent by the corresponding node connector. The second signal terminal of the bus switch is connected to the reset pin of the network card through the corresponding network card connector. The enable terminal of the bus switch is connected to the output terminal of the third AND logic implementation unit.

[0047] In practical implementation, the power and timing signal processing module also includes multiple bus switches for safety isolation and control of the reset signal path between the network interface card (NIC) and the server node. The first signal terminal (input side) of each bus switch is configured to receive a reset signal (e.g., HOST_PERST# signal) sent by the server node from the corresponding node connector. Its second signal terminal (output side) is connected to the corresponding reset pin on the NIC via the corresponding NIC connector. The enable terminals (OE) of all bus switches are not independently controlled but are uniformly connected to the output of the third AND logic implementation unit, which is the generation point of the main power timing signal (MAIN_PWR_EN).

[0048] This implementation method forcibly synchronizes the network interface card's (NIC) reset state with the main power supply's power-on / off timing. When the main power supply is not turned on (i.e., MAIN_PWR_EN is inactive), the bus switch's enable pin is disabled, and the switch is open, preventing the reset signal sent by the node from reaching the NIC. Simultaneously, the NIC's reset pin is maintained at a valid reset level by default within the adapter board via a pull-down resistor, ensuring that the NIC will not enter a working state before full power-on under any unforeseen circumstances, thus avoiding potential bus conflicts or logic errors. Only when the main power supply timing signal is valid (MAIN_PWR_EN is active) is the bus switch synchronously enabled, connecting the reset signals generated by each server node to the NIC. The node can then manage the NIC's reset / unreset operation by controlling these reset signals, achieving safe and reliable hot-swapping.

[0049] As a feasible implementation, the power supply and timing signal processing module further includes a second delay line and a third delay line. The input terminal of the second delay line is connected to the output terminal of the third AND logic implementation unit, the output terminal of the second delay line is connected to the input terminal of the third delay line, and the output terminal of the third delay line is connected to the enable terminal of multiple bus switches.

[0050] In implementation, the input of the second delay line is directly connected to the output of the third AND logic implementation unit, receiving the main power timing signal generated therein. The output of the second delay line is connected to the input of the third delay line, and the final output of the third delay line is connected to the enable pin of all bus switches. After the main power timing signal is valid, the bus switches are not immediately activated; instead, a controlled, phased waiting time is forcibly inserted. The main power timing signal first passes through the second delay line, ensuring that the main power enable command has fully taken effect and providing initial stabilization time for the network card's main power domain to power on. Subsequently, the signal undergoes further delay through the third delay line, ensuring that the network card's internal main power supply has sufficient time to reach a fully stable operating state. Finally, when the signal reaches the bus switch enable pin after two stages of delay, the network card's power supply environment is in a stable and reliable state, at which point the bus switches are allowed to conduct, transmitting the server node's reset signal to the network card. This design strictly adheres to the basic hardware operation principle of "processing reset only after power is stable," effectively preventing network card logic errors or link training failures that may result from performing a reset operation when the power is unstable, and significantly improving the success rate and reliability of the hot-insertion process.

[0051] As a feasible implementation, the system also includes a hot-swap interaction module, which includes: a hot-insert button configured to receive a hot-insert operation and generate a hot-insert button signal; a hot-insert button signal processing unit configured to generate a hot-insert signal based on the hot-insert button signal; a hot-pull-out button configured to receive a hot-pull-out operation and generate a hot-pull-out button signal; and a hot-pull-out button signal processing unit configured to generate a hot-pull-out signal based on the hot-pull-out button signal.

[0052] In practical implementation, the hot-swap interaction module is a crucial interface for safe operation between the operator and the hardware system. Its core function is to receive operator commands and convert them into stable control signals recognizable by the system. The hot-swap interaction module comprises four main parts: First, a hot-swap button, physically configured to receive the operator's hot-swap operation (e.g., pressing), generating a raw hot-swap button electrical signal; second, a hot-swap button signal processing unit, connected to the hot-swap button, responsible for shaping and confirming the received raw hot-swap button signal, ultimately generating a stable hot-swap signal and distributing it to the system's core control logic. Correspondingly, the hot-swap interaction module also includes a hot-pull-out button, used to receive the operator's hot-pull-out operation and generate a raw hot-pull-out button signal; and a hot-pull-out button signal processing unit, whose function is to generate a stable hot-pull-out signal based on this button signal. This modular design transforms unstable mechanical button actions into reliable digital control commands, providing a clear and accidental activation mechanism for the entire hot-swap process.

[0053] As one feasible implementation, the hot-insertion button signal processing unit includes a first debouncing circuit and a first trigger. The hot-insertion button is connected to the first debouncing circuit, the first debouncing circuit is connected to the first trigger, and the first trigger is connected to the signal connectors corresponding to each node. The hot-pull-out button signal processing unit includes a second debouncing circuit and a second trigger. The hot-pull-out button is connected to the second debouncing circuit, the second debouncing circuit is connected to the second trigger, and the second trigger is connected to the signal connectors corresponding to each node.

[0054] In practical implementation, the electrical output of the hot-plug button is directly connected to the input of the first debouncing circuit. This debouncing circuit effectively filters out millisecond-level level jitter generated when the button contacts close or open through hardware RC filtering or a dedicated debouncing chip, outputting a preliminary flat level signal. This signal is then sent to the clock or data input of the first flip-flop, which samples and latches it at the next clock edge, ultimately outputting a clean, jitter-free, and stable hot-plug signal synchronized with the system clock. This signal is then connected to the corresponding signal connector of each node, thus reliably notifying all server nodes of the occurrence of the hot-plug event. Similarly, the hot-pull-out button is sequentially connected to the second debouncing circuit and the second flip-flop, which generates a stable hot-pull-out signal and sends it to each node. This cascaded design of "debouncing circuit + flip-flop" fundamentally eliminates multiple false triggers that may be caused by mechanical jitter, ensuring the accuracy of hot-plug commands and the reliability of system operation.

[0055] As a feasible implementation, the hot-swap interaction module also includes a hot-insertion indicator and a hot-pull-out indicator; the output of the third AND logic implementation unit is connected to the hot-insertion indicator and the hot-pull-out indicator so as to control the hot-insertion indicator and the hot-pull-out indicator according to the main power timing signal output by the third AND logic implementation unit.

[0056] In practical implementation, the hot-swap interaction module also integrates a visual feedback unit, specifically including hot-insertion and hot-removal indicator lights, used to intuitively display the current power status of the network card and the result of the hot-swap operation to the operator. The output of the third logic implementation unit, namely the generated main power timing signal (MAIN_PWR_EN), is connected to the control terminal of the hot-insertion and hot-removal indicator lights. The control mechanism is that the main power timing signal is the final indicator of the network card's core power-on completion. When the main power timing signal is at a valid level, it indicates that the network card's main power domain has been successfully established and stabilized, and the entire hot-swap process has been substantially completed; when the main power timing signal is at an invalid level, it indicates that the network card's main power has been disconnected, and the hot-removal process has been executed. Therefore, driving the indicator lights through the main power timing signal can accurately reflect the core operating status of the network card. For example, when the main power timing signal is valid, the hot-plug indicator light (e.g., green) illuminates, informing the operator that the network card is ready and can be used normally; when the main power timing signal is invalid, the hot-pull indicator light (e.g., red) illuminates, indicating to the operator that the network card has been safely powered down and can be physically removed. This design provides the operator with clear, accurate status indications that are strictly synchronized with the internal power state, greatly improving the safety of hot-plug operations and the user experience.

[0057] As a feasible implementation, the power supply and timing signal processing module further includes a second delay line, a third delay line, and a fourth delay line. The input terminal of the second delay line is connected to the output terminal of the third AND logic implementation unit, the output terminal of the second delay line is connected to the input terminal of the third delay line, the output terminal of the third delay line is connected to the input terminal of the fourth delay line, and the output terminal of the fourth delay line is connected to the hot-insertion indicator and the hot-extraction indicator.

[0058] In practice, the input of the second delay line is connected to the output of the third AND logic implementation unit to receive the original main power timing signal; the output of the second delay line is connected to the input of the third delay line; the output of the third delay line is further connected to the input of the fourth delay line; and the final output of the fourth delay line is connected to the control terminal of the hot-insertion indicator and the hot-pull-out indicator.

[0059] As can be seen, this implementation fully delays and shapes the main power timing signal before driving the indicator light. The delay of the second delay line may be used to ensure the stability of the main power timing signal itself; the signal then passes through the third delay line, which ensures that the main power has been fully established and subsequent critical operations (such as turning on the bus switch and releasing the reset signal) have been completed; finally, the signal passes through the fourth delay line, which may be intentionally set to a relatively long time to ensure that before the indicator light is lit, the network card has not only been powered on but has also successfully established a stable PCIe link with the server node and entered a normal working state. Therefore, when the indicator light is finally lit, it conveys to the operator not only that "the power is on," but also that "the network card is fully ready and can be used for business," thus providing a higher level and more reliable confirmation of operation completion. This effectively prevents operators from misjudging that the operation is completed before the link has been successfully established, greatly improving the availability and security of the system.

[0060] This embodiment provides a server system, such as Figure 2 As shown, it includes a power board 10, multiple server nodes 20, and a network card adapter board 30 as provided in the above embodiment. The power board 10 supplies power to the network card 40 through the network card adapter board 30, and the multiple server nodes 20 are connected to the network card 40 through the network card adapter board 30.

[0061] The power board 10 serves as the centralized power supply unit for the system, connecting to the power connector of the network interface card (NIC) adapter board 30 to provide stable and reliable 12V and 3.3V standby power input for the entire hot-swap operation. Multiple server nodes 20 represent the system's computing units, interconnected with their respective node connectors on the NIC adapter board 30 via their signal interfaces.

[0062] In the server system, one end of the network interface card (NIC) adapter board 30 is connected to the power board 10 to obtain power, and the other end is connected to multiple server nodes 20 for signal interaction. The NIC connector on it is used to plug in NICs 40. Its core workflow is as follows: when the NIC 40 is physically inserted into the adapter board and a hot-plug operation is triggered, the power and timing signal processing module inside the adapter board strictly follows the specified sequence to control the power supplied by the power board to be applied to the NIC in an orderly manner and manage the power-on and power-off sequence. At the same time, the adapter board coordinates the reset signal on / off and the PCIe link establishment / disconnection process between each server node 20 and the NIC 40.

[0063] As one feasible implementation, the server node includes an in-node signal processing module configured to send a reset signal to the network card via a network card adapter board after receiving a hot-insertion signal, in order to establish a communication link with the network card, or to disconnect the communication link with the network card after receiving a hot-out signal.

[0064] In practice, each server node integrates an in-node signal processing module. Its core function is to receive global control signals from the network interface card (NIC) adapter board and execute corresponding link operations. Specifically, when the in-node signal processing module receives a valid hot-plug signal through the NIC adapter board, it doesn't act immediately. Instead, it monitors the power-on and reset timing of the NIC. Only after confirming stable NIC power and that reset conditions are met does the module send a reset signal to the NIC via the bus switch on the NIC adapter board, triggering the PCIe link training process between the node and the NIC, ultimately establishing a stable and reliable communication link. Conversely, when the module receives a hot-plug signal, it immediately initiates a link disconnection process: first, it ensures all ongoing data services have been safely stopped or migrated; then, it actively disconnects the PCIe logical connection with the NIC; and finally, it puts the NIC into a reset state. By deploying this dedicated signal processing module within each server node, multiple nodes can independently, orderly, and securely manage and share NIC connections, achieving multi-node hot-plug collaboration.

[0065] As one feasible implementation, the server system includes a first server node and a second server node, and the network interface card (NIC) is a dual-slot NIC.

[0066] In practical implementation, the server system is specifically a two-node application scenario, with an architecture comprising a first server node and a second server node. These two nodes are logically independent, each undertaking its own computing tasks, but they collaborate through network and system management. Matching this architecture, the network interface cards (NICs) used in the system are specific dual-slot NICs, such as DSFF (Dual Small Form Factor) NICs or TDSFF (Tall Dual Small Form Factor) NICs. The physical characteristic of these NICs is that they have two independent hardware interfaces (such as two 4C+ connectors), allowing them to establish physical connections with both the first and second server nodes simultaneously via a NIC adapter board.

[0067] As can be seen, this embodiment achieves secure sharing and independent thermal management of a single high-performance network interface card (NIC) across multiple server nodes by introducing a dedicated NIC adapter board. Failure or maintenance of any server node will not affect other nodes' continued access to the NIC via this adapter board. The controlled power supply provided by the power board through the adapter board also ensures that the hot-swapping process will not impact system stability.

[0068] Based on the above embodiments, as a preferred implementation, the server system further includes: a dynamic arbitration module, connected to multiple server nodes, configured to obtain the health status information of each of the multiple server nodes before performing a hot-plug operation; if at least one node is in an unhealthy state, the execution of the hot-plug operation is delayed or prohibited, and an alarm signal is sent; if all nodes are in a healthy state, the hot-plug operation is allowed to be executed according to the normal process.

[0069] In practice, the dynamic arbitration module acquires the health status of each server node in real time, such as node power status, temperature, and PCIe link stability. When a user triggers a hot-plug operation (e.g., pressing the hot-insert or hot-out button), the initial signal generated by the hot-plug interaction module is not immediately responded to by the power and timing signal processing module, but is first sent to the dynamic arbitration module for decision-making. The arbitration module checks the health status of all relevant nodes: if any node is found to be in an unhealthy state such as fault, overload, high temperature, or PCIe training failure, the arbitration module will output a control signal to temporarily delay or completely prohibit the execution of this hot-plug operation, and send a detailed alarm to prompt maintenance personnel to prioritize handling node anomalies; only when all nodes are determined to be healthy will the arbitration module allow the hot-plug control signal to pass, thereby triggering the subsequent standard power-on / power-off timing process.

[0070] As can be seen, this implementation effectively prevents risks such as link establishment failure, data loss, or even system downtime that may occur when hot-swapping is performed during node anomalies, greatly improving the system's robustness and reliability. Through a proactive alarm mechanism, potential system problems are exposed to maintenance personnel before the hot-swapping operation, realizing a shift from a reactive fault response to a proactive fault prevention maintenance model, thus improving system maintainability. Simultaneously, it enhances the overall collaborative management capabilities of this complex multi-node server system, ensuring that the high-risk hot-swapping operation is only performed under stable and secure conditions, thereby guaranteeing the continuity of critical business operations and data integrity.

[0071] The following describes an application embodiment provided by the present invention, such as... Figure 3 As shown, the system includes a hot-plug interaction module, a power and timing signal processing module, and an intra-node signal processing module. The hot-plug interaction module includes a hot-plug button, a hot-plug button, and hot-plug / hot-plug indicator lights for interaction with hot-plug operators. The power and timing module powers on the DSFF network card and processes related timing signals after a hot-plug operation, ensuring the power-on timing conforms to specifications and thus guaranteeing normal operation. It also powers off the DSFF network card and processes related timing signals after a hot-plug operation, ensuring proper power-off. The intra-node signal processing module ensures that when two server nodes receive a hot-plug signal from the DSFF network card, they send a PCIe reset signal to the network card and establish a link connection; or, upon receiving a hot-plug signal, they disconnect the link, ensuring the integrity of service data and preventing data loss.

[0072] like Figure 4As shown, the common power board provides power to the DSFF adapter board via P12V_STBY and P3V3_STBY signals. These two signals are converted to P12V_STBY_OCP and P3V3_STBY_OCP signals respectively through the EFUSE chip and connected to the DSFF Primary 4C+ connector (master network card connector) and Second 4C+ connector (slave network card connector) to power the DSFF network card. The corresponding timing management signals for DSFF / TDSFF are AUX_PWR_EN0 (auxiliary power timing signal), MAIN_PWR_EN0 (master power timing signal), and NIC_PWR_GOOD0 (network card power normal signal) on the Primary connector. The AUX_PWR_EN1, MAIN_PWR_EN1, and NIC_PWR_GOOD1 signals on the Second connector are reserved only. After hot-plugging the DSFF network card, press the hot-plug button. The DSFF_HOT_IN_BTN# (hot-insertion button signal) generates a low-level pulse signal. After passing through a debouncing circuit and a trigger, this pulse signal generates a stable DSFF_HOT_IN (hot-insertion signal) high-level signal, indicating that a hot-insertion action has been performed. After the DSFF network card is inserted into the DSFF adapter board, the PRSNTB#[0,1,2,3] and PRSNTB#[4,5,6,7] signals will change. Part of the PRSNTB# signal (present signal) will be pulled low. After passing through AND1 (AND gate 1) and an inverting circuit, PRSNTB#[0,1,2,3] and PRSNTB#[4,5,6,7] generate the DSFF present signal. When this signal is high, it indicates that the DSFF network card is physically present. When the DSFF_HOT_IN signal and the DSFF in-position signal are enabled simultaneously, and no hot-plug action is triggered, the AND2 gate outputs a high level, enabling P12V_STBY_OCP EFUSE (12V power signal) and P3V3_STBY_OCPEFUSE (3.3V power signal), generating P12V_STBY_OCP and P3V3_STBY_OCP power supplies to power the DSFF network card.

[0073] After the P12V_STBY_OCP and P3V3_STBY_OCP power supplies are powered on, the PG signals of the two power supplies are ANDed through AND gate 3 and used as the AUX_PWR_EN0 timing signal for the DSFF network card, connected to the DSFF network card. Simultaneously, the BIF (Bandwidth Indicator) signal is in a fixed pull-up / pull-down mode on the DSFF adapter board, allocating the DSFF network card bandwidth as X16+X16, with each node corresponding to one X16 PCIe. Upon receiving AUX_PWR_EN0, the network card's internal AUX power is activated. After power-up, the network card actively sends the NIC_PWR_GOOD0 signal to both nodes. Meanwhile, when no hot-plugging action is triggered, the NIC_PWR_GOOD0 signal on the DSFF adapter board is ANDed through AND gate 4 and delay line 1 to generate the MAIN_PWR_EN0 signal for the Primary connector, and the network card begins to power on its internal MAIN power.

[0074] After the MAIN_PWR_EN0 signal is valid, it is connected to the enable signals OE of the two BUS SWITCHs via delay line 2. When the OE enable signals of the two BUS SWITCHs are low, the BUS SWITCHs are closed, and the PERST#[0,1,2,3] and PERST#[4,5,6,7] (reset signals) connected to the DSFF network card are pulled low by default on the DSFF adapter board, and the network card is always in a reset state. After the MAIN_PWR_EN0 signal is valid, the enable signals OE of the two BUS SWITCHs are pulled high via delay line 2, the BUS SWITCHs are turned on, and the HOST_PERST#[0,1,2,3] and HOST_PERST#[4,5,6,7] (reset signals) sent by the two nodes can then be connected normally to the DSFF Primary 4C+ connector and Second 4C+ connector. The node provides a 100M reference clock signal to the DSFF network card, which can be provided by the node's internal CPU (Central Processing Unit) or by the node's internal clock generator / clock buffer. Each node's CPU is connected to the network card via a PCIe x16 slot. After receiving the DSFF_HOT_IN signal, the node sends HOST_PERST#[0,1,2,3] and HOST_PERST#[4,5,6,7], opening the BUSSWITCH and connecting it to the DSFF network card. The network card is then de-reset, and the DSFF / TDSFF network card can then function normally. Additionally, after the MAIN_PWR_EN0 signal becomes valid, it passes through delay lines 2 and 3 to illuminate the hot-insertion indicator, indicating that the DSFF network card hot-insertion operation is complete.

[0075] When a DSFF hot-removal operation is required, the hot-remove button must be pressed. DSFF_HOT_REMOVE_BTN# (hot-remove button signal) generates a low-level pulse signal. This pulse signal, after passing through a debouncing circuit and a trigger, generates a stable high-level DSFF_HOT_REMOVE signal, indicating that a hot-removal operation is about to occur. The DSFF_HOT_REMOVE signal is connected to two nodes, informing them that the DSFF network card is about to be hot-removed. Upon receiving this signal, both nodes disconnect the link between their CPU and the DSFF network card. Furthermore, after passing through an inverting circuit, AND4, and delay circuit 1, DSFF_HOT_REMOVE pulls the MAIN_PWR_EN0 signal low, powering down the MAIN power supply on the DSFF network card. The MAIN_PWR_EN0 signal synchronously pulls the enable signals OE of the two BUS SWITCHs low through the delay line 2, disconnecting the BUS SWITCHs. PERST#[0,1,2,3] and PERST#[4,5,6,7] return to their default low state, and the DSFF network card is reset.

[0076] Additionally, the DSFF_HOT_REMOVE signal is connected to AND2 (AND gate 2) after passing through an inverting line and delay line 4. This pulls the output of AND2 low, which in turn pulls the enable signals of the P12V_STBY_OCP and P3V3_STBY_OCP power supplies low, thus powering down the P12V_STBY_OCP and P3V3_STBY_OCP power supplies. Simultaneously, the AUX_PWR_EN0 signal is also pulled low. With the DSFF network card powered down, the MAIN_PWR_EN0 signal illuminates the hot-pull indicator light after passing through delay lines 2 and 3, indicating that the DSFF network card hot-pull operation is complete and the network card can be physically removed.

[0077] like Figure 5As shown, after the DSFF network card is hot-inserted and the hot-insertion button is pressed, the DSFF_HOT_IN signal is generated through the debouncing circuit and trigger to inform the two nodes. This signal is then connected to the enable control P12V_STBY_OCP and P3V3_STBY_OCP of the power supply EFUSE via an AND gate to power on. After power-on, the AUX_PWR_EN0 and MAIN_PWR_EN0 timing signals of the DSFF network card are pulled high in sequence, and the two BUS SWITCH switches are turned on. The HOST_PERST#[0,1,2,3] and HOST_PERST#[4,5,6,7] signals of the two nodes are connected to the DSFF Primary 4C+ connector and Second 4C+ connector, respectively. After the network card is reset, the DSFF network card can work normally. In addition, the MAIN_PWR_EN0 signal also passes through delay lines 2 and 3 to illuminate the network card hot-insertion indicator light, indicating that the network card hot-insertion operation is complete.

[0078] like Figure 6 As shown, after the DSFF network card presses the hot-remove button, it generates a DSFF_HOT_REMOVE signal through a debouncing circuit and a trigger to inform the two nodes. Upon receiving the signal, the two nodes disconnect the PCIe link from the network card. Furthermore, the DSFF_HOT_REMOVE signal, after passing through an inverting circuit, an AND4 gate, and delay circuit 1, pulls the MAIN_PWR_EN0 signal low. The MAIN_PWR_EN0 signal, after passing through delay circuit 2, turns off the two BUS SWITCH switches, pulling the DSFF network card's PERST#[0,1,2,3] and PERST#[4,5,6,7] signals low, resetting the network card. The DSFF_HOT_REMOVE signal also passes through an inverting circuit, delay circuit 4, and an AND2 gate, pulling down the power supply EFUSE enable control P12V_STBY_OCP and P3V3_STBY_OCP, powering down the DSFF network card. After MAIN_PWR_EN0 passes through delay line 2 and delay line 4, the hot-pull indicator light illuminates, indicating that the DSFF network card hot-pull operation is complete and the network card can be physically removed.

[0079] This embodiment provides a method for hot-swapping a dual-node DSFF network card. The method involves interacting with the server via a hot-insert or hot-remove button, informing the two server nodes to establish or disconnect the PCIe link with the network card. Simultaneously, a series of appropriate hardware circuits on the DSFF adapter board ensure that after hot-insertion, the power supply, timing signals, and reset signals are enabled sequentially according to the power-on sequence in the DSFF specification. This allows the DSFF network card to operate normally after power-on and establish connections with the two server nodes. Similarly, when the DSFF network card is hot-removed, the timing signals, reset signals, and electrical signals are deactivated sequentially according to the specification, allowing the DSFF network card to disconnect from the two nodes and power down normally, without affecting the execution of the next hot-insertion operation.

[0080] The foregoing has provided a detailed description of a network interface card (NIC) adapter board and a server system provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A network card adapter board, characterized in that, The device includes a power connector, multiple node connectors, a power and timing signal processing module, and multiple network interface card (NIC) connectors. The power connector is connected to a power board, the multiple node connectors are respectively connected to different server nodes, and the multiple NIC connectors are respectively configured to connect to different interfaces of the NICs. The power and timing signal processing module is respectively connected to the power connector, the multiple node connectors, and the multiple NIC connectors. The power supply and timing signal processing module includes a power enable control unit, an electronic fuse, and a main power supply timing signal generation unit. The power enable control unit is configured to enable the electronic fuse to supply power to the network card when the hot-insertion conditions are met and there is no hot-out operation. The power input terminal of the electronic fuse is connected to the power connector, the power output terminal of the electronic fuse is connected to each network card connector, and the power normal signal output terminal of the electronic fuse is connected to the main network card connector to output an auxiliary power timing signal to the network card to control the auxiliary power of the network card to power on or off; wherein, after the auxiliary power is powered on, the network card returns a network card power normal signal through the main network card connector; The main power timing signal generation unit is configured to output a main power timing signal to the network card through the main network card connector when it receives a normal power signal from the network card and there is no hot-plugging operation, so as to control the main power of the network card to be powered on or off. The network card is a dual-slot network card, which has two independent hardware interfaces to enable the dual-slot network card to establish physical connections with the first server node and the second server node simultaneously.

2. The network card adapter board according to claim 1, characterized in that, The power enable control unit includes: a first AND logic implementation unit, a first inverting circuit, a second AND logic implementation unit, and a second inverting circuit; The input terminal of the first AND logic implementation unit is connected to the presence signal output by each network card connector, and the output terminal of the first AND logic implementation unit is connected to the input terminal of the first inverting line. The input terminal of the second AND logic implementation unit is connected to the hot-insertion signal generated by the hot-insertion operation, the output terminal of the first inverting circuit, and the output terminal of the second inverting circuit, respectively. The output terminal of the second AND logic implementation unit is connected to the enable terminal of the electronic fuse. The input terminal of the second inverting circuit is connected to the hot-pull signal generated by the hot-pull operation; The main power supply timing signal generation unit includes a third AND logic implementation unit; The input terminal of the third AND logic implementation unit is connected to the network card power normal signal and the output terminal of the second inverting line, respectively. The output terminal of the third AND logic implementation unit is configured to output the main power timing signal to the network card through the main network card connector.

3. The network card adapter board according to claim 2, characterized in that, The power enable control unit further includes a first delay line, and the output of the second inverting line is connected to the input of the second AND logic implementation unit through the first delay line.

4. The network card adapter board according to claim 2, characterized in that, The electronic fuse includes a first electronic fuse and a second electronic fuse. The power input terminal of the first electronic fuse is connected to a 12V power supply through the power connector, and the power input terminal of the second electronic fuse is connected to a 3.3V power supply through the power connector. The power and timing signal processing module further includes a fourth AND logic implementation unit, wherein the input terminal of the fourth AND logic implementation unit is connected to the power normal signal output terminal of the first electronic fuse and the second electronic fuse respectively, and the output terminal of the fourth AND logic implementation unit is configured to output the auxiliary power timing signal to the network card through the main network card connector.

5. The network card adapter board according to claim 2, characterized in that, The main power timing signal generation unit further includes a second delay line. The output terminal of the third AND logic implementation unit is connected to the input terminal of the second delay line. The output terminal of the second delay line is connected to the main network card connector. The third AND logic implementation unit is configured to output the main power timing signal to the network card through the second delay line and the main network card connector.

6. The network card adapter board according to claim 2, characterized in that, The power and timing signal processing module further includes a bandwidth configuration signal processing unit. The bandwidth configuration signal processing unit is connected to the bandwidth allocation pin of the network card through each network card connector. The bandwidth configuration signal processing unit is configured to output a preset bandwidth configuration level signal to the network card to configure the network card in a mode where multiple server nodes share bandwidth.

7. The network card adapter board according to claim 2, characterized in that, The power and timing signal processing module also includes multiple bus switches. The first signal terminal of the bus switch is configured to receive a reset signal sent by the corresponding node connector. The second signal terminal of the bus switch is connected to the reset pin of the network card through the corresponding network card connector. The enable terminal of the bus switch is connected to the output terminal of the third AND logic implementation unit.

8. The network card adapter board according to claim 7, characterized in that, The power supply and timing signal processing module further includes a second delay line and a third delay line. The input terminal of the second delay line is connected to the output terminal of the third AND logic implementation unit, the output terminal of the second delay line is connected to the input terminal of the third delay line, and the output terminal of the third delay line is connected to the enable terminal of a plurality of bus switches.

9. The network card adapter board according to claim 2, characterized in that, It also includes a hot-swappable interaction module, which includes: A hot-insert button is configured to receive hot-insert operations and generate a hot-insert button signal. A hot-insertion button signal processing unit is configured to generate a hot-insertion signal based on the hot-insertion button signal; The hot-pull button is configured to receive hot-pull operations and generate a hot-pull button signal. The hot-pull-out button signal processing unit is configured to generate a hot-pull-out signal based on the hot-pull-out button signal.

10. The network card adapter board according to claim 9, characterized in that, The hot-insertion button signal processing unit includes a first debouncing circuit and a first trigger. The hot-insertion button is connected to the first debouncing circuit, the first debouncing circuit is connected to the first trigger, and the first trigger is connected to the signal connectors corresponding to each node. The hot-pull-out button signal processing unit includes a second debouncing circuit and a second trigger. The hot-pull-out button is connected to the second debouncing circuit, the second debouncing circuit is connected to the second trigger, and the second trigger is connected to the signal connectors corresponding to each node.

11. The network card adapter board according to claim 9, characterized in that, The hot-swap interaction module also includes a hot-insertion indicator and a hot-out indicator; The output of the third AND logic implementation unit is connected to the hot-insertion indicator and the hot-pull-out indicator, so as to control the hot-insertion indicator and the hot-pull-out indicator according to the main power timing signal output by the third AND logic implementation unit.

12. The network card adapter board according to claim 11, characterized in that, The power supply and timing signal processing module further includes a second delay line, a third delay line, and a fourth delay line. The input terminal of the second delay line is connected to the output terminal of the third AND logic implementation unit. The output terminal of the second delay line is connected to the input terminal of the third delay line. The output terminal of the third delay line is connected to the input terminal of the fourth delay line. The output terminal of the fourth delay line is connected to the hot-insertion indicator and the hot-pull-out indicator.

13. A server system, characterized in that, The device includes a power supply board, multiple server nodes, and a network interface card (NIC) adapter board as described in any one of claims 1 to 12, wherein the power supply board supplies power to the NIC via the NIC adapter board, and the multiple server nodes are connected to the NIC via the NIC adapter board.

14. The server system according to claim 13, characterized in that, The server node includes an in-node signal processing module configured to send a reset signal to the network card via the network card adapter board after receiving a hot-insertion signal, in order to establish a communication link with the network card, or to disconnect the communication link with the network card after receiving a hot-unplug signal.

15. The server system according to claim 13, characterized in that, The server system includes a first server node and a second server node, and the network card is a dual-slot network card.

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