Image sensor, manufacturing method and imaging method

Abstract

The invention provides an image sensor, a manufacturing method and an imaging method. The image sensor comprises a semiconductor structure layer, a circuit connection layer and an optical structure layer. The semiconductor structure layer comprises a plurality of pixel units, a first isolation structure is arranged between every two adjacent pixel units, and the first isolation structures penetrate through the semiconductor structure layer in the thickness direction; the pixel unit comprises a photosensitive module and an overflow module; the photosensitive module is used for converting the optical signal into a charge signal, and the charge signal comprises a first charge signal and a second charge signal; the overflow module is used for at least storing the second charge signal and realizing the isolation of the overflow module between adjacent pixel units based on the first isolation structure; the circuit connection layer is located on the first surface of the semiconductor structure layer; the optical structure layer is located on the second face of the semiconductor structure layer and comprises a plurality of color filtering units corresponding to the pixel units. According to the invention, the problem in the prior art that the image color and the image effect are influenced by the charge crosstalk between the PDs is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image sensors, in particular to an image sensor, a manufacturing method and an imaging method. BACKGROUND

[0002] With the continuous development of image sensors, the demand for high-quality imaging in the fields of transportation and digital photography is increasing, and high dynamic range is one of the important factors for measuring the imaging quality of image sensors. In daily shooting environments, especially in environments with large areas of high-intensity light sources, such as the sun, car headlights, and smooth surfaces like glass mirrors and metals, it is easy to have some or even large areas of overexposed regions in the captured pictures, which requires adjusting the image sensor to reduce the exposure time to reduce the area of the overexposed region, but this easily makes other areas of the picture too dark and loses some details.

[0003] Therefore, the current solution to this problem is to design a large-capacity lateral overflow integration capacitor (LOFIC) in the pixel structure of the image sensor and place it near the floating diffusion node (FD). The photodiode (PD) in the image overexposed region overflows and stores the signal in the FD and LOFIC through the transfer transistor to save the overexposed region signal. In the subsequent quantization process, the signals in the unsaturated PD and the signals in the overexposed region LOIFC+FD+PD are taken to ensure that the bright area signal is not overexposed and the dark area signal has a high signal-to-noise ratio, thereby achieving high dynamic range imaging.

[0004] This pixel design for achieving high dynamic range is mainly achieved by storing the overflow charge in the high-intensity region PD, and in such a high-intensity environment, the amount of PD overflow charge is huge, which often cannot flow into the FD and LOFIC through the transfer transistor, and a part of the overflow charge will flow from the overexposed PD into the adjacent unsaturated PD, forming crosstalk between the PDs. This type of crosstalk not only affects the color of the image, but also causes the clarity of the picture to decrease, affecting the image effect.

[0005] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide an image sensor, a manufacturing method and an imaging method to solve the problem of affecting the color of the image and the image effect caused by the charge crosstalk between the PDs in the prior art.

[0007] To achieve the above object and other related objects, the present application provides an image sensor, which comprises:

[0008] a semiconductor structure layer, a circuit connection layer and an optical structure layer;

[0009] The semiconductor structure layer comprises a plurality of pixel units, and a first isolation structure is arranged between adjacent pixel units, wherein the first isolation structure penetrates the semiconductor structure layer in the thickness direction of the semiconductor structure layer.

[0010] The pixel unit comprises a light sensing module and an overflow module; the light sensing module is used for converting a light signal into a charge signal, wherein the charge signal comprises a first charge signal and a second charge signal; the overflow module is used for storing at least the second charge signal, and isolation of the overflow module between adjacent pixel units is realized based on the first isolation structure.

[0011] The circuit connection layer is located on a first surface of the semiconductor structure layer.

[0012] The optical structure layer is located on a second surface of the semiconductor structure layer and comprises a plurality of color filter units, each color filter unit corresponding to each pixel unit.

[0013] Optionally, the pixel unit comprises a plurality of pixel sub-units, and a second isolation structure is arranged between adjacent pixel sub-units, wherein the second isolation structure is a non-continuous structure and is divided into at least two parts by an overflow channel in the thickness direction of the semiconductor structure layer.

[0014] Optionally, the image sensor further comprises an isolation enhancement structure for enhancing the isolation effect of the first isolation structure.

[0015] Optionally, the first isolation structure comprises an insulating layer.

[0016] Optionally, the first isolation structure further comprises a conductive layer, and the insulating layer is located outside the conductive layer.

[0017] Optionally, the first isolation structure comprises at least one of a combination structure of a first STI structure and a first BDTI structure, an FDTI structure and an FBDTI structure.

[0018] Optionally, the second isolation structure comprises a combination structure of a second STI structure and a second BDTI structure.

[0019] Optionally, the isolation enhancement structure comprises a first transmission portion in the circuit connection layer, wherein the first transmission portion is electrically connected with the first isolation structure to transmit a voltage signal, the first isolation structure comprises an insulating layer and a conductive layer, and the insulating layer is located outside the conductive layer; or the first transmission portion is electrically connected with a semiconductor substrate of a first region in the semiconductor structure layer to transmit a voltage signal, the first region comprises a region between a corresponding photosensitive element in a corresponding pixel unit and the first isolation structure.

[0020] Optionally, the isolation enhancement structure comprises a first doped portion in a semiconductor substrate of a first region of the semiconductor structure layer and a second transmission portion in the circuit connection layer and electrically connected with the first doped portion to transmit a voltage signal; or the isolation enhancement structure comprises a first gate portion on the first surface of the semiconductor structure layer and abutting or bridging the semiconductor substrate of a corresponding photosensitive element in a corresponding pixel unit and a first region, and a third transmission portion in the circuit connection layer and electrically connected with the first gate portion to transmit a voltage signal; wherein the first region comprises a region between a corresponding photosensitive element in a corresponding pixel unit and the first isolation structure.

[0021] Optionally, the isolation enhancement structure comprises a second doped portion in a semiconductor substrate of a first region of the semiconductor structure layer, a second gate portion on the first surface of the semiconductor structure layer and electrically connected with the second doped portion and a corresponding photosensitive element of a corresponding pixel unit, and a fourth transmission portion in the circuit connection layer and electrically connected with the second doped portion and a floating diffusion node of the corresponding pixel unit; wherein the fourth transmission portion is also used as a light blocking layer.

[0022] Optionally, the photosensitive module comprises a photosensitive element and a transmission transistor, the overflow module comprises an overflow transistor and an overflow capacitor, and the pixel unit further comprises a reset transistor, a source follower transistor and a row selection transistor.

[0023] The control end of the transfer transistor is connected with a transfer control signal, the first end is connected with a floating diffusion node, and the second end is connected with a first potential via the photosensitive element; the control end of the overflow transistor is connected with an overflow control signal, the first end is connected with the floating diffusion node, and the second end is connected with a second potential via the overflow capacitor; the control end of the reset transistor is connected with a reset control signal, the first end is connected with a third potential, and the second end is connected with the floating diffusion node; the control end of the source follower transistor is connected with the floating diffusion node, the first end is connected with a fourth potential, and the second end is connected with the first end of the row select transistor; the control end of the row select transistor is connected with a row select signal, and the second end is connected with a column line.

[0024] Alternatively, the pixel unit further comprises at least one gain transistor; when the number of the gain transistors is one, the control end of the gain transistor is connected with a gain control signal, the first end is connected with the first end of the overflow transistor and the second end of the reset transistor or only connected with the second end of the reset transistor, and the second end is connected with the floating diffusion node; when the number of the gain transistors is more than one, the gain transistors are connected in series, the first end of the series structure is connected with the first end of the overflow transistor and the second end of the reset transistor or only connected with the second end of the reset transistor, and the second end is connected with the floating diffusion node, wherein the control end of each gain transistor is connected with a corresponding gain control signal.

[0025] Alternatively, the photosensitive module comprises a photosensitive element and a transfer transistor, the overflow module comprises an overflow transistor and an overflow capacitor, and the pixel unit further comprises a reset transistor, a source follower transistor and a row select transistor; the control end of the transfer transistor is connected with a transfer control signal, the first end is connected with a floating diffusion node, and the second end is connected with a first potential via the photosensitive element; the control end of the overflow transistor is connected with an overflow control signal, the first end is connected with the floating diffusion node, and the second end is connected with the second end of the reset transistor and connected with a second potential via the overflow capacitor; the control end of the reset transistor is connected with a reset control signal, and the first end is connected with a third potential; the control end of the source follower transistor is connected with the floating diffusion node, the first end is connected with a fourth potential, and the second end is connected with the first end of the row select transistor; the control end of the row select transistor is connected with a row select signal, and the second end is connected with a column line.

[0026] The application further provides a manufacturing method of the image sensor.

[0027] A semiconductor substrate is provided, a first STI structure and a pixel unit are formed on a first surface of the semiconductor substrate, and a circuit connection layer is formed on the first surface of the semiconductor substrate; the second surface of the semiconductor substrate is thinned, a first BDTI structure is formed on the second surface of the semiconductor substrate, and an optical structure layer is formed on the second surface of the semiconductor substrate, wherein the first BDTI structure and the first STI structure are in contact with each other to form the first isolation structure.

[0028] Alternatively, a semiconductor substrate is provided, a FDTI structure and a pixel unit are formed on a first surface of the semiconductor substrate, and a circuit connection layer is formed on the first surface of the semiconductor substrate; the second surface of the semiconductor substrate is thinned until the FDTI structure is exposed, and an optical structure layer is formed on the second surface of the semiconductor substrate, wherein the FDTI structure forms the first isolation structure.

[0029] Alternatively, a semiconductor substrate is provided, a pixel unit is formed on a first surface of the semiconductor substrate, and a circuit connection layer is formed on the first surface of the semiconductor substrate; the second surface of the semiconductor substrate is thinned, a FBDTI structure is formed on the second surface of the semiconductor substrate, and an optical structure layer is formed on the second surface of the semiconductor substrate, wherein the depth of the FBDTI structure is the same as the thickness of the semiconductor substrate to form the first isolation structure.

[0030] Optionally, when the pixel unit includes a plurality of pixel subunits, the manufacturing method further includes the step of manufacturing a second isolation structure; wherein the method of manufacturing the second isolation structure includes manufacturing a second STI structure on the first surface of the semiconductor substrate and manufacturing a second BDTI structure on the second surface of the semiconductor substrate, wherein the second BDTI structure and the second STI structure are separated by an overflow channel.

[0031] Optionally, the manufacturing method further includes the step of manufacturing an isolation enhancement structure; wherein the corresponding doping part and the corresponding gate part in the isolation enhancement structure are manufactured synchronously with the pixel unit, and the corresponding transmission part in the isolation enhancement structure is manufactured synchronously with the circuit connection layer.

[0032] The application also provides an imaging method of the image sensor as described above, the imaging method including: each pixel unit obtaining image information based on photoelectric conversion, wherein in the photoelectric conversion process, each pixel unit isolates the charge crosstalk between adjacent pixel units through the first isolation structure.

[0033] Optionally, when the image sensor further includes an isolation enhancement structure, the isolation effect of the first isolation structure is further enhanced through the isolation enhancement structure.

[0034] Optionally, when the pixel unit comprises a plurality of pixel subunits, in the photoelectric conversion process, each pixel subunit in the same pixel unit is connected through the overflow channel on the second isolation structure.

[0035] Optionally, the method for obtaining image information by the pixel unit comprises: firstly performing correlated double sampling on the first charge signal corresponding to the photosensitive element in the pixel unit, and then performing non-true correlated double sampling on the second charge signal corresponding to the overflow capacitor in the pixel unit; or, when the pixel unit has different conversion gains, firstly performing correlated double sampling on the first charge signal corresponding to the photosensitive element in the pixel unit under different conversion gains, and then performing non-true correlated double sampling on the second charge signal corresponding to the overflow capacitor in the pixel unit.

[0036] As described above, the image sensor, the manufacturing method and the imaging method of the present application can isolate the charge crosstalk between the photosensitive elements in adjacent pixel units through the first isolation structure, and improve the isolation effect of the first isolation structure through the isolation enhancement structure, so as to avoid the influence of the charge crosstalk on the image color and the picture clarity, improve the image color and the image effect, and improve the imaging quality of the image sensor. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figures 1 to 5 The figure shows the structure schematic diagram of each step involved in another manufacturing method of the image sensor in embodiment one, wherein, Figure 1 is a schematic diagram for manufacturing the first STI structure, Figure 2 is a schematic diagram for manufacturing the pixel unit and the circuit connection layer, Figure 3 is a schematic diagram for thinning the semiconductor substrate, Figure 4 is a schematic diagram for manufacturing the first BDTI structure, Figure 5 is a schematic diagram for manufacturing the optical structure layer.

[0038] Figures 6 to 8 The figure shows the structure schematic diagram of each step involved in another manufacturing method of the image sensor in embodiment one, wherein, Figure 6 is a schematic diagram for manufacturing the FDTI structure, the pixel unit and the circuit connection layer, Figure 7 is a schematic diagram for thinning the semiconductor substrate, Figure 8 is a schematic diagram for manufacturing the optical structure layer.

[0039] Figures 9 to 12 The figure shows the structure schematic diagram of each step involved in another manufacturing method of the image sensor in embodiment one, wherein, Figure 9 is a schematic diagram for manufacturing the pixel unit and the circuit connection layer, Figure 10 is a schematic diagram for thinning the semiconductor substrate, Figure 11 is a schematic diagram for manufacturing the FBDTI structure, Figure 12A schematic diagram of a pixel unit.

[0040] Figure 13 A schematic diagram of a pixel unit.

[0041] Figure 14a A schematic diagram of a pixel unit, Figure 14b A schematic diagram of a pixel unit. Figure 14a A process of obtaining image information by the pixel unit. Figure 15 A schematic diagram of a pixel unit.

[0042] Figure 16a A schematic diagram of a pixel unit. Figure 14a A schematic diagram of a pixel unit, Figure 16b A schematic diagram of a pixel unit. Figure 16c A schematic diagram of a pixel unit. Figure 16a A process of obtaining image information by the pixel unit and a timing diagram.

[0043] Figure 17a A schematic diagram of a pixel unit. Figure 15 A schematic diagram of a pixel unit, Figure 17b A schematic diagram of a pixel unit. Figure 17a A process of obtaining image information by the pixel unit.

[0044] Figure 18a A schematic diagram of a pixel unit. Figure 14a A schematic diagram of a pixel unit, Figure 18b A schematic diagram of a pixel unit. Figure 18a A process of obtaining image information by the pixel unit.

[0045] Figure 19a A schematic diagram of a pixel unit. Figure 19b A schematic diagram of a pixel unit. Figure 19a A process of obtaining image information by the pixel unit.

[0046] Figure 20 A schematic diagram of a pixel unit.

[0047] Figure 21 A schematic diagram of a pixel unit.

[0048] Figure 22 A schematic diagram of a pixel unit.

[0049] Figure 23 A schematic diagram of a pixel unit.

[0050] Figure 24 A schematic diagram showing the isolation enhancement structure in Example 2 including a second doped portion, a second gate portion, and a fourth transfer portion.

[0051] Figure 25 A schematic diagram showing the image sensor in Example 3 including a second isolation structure.

[0052] Figure 26 A schematic diagram showing an application of the isolation enhancement structure in an image sensor.

[0053] Figure 27 A schematic diagram showing another application of the isolation enhancement structure in an image sensor.

[0054] Element Number Description

[0055] 10 image sensor

[0056] 100 semiconductor structure layer

[0057] 100' semiconductor substrate

[0058] 110 pixel unit

[0059] 110' pixel subunit

[0060] 120 first isolation structure

[0061] 120al first STI structure

[0062] 120a2 first BDTI structure

[0063] 120b FDTI structure

[0064] 120c FBDTI structure

[0065] 121 insulating layer

[0066] 122 conductive layer

[0067] 130 second isolation structure

[0068] 131 overflow channel

[0069] 132 second STI structure

[0070] 133 second BDTI structure

[0071] 200 circuit connection layer

[0072] 300 optical structure layer

[0073] 310 color filter unit

[0074] 311 color filter layer

[0075] 312 microlens

[0076] 400 isolation enhancement structure

[0077] 410 first transfer portion

[0078] 420 first doped portion

[0079] 430 second transfer portion

[0080] 440 first gate portion

[0081] 450 third transfer portion

[0082] 460 second doped portion

[0083] 470 second gate portion

[0084] 480 fourth transfer portion DETAILED DESCRIPTION

[0085] The present application is herein described, by way of example only, with reference to the accompanying drawings, wherein:

[0086] Reference will now be made to the drawings, wherein: Figures 1 to 27 It is to be understood that the drawings are to be used only for illustrative purposes and that in no way are the figures to be construed as limiting the present application.

[0087] Embodiment 1

[0088] As shown in Figure 5 , Figure 8 and Figure 12 , the present embodiment provides an image sensor 10, which includes a semiconductor structure layer 100, a circuit connection layer 200, and an optical structure layer 300.

[0089] The semiconductor structure layer 100 includes a plurality of pixel units 110, and a first isolation structure 120 is arranged between adjacent pixel units 110; wherein, in the thickness direction of the semiconductor structure layer 100, the first isolation structure 120 penetrates the semiconductor structure layer 100. Further, the first isolation structure 120 is a continuous structure, which can be a continuous structure formed integrally, or a continuous structure formed by a plurality of first isolation structure segments being connected in contact. In specific applications, the first isolation structure 120 can be arranged between the pixel units 110 of the image sensor 10 as shown in Figure 13 The pixel unit 110 can be a pixel unit composed of a single photosensitive element, or a shared pixel unit composed of a plurality of photosensitive elements.

[0090] The pixel unit 110 obtains image information based on photoelectric conversion; in this embodiment, the pixel unit 110 includes a photosensitive module and an overflow module. The photosensitive module is used to convert a light signal into a charge signal, and the charge signal includes a first charge signal and a second charge signal; the photosensitive module is also used to store at least the first charge signal. The overflow module is electrically connected to a floating diffusion node FD, and is used to store at least the second charge signal to adapt to a high-light scene, and the overflow module includes an overflow capacitor. Wherein, the isolation of the overflow modules between adjacent pixel units 110 is realized based on the first isolation structure 120.

[0091] In combination with actual application scenarios, the first charge signal refers to a charge signal corresponding to a potential well part, and the second charge signal refers to a charge signal corresponding to an overflow part after exceeding the potential well part; in some applications, the first charge signal is defined as a potential well charge signal, and the second charge signal is defined as an overflow charge signal. When the amount of charge sensed by the photosensitive module does not reach an overflow state, the charge signal converted thereby only includes the first charge signal, at which time the second charge signal can be considered to be zero; when the amount of charge sensed by the photosensitive module reaches an overflow state, the charge signal converted thereby includes the first charge signal and the second charge signal.

[0092] As an example, as shown in Figure 14a and Figure 15 The pixel unit 110 includes a photosensitive element PD, an overflow capacitor C, a transfer transistor M1, an overflow transistor M2, a reset transistor M3, a source follower transistor M4, and a row selection transistor M5. Wherein, the photosensitive module includes the photosensitive element PD and the transfer transistor M1, and the overflow module includes the overflow capacitor C and the overflow transistor M2.

[0093] The control terminal of the transfer transistor M1 is connected to a transfer control signal TX, the first terminal is connected to the floating diffusion node FD, and the second terminal is connected to the first potential via the photosensitive element PD. The control terminal of the overflow transistor M2 is connected to an overflow control signal OF, the first terminal is connected to the floating diffusion node FD, and the second terminal is connected to the second potential via the overflow capacitor C. The control terminal of the reset transistor M3 is connected to a reset control signal RST, the first terminal is connected to the third potential, and the second terminal is connected to the floating diffusion node FD. The control terminal of the source follower transistor M4 is connected to the floating diffusion node FD, the first terminal is connected to the fourth potential, and the second terminal is connected to the first terminal of the row selection transistor M5. The control terminal of the row selection transistor M5 is connected to a row selection signal RS, and the second terminal is connected to the column line.

[0094] Further, the pixel unit 110 further includes at least one gain transistor M6, and switching of different conversion gains is performed by controlling the opening and closing of each gain transistor M6.

[0095] When the number of gain transistors M6 is one: for the circuit structure shown in Figure 14a , the control terminal of the gain transistor M6 is connected to a gain control signal DCG, the first terminal is connected to the first terminal of the overflow transistor M2 and the second terminal of the reset transistor M3, and the second terminal is connected to the floating diffusion node FD, as shown in Figure 16a ; for the circuit structure shown in Figure 15 , the control terminal of the gain transistor M6 is connected to a gain control signal DCG, the first terminal is connected to the second terminal of the reset transistor M3, and the second terminal is connected to the floating diffusion node FD, as shown in Figure 17a .

[0096] When the number of gain transistors is greater than one: for the circuit structure shown in Figure 14a , each gain transistor is connected in series, and the first terminal of the series structure is connected to the first terminal of the overflow transistor M2 and the second terminal of the reset transistor M3, and the second terminal of the series structure is connected to the floating diffusion node FD, wherein the control terminal of each gain transistor is connected to a corresponding gain control signal. Figure 18a The case where the number of gain transistors is two is shown; for the circuit structure shown in Figure 17a , each gain transistor is connected in series, and the first terminal of the series structure is connected to the second terminal of the reset transistor M3, and the second terminal of the series structure is connected to the floating diffusion node FD, wherein the control terminal of each gain transistor is connected to a corresponding gain control signal.

[0097] In other examples, different from the circuit structure shown in Figure 14a , the overflow transistor M2 has a different connection relationship; for example Figure 19aAs shown, the overflow transistor M2 is connected between the reset transistor M3 and the floating diffusion node FD. Specifically, the control terminal of the transfer transistor Ml is connected to the transfer control signal TX, the first terminal is connected to the floating diffusion node FD, and the second terminal is connected to the first potential via the photosensitive element PD. The control terminal of the overflow transistor M2 is connected to the overflow control signal OF, the first terminal is connected to the floating diffusion node FD, and the second terminal is connected to the second terminal of the reset transistor M3 and connected to the second potential via the overflow capacitor C. The control terminal of the reset transistor M3 is connected to the reset control signal RST, and the first terminal is connected to the third potential. The control terminal of the source follower transistor M4 is connected to the floating diffusion node FD, the first terminal is connected to the fourth potential, and the second terminal is connected to the first terminal of the row select transistor M5. The control terminal of the row select transistor M5 is connected to the row select signal RS, and the second terminal is connected to the column line. Of course, the pixel unit 110 of the circuit structure can also include at least one gain transistor M6 connected between the overflow transistor M2 and the floating diffusion node FD.

[0098] In an implementation manner, the photosensitive element PD is a photodiode, and all the transistors are NMOS transistors, in which case, the control terminal in the above description refers to the gate, the first terminal refers to the drain, and the second terminal refers to the source. Of course, in other implementation manners, the photosensitive element PD includes a grating or a photoconductor, and all the transistors are PMOS transistors. In addition, in an optional solution, the first potential is a ground potential or a negative potential, the second potential is a ground potential (as shown in Figure 14a ) or a variable potential (as shown in Figure 15 ), the third potential is a power supply potential, and the fourth potential is a power supply potential.

[0099] The first isolation structure 120 is used to physically isolate adjacent pixel units 110, in particular, to isolate the charge exchange between the photosensitive elements PD in adjacent pixel units 110, to avoid the occurrence of charge crosstalk. For example, in the case of the overflow module in the present embodiment, the overflow charge is overflowed to the overflow charge storage element via the overflow path during the exposure process, for example, the second charge signal is overflowed to the overflow capacitor via the overflow path. In the above process, the first isolation structure 120 is beneficial to the retention of the overflow charge signal at each node and prevents leakage to adjacent pixel units 110 to generate crosstalk.

[0100] As an example, the first isolation structure 120 includes an insulating layer 121 and a conductive layer 122, the insulating layer 121 is located at the side of the conductive layer 122, such as the sidewall and the bottom of the conductive layer 122; wherein the insulating layer 121 can be a single layer structure or a multi-layer structure, can be at least one of an oxide layer, a nitride layer and a metal oxide layer; in an optional solution, the insulating layer 121 is a multi-layer structure, such as including an oxide layer and a nitride layer, the nitride layer is located outside the oxide layer; the conductive layer 122 can be a metal layer or a polysilicon layer, which has no substantial influence on the embodiment. In other examples, the first isolation structure 120 can also be a structure including only an insulating layer, for example, the first isolation structure 120 is composed of silicon oxide material, of course, can also be composed of high dielectric constant medium layer such as aluminum oxide. In an implementation, the first isolation structure 120 is made based on FDTI process, BDTI process or STI process combined with BDTI process, including at least one of the combination structure composed of FDTI structure, FBDTI structure, first STI structure and first BDTI structure; it should be noted that the FDTI process can refer to a front-side prepared deep trench isolation structure, the STI process can refer to a front-side prepared shallow trench isolation structure, the BDTI process can refer to a back-side prepared deep trench isolation structure, the specific process can be referred to the description in the method below.

[0101] The circuit connection layer 200 is located at the first surface of the semiconductor structure layer 100, such as the front surface of the semiconductor structure layer 100, and realizes signal transmission by electrically connecting with corresponding components in the pixel unit 110. The circuit connection layer 200 can be prepared by using corresponding structure material and process in the existing image sensor, to realize electrical connection of each transistor and signal lead-out.

[0102] The optical structure layer 300 is located at the second surface of the semiconductor structure layer 100, such as the back surface of the semiconductor structure layer 100, and includes a plurality of color filter units 310, wherein each color filter unit 310 corresponds to each pixel unit 110, and is used to obtain specific light information, such as visible light of specific color. When prepared, corresponding structure material and process in the existing image sensor can be used.

[0103] As an example, the color filter unit 310 includes a color filter layer 311 and a microlens 312, which is located on the side of the color filter layer 311 away from the semiconductor structure layer 100; wherein the color filter layer 311 only allows one color of visible light to pass through, such as only allowing red, green or blue light to pass through so as to form a Bayer color array; of course, the color filter layer 311 can also allow other colors of light to pass through according to actual needs, or even other non-visible light. Of course, the color filter layer 311 can also be configured to pass through visible light (white light). In an optional example, one pixel unit 110 corresponds to light of one color, and adjacent pixel units pass through light of different colors. Further, the image sensor can also implement a phase focus (PDAF) function based on the pixel unit 110. In addition, the color filter unit 310 can also include other structures, such as a transition layer, etc., which has no substantial effect on the present embodiment.

[0104] As shown in Figures 1 to 5 , the present embodiment also provides a manufacturing method of the image sensor 10, including the following steps; wherein the image sensor 10 is the same as the structure described above.

[0105] Step S1, providing a semiconductor substrate 100', manufacturing a first STI structure (front shallow trench isolation structure) 120a1 and a pixel unit 110 on a first side of the semiconductor substrate 100', and manufacturing a circuit connection layer 200 on the first side of the semiconductor substrate 100', as shown in Figure 1 and Figure 2 In the present embodiment, the first STI structure 120a1 is manufactured first, and then the pixel unit 110 is manufactured.

[0106] Specifically as follows: first, using an STI process to manufacture the first STI structure 120a1 on the first side of the semiconductor substrate 100', such as etching the first side of the semiconductor substrate 100' to form a shallow trench and then filling to form the first STI structure 120a1, as shown in Figure 1 ; then, defining a pixel region on the first side of the semiconductor substrate 100' based on the first STI structure 120a1, and using a doping, deposition or other process to manufacture each component in the pixel unit 110 in the pixel region, as shown in Figure 2 ; finally, using a deposition or other process to manufacture the circuit connection layer 200 on the first side of the semiconductor substrate 100', as shown in Figure 2 .

[0107] Step S2, after thinning the second surface of the semiconductor substrate 100', a first BDTI structure (backside deep trench isolation structure) 120a2 is made on the second surface of the semiconductor substrate 100', and an optical structure layer 300 is made on the second surface of the semiconductor substrate 100', wherein the first BDTI structure 120a2 and the first STI structure 120a1 are in contact with each other to form a first isolation structure 120, as shown in Figures 3 to 5 .

[0108] Specifically, first, the structure obtained in step S1 is turned over, and then the second surface of the semiconductor substrate 100' is polished and thinned until a predetermined thickness, as shown in Figure 3 ; then, a first BDTI structure 120a2 is made on the second surface of the semiconductor substrate 100' by using a BDTI process, that is, after etching a deep trench on the second surface of the semiconductor substrate 100', the first BDTI structure 120a2 is formed by filling, at this time, the top of the first BDTI structure 120a2 and the bottom of the first STI structure 120a1 are in contact with each other, as shown in Figure 4 ; finally, an optical structure layer 300 is made on the second surface of the semiconductor substrate 100' by using a related process, as shown in Figure 5 . It should be noted that the filling materials of the shallow trench and the deep trench are usually the same, and the related content can be found in the above, which will not be repeated here.

[0109] Of course, the manufacturing method of the image sensor 10 is not limited to the above method, and other feasible methods should also be applicable to the present embodiment, and two other manufacturing methods different from the above method are shown below.

[0110] In the second manufacturing method:

[0111] Step S1, providing a semiconductor substrate 100', making an FDTI structure (frontside through isolation structure) 120b and a pixel unit 110 on the first surface of the semiconductor substrate 100', and making a circuit connection layer 200 on the first surface of the semiconductor substrate 100', as shown in Figure 6 . In the present embodiment, the FDTI structure 120b is made first, and then the pixel unit 110 is made.

[0112] Specifically, first, an FDTI structure 120b is made on the first surface of the semiconductor substrate 100' by using an FDTI process, that is, after etching a deep trench on the first surface of the semiconductor substrate 100', the FDTI structure 120b is formed by filling, as shown in Figure 6 ; then, based on the FDTI structure 120b, a pixel area is defined on the first surface of the semiconductor substrate 100', and each component in the pixel unit 110 is made in the pixel area by using a doping, deposition or other process, as shown in Figure 6As shown; finally, a circuit connection layer 200 is fabricated on the first surface of the semiconductor substrate 100' using processes such as deposition, as shown. Figure 6 As shown.

[0113] Step S2: Thin the second surface of the semiconductor substrate 100' until the FDTI structure 120b is exposed, and fabricate an optical structure layer 300 on the second surface of the semiconductor substrate 100', wherein the FDTI structure 120b forms a first isolation structure 120, as shown below. Figure 7 and Figure 8 As shown.

[0114] Specifically, the process is as follows: First, after flipping the structure obtained in step S1, the second side of the semiconductor substrate 100' is ground and thinned until the FDTI structure 120b is exposed, as follows: Figure 7 As shown; subsequently, an optical structure layer 300 is fabricated on the second side of the semiconductor substrate 100' using relevant processes, as follows. Figure 8 As shown.

[0115] In the third production method:

[0116] Step S1: A semiconductor substrate 100' is provided, a pixel unit 110 is fabricated on the first surface of the semiconductor substrate 100', and a circuit connection layer 200 is fabricated on the first surface of the semiconductor substrate 100', such as... Figure 9 As shown.

[0117] Specifically, the process is as follows: First, a pixel region is defined on the first surface of the semiconductor substrate 100'. Then, various components in the pixel unit 110 are fabricated in the pixel region using processes such as doping and deposition. Figure 9 As shown; subsequently, a circuit connection layer 200 is fabricated on the first surface of the semiconductor substrate 100' using processes such as deposition, as... Figure 9 As shown.

[0118] Step S2: After thinning the second side of the semiconductor substrate 100', an FBDTI structure (back-side through-hole isolation structure) 120c is fabricated on the second side of the semiconductor substrate 100', and an optical structure layer 300 is fabricated on the second side of the semiconductor substrate 100'. The depth of the FBDTI structure 120c is the same as the thickness of the semiconductor substrate 100' to form the first isolation structure 120. Figures 10 to 12 As shown.

[0119] Specifically, the process is as follows: First, after flipping the structure obtained in step S1, the second side of the semiconductor substrate 100' is ground and thinned until the preset thickness is reached, such as... Figure 10 As shown; subsequently, an FBDTI structure 120c is fabricated on the second side of the semiconductor substrate 100' using a BDTI process. For example, the second side of the semiconductor substrate 100' is etched to form a deep trench, which is then filled to form the FBDTI structure 120c.Figure 11 As shown in FIG. 1, the optical structure layer 300 is formed on the second surface of the semiconductor substrate 100' by using a related process. Figure 12 As shown in FIG. 1, the optical structure layer 300 is formed on the second surface of the semiconductor substrate 100' by using a related process.

[0120] In combination with the above-mentioned pixel unit 110, the embodiment further provides an image sensor 10, which comprises a plurality of pixel units 110. Figure 5 , Figure 8 and Figure 12 The embodiment further provides an imaging method of the above-mentioned image sensor 10, which comprises: obtaining image information by each pixel unit 110 based on photoelectric conversion; and isolating, by each pixel unit 110, charge crosstalk between adjacent pixel units 110 in the photoelectric conversion process.

[0121] The circuit structure of the pixel unit 110 involved in the imaging method of the embodiment is as described above, as shown in FIG. 1. Figures 14a to 19a The pixel unit 110 comprises a photosensitive module and an overflow module, the photosensitive module comprises a photosensitive element, and the overflow module comprises an overflow capacitor.

[0122] When the pixel unit 110 has only one conversion gain, i.e., the pixel unit 110 does not comprise a gain transistor, the method for obtaining image information comprises: firstly performing correlated double sampling on a charge signal (i.e., a potential well charge signal, corresponding to a first charge signal) corresponding to the photosensitive element PD in the pixel unit 110, and then performing non-true correlated double sampling on a charge signal (i.e., an overflow charge signal, corresponding to a second charge signal) corresponding to the overflow capacitor C in the pixel unit 110.

[0123] Taking the circuit structure as shown in FIG. 1 as an example, the process of obtaining image information by the pixel unit 110 comprises a reset phase, an exposure phase and a readout phase, as shown in FIG. 2. Figure 14a Figure 14b The process of obtaining image information by the pixel unit 110 comprises a reset phase, an exposure phase and a readout phase, as shown in FIG. 2.

[0124] In the reset phase, the photosensitive element PD, the overflow capacitor C and the floating diffusion node FD are reset, for example, by the reset transistor M3.

[0125] Specifically, the transfer transistor M1, the overflow transistor M2 and the reset transistor M3 are turned on to reset the photosensitive element PD, the overflow capacitor C and the floating diffusion node FD, and then the transfer transistor M1 and the reset transistor M3 are turned off.

[0126] In the exposure phase, the overflow transistor M2 is turned on, the potential well charge signal is stored based on the photosensitive element PD, and the overflow charge signal is stored based on the floating diffusion node FD and the overflow capacitor C. It should be noted that the off state (e.g., the closed sub-threshold state) of the transfer transistor M1 can be controlled to make the overflow charge in the exposure process overflow to the overflow capacitor C through the transfer transistor M1. ​

[0127] Since the overflow transistor M2 is not closed after the reset operation is completed, i.e., the overflow transistor M2 is opened before the exposure stage starts after the reset stage ends, the exposure stage does not need to perform additional opening control on the overflow transistor M2.

[0128] In the readout stage, the overflow transistor M2 is closed, the correlated double sampling of the potential well charge signal is performed, then the overflow transistor M2 is opened, and the non-true correlated double sampling of the overflow charge signal is performed.

[0129] Specifically, the overflow transistor M2 is closed, the row selection transistor M5 is opened, the reset signal (LCG Rst1) corresponding to the potential well charge signal is quantitatively read out, then the transfer transistor M1 is opened for a period of time and closed, the potential well charge signal in the photosensitive element PD is transferred to the floating diffusion node FD for quantitatively readout (LCG Sig1), and the correlated double sampling of the potential well charge signal is completed.

[0130] The overflow transistor M2 is opened, the transfer transistor M1 is opened for a period of time and closed, the overflow charge signal (Lofic Sig2) in the floating diffusion node FD and the overflow capacitor C is quantitatively read out, then the reset transistor M3 is opened, the floating diffusion node FD and the overflow capacitor C are reset, the reset transistor M3 is closed, the reset signal (Lofic Rst2) corresponding to the overflow charge signal is quantitatively read out, and the non-true correlated double sampling of the overflow charge signal is completed.

[0131] It should be noted that, Figure 19a The image information obtaining process corresponding to the circuit structure shown in the above is the same as the above, and will not be described here. Figure 19b

[0132] When the pixel unit 110 has different conversion gains, i.e., the pixel unit 110 includes at least one gain transistor, the method for obtaining image information includes: first performing correlated double sampling on the charge signal (i.e., the potential well charge signal, corresponding to the first charge signal) corresponding to the photosensitive element PD in the pixel unit 110 under different conversion gains, and then performing non-true correlated double sampling on the charge signal (i.e., the overflow charge signal, corresponding to the second charge signal) corresponding to the overflow capacitor C in the pixel unit 110.

[0133] Taking the circuit structure shown in the above as an example, as shown in the above, Figure 16a Figure 16b and Figure 16c The process of obtaining image information by the pixel unit 110 includes a reset stage, an exposure stage and a readout stage; wherein the presence of the gain transistor M6 makes the pixel unit 110 have a gain node LCG, and the switching of different conversion gains, such as the switching of high and low conversion gains, is performed by opening and closing the gain transistor M6.​​

[0134] In the reset stage, the photodetector PD, the overflow capacitor C, the floating diffusion node FD and the gain node LCG are reset, for example, by the reset transistor M3.

[0135] Specifically, the transfer transistor M1, the overflow transistor M2, the reset transistor M3 and the gain transistor M6 are turned on to reset the photodetector PD, the overflow capacitor C, the floating diffusion node FD and the gain node LCG, and then the transfer transistor M1 and the reset transistor M3 are turned off.

[0136] In the exposure stage, the overflow transistor M2 and the gain transistor M6 are turned on, the potential well charge signal is stored based on the photodetector PD, and the overflow charge signal is stored based on the floating diffusion node FD, the gain node LCG and the overflow capacitor C.

[0137] Since the overflow transistor M2 and the gain transistor M6 are not turned off after the reset operation is completed, that is, the overflow transistor M2 and the gain transistor M6 are turned on before the exposure stage starts after the reset stage ends, the overflow transistor M2 and the gain transistor M6 do not need to be controlled to be turned on additionally in the exposure stage.

[0138] In the readout stage, the overflow transistor M2 is turned off, the correlated double sampling of the potential well charge signal is performed at different conversion gains by controlling the turning on and turning off of the gain transistor M6, and then the overflow transistor M2 is turned on to perform non-true correlated double sampling of the overflow charge signal.

[0139] Specifically, the overflow transistor M2 is turned off and the row selection transistor M5 is turned on, since the gain transistor M6 is in the turned-on state, the pixel unit 110 is in a low conversion gain, and the reset signal corresponding to the potential well charge signal is quantitatively read out (LCG Rst1) at the low conversion gain; then the gain transistor M6 is turned off, the pixel unit 110 is switched from the low conversion gain to a high conversion gain, and the reset signal corresponding to the potential well charge signal is quantitatively read out (HCG Rst2) at the high conversion gain.

[0140] Subsequently, the transfer transistor M1 is turned on for a period of time and then turned off, the potential well charge signal in the photodetector PD is transferred to the floating diffusion node FD for quantitative readout (HCG Sig2) at the high conversion gain; finally, the gain transistor M6 is turned on, the pixel unit 110 is switched to the low conversion gain again, the transfer transistor M1 is turned on for a period of time and then turned off, and the potential well charge signal is transferred to the floating diffusion node FD and the gain node LCG for quantitative readout (LCG Sig1) at the low conversion gain, so that the correlated double sampling of the potential well charge signal at different conversion gains is completed.

[0141] The overflow transistor M2 is opened, the transfer transistor M1 is opened for a period of time and then closed, the overflow charge signal in the floating diffusion node FD, the gain node LCG and the overflow capacitor C is quantitatively read out (Lofic Sig3), then the reset transistor M3 is opened to reset the floating diffusion node FD, the gain node LCG and the overflow capacitor C, and then the reset transistor M3 is closed, the reset signal corresponding to the overflow charge signal is quantitatively read out (Lofic Rst3), and the non-true correlated double sampling of the overflow charge signal is completed.

[0142] It should be noted that, Figure 17a The image information obtaining process corresponding to the circuit structure is the same as above, as shown in Figure 17b , which will not be described here; in addition, Figure 18a The image information obtaining process corresponding to the circuit structure is similar to the above, as shown in Figure 18b , which will not be described here.

[0143] Embodiment two

[0144] As shown in Figures 20 to 24 , the embodiment provides an image sensor 10, which is different from the first embodiment in that the isolation enhancement structure 400 is used to enhance the isolation effect of the first isolation structure 120.

[0145] As an example, as shown in Figure 20 , the isolation enhancement structure 400 includes a first transfer part 410 located in the circuit connection layer 200; wherein the first transfer part 410 is electrically connected with the first isolation structure 120 to transfer the voltage signal, such as the first transfer part 410 realizing electrical connection based on the conductive layer 122 in the first isolation structure 120. In this example, a negative voltage is applied to the first isolation structure 120 through the first transfer part 410, so that positive electricity is induced on both sides of the first isolation structure 120, and the overflow charge of the photosensitive element PD is adsorbed by using the induced positive electricity, thereby enhancing the isolation effect.

[0146] Different from Figure 20 , the first transfer part 410 has different connection relationship; as shown in Figure 21 , the first transfer part 410 is electrically connected with the semiconductor substrate 100' in the first region of the semiconductor structure layer 100 to transfer the voltage signal, wherein the first region includes the region between the corresponding photosensitive element PD and the first isolation structure 120 in the corresponding pixel unit 110. In this example, the semiconductor substrate 100' is a P-type substrate, and a positive voltage is applied to the semiconductor substrate 100' through the first transfer part 410 to attract the overflow charge of the photosensitive element PD and directly lead out, thereby enhancing the isolation effect.

[0147] In other examples, the isolation enhancement structure 400 can be implemented in different ways, and other ways that can enhance the isolation effect of the first isolation structure 120 should also be applicable to this embodiment.

[0148] In another example, such as Figure 22 As shown, the isolation enhancement structure 400 includes a first doped portion 420 and a second transport portion 430. The first doped portion 420 is located in the semiconductor substrate 100' of the first region of the semiconductor structure layer 100, and the second transport portion 430 is located in the circuit connection layer 200 and is electrically connected to the first doped portion 420 to transmit voltage signals. In this example, the semiconductor substrate 100' is a P-type substrate, and the first doped portion 420 is N-type doped. The second transport portion 430 applies a positive voltage to the first doped portion 420 to attract the overflow charge of the photosensitive element PD and directly conduct it, thereby enhancing the isolation effect.

[0149] In yet another example, such as Figure 23 As shown, the isolation enhancement structure 400 includes a first gate portion 440 and a third transmission portion 450. In one optional example, the first gate portion 440 is located on the first surface of the semiconductor structure layer 100, and its projection on the semiconductor substrate surface is adjacent to the projection of the corresponding photosensitive element PD on the semiconductor substrate surface in a first region. In other optional examples, the first gate portion 440 is located on the first surface of the semiconductor structure layer 100 and spans the corresponding photosensitive element PD in the corresponding pixel unit 110 and the semiconductor substrate 100' of the first region. The third transmission portion 450 is located in the circuit connection layer 200 and is electrically connected to the first gate portion 440 to transmit voltage signals. The first region includes the region between the corresponding photosensitive element PD in the corresponding pixel unit 110 and the first isolation structure 120. In one implementation, the first gate portion 440 can have the same gate structure as other transistors in the pixel unit and be fabricated using the same process. In this case, the first gate portion 440 includes a gate layer made of polysilicon and a gate oxide layer located on the surfaces of the polysilicon and the semiconductor substrate. The gate oxide layer includes, but is not limited to, a silicon oxide layer. In this example, the first gate portion 440 and the P-type semiconductor substrate 100' form a MOS capacitor. A negative voltage is applied to the MOS capacitor through the third transmission portion 450, and a positive charge is induced at the corresponding electrode plate of the MOS capacitor. The induced positive charge is used to adsorb the overflow charge of the photosensitive element PD, thereby enhancing the isolation effect.

[0150] In yet another example, such as Figure 24As shown, the isolation enhancement structure 400 includes a second doped portion 460, a second gate portion 470 and a fourth transfer portion 480. The second doped portion 460 is located in the semiconductor substrate 100' of the first region of the semiconductor structure layer 100. The second gate portion 470 is located on the first surface of the semiconductor structure layer 100 and electrically connected to the second doped portion 460 and the corresponding photosensitive element of the corresponding pixel unit. The fourth transfer portion 480 is located in the circuit connection layer 200 and electrically connected to the second doped portion 460 and the floating diffusion node FD of the corresponding pixel unit 110. The fourth transfer portion 480 is also used as a light blocking layer. In an implementation, the second gate portion 470 can be the same as the gate structure of other transistors of the pixel unit and is prepared based on the same process. In the example, the second gate portion 470, the N-type doped second doped portion 460 and the photosensitive element PD form a structure similar to a MOS transistor. The capacity of the floating diffusion node FD is expanded by electrically connecting the structure similar to the MOS transistor to the floating diffusion node FD through the fourth transfer portion 480, so as to absorb more overflow charges of the photosensitive element PD, thereby achieving the enhanced isolation effect. In addition, the fourth transfer portion 480 can also be used as a light blocking layer to prevent waste and crosstalk caused by the overflow of the light signal beyond the photosensitive region.

[0151] It should be noted that the voltage applied to the isolation enhancement structure 400 in the embodiment can provide a suitable voltage value according to the design of the device in the actual pixel unit, so as not to affect the normal process of the pixel unit, and can achieve the enhanced isolation effect based on the isolation enhancement structure 400, so as to prevent the overflow charges of the overexposure from leaking to the adjacent pixel unit to cause crosstalk.

[0152] Correspondingly, the manufacturing method of the image sensor 10 of the embodiment further includes a step of manufacturing the isolation enhancement structure 400. When the isolation enhancement structure 400 includes a corresponding doped portion, the corresponding doped portion is manufactured synchronously with the pixel unit 110. When the isolation enhancement structure 400 includes a corresponding gate portion, the corresponding gate portion is manufactured synchronously with the gate of the transistor of the pixel unit 110. When the isolation enhancement structure 400 includes a corresponding transfer portion, the corresponding transfer portion is manufactured synchronously with the circuit connection layer 200.

[0153] Correspondingly, the imaging method of the image sensor 10 of the embodiment further includes enhancing the isolation effect of the first isolation structure 120 by the isolation enhancement structure 400.

[0154] Embodiment Three

[0155] As Figure 25As shown, the embodiment provides an image sensor 10, which is different from the first embodiment in that a second isolation structure 130 is provided to realize pixel communication. Based on the design of the overflow channel 131, the signal between the pixel subunits of the same pixel unit can interact with each other, for example, when the signal of the photosensitive element of a pixel subunit is full, the photo-generated electrons can flow to the connected other pixel subunits through the overflow channel, so that when the signals of the multiple pixel subunits with overflow channels are combined, the linearity of the combined signal can be improved. Of course, the electron movement and interaction can also be realized at the potential position where interaction is needed through the control of the overflow channel and the surrounding potential. The position of the overflow channel and the number of connected pixel subunits can be designed according to actual needs. Based on the process of preparing the first isolation structure on both sides of the image sensor according to the present application, the preparation of the overflow channel inside the pixel unit can be facilitated, the process can be simplified, and the imaging quality can be improved.

[0156] In the image sensor 10 of the embodiment, the pixel unit 110 includes a plurality of pixel subunits 110', and the second isolation structure 130 is arranged between adjacent pixel subunits 110'. In the thickness direction of the semiconductor structure layer 100, the second isolation structure 130 is a discontinuous structure and is divided into at least two parts by the overflow channel 131. Through the design of the overflow channel 131, the pixel subunits 110' in the same pixel unit 110 can realize pixel communication.

[0157] In actual application, the second isolation structure 130 has the same structure as the first isolation structure 120, and the related content can be found in the first embodiment, which will not be described here. In one implementation, the second isolation structure 130 is made based on the STI process combined with the BDTI process, including a second STI structure 132 and a second BDTI structure 133, which are separated by the overflow channel 131.

[0158] Further, the image sensor 10 of the embodiment further includes an isolation enhancement structure 400 for enhancing the isolation effect of the first isolation structure 120. The related content of the isolation enhancement structure 400 can be found in the second embodiment, which will not be described here.

[0159] It should be noted that for the structure of the image sensor described in the first to third embodiments, when the isolation enhancement structure 400 is present, the isolation enhancement structure 400 can be arranged at the corner of the pixel unit 110. As shown in Figure 26 and Figure 27 As shown, a pixel array schematic diagram composed of a pixel unit with four pixel subunits is shown, and the isolation enhancement structure 400 is arranged at the corner of the pixel unit 100, as shown in Figure 26 As shown, the isolation enhancement structure 400 can be arranged at the corner of the pixel unit 110, as shown in Figure 20The arrangement of the enhanced isolation structure in the first region directly realizes the electrical connection of the first transfer unit 410. Figure 26 As shown in the line highlighted area, as shown in the line highlighted area, Figure 27 As shown in the line highlighted area, as shown in the line highlighted area, Figure 21 And Figure 22 The arrangement of the enhanced isolation structure in the first region directly realizes the electrical connection of the corresponding transfer unit. Figure 27 As shown in the filling area.

[0160] Correspondingly, the manufacturing method of the image sensor 10 also includes the step of manufacturing the second isolation structure 130; wherein the method of manufacturing the second isolation structure 130 includes: manufacturing the second STI structure 132 on the first surface of the semiconductor substrate 100', and manufacturing the second BDTI structure 133 on the second surface of the semiconductor substrate 100', wherein the second BDTI structure 133 is separated from the second STI structure 132 by the overflow channel 131.

[0161] In actual application, if the manufacturing method includes the step of manufacturing the second isolation structure 130, in order to simplify the process steps, the first isolation structure 120 is usually also manufactured based on the STI process combined with the BDTI process, at this time, the second isolation structure 130 is manufactured synchronously with the first isolation structure 120, and the width of the corresponding groove in the second isolation structure 130 can be controlled to be greater than the width of the corresponding groove in the first isolation structure 120, so as to realize that the second isolation structure 130 is a non-continuous structure and the first isolation structure 120 is a continuous structure in the thickness direction.

[0162] Further, the manufacturing method of the embodiment can also include the step of manufacturing the isolation enhancement structure 400; wherein when the isolation enhancement structure 400 includes a corresponding doping part, the corresponding doping part is manufactured synchronously with the doping area of the transistor element in the pixel unit 110; when the isolation enhancement structure 400 includes a corresponding gate part, the corresponding gate part is manufactured synchronously with the transistor gate in the pixel unit 110; when the isolation enhancement structure 400 includes a corresponding transfer part, the corresponding transfer part is manufactured synchronously with the circuit connection layer 200.

[0163] Correspondingly, the imaging method of the image sensor 10 of the embodiment, in the photoelectric conversion process, each pixel sub-unit 110' in the same pixel unit 110 is connected between pixels through the overflow channel 131 on the second isolation structure 130.

[0164] Further, the imaging method of the embodiment can also include enhancing the isolation effect of the first isolation structure 120 by the isolation enhancement structure 400.

[0165] In summary, the image sensor, manufacturing method, and imaging method of the present invention isolate charge crosstalk between photosensitive elements in adjacent pixel units through a first isolation structure, and enhance the isolation effect of the first isolation structure through an isolation enhancement structure. This avoids the impact of charge crosstalk on image color and image clarity, improves image color and image quality, and enhances the imaging quality of the image sensor. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0166] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized by, The image sensor comprises: a semiconductor structure layer, a circuit connection layer, and an optical structure layer; the semiconductor structure layer comprises a plurality of pixel units, and a first isolation structure is arranged between adjacent pixel units, wherein the first isolation structure penetrates the semiconductor structure layer in a thickness direction of the semiconductor structure layer; the pixel unit comprises a photosensitive module and an overflow module; the photosensitive module is configured to convert a light signal into a charge signal, wherein the charge signal comprises a first charge signal and a second charge signal; and the overflow module is configured to store at least the second charge signal, wherein the first isolation structure is configured to at least achieve isolation of the overflow modules between adjacent pixel units; the circuit connection layer is located on a first surface of the semiconductor structure layer; the optical structure layer is located on a second surface of the semiconductor structure layer and comprises a plurality of color filter units, each color filter unit corresponding to each pixel unit.

2. The image sensor of claim 1, wherein, The pixel unit comprises a plurality of pixel sub-units, and a second isolation structure is arranged between adjacent pixel sub-units, wherein the second isolation structure is a non-continuous structure and is divided into at least two parts by an overflow channel in the thickness direction of the semiconductor structure layer.

3. The image sensor according to claim 1 or 2, characterized by The image sensor further comprises an isolation enhancement structure configured to enhance the isolation effect of the first isolation structure; and / or the first isolation structure comprises an insulating layer, or the first isolation structure further comprises a conductive layer and the insulating layer is located on the outer side of the conductive layer; and / or the first isolation structure comprises at least one of a combination structure of a first STI structure and a first BDTI structure, an FDTI structure, and an FBDTI structure; and / or the second isolation structure comprises a combination structure of a second STI structure and a second BDTI structure.

4. The image sensor of claim 3, wherein, The isolation enhancement structure comprises a first transmission part located in the circuit connection layer; wherein the first transmission part is electrically connected with the first isolation structure to transmit a voltage signal, the first isolation structure comprises an insulating layer and a conductive layer and the insulating layer is located on the outer side of the conductive layer; or the first transmission part is electrically connected with a semiconductor substrate of a first region in the semiconductor structure layer to transmit a voltage signal, the first region comprising a region between a corresponding photosensitive element in a corresponding pixel unit and the first isolation structure.

5. The image sensor of claim 3, wherein, The isolation enhancement structure comprises a first doped portion and a second transmission portion, the first doped portion is located in the semiconductor substrate of the first region of the semiconductor structure layer, and the second transmission portion is located in the circuit connection layer and is electrically connected with the first doped portion to transmit a voltage signal; or the isolation enhancement structure comprises a first gate portion and a third transmission portion, the first gate portion is located on the first surface of the semiconductor structure layer and is adjacent to the projection of the corresponding photosensitive element on the semiconductor substrate surface in the first region or the first gate portion is located on the first surface of the semiconductor structure layer and crosses the corresponding photosensitive element in the corresponding pixel unit and the semiconductor substrate of the first region, and the third transmission portion is located in the circuit connection layer and is electrically connected with the first gate portion to transmit a voltage signal; wherein the first region comprises a region between the corresponding photosensitive element in the corresponding pixel unit and the first isolation structure.

6. The image sensor of claim 3, wherein, The isolation enhancement structure comprises a second doped portion, a second gate portion and a fourth transmission portion, the second doped portion is located in the semiconductor substrate of the first region of the semiconductor structure layer, the second gate portion is located on the first surface of the semiconductor structure layer and is electrically connected with the second doped portion and the corresponding photosensitive element of the corresponding pixel unit, and the fourth transmission portion is located in the circuit connection layer and is electrically connected with the second doped portion and the floating diffusion node of the corresponding pixel unit; wherein the fourth transmission portion is also used as a light blocking layer.

7. The image sensor of claim 1, wherein, The photosensitive module comprises a photosensitive element and a transfer transistor, the overflow module comprises an overflow transistor and an overflow capacitor, and the pixel unit further comprises a reset transistor, a source follower transistor and a row selection transistor, wherein: The control end of the transfer transistor is connected with a transfer control signal, the first end is connected to a floating diffusion node, and the second end is connected with a first potential via the photosensitive element; the control end of the overflow transistor is connected with an overflow control signal, the first end is connected to a floating diffusion node, and the second end is connected with a second potential via the overflow capacitor; the control end of the reset transistor is connected with a reset control signal, the first end is connected with a third potential, and the second end is connected to a floating diffusion node; the control end of the source follower transistor is connected to a floating diffusion node, the first end is connected with a fourth potential, and the second end is connected to the first end of the row selection transistor; the control end of the row selection transistor is connected with a row selection signal, and the second end is connected to a column line; Or, the pixel unit further comprises at least one gain transistor; when the number of gain transistors is one, the control end of the gain transistor is connected with a gain control signal, the first end is connected with the first end of the overflow transistor and the second end of the reset transistor or only connected with the second end of the reset transistor, and the second end is connected to a floating diffusion node; when the number of gain transistors is more than one, the gain transistors are connected in series, the first end of the series connection structure is connected with the first end of the overflow transistor and the second end of the reset transistor or only connected with the second end of the reset transistor, and the second end is connected to a floating diffusion node, wherein the control end of each gain transistor is connected with a corresponding gain control signal.

8. The image sensor of claim 1, wherein, The photosensitive module comprises a photosensitive element and a transfer transistor, the overflow module comprises an overflow transistor and an overflow capacitor, the pixel unit further comprises a reset transistor, a source follower transistor and a row selection transistor; a control end of the transfer transistor is connected to a transfer control signal, a first end is connected to a floating diffusion node, and a second end is connected to a first potential via the photosensitive element; a control end of the overflow transistor is connected to an overflow control signal, a first end is connected to the floating diffusion node, and a second end is connected to a second end of the reset transistor and connected to a second potential via the overflow capacitor; a control end of the reset transistor is connected to a reset control signal, a first end is connected to a third potential; a control end of the source follower transistor is connected to the floating diffusion node, a first end is connected to a fourth potential, and a second end is connected to a first end of the row selection transistor; a control end of the row selection transistor is connected to a row selection signal, and a second end is connected to a column line.

9. A method of manufacturing an image sensor as claimed in any one of claims 1 to 8, characterized in that The manufacturing method comprises: providing a semiconductor substrate, manufacturing a first STI structure and a pixel unit on a first surface of the semiconductor substrate, and manufacturing a circuit connection layer on the first surface of the semiconductor substrate; thinning a second surface of the semiconductor substrate, manufacturing a first BDTI structure on the second surface of the semiconductor substrate, and manufacturing an optical structure layer on the second surface of the semiconductor substrate, wherein the first BDTI structure and the first STI structure are in contact with each other to form the first isolation structure; or, providing a semiconductor substrate, manufacturing a FDTI structure and a pixel unit on a first surface of the semiconductor substrate, and manufacturing a circuit connection layer on the first surface of the semiconductor substrate; thinning a second surface of the semiconductor substrate until the FDTI structure is exposed, and manufacturing an optical structure layer on the second surface of the semiconductor substrate, wherein the FDTI structure forms the first isolation structure; or, providing a semiconductor substrate, manufacturing a pixel unit on a first surface of the semiconductor substrate, and manufacturing a circuit connection layer on the first surface of the semiconductor substrate; thinning a second surface of the semiconductor substrate, manufacturing a FBDTI structure on the second surface of the semiconductor substrate, and manufacturing an optical structure layer on the second surface of the semiconductor substrate, wherein the depth of the FBDTI structure is the same as the thickness of the semiconductor substrate to form the first isolation structure.

10. The method of manufacturing an image sensor according to claim 9, wherein When the pixel unit comprises a plurality of pixel subunits, the manufacturing method further comprises the step of manufacturing a second isolation structure; wherein the method of manufacturing the second isolation structure comprises: manufacturing a second STI structure on the first surface of the semiconductor substrate, and manufacturing a second BDTI structure on the second surface of the semiconductor substrate, wherein the second BDTI structure and the second STI structure are separated by an overflow channel.

11. The method of manufacturing an image sensor according to claim 9 or 10, wherein The manufacturing method further comprises the step of manufacturing an isolation enhancement structure; wherein a corresponding doping portion and a corresponding gate portion in the isolation enhancement structure are manufactured synchronously with the pixel unit, and a corresponding transfer portion in the isolation enhancement structure is manufactured synchronously with the circuit connection layer.

12. An imaging method of the image sensor as claimed in any one of claims 1 to 8, characterized by, The imaging method comprises: obtaining image information by each pixel unit based on photoelectric conversion, wherein in the photoelectric conversion process, each pixel unit is isolated from the charge crosstalk between adjacent pixel units by the first isolation structure.

13. The imaging method of an image sensor according to claim 12, wherein, When the image sensor further comprises an isolation enhancement structure, the isolation effect of the first isolation structure is further enhanced by the isolation enhancement structure.

14. The imaging method of an image sensor according to claim 12, wherein, When the pixel unit comprises a plurality of pixel sub-units, in the photoelectric conversion process, each pixel sub-unit in the same pixel unit is connected by an overflow channel on the second isolation structure.

15. The imaging method of an image sensor according to any one of claims 12 to 14, characterized by, The method for obtaining image information by the pixel unit comprises: firstly performing correlated double sampling on a first charge signal corresponding to a light sensing element in the pixel unit, and then performing non-true correlated double sampling on a second charge signal corresponding to an overflow capacitor in the pixel unit; or, when the pixel unit has different conversion gains, firstly performing correlated double sampling on the first charge signal corresponding to the light sensing element in the pixel unit under different conversion gains, and then performing non-true correlated double sampling on the second charge signal corresponding to the overflow capacitor in the pixel unit.

Images