Dynamic characteristic enhancement structure of siC VDMOSFET with multi-stage field plate junction and preparation process thereof

Abstract

The application relates to the field of MOS semiconductor technology and discloses a SiC VDMOSFET dynamic characteristic enhancement structure with a multi-stage field plate junction and a preparation process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprises a drain, a semiconductor epitaxial layer, a gate, a gate oxide field plate and a source, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, the gate oxide field plate is located between the gate and the semiconductor epitaxial layer, and a field plate junction is deposited between the gate oxide field plate and the gate, the field plate junction is composed of a plurality of mutually non-contacting silicon dioxide deposition blocks. By adopting the self-aligned multi-stage field plate structure, the application realizes the optimized modulation of the electric field distribution on the gate oxide field plate, effectively suppresses the electric field concentration phenomenon at the edge of the gate, and significantly improves the breakdown voltage and dynamic stability of the device, so that the device shows higher reliability in high-voltage switch applications.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a SiC VDMOSFET dynamic characteristic enhancement structure with a multi-stage field plate junction and a preparation process thereof. BACKGROUND

[0002] Silicon carbide (SiC) VDMOSFET as a new generation of power semiconductor devices, due to its high breakdown field strength, high thermal conductivity and low switching loss, etc. advantages, in high temperature, high frequency and high voltage application scenarios show great potential. However, the traditional SiC VDMOSFET in the dynamic working process, due to the edge of the gate electric field concentration, drift region electric field distribution is uneven and interface state effect, etc. problems, prone to current collapse, switching speed decline and reliability degradation and other phenomena, restrict its further application in high performance power system.

[0003] The existing patent discloses a preparation method of high-density self-aligned silicon carbide MOS device (publication number CN115188674A). The existing patent has the problem of dynamic characteristic deterioration caused by uneven electric field distribution, specifically, the reliability decline caused by the edge of the gate electric field concentration in the high voltage switching process, the contradiction between the on-resistance and the breakdown voltage caused by the insufficient drift region electric field modulation, and the high frequency switching loss and current collapse caused by the interface state effect and poor capacitance characteristics. SUMMARY

[0004] The present application provides a SiC VDMOSFET dynamic characteristic enhancement structure with a multi-stage field plate junction and a preparation process thereof to solve the existing technical problems, which solves the problem of limited electric field modulation effect and insignificant dynamic characteristic improvement.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a SiC VDMOSFET dynamic characteristic enhancement structure with a multi-stage field plate junction, comprising a plurality of MOS cells arranged side by side, each MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide field plate and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, the gate oxide field plate being located between the gate and the semiconductor epitaxial layer, wherein a field plate junction is deposited between the gate oxide field plate and the gate, the field plate junction being composed of a plurality of mutually non-contacting silicon dioxide deposition blocks;

[0006] Among them, the range of the silicon dioxide deposition block at the middle covering on the gate oxide field plate is large, and the range of the silicon dioxide deposition block at both sides covering on the gate oxide field plate is small.

[0007] Further, the inside of the N substrate layer is formed with a plurality of mutually non-contacting contact P-type junction regions by ion implantation, and the contact P-type junction region is in ohmic contact with the drain.

[0008] Further, the cross-sectional width of the P-type junction region in the middle of the single MOS cell is larger, and the cross-sectional width of the P-type junction region on both sides is smaller.

[0009] Further, the inside of the N substrate layer and above the P-type junction region is formed with a contact cover layer by ion implantation, the contact cover layer is of N-type material with a doping concentration larger than that of the N substrate layer, and the contact cover layer is in ohmic contact with the drain.

[0010] Further, the inside of the N drift layer and below the gate oxide field plate is formed with a plurality of P-type field plate junctions that are not in contact with each other by ion implantation.

[0011] Further, the cross-sectional depth of the P-type field plate junction in the middle is larger, and the cross-sectional depth of the P-type field plate junction on both sides is smaller.

[0012] Further, the P-type junction region further includes a gradient junction region, the cross-sectional height of the gradient junction region in the middle of the single MOS cell is lower, and the cross-sectional height of the gradient junction region on both sides is higher.

[0013] Further, the inside of the N drift layer is formed with a plurality of intermediate P-type junction regions that are not in contact with each other by ion implantation, the cross-sectional width of the intermediate P-type junction region in the middle is large, and the cross-sectional width of the intermediate P-type junction region on both sides is small, and the bottom end of the intermediate P-type junction region is in direct contact with the N substrate layer.

[0014] Further, the inside of the N drift layer and above the intermediate P-type junction region is formed with an intermediate cover layer by ion implantation, the intermediate cover layer is in direct contact with the N substrate layer, and the intermediate cover layer is of N-type material with a doping concentration larger than that of the N drift layer.

[0015] Further, the inside of the N drift layer and above the intermediate cover layer is formed with an intermediate N-layer by ion implantation, the doping concentration of the intermediate N-layer is lower than that of the N drift layer.

[0016] The preparation process of the SiC VDMOSFET dynamic characteristic enhancement structure with multi-level field plate junctions specifically includes:

[0017] S1, forming an N drift layer on an N substrate layer by epitaxial growth;

[0018] S2, sequentially forming a P well layer, an N well layer, and a P+ layer in the N drift layer by ion implantation, and activating the implanted ions by high-temperature annealing;

[0019] S3, growing a gate oxide layer on the semiconductor epitaxial layer, and forming a gate oxide field plate by a photolithography and etching process;

[0020] S4, depositing a silicon dioxide layer on the gate oxide field plate, and forming a field plate knot by a self-aligned photolithography and etching process, the field plate knot is composed of a plurality of non-contacting silicon dioxide deposition blocks, and the silicon dioxide deposition block in the middle covers a large range on the gate oxide field plate, and the silicon dioxide deposition blocks on both sides cover a small range on the gate oxide field plate;

[0021] S5, depositing a polysilicon or metal layer on the field plate knot, and forming a gate electrode by photolithography and etching;

[0022] S6, forming a contact area of a source in the N well layer and the P+ layer by an ion implantation and annealing process, and forming a contact area of a drain on the back of the N substrate layer;

[0023] S7, depositing a metal layer, forming an ohmic contact of the source and the drain by photolithography and etching, and completing the preparation of the device.

[0024] The SiC VDMOSFET dynamic characteristic enhancement structure with a multi-stage field plate knot and the preparation process thereof provided by the application have the following effects compared with the prior art:

[0025] 1. By adopting the self-aligned multi-stage field plate structure, the application optimizes the modulation of the electric field distribution on the gate oxide field plate, effectively suppresses the electric field concentration phenomenon at the edge of the gate, thereby significantly improving the breakdown voltage and dynamic stability of the device, and making it show higher reliability in high-voltage switch applications.

[0026] 2. By introducing a depth-gradually-changing P-type junction region below the field plate and combining with a width-gradually-changing contact P-type junction region in the substrate, a multi-dimensional electric field modulation mechanism is formed, which not only optimizes the electric field distribution of the drift region, but also effectively reduces the on-resistance and improves the dynamic response characteristics of the device in the high-speed switching state.

[0027] 3. By introducing a high-doped N-type cover layer above the contact junction region and forming an ohmic contact with the drain, the current spreading performance and contact characteristics are improved, the on-resistance and thermal resistance of the device are reduced, thereby improving the overall energy efficiency and high-temperature working stability.

[0028] 4. By constructing a composite terminal structure of the middle-wide and both-side-narrow P-type junction region combined with the high-doped N-type cover layer in the drift region, effective charge compensation is realized, the voltage withstanding capability of the device is further enhanced, and the output capacitance is reduced, which is beneficial to improve the switching speed and reduce the switching loss.

[0029] 5. By introducing a low-doped middle N-type layer on the upper part of the drift region, a longitudinal doping gradient structure is formed, which effectively optimizes the capacitance characteristics and electric field distribution of the device, significantly reduces the energy loss in the switching process, and improves the comprehensive performance of the device in high-frequency applications. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention;

[0031] Figure 2 This is a schematic diagram of Embodiment 2 of the present invention;

[0032] Figure 3 This is a schematic diagram of Embodiment 3 of the present invention;

[0033] Figure 4 This is a schematic diagram of Embodiment 4 of the present invention;

[0034] Figure 5 This is a schematic diagram of Embodiment 5 of the present invention;

[0035] Figure 6 This is a schematic diagram of Embodiment Six of the present invention.

[0036] In the diagram: 1. Drain; 2. Gate; 3. Gate oxide field plate; 4. Source; 5. N-substrate layer; 6. N-drift layer; 7. N-well layer; 8. P+ layer; 9. P-well layer; 10. Field plate junction; 11. Contact P-type junction region; 12. Contact capping layer; 13. P-type field plate junction; 14. Intermediate P-type junction region; 15. Intermediate capping layer; 16. Intermediate N-layer; 1101. Gradient junction region. Detailed Implementation

[0037] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, the fabrication process of the SiC VDMOSFET dynamic characteristic enhancement structure with multi-level field junctions specifically includes:

[0039] Step 1: An N-drift layer 6 is formed on the N-substrate layer 5 by epitaxial growth. By epitaxially growing an N-drift layer with precise doping concentration and thickness on the N-type SiC substrate, a high-quality high-voltage bearing region is constructed for the device. The drift layer formed in this step has a uniform doping distribution and excellent crystal quality, which provides an ideal foundation for subsequent ion implantation and terminal structure fabrication, thereby ensuring that the device has the potential for low on-resistance and high breakdown voltage.

[0040] Step 2: P-well layer 9, N-well layer 7, and P+ layer 8 are sequentially formed in N-drift layer 6 by ion implantation, and the implanted ions are activated by high-temperature annealing. Through multi-step ion implantation, P-well, N-well, and P+ contact regions are precisely formed, defining the cell structure and conductive channels of the device. Combined with the high-temperature annealing process, the implanted ions are effectively activated and lattice damage is repaired. This step achieves precise control of the conductive channel and bulk region, providing the device with good threshold voltage stability and reliable conduction characteristics.

[0041] Step three, growing a gate oxide layer on the semiconductor epitaxial layer, and forming a gate oxide field plate 3 through a photoetching and etching process; growing a high-quality gate oxide layer through thermal oxidation and photoetching to form a gate oxide field plate, the gate oxide medium prepared in this step has low interface state density and high breakdown field strength characteristics, the formation of the gate oxide field plate not only provides insulation isolation for the gate, but also lays a foundation for the preparation of subsequent multi-level field plate structures, effectively improving the reliability and stability of the gate.

[0042] Step four, depositing a silicon dioxide layer on the gate oxide field plate 3, and forming a field plate knot 10 through a self-aligned photoetching and etching process, the field plate knot 10 is composed of several silicon dioxide deposition blocks that do not contact each other, and the silicon dioxide deposition block in the middle covers a large range on the gate oxide field plate 3, and the silicon dioxide deposition blocks on both sides cover a small range on the gate oxide field plate 3; using a self-aligned photoetching technology to prepare a silicon dioxide field plate knot with gradient coverage characteristics on the gate oxide field plate, this step realizes accurate control of the size of the field plate, optimizes the electric field distribution through the design of large coverage in the middle and small coverage on both sides, effectively alleviates the electric field concentration at the edge of the gate, and significantly improves the voltage withstand capability and dynamic stability of the device.

[0043] Step five, depositing a polysilicon or metal layer on the field plate knot 10, and forming a gate 2 through photoetching and etching; depositing a conductive layer and photoetching to form a gate electrode, this step realizes good contact and accurate alignment with the field plate structure, and the formed gate has good conductivity and interface characteristics, which not only ensures the gate control capability but also avoids introducing additional parasitic parameters, providing a guarantee for the high-frequency switching performance of the device.

[0044] Step six, forming a contact area of a source 4 in the N well layer 7 and the P+ layer 8 through an ion implantation and annealing process, and forming a contact area of a drain 1 on the back of the N substrate layer 5; forming a source ohmic contact in the N well and the P+ region through selective ion implantation, and simultaneously preparing a drain contact on the back of the substrate, this step realizes the formation of a low-resistance ohmic contact, optimizes the current transmission path of the device, reduces the contact resistance and series resistance, and improves the conduction efficiency and current handling capability of the device.

[0045] Step seven, depositing a metal layer, forming an ohmic contact of the source 4 and the drain 1 through photoetching and etching, and completing the preparation of the device. Through metal deposition and photoetching process, the electrode preparation of the source and the drain is completed, this step forms a low-resistance and reliable metal-semiconductor ohmic contact, which optimizes the distribution characteristics of the current in the horizontal and vertical directions, not only reduces the conduction loss of the device, but also improves the thermal stability and long-term working reliability of the device.

[0046] Example 1

[0047] As Figure 1As shown, the SiC VDMOSFET dynamic characteristic enhancement structure with multi-level field junctions includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, a gate oxide field plate 3, and a source 4. The semiconductor epitaxial layer includes an N substrate layer 5, an N drift layer 6, an N well layer 7, a P+ layer 8, and a P well layer 9. The gate oxide field plate 3 is located between the gate 2 and the semiconductor epitaxial layer. A field junction 10 is deposited between the gate oxide field plate 3 and the gate 2. The field junction 10 is composed of several non-contact silicon dioxide deposits. The silicon dioxide deposits in the middle cover a large area on the gate oxide field plate 3, while the silicon dioxide deposits on both sides cover a small area on the gate oxide field plate 3.

[0048] By employing a silicon dioxide deposition block structure with a large central coverage area and small side coverage areas in the field junction 10, the electric field gradient on the gate oxide field plate 3 was optimized using a self-aligned process. The principle is that by adjusting the coverage area of ​​the field junction 10 at different positions, the electric field distribution at the edge of the gate 2 is effectively modulated, thereby suppressing electric field concentration and improving the breakdown voltage and dynamic stability of the device. The advantage is a significant enhancement of the reliability of the VDMOSFET during high-voltage switching.

[0049] Example 2

[0050] like Figure 2 As shown, several non-contacting P-type junction regions 11 are formed inside the N-substrate layer 5 through ion implantation. These P-type junction regions 11 are in 1-ohm contact with the drain. The cross-sectional width of the P-type junction region 11 at the center of a single MOS cell is larger, while the cross-sectional width of the P-type junction region 11 at both sides is smaller.

[0051] A contact P-type junction region 11 with a gradually varying cross-sectional width is formed in the N-substrate layer 5. The structure design, which is wider in the middle and narrower on both sides, makes the depletion region expand more uniformly in both the longitudinal and lateral directions. The principle is to optimize the charge balance by varying the width of the contact P-type junction region 11, thereby reducing the peak electric field on the drain side. The advantage is that it effectively reduces the on-resistance, while improving the device's breakdown voltage and dynamic response speed.

[0052] Example 3

[0053] like Figure 3 As shown, a contact capping layer 12 is formed inside the N substrate layer 5 and above the contact P-type junction region 11 by ion implantation. The contact capping layer 12 is an N-type material with a doping concentration greater than that of the N substrate layer 5 (the contact capping layer 12 is in a state of semi-enclosing the contact P-type junction region 11), and the contact capping layer 12 is in 1-ohm contact with the drain electrode.

[0054] A high-doped N-type contact layer 12 is introduced above the P-type junction region 11, which forms an ohmic contact with the drain 1, and its semi-enclosed structure enhances the contact performance of the junction region and the electrode. The principle is to reduce the contact resistance by high-concentration doping and improve the current spreading. The advantage is to improve the on-state efficiency and thermal stability of the device, which is suitable for high-frequency and high-current application scenarios.

[0055] Embodiment 4

[0056] As shown in Figure 4 , the inside of the N drift layer 6 and below the gate oxide field plate 3 are formed by ion implantation with a plurality of P-type field plate junctions 13 that are not in contact with each other; and the cross-sectional depth of the P-type field plate junction 13 in the middle is larger, and the cross-sectional depth of the P-type field plate junction 13 on both sides is smaller. The P-type junction region 11 also includes a gradual junction region 1101, and the cross-sectional height of the gradual junction region 1101 in the middle of a single MOS cell is lower, and the cross-sectional height of the gradual junction region 1101 on both sides is higher.

[0057] The depth-graded P-type field plate junction 13 is provided below the gate oxide field plate 3, and cooperates with the height-graded junction region 1101 in the P-type junction region 11 to form a multi-dimensional electric field modulation structure. The principle is to realize the sharing of electric field in the vertical and horizontal directions through the coordinated gradient design of junction depth and junction height, and the advantage is to further suppress the current collapse phenomenon in the dynamic switching process, and to improve the high-frequency dynamic characteristics of the device.

[0058] Embodiment 5

[0059] As shown in Figure 5 , the inside of the N drift layer 6 is formed by ion implantation with a plurality of intermediate P-type junction regions 14 that are not in contact with each other, and the cross-sectional width of the intermediate P-type junction region 14 in the middle is large, and the cross-sectional width of the intermediate P-type junction region 14 on both sides is small, and the bottom end of the intermediate P-type junction region 14 is in direct contact with the N substrate layer 5. The inside of the N drift layer 6 and below the intermediate P-type junction region 14 is formed by ion implantation with an intermediate cover layer 15, which is in direct contact with the N substrate layer 5, and the intermediate cover layer 15 is of N-type material with a doping concentration greater than that of the N drift layer 6.

[0060] The intermediate P-type junction region 14 with a wide middle and narrow sides is introduced in the N drift layer 6, and is combined with the highly doped N-type intermediate cover layer 15 to form a composite termination structure. The principle is to build a charge compensation effect through the alternating arrangement of P-type junction regions (intermediate P-type junction regions 14) and N-type cover layers (intermediate cover layers 15), and the advantage is to effectively reduce the resistance of the drift region and improve the overall voltage withstand level and dynamic stability of the device.

[0061] Embodiment 6

[0062] As shown in Figure 6As shown, the inside of the N drift layer 7 is formed with several intermediate P-type junction regions 14 by ion implantation, the cross-sectional width of the intermediate P-type junction regions 14 at the middle is large, the cross-sectional width of the intermediate P-type junction regions 14 at both sides is small, and the bottom end of the intermediate P-type junction regions 14 is in direct contact with the N substrate layer 5. The inside of the N drift layer 6 and above the intermediate P-type junction regions 14 is formed with an intermediate cover layer 15 by ion implantation, the intermediate cover layer 15 is in direct contact with the N substrate layer 5, and the intermediate cover layer 15 is of N type material with a doping concentration greater than that of the N drift layer 6. The inside of the N drift layer 6 and above the intermediate cover layer 15 is formed with an intermediate N layer 16 by ion implantation, and the doping concentration of the intermediate N layer 16 is lower than that of the N drift layer 6.

[0063] The low-doped intermediate N layer 16 is added above the intermediate cover layer 15 to form a three-layer longitudinal doping gradient structure. The principle is to introduce a lightly doped layer on the upper part of the drift region 6 to slow down the rate of change of the electric field and optimize the output capacitance characteristics, and the advantage is to significantly reduce the switching loss and improve the energy efficiency and reliability of the device in high-speed switching applications.

[0064] The above-described embodiments only express several embodiments of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A multi-stage field plate junction SiC VDMOSFET dynamic characteristic enhancement structure, comprising a plurality of MOS cells arranged in parallel, each of the MOS cells comprising a drain electrode (1), a semiconductor epitaxial layer, a gate electrode (2), a gate oxide field plate (3) and a source electrode (4), the semiconductor epitaxial layer comprising an N substrate layer (5), an N drift layer (6), an N well layer (7), a P+ layer (8) and a P well layer (9), characterized in that: The gate oxide field plate (3) is located between the gate (2) and the semiconductor epitaxial layer, wherein a field plate knot (10) is deposited between the gate oxide field plate (3) and the gate (2), and the field plate knot (10) is composed of a plurality of mutually non-contacting silicon dioxide deposition blocks; ​ Wherein, the range of the silicon dioxide deposition block at the middle part covering on the gate oxide field plate (3) is large, and the range of the silicon dioxide deposition block at the two sides covering on the gate oxide field plate (3) is small.

2. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction according to claim 1, characterized in that: The inside of the N substrate layer (5) is formed with a plurality of mutually non-contacting contact P-type junction regions (11) by ion implantation, and the contact P-type junction region (11) is in ohmic contact with the drain (1).

3. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction according to claim 2, characterized in that: The cross-sectional width of the contact P-type junction region (11) at the middle part of the single MOS cell is larger, and the cross-sectional width of the contact P-type junction region (11) at the two sides is smaller.

4. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction according to claim 2, characterized in that: The inside of the N substrate layer (5) and above the contact P-type junction region (11) is formed with a contact cover layer (12) by ion implantation, the contact cover layer (12) is of N-type material with a doping concentration greater than that of the N substrate layer (5), and the contact cover layer (12) is in ohmic contact with the drain (1).

5. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction according to claim 3, characterized in that: The inside of the N drift layer (6) and below the gate oxide field plate (3) is formed with a plurality of mutually non-contacting P-type field plate knots (13) by ion implantation; And the cross-sectional depth of the P-type field plate knot (13) at the middle part is larger, and the cross-sectional depth of the P-type field plate knot (13) at the two sides is smaller.

6. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction of claim 5, wherein: The contact P-type junction region (11) further includes a gradual junction region (1101), the cross-sectional height of the gradual junction region (1101) at the middle part of the single MOS cell is lower, and the cross-sectional height of the gradual junction region (1101) at the two sides is higher.

7. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction of claim 1, wherein: The inside of the N drift layer (6) is formed with a plurality of mutually non-contacting middle P-type junction regions (14) by ion implantation, and the cross-sectional width of the middle P-type junction region (14) at the middle part is large, and the cross-sectional width of the middle P-type junction region (14) at the two sides is small, and the bottom end of the middle P-type junction region (14) is in direct contact with the N substrate layer (5).

8. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction of claim 7, wherein: The inside of the N drift layer (6) and above the middle P-type junction region (14) is formed with a middle cover layer (15) by ion implantation, the middle cover layer (15) is in direct contact with the N substrate layer (5), and the middle cover layer (15) is of N-type material with a doping concentration greater than that of the N drift layer (6).

9. The SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction of claim 8, wherein: The inside of the N drift layer (6) and above the middle cover layer (15) is formed with a middle N-layer (16) by ion implantation, and the doping concentration of the middle N-layer (16) is lower than that of the N drift layer (6).

10. A process for fabricating a SiC VDMOSFET dynamic performance enhancement structure with multi-level field plate junction, characterized in that, The preparation process of the SiC VDMOSFET dynamic characteristic enhancement structure with multi-level field plate knot applied to the SiC VDMOSFET dynamic characteristic enhancement structure with multi-level field plate knot of claim 1, specifically includes: S1, forming an N drift layer (6) on the N substrate layer (5) by epitaxial growth; S2, sequentially forming a P well layer (9), an N well layer (7) and a P+ layer (8) in the N drift layer (6) by ion implantation, and activating the implanted ions by high temperature annealing; S3, growing a gate oxide layer on the semiconductor epitaxial layer, and forming a gate oxide field plate (3) through a photolithography and etching process; S4, depositing a silicon dioxide layer on the gate oxide field plate (3), and forming a field plate knot (10) through a self-aligned photolithography and etching process, the field plate knot (10) is composed of several mutually non-contacting silicon dioxide deposition blocks, and the silicon dioxide deposition block in the middle covers a large range on the gate oxide field plate (3), and the silicon dioxide deposition blocks on both sides cover a small range on the gate oxide field plate (3); S5, depositing a polysilicon or metal layer on the field plate knot (10), and forming a gate electrode (2) through a photolithography and etching process; S6, forming a contact area of a source electrode (4) in the N well layer (7) and the P+ layer (8) through an ion implantation and annealing process, and forming a contact area of a drain electrode (1) on the back of the N substrate layer (5); S7, depositing a metal layer, forming an ohmic contact of the source electrode (4) and the drain electrode (1) through a photolithography and etching process, and completing the preparation of the device.

Images