Method and apparatus for modulating light

Abstract

A light modulation array is disclosed that includes a plurality of light modulation elements, wherein each light modulation element includes a plurality of electrical interconnects and a heater element coupled to the plurality of electrical interconnects, and the heater element is configured to receive electrical energy via the plurality of electrical interconnects. Each light modulation element of the device further includes a phase change material disposed proximate to the heater element and an insulator encapsulating the heater element and the phase change material, wherein the phase change material is configured to exhibit a change in crystalline state based on a thermal contribution from the heater element.

Description

[0001] Inventors:

[0002] Dmitri Choutov, Silviu Crisan, Luis Diego Hoffman, Theodore Michel Marescaux, Richard Stahl, Bruno Figeys, Roelof Jansen, Kristof Lodewijks, Vladimir Pejovic, Xavier Rottenberg, Sandeep Seema Saseendran, TECHNICAL FIELD

[0003] The present subject disclosure relates to light modulation devices for optical and non-optical applications using spatial modulation. BRIEF DESCRIPTION OF DRAWINGS

[0004] Reference will now be made to the drawings, which are not necessarily drawn to scale, and wherein:

[0005] FIG. 1A A cross-sectional view of an exemplary light modulation unit cell array according to various aspects described herein is provided;

[0006] FIG. 1B An exemplary heater driver matrix of a light modulation unit cell array according to various aspects described herein is provided;

[0007] FIG. 2A A cross-sectional view of another exemplary light modulation unit cell array according to various aspects described herein is provided;

[0008] FIG. 2B A cross-sectional view of an exemplary light modulation unit cell according to various aspects described herein is provided;

[0009] FIGS. 3A-3F A cross-sectional view of exemplary manufacturing steps of a light modulation unit cell according to various aspects described herein is provided;

[0010] FIG. 3G A flowchart of another exemplary method for manufacturing a light modulation unit cell according to various aspects described herein is illustrated;

[0011] FIGS. 3H-3M A cross-sectional view of exemplary manufacturing steps of a light modulation unit cell according to various aspects described herein is provided;

[0012] FIG. 4A A cross-sectional view of an exemplary light modulation unit cell array according to various aspects described herein is provided;

[0013] FIG. 4B A cross-sectional view of another exemplary light modulating cell array according to various aspects described herein is provided;

[0014] FIG. 4C A cross-sectional view of another exemplary light modulating cell array according to various aspects described herein is provided;

[0015] FIG. 4D A cross-sectional view of another exemplary light modulating cell array according to various aspects described herein is provided;

[0016] FIG. 4E A cross-sectional view of another exemplary light modulating cell array according to various aspects described herein is provided;

[0017] FIG. 5A A flowchart of an exemplary method for fabricating a light modulating cell according to various aspects described herein is illustrated;

[0018] FIG. 5B A flowchart of another exemplary method for fabricating a light modulating cell according to various aspects described herein is illustrated;

[0019] FIGS. 6A-6D An exemplary heater element configuration according to various aspects described herein is illustrated;

[0020] FIGS. 7A-7C An exemplary heater element electrode configuration according to various aspects described herein is illustrated;

[0021] FIGS. 8A-8D An exemplary heater element profile according to various aspects described herein is illustrated;

[0022] FIGS. 9A-9C An exemplary heater element and electrode configuration according to various aspects described herein is illustrated; and

[0023] FIG. 10 An exemplary array of heater elements in a light modulating cell array according to various aspects described herein is illustrated. DETAILED DESCRIPTION

[0024] One or more examples will now be described with reference to the attached drawings, where like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more examples. It can be evident, however, that various examples can be practiced without

[0025] FIG. 1AA cross-sectional view of an exemplary light modulating cell array 100 is provided. In various examples, light modulation can be described as a process that controls one or more properties of light, such as intensity, phase, polarization, or frequency. In one example, the light modulation process can be a static process. In another example, the light modulation process can be a dynamic process. In further examples of implementation and operation, light modulation can include spatial light modulation, which can be described as a process that changes the spatial distribution of the amplitude, phase, and / or polarization of a light field. In another example, spatial light modulation can be described as a process that changes the spatial distribution of the amplitude, phase, and / or polarization of an electromagnetic field. In one example, a spatial light modulator can be a two-dimensional array of pixels that can be used to dynamically modulate light in space and time. In various examples, spatial light modulation can be achieved by altering the phase, amplitude, polarization, or any combination thereof of light. In one specific example, an adjustable array of pixels can be used to diffract an incident light beam, thereby enabling two-dimensional (2D) and three-dimensional (3D) light field temporal projection to an observer. In a related example, the incident light beam spectrum can be chosen such that the projected rendering is substantially within the visible spectrum (wavelength range of 400 nm - 700 nm) for human observation.

[0026] In one example, the cells 112 are formed in a stack on the substrate 102, collectively forming the cell array 100. As used herein, the term "cell" can interchangeably refer to a light modulating element, a light modulating element, an independently addressable light modulating element, and / or a pixel in an array of pixels. Thus, a cell array can refer to an array of light modulating elements, a light modulating array, or an array of pixels. In one example of implementation, the substrate 102 can be an integrated circuit fabricated through front-end-of-line (FEOL) steps required to form isolated CMOS elements, interconnects, logic structures, and control structures. In a more specific example, the substrate 102 is fabricated to provide elements configured for electrical connections, such as the contact pads 106 for connection to the cells 112. In an alternative example, the contact pads 106 can be formed on the substrate 102 as one or more process steps used in the formation of the cells 112. In one example, the contact pads 106 are adapted to electrically couple the substrate 102 to each of the cells 112 including the cell 112. In yet another example, the substrate 102 can include CMOS back-end-of-line (BEOL) elements configured to provide electrical interconnects to the CMOS elements and electrical connections to the cells 112.

[0027] In one example of implementation and operation, electrical interconnects 104 are formed on the substrate 102 to provide electrical connections between various elements of the substrate 102 and elements of the unit cell 112. In a more particular example, the interconnects 104 are formed from one or more electrically conductive materials separated by one or more insulating materials (dielectrics) including at least a portion of the dielectric 116-1 to provide thermal separation and / or electrical isolation between individual elements of the unit cell 112 and electrical isolation between the electrical interconnects 104. In various examples, each of the interconnects 104 is adapted to provide electrical connections between a contact pad of the contact pads 106 at a first end and another element of the unit cell 112 at a second end. In one example, the dielectric 116-1 is configured to provide electrical isolation between some or all of the interconnects 104. Exemplary insulating and / or dielectric materials can include, but are not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), and low-K dielectrics including various organic and inorganic low-K materials such as fluorinated silicon dioxide (SiOF), organosilicate glass (OSG), and porous low-K dielectrics. Other potential dielectric materials include high-K dielectric materials which can be characterized as providing a reduced physical thickness of a given dielectric layer, with examples including hafnium oxide (HfO2), zirconium oxide (ZrO2), and aluminum oxide (Al2O3). Other example dielectrics include organic polymers such as polyimides, borophosphosilicate glass (BPSG), and spin-on-glass (SOG).

[0028] In one example, the dielectric 116-1 can be deposited, patterned, and etched using various photolithographic methods to provide voids for formation of the interconnects 104 in the voids. In one example, the dielectric 116-1 can be provided with voids for formation of the interconnects 104 by depositing a conductive material over the dielectric 116-1 such that the conductive material forms a plurality of conductive structures between the substrate 102 and other elements of the unit cell 112. Exemplary conductive materials include one or more of aluminum, copper alloys, or any other reasonably efficient electrical conductor, but need not include metallic materials. In a related example, the conductive material can be at least partially removed (e.g., using a planarization process and / or a patterning and etching process) to form the interconnects 104 to enable coupling to the other elements of the unit cell 112. In one example of implementation and operation, the interconnects 104 can be formed in multiple steps, with each of the interconnects 104 including additional elements such as the elements shown in reference to FIG. 2B More detailed elements are shown. In various examples, the additional elements can be formed using multiple photolithographic operations to provide wiring and connectivity between the contact pads 106 and various elements of the unit cell 112.

[0029] In one example of a particular implementation, the substrate 102 can be configured to include processing circuitry for controlling the flow of electrical potential and current through each of the interconnects 104, such that the arrangement of one or more of the interconnects comprising the interconnects 104 can be independently controlled. In one example of a particular implementation and operation, a heater material can be formed over a surface adapted to provide connectivity to at least some of the interconnects 104. In this example, the heater material can be deposited over the surface of the interconnects 104, one or more etching or planarization processes can be used to expose the surface, thereby enabling coupling of the interconnects 104 to the heater material. In one related example, the heater material can be patterned to isolate the heater material in each unit cell from adjacent unit cells, so as to create heater elements 108, where each of the heater elements 108 is associated with a unit cell of the unit cell array 100. In one example of operation, the unit cell array 100 can be adapted to provide substantially independent application of electrical current to each of the heater elements 108. In one example of operation, the heater elements 108 are configured to receive electrical energy via the plurality of interconnects 104, thereby inducing Joule heating in the heater material. Exemplary heater materials include tantalum nitride (TaN), a conductive metal oxide material such as indium tin oxide (ITO), or any other material having a suitable resistivity. In one example, the stoichiometry of the TaN (ratio of tantalum atoms to nitrogen atoms) can be adjusted to achieve the electrical resistance required for the heater, while optimizing the current and voltage applied to the heater element. In one particular related example, an additional factor defining the heater resistance can be the TaN thin film thickness. In one example, by varying the TaN stoichiometry and thin film thickness, the resistance of the heater element can be adjusted in the range of 1 Ohm - 1000 Ohms.

[0030] In one example of a particular implementation and operation, various materials such as those described with reference to FIG. 1A and other figures described herein can be formed over the heater material used to form the heater elements 108 in the complete unit cell stack of the unit cell 112. In one example, each unit cell stack includes a phase change material 114 over the heater material comprising the heater elements 108. In various examples, the phase change material 114 can be a material having reversible crystalline phase properties.

[0031] In FIGS. 1A-4EIn one example, the phase change material (such as phase change material 114) can be adapted to thermally interconvert between one or more crystalline states and one or more amorphous states on a relatively short timescale using, for example, a temperature pulse from a heat source. In one example, when changing phase change material 114 between a relatively resistive amorphous state and a conductive crystalline state, the refractive index of phase change material 114 changes such that the amplitude and / or phase of reflected light can be changed. In one example, once the pulse of temperature is terminated, the state of phase change material 114 is "locked" and remains unchanged in the absence of a thermal interconversion event. In various examples, phase change material 114 can be deposited as a thin film on top of a dielectric material configured by dielectric 116-2. Deposition techniques to deposit phase change material 114 can include, for example, physical vapor deposition (PVD), in which the phase change material is evaporated from a solid source and then condensed onto a substrate. In another example, chemical vapor deposition (CVD) can be used to deposit phase change material 114, in which a chemical reaction of gaseous precursors is used to form a thin film phase change material on the surface of dielectric 116-2. Exemplary phase change materials include, but are not limited to, Ge x Sb y Te z (Germanium Antimony Tellurium), Sb x S y (Antimony Sulfide), Sb x Se y (Antimony Selenide), and Mo x O y (Molybdenum Oxide).

[0032] In one related example, dielectric 116-2 can include one or more materials for providing mechanical, electrical, or chemical protection to phase change material 114. In one example of implementation and operation, dielectric 116-2 is configured as a diffusion barrier material for phase change material 114. In one example of implementation, passivation 110 is adapted to provide mechanical and / or electrical protection to cell 112. In one additional example, passivation 110 can include one or more materials having relatively high thermal insulating properties, including but not limited to SiO2or TiO2.

[0033] In one example of implementation and operation, the phase change material of the unit cells, such as phase change material 114, can be adapted to change between two states. In one example, the two states can be fully crystalline in a first state and fully amorphous in a second state. In an alternative example, the phase change material of the unit cells can be adapted to change between more than two states: a generally crystalline state, a generally amorphous state, and some state between crystalline and amorphous in one or more additional states. In one illustrative example, a state defined between the fully crystalline state and the fully amorphous state can indicate the formation and growth / expansion of one or more crystalline nucleation sites within the amorphous state. In another illustrative example, the fully crystalline state indicates that one or more crystalline nucleation sites have expanded sufficiently such that the amorphous state no longer exists. In one specific example, the various states between the fully crystalline state and the fully amorphous state can be implemented in practice by intentionally stopping the growth of one or more crystalline nucleation sites at each of a plurality of growth stages.

[0034] FIG. 1B An exemplary heater driver matrix 10 for an array of light modulating unit cells is provided. In one example of implementation and operation, a matrix G of size M x N includes row drivers and column drivers coupled to resistive switching devices, each resistive switching device including a resistive heating element 12 and a selector element 14. In various examples, the heating element 12 can be a heater element 108 in FIG. 1A , a heater element 128 in FIG. 2A , a heater element 152 in FIG. 2B , and so on. With reference to the various figures contained herein, each resistive heating element 12 can be a heater material patterned into a heater element, where the heater element is associated with a unit cell in an array of light modulating unit cells. In one example of operation, the combination of the resistive heating element 12 and the selector element 14 can be used to provide generally independent application of electrical energy to the heater element, enabling independent control of thermal energy provided to each unit cell in the array of unit cells. In one specific example, the selector element 14 can be implemented as a PNP bipolar junction transistor (BJT) such that driving a voltage on the word line n-1 (WL n-1 ) and the bit line n-1 (BL n-1The voltage on the selector element 14 biases the selector element 14, allowing current to flow through the resistive heating element 12. In an alternative embodiment, the selector element 14 may be implemented as an NPN bipolar junction transistor, but with the opposite polarity to a PNP bipolar junction transistor. Alternative embodiments of the selector element 14 include, but are not limited to, any of a field-effect transistor, a Darlington transistor pair, an insulated-gate bipolar transistor, a silicon controlled rectifier, and a bidirectional threshold switch (OTS) selector device. In one embodiment, when the selector element 14 is implemented as a PNP bipolar junction transistor, the selector element 14 can be adapted to switch to the on state when a negative voltage (relative to the emitter) is applied to the base of the BJT. In one embodiment, when the selector element 14 is in the on state, sufficient current can controllably flow through the resistive heating element 12 to influence the phase transition of the phase change material associated with the resistive heating element 12 and the selector element 14. FIG. 1B In the examples, M=3 and N=3, such that the matrix size is 3x3. In various examples, the optical modulation unit cell array can include a large heater driver matrix, thereby enabling large displays and projection devices. FIGS. 1A-4E In related examples, by controlling the current flowing through the resistance heating element 12 or an equivalent element, the associated phase change material can be controllably transformed between a conductive crystalline phase and a resistive amorphous phase over a relatively short timescale.

[0035] FIG. 2A Another exemplary cross-sectional view of an optical modulation cell array is provided. In this example, each cell of the cell array 120 is formed in a stacked manner on a substrate 122, together forming cell 134. In one example, substrate 122 may be a CMOS front-end process of an integrated circuit fabricated to include elements configured for electrical connection, such as contact pads 126 for connecting to heater elements 128 of cell 134. In an alternative example, contact pads 126 may be formed on substrate 122 as one or more process steps used in the formation of cell 134.

[0036] In one embodiment and operation, electrical interconnects 124 are formed on substrate 122 to provide electrical connections between individual elements of substrate 122 and elements of unit cell 134. In a more specific embodiment, interconnects 124 are formed of one or more conductive materials separated by dielectric 146-1 to provide thermal separation and / or electrical isolation between individual elements of unit cell 134 and electrical isolation between electrical interconnects 124. In various embodiments, each interconnect in interconnects 124 is adapted to provide an electrical connection at a first end between a contact pad in contact pad 126 and another element of unit cell 134 at a second end.

[0037] In one example, the dielectric 146-1 can be deposited, patterned, and etched using various photolithographic methods to provide voids for forming interconnects 124 in the voids. In one example, the interconnects 124 can be formed by depositing a conductive material on the dielectric 146-1 that has been configured with voids, such that the conductive material forms a plurality of electrical interconnects between the substrate 122 and other elements of the cell 134. In a related example, the conductive material can be at least partially removed (e.g., using a planarization process and / or an etching process) to accommodate the formation of the interconnects 124 for coupling to the other elements of the cell 134.

[0038] In one example of implementation and operation, the interconnects 124 can be formed in a plurality of steps, where each of the interconnects 124 includes additional elements. Referring to FIG. 1, the interconnects 124 can be formed in a plurality of steps, where each of the interconnects 124 includes additional elements. In one example, the interconnects 124 can be formed by depositing a conductive material on the dielectric 146-1 that has been configured with voids, such that the conductive material forms a plurality of electrical interconnects between the substrate 122 and other elements of the cell 134. In a related example, the conductive material can be at least partially removed (e.g., using a planarization process and / or an etching process) to accommodate the formation of the interconnects 124 for coupling to the other elements of the cell 134. FIG. 2B The additional elements can be formed using additional photolithographic operations to provide wiring and connectivity between the contact pads 126 and the various elements of the cell 134.

[0039] In one example of implementation and operation, a heater material can be formed over a surface adapted to provide connectivity to at least some of the interconnects in the interconnects 124. In this example, the heater material is patterned into individual heater elements 128, where each of the heater elements 128 is associated with a cell in the cell array 134. In one example of operation, the cell array 120 can be adapted to provide substantially independent electrical power to each of the heater elements 128, enabling independent control of thermal energy provided to each of the cells 134.

[0040] In one example of implementation and operation, a mirror surface 130 can be formed between the heater elements 128 and the phase change material 136 of each of the cells 134. In one example, the mirror surface 130 can be adapted to act as a reflective element to improve the optical performance of the cell array 120.

[0041] In another example of implementation, an isolation structure can be formed between adjacent cells 134 to provide isolation between adjacent cells. In a related example, the isolation structure can be configured as a trench between individual cells 134. In various examples, thermal interconversion between the crystalline phase and the amorphous phase of the phase change material 136 can induce thermal "cross-talk" between individual cells that are being interconverted and adjacent cells that are not intended to be interconverted. In another example, isolation between each of the adjacent cells 134 can enable lower power consumption when the cells are selected for interconversion.

[0042] In one specific example of implementation and operation, the dielectric 146-2 can include Si3N4or other material having a relatively high thermal conductivity, where thermal conductivity can be described as the rate of heat transfer through a material per unit area and per unit temperature gradient. In one example, Si3N4may exhibit a higher thermal conductivity relative to the above-mentioned dielectric materials, such as SiO2and TiO2. In one example, the dielectric 146-2 can be adapted to encapsulate a heater element of the heater elements 128 along with the associated phase change material 136, such that heat generated by the heater element is conducted to the associated phase change material 136 in a relatively efficient manner. In one supplemental example (described in additional detail in the text accompanying FIGS. 3H-3M the drawings), the dielectric 146-1 can include SiO2, where SiO2having a relatively low thermal conductivity can help maintain heat generated by the heater elements 128 within the encapsulation provided by the dielectric 146-2.

[0043] In one related example of implementation and operation, the dielectric 146-2 can be configured in one or more fabrication steps to encapsulate selected elements of each light modulating element, such as a heater element of the heater elements 128, the associated mirror 130, and the associated phase change material 136, to effect confinement of thermal energy and to confine the phase change material 114 as it is in various molten and / or semi-molten states. Such molten and / or semi-molten states can occur during a transition of a crystalline state of the phase change material between an amorphous state and a crystalline state. In further examples, one or more passivation materials, such as the passivation layer 132, can be adapted as a top layer of each of the unit cells 112.

[0044] In one specific example of implementation and operation, the array of light modulating cells can include a plurality of light modulating cells, where a plurality of isolation structures, such as isolation trenches 138, are configured to provide substantial thermal and / or electrical isolation between each cell in the array of cells 134 and every other cell in the array of cells. In an alternative example, the isolation structures are configured to provide one or more of thermal, electrical, and / or optical isolation between each cell in the array of cells 134 and every other cell in the array of cells. In one specific example, the isolation trenches 138 include air gaps (sometimes referred to as gas-filled isolation trenches). In another example, the isolation trenches 138 are configured as vacuum isolation trenches by providing vacuum isolation. In an alternative example, the isolation trenches 138 include voids that are adapted to be backfilled with an insulating material, such as dielectric 146-2, to form filled isolation trenches. In a related example, the trench insulating material is deposited into the trenches. In an alternative example, the trench insulating material is a spin-on material applied on a wafer provided with the cells 134.

[0045] In one example, the heater elements (such as the heater elements 108 in FIG. 1A , the heater elements 128 in FIG. 2A , etc.) can interact with incident light that is illuminated onto the surface of the cells 134 (such as the cells 112 in FIG. 1A , the cells 134 in FIG. 2A , etc.). In one example, the incident light can refer to one or more light sources located outside of the array of cells and / or one or more light sources integrated with the array of cells. In one example, the incident light can bypass and / or pass through the heater elements (such as the heater elements 128 in FIG. 2A , causing functional errors in CMOS elements in the integrated circuit including the substrate 122 during operation. In a related example of implementation, a metal or other opaque material can be used to block light that would otherwise leak through the heater elements (such as the heater elements 128 in FIG. 2A . In one specific example, the metal or other opaque material can be part of the manufacturing process. In one example, a light-blocking metal layer can be patterned into sub-wavelength (less than ½ wavelength) features and configured to act as a metasurface to block specific wavelengths of light that are detrimental to the proper functioning of elements formed in the CMOS front-end-of-line (FEOL). In a related example, one or more light-blocking metal layers can be adapted to block RGB wavelengths by combining features with shapes and sizes tuned for RGB wavelengths. Alternatively, different metasurface layers can be used for each of the respective red, green, blue (RGB) wavelengths. In one example, the light-blocking structures are adapted as part of the CMOS back-end-of-line.

[0046] FIG. 2B A cross-sectional view of an exemplary light modulation cell 140 is provided. In one example, various CMOS processes can be used to form components of a CMOS front-end-of-line (FEOL), such as a CMOS front-end substrate 142. After formation of the FEOL, various exemplary CMOS back-end-of-line (BEOL) structures can be formed on the CMOS FEOL to electrically couple components of the CMOS FEOL to one or more cells in an array, such as the cell 140 in FIG. 2B In various examples related to embodiments disclosed herein, multi-layer CMOS BEOL interconnect structures can be used to couple CMOS front-end substrate 142 elements to heater elements, such as the heater element 152.

[0047] In one example of a particular implementation, CMOS BEOL formation can include various process steps, including deposition of dielectric layers, deposition of metal layers, patterning using photolithography and etching processes, deposition of dielectric layers, formation of vias, and formation of interconnects. In one example, the CMOS BEOL can include multiple interconnect layers. For example, in the example of FIG. 2B In one example of a particular implementation, CMOS BEOL formation can include various process steps, including deposition of dielectric layers, deposition of metal layers, patterning using photolithography and etching processes, deposition of dielectric layers, formation of vias, and formation of interconnects. In one example, the CMOS BEOL can include multiple interconnect layers. For example, in the example of

[0048] In one example, the CMOS back-end-of-line 170 is configured to electrically couple the CMOS front-end substrate 142 to the heater element 152. The heater element 152 can be electrically isolated from the phase change material 156 using a dielectric 162-3, where the heater element 152 and the phase change material 156 together form a phase change modulator 180 of the cell 140. In this example, as discussed with reference to FIG. 2A In one example, a light-reflecting layer (such as a metal layer) can be configured between the heater element 152 and the phase change material 156 and adapted to act as a mirror 154 to improve optical performance of the cell in the cell 134. In FIG. 2BIn the example shown, the dielectric 162-3 provides electrical isolation between the mirror facets 154 and the phase change material 156. In an alternative example, the mirror facets 154 and the phase change material 156 can be configured to be in direct contact with each other.

[0049] In one specific example of implementation and operation, the dielectric 162-3 can include Si3N4or other material having a relatively high thermal conductivity, where thermal conductivity can be described as the rate of heat transfer through a material per unit area and per unit temperature gradient. In one example, Si3N4may exhibit a higher thermal conductivity relative to a dielectric material having a lower thermal conductivity, such as SiO2. In one example, the dielectric 162-3 can be adapted to encapsulate the heater material defined as the heater element 152 and the phase change material 156, such that heat generated by the heater element 152 is conducted to the phase change material 156 in a relatively efficient manner. In one supplemental example, the dielectrics 162-1 and 162-2 can include SiO2, where SiO2having a relatively lower thermal conductivity can help maintain heat generated by the heater element 152 within the encapsulation provided by the dielectric 162-3.

[0050] In one related example of implementation and operation, the dielectric 162-3 can be configured in one or more fabrication steps to encapsulate selected elements of each light modulating element, such as the heater element 152, the associated mirror facet 154, and the associated phase change material 156, to enable each unit cell to help limit thermal energy and confine it to the phase change material 156 when in various molten and / or semi-molten states.

[0051] FIGS. 3A-3F A cross-sectional view of an example fabrication step of an array of light modulating unit cells is provided. FIG. 3A Formation of a bottom electrode via layer (BEVA) 180 is shown, where connection vias have been formed in a dielectric and planarized, while deposition of a heater material is shown to provide a heating layer 182. FIG. 3B A final structure is shown after the heating layer 182 from FIG. 3A has been patterned, etched, backfilled with a dielectric 184-1, and planarized to provide a heater element 186. The structure includes deposition of a dielectric 184-2 over the patterned heater element 186, followed by deposition of a mirror layer 188, and then deposition of a second dielectric 184-2 over the mirror layer 188. FIG. 3C Addition of a phase change material layer 192 over the second layer of dielectric 184-2 is shown, followed by deposition of a dielectric 184-3 over the phase change layer 192. In FIG. 3DIn some embodiments, isolation trenches 194 are formed to provide electrical and / or thermal isolation of the unit cells from adjacent unit cells. Isolation trenches 194 can be formed using, for example, various etching processes, including but not limited to wet etching processes, reactive ion etching (RIE) processes, and deep reactive ion etching (DRIE) processes. FIG. 3E Application of dielectric 184-4 over the completed unit cell is shown, while FIG. 3F The final finished unit cell is shown after one or more planarization steps to provide planarized surface 190. In various embodiments, additional steps can be added to provide bond pads and the like for coupling the array of light modulating unit cells in a display and / or projection device.

[0052] FIG. 3G A flowchart of an exemplary method for fabricating a light modulating unit cell is shown. Note that, FIG. 3GThe flowchart of FIG. 1, along with the other flowcharts included herein, is not intended to encompass every and each process and / or manufacturing step required to provide a complete light modulating unit cell. Rather, some steps that would be apparent to one of skill in the art have been omitted, thus providing a more succinct disclosure of the various included embodiments. The method begins at step 200, where a dielectric is formed on an integrated circuit that has been fabricated through CMOS front end of line (FEOL) manufacturing. At step 202, the method continues by forming interconnects for electrical connection to contact pads provided in the CMOS FEOL. The method continues at step 203, where another dielectric layer is formed over the interconnects formed at step 202, and then at step 204, interconnects are formed in the dielectric layer formed at step 203. In one example, steps 203 and 204 can be repeated for multiple layers of interconnects as needed. At step 206, the method proceeds to form a layer of heater material 206. In one example, the heater material can be deposited to provide electrical coupling to the interconnects formed at step 204. At step 208, the heater material is patterned and etched to isolate the heater material in each unit cell from adjacent unit cells. The method continues at step 210, where a dielectric is deposited over the patterned heater material. In optional step 212, a mirror layer is deposited over the dielectric deposited at step 210. In one example, the mirror can be a deposited layer adapted to function as a mirror to improve the optical performance of the light modulating unit cell. When the optional mirror is formed at step 212, the method continues at step 214 by forming additional dielectric over the mirror formed at step 212. In one example, when optional step 212 is not completed, the method can be executed without adding a layer of dielectric at step 214. Then, the method continues at step 216 by forming a layer of phase change material over the dielectric layer formed at step 210, or in the case of the optional mirror layer, over the dielectric layer formed at step 214. Finally, the method continues by forming a dielectric over the phase change material layer formed at step 218.

[0053] FIGS. 3H-3M A cross-sectional view of another example of a manufacturing step of a light modulating unit cell array is provided. FIG. 3H Formation of a bottom electrode via layer (BEVA) 180 is shown, where connection vias have been formed in low thermal conductivity dielectric 184-2 and high thermal conductivity dielectric 184-5 and planarized, along with deposition of a heater material to provide heater layer 182. In various examples, high thermal conductivity dielectric 184-5 is used to facilitate efficient propagation of heat generated at heating elements 186 within the unit cells of the light modulating unit cell array. FIG. 3I Formation of a bottom electrode via layer (BEVA) 180 is shown, where connection vias have been formed in low thermal conductivity dielectric 184-2 and high thermal conductivity dielectric 184-5 and planarized, along with deposition of a heater material to provide heater layer 182. In various examples, high thermal conductivity dielectric 184-5 is used to facilitate efficient propagation of heat generated at heating elements 186 within the unit cells of the light modulating unit cell array. FIG. 3HThe heater layer 182 has been patterned, etched, backfilled with dielectric 184-5 and planarized to provide the heater element 186, followed by deposition of the mirror layer 188, and then the final structure of dielectric 184-5 over the mirror layer 188. FIG. 3J A combination of fabrication steps is demonstrated, including the addition of a layer of phase change material 192 over the high thermal conductivity dielectric 184-5, followed by deposition of dielectric 184-5 over the phase change material 192. In this example, the dielectric 184-2 is formed of a low thermal conductivity dielectric material, enabling the dielectric 184-2 to facilitate confinement of heat within each of the array of light modulating cells.

[0054] FIG. 3K Formation of an isolation trench 194 is demonstrated, where the interior walls of the isolation trench are implemented with a low thermal conductivity material, such as the dielectric 184-2. The isolation trench provides electrical and / or thermal isolation of a cell from an adjacent cell. In this example, a first trench is formed between cells to extend through the dielectric 184-5, phase change material 192, dielectric 184-5, mirror layer 188, dielectric 184-5 and into the dielectric 184-2. The first trench is then backfilled with the dielectric 184-2, followed by formation of the isolation trench 194. In an alternative example of implementation and operation, a low thermal conductivity material can be deposited on the interior sidewalls of the isolation trench to form the isolation trench 194. In this example, the dielectric 184-2 provides a general confinement of the heater element 186 and the phase change material layer 192 within the high thermal conductivity dielectric package, enabling the dielectric 184-2 to facilitate confinement of heat within each of the array of light modulating cells, while allowing efficient transfer of heat from the heater element 186 to the phase change material layer 192. The isolation trench, including backfilling of the isolation trench 194, can be formed using, for example, various etching processes, including but not limited to wet etching processes, reactive ion etching (RIE) processes, ion drilling and deep reactive ion etching (DRIE) processes. FIG. 3F A final finished cell is demonstrated after one or more planarization steps to provide a planarized surface 190. In various examples, additional steps can be added to provide bond pads, etc., for coupling the array of light modulating cells in a device, such as a display and / or projection device.

[0055] In the example demonstrated in FIGS. 1A-3K The order of layers in the formation of the stack of a cell in the example demonstrated in FIG. 2A and 2B In the example demonstrated in, the mirror can be disposed between the heater element and the phase change material in the stack of a cell, where the thermal path between the heater element and the phase change material passes through the mirror. In one example of implementation,FIG. 2A and 2B The mirror surface in the configuration of

[0056] FIG. 4A A cross-sectional view of another example light modulating cell array 300 is provided. In this example, the mirror surface 310 is disposed below the heater element 308, rather than above the heater element 308. In one example, each cell of the cell array 300 is formed in a stack on the substrate 302, together forming a cell 314. In one example, the substrate 302 can include a CMOS front-end process of an integrated circuit fabricated to include elements configured for electrical connections, such as the contact pads 306 for connecting to the heater element 308 of the cell 314. In one example, the substrate 302 is fabricated to provide elements configured for electrical connections, such as the contact pads 306 for connecting to the heater element 308 of the cell 314. In an alternative example, the contact pads 306 can be formed on the substrate 302 as one or more process steps used in the formation of the cell 314.

[0057] In one example of a specific implementation and operation, the electrical interconnects 304 are formed on the substrate 302 to provide electrical connections between various elements of the substrate 302 and elements of the cell 314. In a more specific example, the interconnects 304 are formed from one or more conductive materials separated by one or more insulating materials, including at least a portion of the dielectric 320-1 configured to provide thermal separation and / or electrical isolation between individual elements of the cell 314, and electrical isolation between the electrical interconnects 304. In various examples, each of the interconnects 304 can be adapted to provide an electrical connection between a contact pad 306 at a first end and another element of a cell 314 at a second end.

[0058] In one example, the dielectric 320-1 can be deposited, patterned, and etched using various photolithographic methods to provide spaces for forming the interconnects 304 and / or the mirror surface 310. In an alternative example, a dielectric material, such as the dielectric 320-1, can provide a planarized surface on which a reflective layer can be deposited, followed by a patterning and etching process to form individual mirror surfaces, such as the mirror surface 310. In FIG. 4AIn one example, vias are etched in the mirror 310 to form insulating interconnects 304 to couple to the heater element 308. In one example, a dielectric 320-1 can be added over the mirror 310. In one example, the interconnects 304 can be formed by depositing a conductive material over the dielectric 320-1, where the dielectric 320-1 has been configured with voids such that the conductive material forms a plurality of electrical interconnects between the substrate 302 and other elements of the cell 314.

[0059] In one example of a particular implementation, the mirror 310 can be adapted to act as a reflective element to improve the optical performance of the cell array 300. In another example, the mirror 310 can be adapted to substantially block incident light from passing through the substrate 302 to mitigate the effects of light passing through the cell 314 on CMOS elements in an integrated circuit including the substrate 302, thereby avoiding undesirable errors from these CMOS elements during operation. In one related example of a particular implementation, the mirror 310 can be composed of a metal or other opaque material adapted to block light that would otherwise pass through the cell array 300. In one particular example, the metal or other opaque material can be part of a fabrication process in which the material is specially patterned to block light from reaching the CMOS surface. In one example, the mirror 310 can include one or more reflective light blocking layers that can be patterned with sub-wavelength (less than 1 / 2 wavelength) features and configured as a metasurface to block light of specific wavelengths that are detrimental to the proper functioning of elements formed in the CMOS front end (FEOL). In one related example, the one or more reflective layers of the mirror 310 can be adapted to block RGB wavelengths by combining features that are shaped and sized for the RGB wavelengths. Alternatively, different mirror 310 components can be used for the respective red, green, and blue (RGB) wavelengths.

[0060] In one example of implementation and operation, a dielectric 320-2 is deposited over the interconnect 304 and over the mirror 310, then the interconnect 304 is formed through the dielectric 320-2, and a heater material is applied, from which a heater element 308 can be formed. In one specific example, the heater material can be a metal or a semi-metal. In one specific example, the heater can be configured thin enough to be transparent or semi-transparent to certain wavelengths of light, enabling incident light of those certain wavelengths to pass through the heater element 308 and reach the underlying mirror 310. The mirror 310 can reflect the incident light and increase the diffraction efficiency (i.e., the ratio of diffracted optical power to incident optical power), thereby increasing the diffraction efficiency of the cell. Exemplary heater materials include, but are not limited to, tantalum nitride (TaN) with a thickness of 20 nm and below. In another example, a metal oxide heater material can be used, in which the metal oxide is adapted to be transparent or weakly absorbing to certain wavelengths of light. Exemplary metal oxide heater materials include indium tin oxide (ITO). In one example, ITO and other metal oxides can be relatively transparent or weakly absorbing at certain wavelengths.

[0061] FIG. 4B A cross-sectional view of another exemplary light modulating cell array 300 is provided. In one example of implementation and operation, a dielectric 320-2 is deposited over the interconnect 304 and over the mirror 310, then a heater material is applied, from which a heater element 330 can be formed. In one specific example, the heater material can be a metal or a semi-metal. In one specific example, the heater can be configured thin enough to be transparent or semi-transparent to certain wavelengths of light, enabling incident light of those certain wavelengths to pass through the heater element 330 and reach the underlying mirror 310. The mirror 310 can reflect the incident light and increase the diffraction efficiency (i.e., the ratio of diffracted optical power to incident optical power), thereby increasing the diffraction efficiency of the cell. Exemplary heater materials include, but are not limited to, tantalum nitride (TaN) with a thickness of 20 nm and below. In another example, a metal oxide heater material can be used, in which the metal oxide is adapted to be transparent or weakly absorbing to certain wavelengths of light. Exemplary metal oxide heater materials include indium tin oxide (ITO). In one example, ITO and other metal oxides can be relatively transparent or weakly absorbing at certain wavelengths. FIG. 4B In one example, a void is formed in each of the heater elements 330, enabling light to reach and reflect off the underlying mirror 310. In one example, the modified heater element 330 includes a heater material 510, in which the heater material 510 can be any of the heater materials described above, and a heater void 514 is formed in the modified heater element 330. Incident light can pass through the heater void 514 to the mirror 310, from which reflected light reflects back toward the top of the cell array 314.

[0062] In one example of implementation and operation, the diffraction efficiency of the light modulating cell 314 can be improved by using a metal oxide conductive material instead of a traditional conductive material, such as copper (Cu) and copper tungsten (CuW). Metal oxide conductive materials include, but are not limited to, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). In certain examples, the metal oxide conductive material can be used in the formation of (semi-)transparent vias to mitigate optical loss and phase mismatch with the mirror 310. In one illustrative example, a metal via can have a highly reflective top surface, which can cause a phase mismatch due to the difference in the location of the top surface of the metal via compared to the location of the mirror 310.

[0063] FIG. 4C A cross-sectional view of another example light modulating cell array is provided. In one example, an alternative mirror configuration, such as a distributed Bragg reflector (DBR), is used to replace the mirror 310 in FIG. 4A and 4B In various examples, the DBR can be used to reflect light of specific wavelengths and transmit light of other wavelengths. The DBR structure can be configured with alternating layers of materials having different refractive indices to achieve the reflective properties desired for the light modulating cell array 340. In one example, the mirror is formed by fabricating a stack of layers with alternating high refractive index (such as high n 342-2) and low refractive index (such as low n 342-3). In one example, the stack of alternating layers can be fabricated with through-holes formed directly through the dielectric stack. In various examples, the alternating layers can include two different materials having different refractive indices, where the contrast in refractive index between adjacent layers is important to the reflective properties of the DBR. In some examples, the alternating layers can be composed of semiconductor and / or dielectric materials. In an alternative example, the mirror includes one or more materials that provide a continuous variation in refractive index between the bottom surface and the top surface of the mirror. In one example, the one or more materials included in the mirror can be doped such that a continuous variation in refractive index between the bottom surface and the top surface of the mirror is achieved. This is in contrast to a configuration where the mirror includes alternating layers of high n and low n materials, as the latter results in a step function in refractive index transitioning from high n to low n and from low n to high n. In one example of implementation, a reflective layer serving as the mirror has a respective top surface and a respective bottom surface, where the reflective layer is adapted to have a continuously variable refractive index between the top surface and the bottom surface.

[0064] In one example, the passivation layer 312 in FIGS. 4A-4C may include a material having a relatively higher refractive index than the relatively lower refractive index of a typical passivation or capping layer. Thus, a capping layer including SiN x layers (plasma-enhanced chemical vapor deposition based on SiH4 and NH3) or titanium oxide (TiO2) layers, rather than SiO2 or equivalent materials, can be deposited on the dielectric 320-2 to increase the relative reflectivity at the capping layer and air interface. In one example, the capping layer composed of SiN x or TiO2 (or equivalent materials) has a relatively higher contrast between the capping layer and the air interface than a low refractive index material used as a capping layer, which can provide a higher relative reflectivity. In one example of operation, a capping layer configured with SiN x or TiO2 (or equivalent materials) can provide a stronger optical cavity relative to SiO2.

[0065] FIG. 4D A cross-sectional view of another example light modulating cell array is provided. In one example of implementation and operation, a distributed Bragg reflector (DBR) such as the DBR described with reference to FIG. 4C The DBR can be provided as a passivation or capping layer. In one alternative example, a passivation or capping layer such as the passivation or capping layer described with reference to FIG. 1A , 2A 2B and 4A-4E can be implemented with one or more materials that provide a continuous variation in refractive index between a bottom surface and a top surface of the passivation or capping layer. In one example, one or more materials comprising the passivation layer can be doped to provide a continuous variation in refractive index between a bottom surface and a top surface of the passivation layer, rather than alternating layers of high n and low n materials, thereby avoiding a step function in refractive index when transitioning from high n to low n and from low n to high n. In one example of implementation, the passivation layer has a respective top surface and a respective bottom surface, wherein the passivation layer is adapted to have a continuously variable refractive index between the top surface and the bottom surface.

[0066] FIG. 4E A cross-sectional view of another example light modulating cell array is provided. In one example of implementation and operation, a distributed Bragg reflector (DBR) such as the DBR described with reference to FIG. 4C The DBR can be provided as a passivation or capping layer. It is noted that a stack of alternating layers of high n and low n dielectric materials can also be implemented as FIG. 1A , 2A and / or the passivation or capping layer of the examples referenced in 2B, wherein a mirror surface is provided between the heater element and the phase change material.

[0067] In the example of FIGS. 4A-4E the stack forming each cell has a layer sequence with the heater element located between the mirror surface and the phase change material. In other words, the mirror surface is located outside the thermal path between the heater element and the phase change material. In one example of implementation, the mirror surface can be located 100 nm to 200 nm or further away from the heating element. In one example of implementation, a mirror surface material with a relatively low melting temperature can be used, which is lower than the temperature at which the crystal structure of the phase change material can be changed. In one specific example of implementation, the mirror surface can comprise a metal or a similar material with a low melting point, such as aluminum (Al). In one example of implementation, the location of the mirror surface can be configured to produce a maximum standing wave electric field at the location of the phase change material, thereby optimizing the optical cavity and achieving maximum tunability. In one additional example of implementation, FIGS. 4A-4EThe mirror in the mirror can be disposed in a dielectric material having a relatively low thermal conductivity, where the low thermal conductivity dielectric enables a lower melting point mirror material by insulating the mirror material from the heater element. In one related example, a high thermal conductivity dielectric material can be used to enable relatively high efficient heat transfer from the heater element to the associated phase change material, while a low thermal conductivity dielectric material is used to encapsulate the heater element and phase change material to prevent the transfer of excess heat to the mirror disposed beneath the heater element, thereby enabling higher relative power efficiency, reduced relative material cost, and reduced relative manufacturing cost.

[0068] In one example of a specific implementation of the mirror, the mirror is disposed between the heater element and the phase change material. In one example of a specific implementation, the mirror is disposed between the heater element and the phase change material to reduce the distance between the heater element and the phase change material. In one example of a specific implementation, the mirror can be disposed in a dielectric material having a relatively low thermal conductivity, where the low thermal conductivity dielectric enables a lower melting point mirror material by insulating the mirror material from the heater element. In one related example, a high thermal conductivity dielectric material can be used to enable relatively high efficient heat transfer from the heater element to the associated phase change material, while a low thermal conductivity dielectric material is used to encapsulate the heater element and phase change material to prevent the transfer of excess heat to the mirror disposed beneath the heater element, thereby enabling higher relative power efficiency, reduced relative material cost, and reduced relative manufacturing cost. FIGS. 4A-4E In one example of a specific implementation of the mirror, the mirror is disposed between the heater element and the phase change material. In one example of a specific implementation, the mirror is disposed between the heater element and the phase change material to reduce the distance between the heater element and the phase change material. In one example of a specific implementation, the mirror can be disposed in a dielectric material having a relatively low thermal conductivity, where the low thermal conductivity dielectric enables a lower melting point mirror material by insulating the mirror material from the heater element. In one related example, a high thermal conductivity dielectric material can be used to enable relatively high efficient heat transfer from the heater element to the associated phase change material, while a low thermal conductivity dielectric material is used to encapsulate the heater element and phase change material to prevent the transfer of excess heat to the mirror disposed beneath the heater element, thereby enabling higher relative power efficiency, reduced relative material cost, and reduced relative manufacturing cost.

[0069] FIG. 5A A flowchart illustrating another example method for fabricating an optical modulation array is shown. The method begins at step 400 by forming a dielectric layer on an integrated circuit CMOS front end of line process. At step 401, the method continues by forming an interconnect for electrically connecting to a CMOS FEOL contact pad. The method continues at step 402 by forming another dielectric layer over the interconnect formed at step 401, and then at step 403, forming an interconnect in the dielectric layer formed at step 402. In one example, steps 402 and 403 can be repeated for multiple layers of interconnects as needed / desired. At step 404, the method continues by forming a mirror layer. In one alternative example, step 404 further includes patterning and etching the mirror layer. If desired, patterning and etching can be used to create individual mirrors as well as apertures in each mirror for insulating the interconnects. In one example of a specific implementation, cavities can be formed after step 403 by patterning and etching the dielectric layer from step 402, followed by depositing a mirror layer in the cavities and a planarization step at step 404. In one alternative example, the interconnects and mirror layer can be formed in one or more steps, where the interconnect vias and mirrors are formed in one or more common fabrication steps. In yet another example, the mirror layer can be formed in a second deposition after the interconnects are formed and before planarization. In one alternative operation, step 404 can include multiple process steps to form alternating layers of high and low refractive index materials to provide a distributed Bragg reflector (DBR) as the mirror layer.

[0070] In one instance, the mirror layer can be adapted to act as a reflective element to improve the optical performance of the cell array. In another instance, the mirror layer can be adapted to interact with incident light illuminating the surface of the cell to mitigate the impact of light passing through the cell to CMOS devices in the front-end processing (FEOL) of the integrated circuit.

[0071] In one instance of operation, reducing the incident light passing through the unit cell to the CMOS element can mitigate unwanted errors from these CMOS elements during operation. In a related instance of implementation, the mirror layer may be made of copper (Cu) and copper-tungsten alloy (CuW). In an alternative instance of implementation, the mirror layer may be made of one or more metal oxide materials, including but not limited to indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). In one instance, the mirror material may be provided as one or more steps in the manufacturing process, wherein the mirror material is specifically patterned to cover virtually any channel for light to pass through to the CMOS surface.

[0072] Then, the method continues at step 405 by depositing a dielectric layer on the patterned mirror layer, forming vias in the dielectric layer, and forming electrical interconnects in the vias formed at step 403. The method continues at step 406 by forming a heater material layer. In one example, heater material may be deposited to provide electrical coupling with the interconnects formed at step 405. At step 408, the heater material is patterned and etched to isolate the heater material in each unit cell from adjacent unit cells, thereby forming a separate heater element for each unit cell in the optical modulation unit cell array. In one example of an alternative specific implementation ( FIG. 5A (Not shown in the image), the heater material is further patterned and etched to provide voids in each heater element. In one example, the heater element voids allow incident light to be reflected by the specular layer described in step 404. The method then continues at step 410, where a dielectric layer is deposited on the patterned heater material. The method then continues at step 414, where the dielectric layer deposited in step 410 can be planarized, subsequently forming a phase change material layer. The method then continues at step 416, where a dielectric layer is then formed on the phase change material layer that completes step 416.

[0073] FIG. 5BA flowchart illustrating another exemplary method for fabricating a light modulation cell is shown. The method begins at step 900 by forming a complete CMOS front-end-of-line integrated circuit. At step 902, the method continues by forming a metasurface adapted to block incident light from the integrated circuit formed at step 900. In an alternative example, step 902 can be skipped and the method continues directly to step 904. The method continues at step 904 by forming word lines and vias over and through the metasurface formed at step 902 in multiple steps. Then, the method continues at step 906 by forming bit lines and associated vias. In an alternative example, where step 902 has been skipped, the method continues with step 902 after step 906 by forming a metasurface adapted to block incident light from the integrated circuit formed at step 900. At step 908, the method continues by forming a heater element for a light modulation cell array. Then, the method continues at step 910 by forming a dielectric over the heater element.

[0074] In optional step 912, a mirror layer is formed over the dielectric formed at step 910, followed by another dielectric at step 914. In one example, the mirror layer can be configured as a reflective element to improve the optical performance of the cell array. In another example, the mirror layer can be adapted to interact with incident light that is illuminated to the surface of the cell in order to mitigate the effects of light leakage through individual cells in the cell array to CMOS elements in the integrated circuit front-end-of-line (FEOL). In various examples, the mirror layer can be composed of materials such as copper (Cu) and copper tungsten alloy (CuW) and / or one or more metal oxide conductive materials including, but not limited to, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO).

[0075] The method continues at step 916 by forming a layer of phase change material over the dielectric layer formed at step 910; or alternatively, when a mirror is included, the phase change material layer is formed over the dielectric layer formed at step 914. Then, the method continues at step 918 by forming a dielectric layer to cover the phase change material layer formed at step 916. Finally, the method continues at step 920 by forming input / output bond pads in multiple steps to provide a complete light modulation cell array.

[0076] FIG FIGS. 6A-6DExemplary heater element configurations for light modulating cells are demonstrated. In various examples, the shape of the heater element, along with the relative positions of the electrodes applied to the heater element, can be used to influence the heat pattern generated by the heater element. In various examples, the current flowing through the heater element can distribute heat across the heater element in a non-optimal manner. By changing the shape of the heater element, the current can be directed to provide heat in one or more specific / desired areas. In one example of a specific implementation, the heater element can be configured in a two-dimensional geometric shape with straight sides (or edges) having multiple corners or vertices. Thus, an exemplary heater element can be configured with multiple electrodes, with each electrode positioned at a different heater element vertex.

[0077] In FIG. 6A one example, the electrodes 502 are coupled opposite one another at the diagonal opposite corners of a square heater element composed of heater material 500. In one example, the current flowing through the resistive heater material 500 will tend to position a heat maximum between the diagonally placed electrodes. In FIG. 6A one example, the electrodes positioned a maximum distance from one another provide a longer resistive path to the heater material 500, which can be higher in resistance, and thus a higher relative heat maximum than electrodes positioned closer to one another.

[0078] In FIG. 6B one example, the electrodes 502 are again coupled opposite one another at the opposite diagonal corners of a square heater element composed of heater material 500, however, a heater void 504 positioned at the center of the heater material 500 can affect the current flow around the perimeter of the heater element. In FIG. 6B one example, the electrodes 502 are positioned a maximum distance from one another, along with the current flow path around the perimeter of the heater material 500 having a square shape, as compared to FIG. 6A this provides a longer resistive path to the heater material 500, which can provide a higher resistance, and thus a higher heat maximum. Furthermore, because FIG. 6B the exemplary heater material provides two current flow paths, the resulting heater element can include two heat maxima, one at each diagonal where no electrode is coupled thereto.

[0079] In FIG. 6C one example, the electrodes 502 are again positioned a maximum distance from one another, along with the current flow path around the perimeter of the heater material 500 having a square shape, as compared to FIG. 6A this provides a longer relative resistive path to the heater material 500, however, the heater void 504 is smaller relative to FIG. 6B the heater void 504 of FIG. 6CThe exemplary heater material provides two current flow paths and two thermal maxima, respectively, at each opposite angle of the diagonal line between the electrodes, thus providing a larger relative thermal map because the current can flow over a wider area. FIG. 6D In this example, the electrodes are again located diagonally; however, the single current path, shaped like an "S," provides... FIGS. 6A-6D The longest resistance path of either electrode may provide a higher overall resistance and therefore a higher maximum thermal value, which is located at the linear center point between the two electrodes.

[0080] FIGS. 7A-7C An exemplary heater element electrode configuration is shown. FIG. 7A In one example, electrodes 512 are coupled to heater material 510 opposite each other at opposite corners of the diagonal of the square heater element, wherein the electrodes at the coupling locations are square / symmetrical electrodes. FIG. 7B In this example, electrode 512 is rectangular and relatively large along one axis, thus providing a large overall coupling area on heater material 510. Due to the large coupling area, a given current can provide [the required current]. FIG. 7A Different heat map patterns, relative to FIG. 7A The heater element has lower coupling resistance and a wider area from which current can flow. FIG. 7C In this example, the electrodes 512 are again rectangular; however, the electrodes 512 are positioned opposite each other and centered on the side of the square heater element. In one example, the current flowing through the heater material 510 will have the same characteristics as... FIG. 7A While the current flow area is roughly the same as that shown in the figure, a larger electrode coupling area can provide lower resistance and / or lower capacitance at the electrode coupling.

[0081] FIGS. 8A-8D An exemplary heater element outline is shown. FIG. 8A In this example, heater 520 is configured with a generally uniform thickness across the heater element boundary. FIGS. 8B-8DIn one example of the foregoing, the heater material is configured to be thicker at its periphery. In one example of operation, the heater element comprising the heater 520 is configured with thicker periphery material at the electrode 522. In one related example, the heater element profile can be adapted to achieve a regular ohmic effect, controllably increasing the electrical resistance closer to the center of a given unit cell. In another related example, the heater element shape can be adapted to achieve a non-linear effect of the electron mean free path, which can also increase the electrical resistance at the center of a unit cell. Thus, a heater element configured to be thinner, closer to the center of a unit cell, can provide a relatively higher electrical resistance at the center of the heater, while also providing heat dissipation and reducing thermal cross-talk between adjacent unit cells. In yet another example, the heater shape can be adapted to provide substantially optimized current requirements to the array of unit cells during operation. In one example of implementation, various combinations of heater / heater element shape and configuration, such as those illustrated in FIGS. 6A-8D may be used to manage and influence the thermal map of the heater elements in the array of light modulating unit cells.

[0082] FIG. FIGS. 9A-9C illustrates various heater element and electrode configurations for a light modulating unit cell. FIG. 9A illustrates a unit cell heater element comprising diagonally spaced electrodes 542 on a square heater material 540. In one example, a hot zone 550 can form a relatively central point between the electrodes when current flows between the electrodes 542. In one example, FIG. 9A the unit cell layout of may result in non-uniform current density across the heater element, with cold zones requiring additional energy to reach a required temperature threshold. FIG. 9B illustrates another unit cell layout for a unit cell configured with heater voids 544 in the heater material 540. In one example, one or more heater voids 544 can be provided between the electrodes 542 in the heater material 540. In various examples, the heater voids 544 can help reduce electrical power due to higher heater resistance at the same current. In one example of implementation, the conductive gaps in the heater element are formed with a common heater / resistor mask and etched to create the heater voids 544. FIG. 9C illustrates yet another unit cell layout for a unit cell configured with a single heater void 544 in the heater material 540 to improve current uniformity. In one example, FIG. 9C In one example of the foregoing, the heater material 540 is rectangular (rather than square), providing two hot zones: hot zone 554-1 and hot zone 554-2.

[0083] FIG. 10An exemplary heater array structure 600 is shown that includes a 9X9 array of heater elements 612 of a 9X9 array of light modulating cells. In this example, each cell 610 in the array is associated with a heater element 612 that includes 8 electrodes 614 configured to flow current through the heater element 612 from 4 electrodes 614 on one side of the heater element 612 to 4 electrodes 614 on a second side of the heater element 612. In various examples included herein, interconnects are formed to provide electrical connections between various elements of the CMOS FEOL and the elements of each cell in the cell array. Thus, the electrodes 614 can be defined as interconnects that are configured to provide electrical connections to the heater elements 612.

[0084] In one example, a heater gap 616 is provided between the first and second sides of the heater element 612 to control the thermal map pattern of each heater element 612. In one example, an isolation trench 618 can be used to mitigate thermal cross-talk between adjacent cells 610. In another example, the isolation trench 618 can be used to achieve substantially optimized current requirements for the heater array structure 600 and associated cells. In yet another example, the heater elements 612 can be formed on a dielectric 620 that is adapted to leave insulating regions around the heater elements 620 to provide electrical and / or thermal isolation from adjacent heater elements.

[0085] It should be noted that while the above description primarily refers to devices for displaying and / or projecting images, the light modulating elements described herein can be used in a wide range of applications such as, for example, storage devices, optical routers, optical tweezers, neutral atom computing devices, cell trapping devices, microscopy devices, imaging devices, light sheet devices, printing devices, 3D projection devices, 3D displays, 2D projection devices, 2D displays, heads-up displays (HUDs), virtual reality devices, wavefront shaping devices, augmented reality devices, and stereoscopic displays.

[0086] It should be noted that terms such as bitstream, stream, signal sequence, and the like (or equivalents thereof) as can be used herein have been used interchangeably to describe digital information corresponding to any of a number of desired types of content (e.g., data, video, voice, text, graphics, audio, etc., any of which can generally be referred to as ‘data’).

[0087] As can be used herein, the terms "substantially" and "approximately" provide an industry-accepted tolerance for its corresponding term and / or expression to permit a reasonable amount of variance to exist ranging equal to or within less than about 1 percent to about 50 percent of that value. Other instances of industry-accepted tolerances can range from less than about 1 percent to about 50 percent of that value. It is common for industry-accepted tolerances to not include a range of zero percentage within about 1 percent to about 50 percent of that value. Such variations are not to be construed as errors or defects in the disclosure. The terms "substantially" and "approximately" can be used herein to relate to a relative term and / or expression to permit a reasonable amount of variance to exist ranging equal to or within less than about 1 percent to about 50 percent of that value. The relative term and / or expression can range from less than about 1 percent to about 50 percent of that value. Other relative terms and / or expressions can range from several percent to a large difference.

[0088] As can also be used herein, the terms "configured to," "operatively coupled to," "coupled to," and / or "coupled" include direct coupling and / or indirect coupling between items and / or through intervening items, such as components, elements, circuitry, and / or modules, where for an instance of indirect coupling, the intervening item does not modify the information of a signal but can adjust its current level, voltage level, and / or power level. As can be further used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as "coupled to."

[0089] As can even be further used herein, the terms "configured to," "operable to," "coupled to," or "operatively coupled to" indicate one or more of a power connection, an input, an output, etc., for performing one or more of its corresponding functions when activated, and can further include inferred coupling to one or more other items. As can still be further used herein, the term "associated with" includes direct and / or indirect coupling of separate items, and / or one item embedded in another item.

[0090] As can be used herein, the term "favorably compared" indicates a comparison between two or more items, signals, etc., indicating a favorable relationship that will be apparent to one of skill in the art in light of the present disclosure and based on, for example, the nature of the signals / items being compared. As can be used herein, the term "unfavorably compared" indicates a comparison between two or more items, signals, etc., that fails to provide such a favorable relationship and / or provides an unfavorable relationship. Such items / signals can correspond to one or more numerical values, one or more measurements, one or more counts and / or ratios, one or more types of data, and / or other information having attributes that can be compared to thresholds, to each other, and / or to other information to determine whether a favorable or unfavorable comparison exists. Examples of such a favorable relationship can include: one item / signal being greater than (or greater than or equal to) a threshold, one item / signal being less than (or less than or equal to) a threshold, one item / signal being greater than (or greater than or equal to) another item / signal, one item / signal being less than (or less than or equal to) another item / signal, one item / signal matching another item / signal, one item / signal substantially matching another item / signal within a predefined or industry accepted tolerance (such as 1%, 5%, 10%, or other range), etc. Further, one of skill in the art will recognize that such a comparison between two items / signals can be performed in different ways. For example, when the favorable relationship is that signal 1 has a greater magnitude than signal 2, then a favorable comparison can be achieved when the magnitude of signal 1 is greater than the magnitude of signal 2 or when the magnitude of signal 2 is less than the magnitude of signal 1. Similarly, one of skill in the art will recognize that comparisons of the inverse or opposite of an item / signal and / or other forms of mathematical or logical equivalency can likewise be used in equivalent fashion. For example, a comparison to determine whether signal X is > 5 is equivalent to determining whether -X is <-5, and a comparison to determine whether signal A matches signal B can likewise be performed by determining whether -A matches -B or whether non-A matches non-B. As discussed herein, a determination of whether a particular relationship (favorable or unfavorable) exists can be used to automatically trigger a particular action. Unless explicitly stated otherwise, it can be assumed that the particular condition does not exist, implying that the particular action will not be automatically triggered. In other examples, a determination of whether a particular relationship (favorable or unfavorable) exists can be used as a basis or consideration for determining whether to perform one or more actions. Note that such a basis or consideration can be considered alone or in combination with one or more other bases or considerations in determining whether to perform one or more actions. In one example, where multiple bases or considerations are used in determining whether to perform one or more actions, the respective bases or considerations are given equal weight in such determination. In another example, where multiple bases or considerations are used in determining whether to perform one or more actions, the respective bases or considerations are given unequal weight in such determination.

[0091] As may be used herein, one or more claims may include the phrase "at least one of a, b, and c" in a specific form of this general form or the phrase "at least one of a, b, or c" in the general form, along with elements more or fewer than "a," "b," and "c." In either wording, the phrase is interpreted the same way. Specifically, "at least one of a, b, and c" is equivalent to "at least one of a, b, or c," and both mean a, b, and / or c. As an example, it means: only "a," only "b," only "c," "a" and "b," "a" and "c," "b" and "c," and / or "a," "b," and "c."

[0092] As may also be used herein, the terms “processing module,” “processing circuit,” “processor,” “processing circuit system,” and / or “processing unit” can refer to a single processing device or multiple processing devices. Such processing devices can be microprocessors, microcontrollers, digital signal processors, microcomputers, central processing units, field-programmable gate arrays, programmable logic devices, state machines, logic circuit systems, analog circuit systems, digital circuit systems, and / or any device that manipulates signals (analog and / or digital) based on hard-coded circuit systems and / or operating instructions. A processing module, module, processing circuit, processing circuit system, and / or processing unit can be or further include memory and / or integrated memory elements, which can be a single storage device, multiple storage devices, and / or another embedded circuit system of a processing module, module, processing circuit, processing circuit system, and / or processing unit. Such storage devices can be read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and / or any device storing digital information. It should be noted that if a processing module, module, processing circuit, processing circuit system, and / or processing unit comprises more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via wired and / or wireless bus structures) or distributed (e.g., cloud computing via indirect coupling through a local area network and / or wide area network). It should further be noted that if a processing module, module, processing circuit, processing circuit system, and / or processing unit implements one or more of its functions through a state machine, analog circuit system, digital circuit system, and / or logic circuit system, then the memory and / or memory element storing the corresponding operation instructions may be embedded within or outside the circuit system including the state machine, analog circuit system, digital circuit system, and / or logic circuit system. Still, it should be further noted that the memory element may store and process hard-coded and / or operation instructions corresponding to at least some of the steps and / or functions shown in one or more of the figures, and the processing module, module, processing circuit, processing circuit system, and / or processing unit. Such a storage device or memory element may be included in the article of manufacture.

[0093] The above has described one or more embodiments by way of method steps that illustrate the performance of specified functions and their relationships. For ease of description, the boundaries and order of these functional building blocks and method steps are arbitrarily defined herein. Alternate boundaries and order can be defined, as long as the specified functions and their relationships are appropriately performed. Accordingly, any such alternate boundaries or order are within the scope and spirit of the claims. Further, for ease of description, the boundaries of these functional building blocks are also arbitrarily defined herein. Alternate boundaries can be defined, as long as some important function is appropriately performed. Similarly, the flowchart diagrams herein can also be arbitrarily defined to illustrate certain important functions.

[0094] Within the scope of use, the flowchart boundaries and order can be defined in other ways and still perform some important function. Accordingly, such alternate definitions of the functional building blocks and flowchart and order are within the scope and spirit of the claims. One of ordinary skill in the art will further appreciate that the functional building blocks and other illustrative blocks, modules and components herein can be implemented as illustrated, or by discrete components, an application specific integrated circuits, a processor executing appropriate software, and / or otherwise implemented.

[0095] Additionally, the flowcharts can include a "start" and / or "continue" indication. The "start" and "continue" indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with one or more other routines, either by itself or with other steps or in other manners, as will be appreciated by those skilled in the art. Additionally, the flowcharts can include an "end" and / or "continue" indication. The "end" and / or "continue" indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with one or more other routines, either by itself or with other steps or in other manners, as will be appreciated by those skilled in the art. In this context, "end" indicates the end of the functional building blocks presented and can be followed by other activities that, for clarity, are not further shown or described, or else can be understood as implying activities not specifically shown or described. Further, "continue" indicates that the functional building blocks presented can be optionally repeated one or more times or used in conjunction with other activities that, for clarity, are not further shown or described, or else can be understood as implying activities not specifically shown or described. Further, while a particular order is shown in the flowcharts, this ordering is merely illustrative and alternative ordering is possibilities depending on the particular implementation.

[0096] The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts and / or one or more instances. Physical embodiments of devices, articles, machines and / or processes can incorporate one or more of the aspects, features, concepts, instances, etc. described with reference to one or more of the embodiments discussed herein. Further, throughout the drawings, embodiments can incorporate functionality, steps, modules, etc. that can use the same or similar names that can use the same or different reference numerals, and as such, the functionality, steps, modules, etc. can be the same or similar functionality, steps, modules, etc. or not.

[0097] Unless explicitly stated otherwise, signals to / from elements in the figures presented herein and / or between elements in the figures presented herein can be analog or digital, continuous-time or discrete-time, and single-ended or differential. For example, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. Although one or more specific architectures are described herein, other architectures, using one or more data buses, direct connections between elements, and / or indirect coupling between elements using other hardware, can likewise be implemented.

[0098] The term "module" is used to describe one or more of the embodiments presented. A module implements one or more functions through means such as a processor or other processing device or other hardware, which can include or operate in association with memory storing operational instructions. Modules can operate independently and / or in conjunction with software and / or firmware. As also used herein, a module can contain one or more sub-modules, each of which can be one or more modules.

[0099] Although specific combinations of features and functionalities of the one or more embodiments have been explicitly described herein, other combinations of these features and functionalities are likewise possible. The present disclosure is not limited to the specific examples disclosed herein, and expressly incorporates these other combinations. CLAIM (MODIFIED PURSUANT TO ARTICLE 19 OF THE TREATY) 1. An optical modulation array, comprising: a plurality of optical modulation elements, wherein an optical modulation element comprises: a plurality of electrical interconnects; a heater element coupled to the plurality of electrical interconnects, wherein the heater element is configured to receive electrical energy via the plurality of electrical interconnects; a phase change material disposed proximate to the heater element, wherein the phase change material is adapted to exhibit a change in state based on a thermal contribution from the heater element; and a dielectric layer disposed between the heater element and the phase change material. 2. The optical modulation array of claim 1, further comprising: an integrated circuit electrically coupled to the optical modulation elements, wherein the integrated circuit is adapted to control the electrical energy received by the optical modulation elements. 3. The optical modulation array of claim 2, wherein the integrated circuit is adapted to independently address each optical modulation element of the plurality of optical modulation elements. 4. The optical modulation array of claim 2, wherein the plurality of optical modulation elements are integrated on the integrated circuit. 5. The optical modulation array of claim 1, further comprising a plurality of isolation structures configured to isolate an optical modulation element of the plurality of optical modulation elements from every other optical modulation element in the array. 6. The optical modulation array of claim 5, wherein the isolation structure is selected from the group consisting of: an isolation trench, a filled isolation trench, a gas-filled isolation trench, a vacuum isolation trench, a high-k material-filled isolation trench, and a low-k material-filled isolation trench. 7. The optical modulation array of claim 5, wherein the plurality of isolation structures are configured to provide an optical modulation element of the plurality of optical modulation elements with isolation from every other optical modulation element in the array, wherein the isolation is selected from the group consisting of thermal isolation, electrical isolation, and optical isolation. 8. The optical modulation array of claim 5, wherein the plurality of isolation structures are configured to provide an optical modulation element of the plurality of optical modulation elements with thermal isolation from every other optical modulation element in the array. 9. The optical modulation array of claim 1, wherein the phase change material is adapted to change from a first state to a second state in response to the thermal contribution from the heater element. 10. The optical modulation array of claim 1, wherein the phase change material is adapted to change between a plurality of respective states in response to a thermal contribution from the heater element. 11. The optical modulation array of claim 1, wherein optical modulation element further comprises: a first dielectric material and a second dielectric material, the first dielectric material comprising the dielectric layer, wherein the first dielectric material is configured to encapsulate the heater element and the phase change material, wherein the first dielectric material is adapted to have a higher relative thermal conductivity than the second dielectric material. 12. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface and four respective sides, wherein a first one or more interconnects of the plurality of interconnects are coupled at a first side of the four sides and a second one or more interconnects of the plurality of interconnects are coupled at a side opposite the first side. 13. The optical modulation array of claim 1, wherein the heater element is further provided with one or more voids for directing electrical energy between the first side and the side opposite the first side. 14. The optical modulation array of claim 1, wherein the heater element is configured to have a higher relative resistance at a center of the heater between the first one or more interconnects and the second one or more interconnects. 15. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface and a plurality of vertices, wherein a first interconnect of the first one or more interconnects is coupled to the heater element at a first vertex of the plurality of vertices, wherein a second interconnect of the second one or more interconnects is coupled to the heater element at a second vertex of the plurality of vertices. 16. The optical modulation array of claim 1, wherein the optical modulation element further comprises a reflective layer disposed between the heater element and the phase change material, wherein the reflective layer is adapted to at least partially reflect incident light through the phase change material. 17. The optical modulation array of claim 16, wherein the reflective layer comprises a material selected from the group consisting of: 1) copper (Cu); 2) copper tungsten alloy (CuW); 3) indium tin oxide (ITO); 4) indium gallium zinc oxide (IGZO); and 5) indium tin zinc oxide (ITZO); 6) tantalum (Ta); and 7) ruthenium (Ru). 18. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface, wherein the optical modulation element further comprises a reflective layer disposed proximate the bottom surface of the heater element, wherein the optical modulation element further comprises a phase change material disposed proximate the top surface of the heater element, and wherein the reflective layer is adapted to at least partially reflect incident light through the phase change material and the heater element. 19. The optical modulation array of claim 18, wherein the reflective layer comprises a material selected from the group consisting of: 1) copper (Cu); 2) copper tungsten alloy (CuW); 3) indium tin oxide (ITO); 4) indium gallium zinc oxide (IGZO); 5) indium tin zinc oxide (ITZO); 6) aluminum (Al); 7) tantalum (Ta); and 8) ruthenium (Ru). 20. The optical modulation array of claim 18, wherein the heater element is further provided with one or more voids, wherein the one or more voids are adapted to allow incident light to pass through the heater element to the reflective layer. 21. The optical modulation array of claim 18, wherein the reflective layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a first material having a refractive index R and a second sub-layer comprising a second material having a refractive index S, wherein R is greater than S. 22. The optical modulation array of claim 18, the reflective layer having a respective top surface and a respective bottom surface, wherein the reflective layer is adapted to have a continuously variable refractive index between the top surface and bottom surface. 23. The optical modulation array of claim 1, wherein the heater element is adapted to be at least semi-transparent. 24. The optical modulation array of claim 1, wherein one or more of the plurality of electrical interconnects is adapted to be at least semi-transparent. 25. The optical modulation array of claim 1, wherein one or more of the plurality of electrical interconnects comprises a metal oxide. 26. The optical modulation array of claim 25, wherein the metal oxide is selected from the group consisting of: 1) indium gallium zinc oxide (IGZO); and 2) indium tin zinc oxide (ITZO). 27. The optical modulation array of claim 1, further comprising a passivation layer configured to provide mechanical protection to the optical modulation elements. 28. The optical modulation array of claim 27, wherein the passivation layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a material having a refractive index R and a second sub-layer comprising a material having a refractive index S, wherein R is greater than S. 29. The optical modulation array of claim 27, the passivation layer having a respective top surface and a respective bottom surface, wherein the passivation layer is adapted to have a continuously variable refractive index between the top surface and bottom surface. 30. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface, the heater element further configured to have a serpentine shape with a first end and a second end, wherein a first one or more of the plurality of interconnects is coupled to the first end and a second one or more of the plurality of interconnects is coupled to the second end of the heater element. 31. The optical modulation array of claim 1, wherein the optical modulation array is adapted for use in a device selected from the group consisting of: a storage device, an optical router, an optical tweezer, a neutral atom computing device, a cell capturing device, a microscope device, an imaging device, an optical sheet device, a printing device, and a wavefront shaping device. 32. The optical modulation array of claim 1, wherein the modulation array is adapted for use in a device selected from the group consisting of: a 3D projection device, a 3D display, a 2D projection device, a 2D display, a heads-up display (HUD), a virtual reality device, an augmented reality device, and a stereoscopic display. 33. A method for fabricating an optical modulation unit cell, the method comprising: forming a first dielectric layer on an integrated circuit front end process; forming an interconnect in the first dielectric layer; forming a heater material layer; patterning and etching the heater material to form a heater element; forming a second dielectric layer on the heater element; forming a mirror layer over the second dielectric layer; forming a third dielectric layer on the mirror layer; forming a phase change material layer over the third dielectric layer; and forming a fourth dielectric layer over the phase change material layer. 34. The method of claim 33, further comprising: forming a metasurface layer, wherein the metasurface layer is adapted to block light of a predetermined wavelength. 35. The method of claim 33, wherein the patterning and etching the heater material further comprises forming one or more voids in the heater element. 36. A method for fabricating an optical modulation unit cell, the method comprising: forming a first dielectric layer on an integrated circuit front end process; forming an interconnect in the first dielectric layer; forming a mirror layer over the first dielectric layer; forming a second dielectric layer over the mirror layer; forming a heater material layer; patterning and etching the heater material to form a heater element; forming a third dielectric layer on the heater element; forming a phase change material layer on the third dielectric layer; and forming a fourth dielectric layer over the phase change material layer. 37. The method of claim 36, wherein the heater material is further patterned and etched to provide one or more voids in the heater element. 38. The method of claim 36, wherein the mirror layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a material having a refractive index R and a second sub-layer comprising a material having a refractive index S, wherein R is greater than S. 39. The method of claim 36, wherein the mirror layer has a respective top surface and a respective bottom surface, wherein the mirror layer is adapted to have a continuously variable refractive index between the top surface and bottom surface. 40. The method of claim 36, wherein the fourth dielectric layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a material having a refractive index R and a second sub-layer comprising a material having a refractive index S, wherein R is greater than S. 41. The method of claim 36, wherein the fourth dielectric layer has a respective top surface and a respective bottom surface, wherein the fourth dielectric layer is adapted to have a continuously variable refractive index between the top surface and bottom surface. 42. A method for fabricating an optical modulation unit cell, the method comprising: forming a metasurface layer on an integrated circuit front end of line; forming a first dielectric layer; forming an interconnect in the first dielectric layer; forming a mirror layer over the first dielectric layer; forming a second dielectric layer on the mirror layer; forming a heater material layer; patterned and etching the heater material to form a heater element; forming a third dielectric layer on the heater element; forming a phase change material layer over the third dielectric layer; and forming a fourth dielectric layer over the phase change material layer. 43. A method for fabricating an optical modulation unit cell, the method comprising: forming a first dielectric layer on an integrated circuit front end of line; forming an interconnect in the first dielectric layer; forming a metasurface layer; forming a mirror layer over the metasurface layer; forming a second dielectric layer on the mirror layer; forming a heater material layer; patterning and etching a heater material to form a heater element; forming a third dielectric layer on the heater element; forming a layer of phase change material over the third dielectric layer; and forming a fourth dielectric layer over the layer of phase change material. 44. A system comprising: a light source for generating and emitting light; an array of light modulating elements, wherein a light modulating element comprises: a plurality of electrical interconnects; a heater element configured to receive electrical energy via the plurality of electrical interconnects; a phase change material disposed proximate to the heater element, the phase change material configured to exhibit a change in state based on a thermal contribution from the heater element; and a dielectric layer disposed between the heater element and the phase change material.

Claims

1. A light modulating array comprising: a plurality of light modulating elements, wherein a light modulating element comprises: a plurality of electrical interconnects; a heater element coupled to the plurality of electrical interconnects, wherein the heater element is configured to receive electrical energy via the plurality of electrical interconnects; and a phase change material disposed proximate to the heater element, wherein the phase change material is adapted to exhibit a state change based on a thermal contribution from the heater element.

2. The light modulating array of claim 1, further comprising: an integrated circuit electrically coupled to the light modulating elements, wherein the integrated circuit is adapted to control the electrical energy received by the light modulating elements.

3. The light modulating array of claim 2, wherein the integrated circuit is adapted to independently address each light modulating element of the plurality of light modulating elements.

4. The light modulating array of claim 2, wherein the plurality of light modulating elements are integrated on the integrated circuit.

5. The light modulating array of claim 1, further comprising a plurality of isolation structures configured to isolate a light modulating element of the plurality of light modulating elements from each other light modulating element in the array.

6. The light modulating array of claim 5, wherein the isolation structure is selected from the group consisting of: an isolation trench, a filled isolation trench, a gas-filled isolation trench, a vacuum-filled isolation trench, an isolation trench filled with a high-k material, and an isolation trench filled with a low-k material.

7. The light modulating array of claim 5, wherein the plurality of isolation structures are configured to provide a light modulating element of the plurality of light modulating elements with isolation from each other light modulating element in the array, wherein the isolation is selected from the group consisting of thermal isolation, electrical isolation, and optical isolation.

8. The light modulating array of claim 5, wherein the plurality of isolation structures are configured to provide a light modulating element of the plurality of light modulating elements with thermal isolation from each other light modulating element in the array.

9. The light modulating array of claim 1, wherein the phase change material is adapted to change from a first state to a second state in response to the thermal contribution from the heater element.

10. The light modulating array of claim 1, wherein the phase change material is adapted to change between a plurality of respective states in response to a thermal contribution from the heater element.

11. The light modulating array of claim 1, wherein a light modulating element further comprises: a first dielectric material and a second dielectric material, wherein the first dielectric material is configured to encapsulate the heater element and the phase change material, wherein the first dielectric material is adapted to have a higher relative thermal conductivity than the second dielectric material.

12. The light modulating array of claim 1, the heater element having a respective top surface and a respective bottom surface and four respective sides, wherein a first one or more of the plurality of interconnects is coupled at a first side of the four sides and a second one or more of the plurality of interconnects is coupled at a side opposite the first side.

13. The optical modulation array of claim 1, wherein the heater element is further provided with one or more voids for directing electrical energy between the first side and the side opposite the first side.

14. The optical modulation array of claim 1, wherein the heater element is configured to have a higher relative electrical resistance at a center of the heater between the first one or more interconnects and the second one or more interconnects.

15. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface and a plurality of vertices, wherein a first interconnect of the first one or more interconnects is coupled to the heater element at a first vertex of the plurality of vertices, wherein a second interconnect of the second one or more interconnects is coupled to the heater element at a second vertex of the plurality of vertices.

16. The optical modulation array of claim 1, wherein the optical modulation element further comprises a reflective layer disposed between the heater element and the phase change material, wherein the reflective layer is adapted to at least partially reflect incident light through the phase change material.

17. The optical modulation array of claim 16, wherein the reflective layer comprises a material selected from the group consisting of: 1) copper (Cu); 2) copper tungsten alloy (CuW); 3) indium tin oxide (ITO); 4) indium gallium zinc oxide (IGZO); and 5) indium tin zinc oxide (ITZO); 6) tantalum (Ta); and 7) ruthenium (Ru).

18. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface, wherein the optical modulation element further comprises a reflective layer disposed proximate the bottom surface of the heater element, wherein the optical modulation element further comprises a phase change material disposed proximate the top surface of the heater element, and wherein the reflective layer is adapted to at least partially reflect incident light through the phase change material and the heater element.

19. The optical modulation array of claim 18, wherein the reflective layer comprises a material selected from the group consisting of: 1) copper (Cu); 2) copper tungsten alloy (CuW); 3) indium tin oxide (ITO); 4) indium gallium zinc oxide (IGZO); 5) indium tin zinc oxide (ITZO); 6) aluminum (Al); 7) tantalum (Ta); and 8) ruthenium (Ru).

20. The optical modulation array of claim 18, wherein the heater element is further provided with one or more voids, wherein the one or more voids are adapted to allow incident light to pass through the heater element to the reflective layer.

21. The optical modulation array of claim 18, wherein the reflective layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a first material having a refractive index R and a second sub-layer comprising a second material having a refractive index S, wherein R is greater than S. ​ 22. The optical modulation array of claim 18, the reflective layer having a respective top surface and a respective bottom surface, wherein the reflective layer is adapted to have a continuously variable refractive index between the top and bottom surfaces.

23. The optical modulation array of claim 1, wherein the heater element is adapted to be at least semi-transparent.

24. The optical modulation array of claim 1, wherein one or more of the plurality of electrical interconnects is adapted to be at least semi-transparent.

25. The optical modulation array of claim 1, wherein one or more electrical interconnects comprises a metal oxide.

26. The optical modulation array of claim 25, wherein the metal oxide is selected from the group consisting of: 1) indium gallium zinc oxide (IGZO); and 2) indium tin zinc oxide (ITZO).

27. The optical modulation array of claim 1, further comprising a passivation layer configured to provide mechanical protection to the optical modulation elements.

28. The optical modulation array of claim 27, wherein the passivation layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a material having a refractive index R and a second sub-layer comprising a material having a refractive index S, wherein R is greater than S.

29. The optical modulation array of claim 27, the passivation layer having a respective top surface and a respective bottom surface, wherein the passivation layer is adapted to have a continuously variable refractive index between the top and bottom surfaces.

30. The optical modulation array of claim 1, the heater element having a respective top surface and a respective bottom surface, the heater element further configured to have a serpentine shape with a first end and a second end, wherein a first one or more of the plurality of interconnects is coupled to the first end and a second one or more of the plurality of interconnects is coupled to the second end of the heater element.

31. The optical modulation array of claim 1, wherein the optical modulation array is adapted for use in a device selected from the group consisting of: a storage device, an optical router, an optical tweezer, a neutral atom computing device, a cell trapping device, a microscope device, an imaging device, an optical sheet device, a printing device, and a wavefront shaping device.

32. The optical modulation array of claim 1, wherein the modulation array is adapted for use in a device selected from the group consisting of: a 3D projection device, a 3D display, a 2D projection device, a 2D display, a head-up display (HUD), a virtual reality device, an augmented reality device, and a stereoscopic display.

33. A method for fabricating an optical modulation unit cell, the method comprising: forming a first dielectric layer on an integrated circuit front end process; forming an interconnect in the first dielectric layer; forming a heater material layer; patterning and etching the heater material to form a heater element; forming a second dielectric layer on the heater element; forming a mirror layer over the second dielectric layer; forming a third dielectric layer on the mirror layer; forming a phase change material layer over the third dielectric layer; and forming a fourth dielectric layer over the phase change material layer.

34. The method of claim 33, further comprising: forming a metasurface layer, wherein the metasurface layer is adapted to block light of a predetermined wavelength.

35. The method of claim 33, wherein the patterning and etching the heater material further comprises forming one or more voids in the heater element.

36. A method for fabricating an optical modulation unit cell, the method comprising: forming a first dielectric layer on an integrated circuit front end of line; forming an interconnect in the first dielectric layer; forming a mirror layer over the first dielectric layer; forming a second dielectric layer over the mirror layer; forming a heater material layer; patterning and etching a heater material to form a heater element; forming a third dielectric layer over the heater element; forming a phase change material layer over the third dielectric layer; and forming a fourth dielectric layer over the phase change material layer.

37. The method of claim 36, wherein the heater material is further patterned and etched to provide one or more voids in the heater element.

38. The method of claim 36, wherein the mirror layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a material having a refractive index R and a second sub-layer comprising a material having a refractive index S, wherein R is greater than S.

39. The method of claim 36, wherein the mirror layer has a respective top surface and a respective bottom surface, wherein the mirror layer is adapted to have a continuously variable refractive index between the top surface and bottom surface.

40. The method of claim 36, wherein the fourth dielectric layer comprises a plurality of sub-layers, wherein the plurality of sub-layers comprises a first sub-layer comprising a material having a refractive index R and a second sub-layer comprising a material having a refractive index S, wherein R is greater than S.

41. The method of claim 36, wherein the fourth dielectric layer has a respective top surface and a respective bottom surface, wherein the fourth dielectric layer is adapted to have a continuously variable refractive index between the top surface and bottom surface.

42. A method for fabricating an optical modulation unit cell, the method comprising: forming a metasurface layer on an integrated circuit front end of line; forming a first dielectric layer; forming an interconnect in the first dielectric layer; forming a mirror layer over the first dielectric layer; forming a second dielectric layer over the mirror layer; forming a heater material layer; patterning and etching a heater material to form a heater element; forming a third dielectric layer over the heater element; forming a phase change material layer over the third dielectric layer; and forming a fourth dielectric layer over the phase change material layer.

43. A method for fabricating an optical modulation unit cell, the method comprising: forming a first dielectric layer on an integrated circuit front end of line; forming an interconnect in the first dielectric layer; forming a metasurface layer; forming a mirror layer over the metasurface layer; forming a second dielectric layer over the mirror layer; forming a heater material layer; patterning and etching a heater material to form a heater element; forming a third dielectric layer on the heater element; forming a layer of phase change material over the third dielectric layer; and forming a fourth dielectric layer over the layer of phase change material.

44. A system comprising: a light source for generating and emitting light; an array of light modulating elements, wherein a light modulating element comprises: a plurality of electrical interconnects; a heater element configured to receive electrical energy via the plurality of electrical interconnects; and a phase change material disposed proximate to the heater element, the phase change material configured to exhibit a change in state based on a thermal contribution from the heater element.

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