Conditional branch instructions for aggregating conditional branch operations

Abstract

In an example, a system (100) is provided that includes instruction fetch circuitry (101), decoder circuitry (103), and condition aggregation circuitry (113). The instruction fetch circuitry (101) fetches a conditional branch instruction (CBI) (125) from a memory (121), the CBI identifying a plurality of register locations (115 and 116) and a conditional aggregation operation. The condition aggregation operation represents an instruction identifying a plurality of conditions to be checked. The instruction fetch circuitry (101) provides the CBI (125) to the decoder circuitry (103). In response, the decoder circuitry (103) causes the condition aggregation circuitry (113) to perform a plurality of condition checks with respect to values stored in the plurality of register locations (115 and 116).

Description

[0001] This manual covers computing hardware and software in general, and more specifically conditional branch instructions. Background Technology

[0002] Conditional branching statements are a type of program statement that supports conditional execution of code. For example, conditional branching statements in the source code of a software program can instruct the program to branch to another part of the program when a specified condition is true.

[0003] The source code of a software program is eventually compiled into binary program instructions, which are executed by the circuitry on the computing device. In the case of conditional branch statements, the resulting program instructions may include, for example, comparison instructions and branch instructions, both of which are executed by the corresponding circuitry on the computing device.

[0004] Multi-condition branching statements involve evaluating multiple conditions. In a simple example, a statement in the source code might call for the evaluation of two conditions, the result of which controls the execution order of the software program. The compiled code generated by such multi-condition branching statements contains a long chain of comparison and branch instructions, the completion of which requires numerous execution cycles. More complex instances of multi-condition branching statements can lead to even longer chains of comparison and branch instructions, resulting in even more execution cycles.

[0005] The problem is that current techniques for executing conditional branching statements are limited in that they can only check one condition at a time. Therefore, devices implementing conditional branching may require a large number of execution cycles. Furthermore, conditional branching statements increase program size when finally compiled into binary program instructions, thus increasing the memory requirements of the execution device. Summary of the Invention

[0006] This paper describes improvements to the compilation and execution of multi-condition branching statements. In various instances, conditional branching instructions (CBIs) are introduced, which instruct the processing system or its components to aggregate multiple condition checks of a conditional branching statement, thereby reducing the number of execution cycles required to evaluate multiple conditions.

[0007] In one example, a system includes an instruction fetching circuitry, a decoder circuitry coupled to the instruction fetching circuitry, and a condition aggregation circuitry coupled to the decoder circuitry. The instruction fetching circuitry fetches a Conditional Interface (CBI) from memory. The CBI identifies multiple register locations and a condition aggregation operation. The condition aggregation operation identifies multiple condition checks to be performed by the condition aggregation circuitry. The instruction fetching circuitry provides the CBI to the decoder circuitry. In response, the decoder circuitry causes the condition aggregation circuitry to perform multiple condition checks on values ​​stored in the multiple register locations.

[0008] This summary is provided to introduce, in a simplified form, a series of concepts further described below in the detailed embodiments. This summary does not necessarily identify the key or essential features of the claimed subject matter, nor does it necessarily limit the scope of the claimed subject matter. Attached Figure Description

[0009] The components in the drawings are not necessarily to scale; the emphasis is on clearly illustrating the principles of this specification. Furthermore, similar reference numerals are used throughout the drawings to denote corresponding parts. While several examples are described in conjunction with these drawings, this specification is not limited to the examples described herein. Rather, it is intended to cover all alternatives, modifications, and equivalents.

[0010] Figure 1 The operating environment described in the implementation plan is explained.

[0011] Figure 2 The conditional branching aggregation process in the implementation plan is explained.

[0012] Figure 3 The operational sequence in the implementation plan is explained.

[0013] Figure 4 The operating environment described in the implementation plan is explained.

[0014] Figure 5A , 5B 5C, 5D, and 5E illustrate the operational scenarios in the implementation plan.

[0015] Figure 6 This describes computing systems applicable to the various operating environments, architectures, processes, scenarios, and sequences described below with reference to other diagrams. Detailed Implementation

[0016] This paper describes techniques for improving the execution of multi-condition branching logic. Multi-condition branching logic involves evaluating multiple conditions, the results of which determine the program's execution path. When executed, multi-condition branching logic causes the Central Processing Unit (CPU) to determine whether a set of conditions are true or false and outputs the results. Based on the obtained values, the CPU can then decide the next program segment to branch to.

[0017] For example, if one variable is less than the second variable, and if the second variable is greater than the third variable (i.e., If both conditions are true, the program branches to the specified code segment; otherwise, the program continues its linear operation.

[0018] Existing technology implements the aforementioned multi-condition branching logic via a long sequence of comparison and branch instructions. For example, the first comparison instruction causes the circuit system to compare a first variable with a second variable (i.e., The first comparison instruction, following the first comparison instruction, causes the circuit to evaluate the result of the first comparison. If true, the first branch instruction causes the circuit to branch to a program segment containing a second comparison instruction. The second comparison instruction causes the circuit to compare the second variable with the third variable (i.e., ...). The second comparison instruction then stores the result (e.g., 1 or 0) in a second register. Following the second comparison instruction is a second branch instruction that evaluates the result of the second comparison. If true, the second branch instruction causes the circuit system to branch to a specified program segment in memory.

[0019] In summary, instance-based multi-condition branching logic can utilize at least two condition checks (i.e., first and second comparison instructions) and two condition branch operations (i.e., first and second branch instructions). Therefore, the completion of condition branch operations in a pipelined processor may require multiple execution cycles, potentially increasing execution costs. In contrast, this paper describes a novel Conditional Branch Instruction (CBI) that executes multi-condition branching logic within a single execution cycle.

[0020] First, the same multi-condition branching logic expressed in the source code is compiled into two comparison instructions (i.e., and The instruction result is stored in two registers. The new CBI can compare these two results in one execution cycle, instead of requiring two. In this context, an execution cycle includes both the condition that the processing circuitry (e.g., processing circuitry 105 described below) can proceed from receiving the instruction to obtaining the result in one clock cycle, and a pipelined architecture in which the processing circuitry requires several clock cycles to proceed from receiving the instruction to obtaining the result, but the instruction occupies only one slot in the pipeline. In the case of a pipelined architecture, the first instruction may allow the second instruction to complete in the clock cycle immediately preceding the completion of the first instruction, or it may allow the third instruction to complete in the clock cycle immediately following the completion of the first instruction. Therefore, in effect, the first instruction only delays the subsequent third instruction by one clock cycle.

[0021] The new CBI takes the results of two or more comparison instructions as input and evaluates the results of the instructions in a single cycle using logic expressed in the source code, regardless of whether the logic is AND, OR, XOR, or other Boolean logic. The advantage of the new CBI is that it allows the same multi-condition branching logic to be executed in just one cycle, whereas the existing solutions described above require multiple cycles. While the benefits may seem minor, the improvement becomes increasingly apparent as the number of logic combinations increases.

[0022] For a simple example, the source code might need to evaluate two separate AND statements, which are then combined using an OR statement (e.g., if: or Existing techniques may utilize at least four execution cycles, depending on the variable values: 1) two or more execution cycles for evaluating the first set of two conditions; and 2) two or more execution cycles for evaluating the second set of two conditions, potentially resulting in four condition evaluation operations and four condition branching operations (one operation for each condition to be examined). In contrast, the CBI described in this paper takes the outputs of all four conditions as input and performs one condition branching operation within a single execution cycle based on the evaluation of the comparison results.

[0023] In one example, a system is provided that includes an instruction fetch circuitry, a decoder circuitry coupled to the instruction fetch circuitry, and a condition aggregation circuitry coupled to the decoder circuitry. The instruction fetch circuitry is configured to fetch conditional branch instructions (CBIs) from memory and provide the CBIs to the decoder circuitry. A CBI represents a program instruction that instructs the corresponding circuitry to perform one or more operations. A CBI identifies multiple register locations and condition aggregation operations.

[0024] In this implementation, the multiple register locations include four status register locations. Each status register location represents a register that stores the result of a first-order condition check. The first-order condition check represents the first set of comparison operations performed by the CPU's processing circuitry. For example, the arithmetic logic unit (ALU) can perform the first set of comparison operations, and the program control unit can check the result of the ALU and store an indication of each result in a different status register. The output of the program control unit indicates whether the comparison operation identified by the first-order condition check is true or false.

[0025] CBI's conditional aggregation operations are represented by hexadecimal values ​​that identify multiple conditional checks to be performed and the desired combinations of those checks. In implementations, the multiple conditional checks of a conditional aggregation operation represent second-order conditional checks. A second-order conditional check represents a second set of comparison operations performed relative to the results of first-order conditional checks. In implementations, second-order conditional checks allow for any logical combination of the results of first-order conditional checks. In an example, the conditional aggregation operation specifies whether to branch based on the various combinations of first-order conditional checks by specifying a lookup table (LUT) for the combinations of first-order conditional checks.

[0026] Upon receiving a CBI, the decoder circuitry causes the condition aggregation circuitry to perform multiple condition checks on the values ​​stored in multiple register locations. Therefore, the condition aggregation circuitry outputs a true or false indication, depending on whether the result of the first-order condition check satisfies the requirements of the second-order condition check.

[0027] In the implementation scheme, the conditional aggregation circuit system includes a LUT circuit system for performing a second-order condition check to perform the conditional aggregation operation. In operation, the LUT circuit system receives a CBI and, in response, outputs the result of the second-order condition check. When the second-order condition check is satisfied, the LUT circuit system outputs a true indication; otherwise, it outputs a false indication. Based on the output of the LUT circuit system, the instruction fetching circuit system can determine the next instruction to be executed.

[0028] The advantage of this technique lies in improving the efficiency of systems utilizing conditional branching. Existing solutions for executing multi-conditional branching logic are limited by the fact that only one condition can be checked at a time. Therefore, existing solutions require a large number of execution cycles to perform conditional branching operations. In contrast, this paper describes systems and methods for performing multiple condition checks within a single execution cycle, thereby reducing the time and code size required to execute multi-conditional branching logic.

[0029] Now refer to the various figures. Figure 1 The operating environment 100 in the implementation scheme is described. Operating environment 100 represents an instance operating environment configurable to execute program code such as conditional branch instructions (CBI). Operating environment 100 includes instruction fetch circuitry 101, decoder circuitry 103, processing circuitry 105, and memory 121. In some instances, the components shown in operating environment 100 may be included within the processing system, such as a microcontroller unit (MCU) or central processing unit (CPU). In some instances, some components shown in operating environment 100 may be included outside the processing system.

[0030] Instruction fetch circuitry 101 represents a circuitry configured to fetch instructions from memory and provide those instructions to the decoder. For example, instruction fetch circuitry 101 may fetch instructions from memory 121 and provide those instructions to decoder circuitry 103.

[0031] Decoder circuitry 103 represents circuitry configured to decode instructions fetched from memory. For example, instruction fetching circuitry 101 may fetch instructions from memory 121 and provide the fetched instructions to decoder circuitry 103. In response, decoder circuitry 103 decodes the fetched instructions and routes the decoded instructions to the appropriate circuitry in processing circuitry 105. In embodiments, the decoded instructions identify the operation to be performed and the associated memory location for performing the desired operation. For example, a decoded instruction may represent a CBI, which identifies multiple conditions to be checked and multiple register locations for performing the multiple condition checks. Although Figure 1 Only one decoder (decoder circuitry 103) is shown, but the operating environment 100 may contain several decoders or decoder circuits. For example, each circuit in the processing circuitry 105 may contain a separate decoder circuitry.

[0032] Processing circuit system 105 represents one or more circuits capable of executing program instructions. Processing circuit system 105 may be coupled to instruction fetching circuit system 101, decoder circuit system 103, and memory 121. Processing circuit system 105 includes, but is not limited to, arithmetic logic circuit system 107, program control circuit system 111, condition aggregation circuit system 113, register 115, and register 116.

[0033] Arithmetic logic circuit system 107 represents a circuit system configured to perform arithmetic operations. For example, arithmetic logic circuit system 107 can determine whether a value stored in a first register location is less than, greater than, and / or equal to a value stored in a second register location. In an embodiment, the output of arithmetic logic circuit system 107 is stored in memory 121.

[0034] Program control circuitry 111 represents a circuitry configured to manage the execution of program code. In various instances, program control circuitry 111 may instruct instruction fetching circuitry 101 to fetch certain instructions in a specific order while other circuitry systems, such as arithmetic logic circuitry 107 and conditional aggregation circuitry 113, execute instructions during runtime operation.

[0035] In an implementation, program control circuitry system 111 further represents a circuitry system configured to perform a first-order condition check. The first-order condition check represents an analysis performed on the result of a comparison operation. For example, arithmetic logic circuitry system 107 can perform the comparison operation, and program control circuitry system 111 can examine the output of arithmetic logic circuitry system 107 to determine whether the comparison operation satisfies the first-order condition check. In an implementation, program control circuitry system 111 stores the result of the first-order condition check in a register of processing circuitry system 105. For example, if program control circuitry system 111 determines that the first-order condition is satisfied, program control circuitry system 111 can store a "1" in register 115 to indicate that the condition is satisfied; otherwise, program control circuitry system 111 can store a "zero" in register 115 to indicate that the condition is not satisfied. Alternatively, arithmetic logic circuitry system 107 can determine the first-order condition and write it directly to register 115.

[0036] Condition aggregation circuit system 113 represents a circuit system configured to execute conditional branch instructions (CBI). More specifically, condition aggregation circuit system 113 represents a circuit system capable of aggregating multiple conditions of a CBI. In an embodiment, the decoded CBI identifies the condition aggregation operation and multiple register locations used to execute the condition aggregation operation. The condition aggregation operation may represent a hexadecimal value that identifies multiple conditions to be checked. The multiple conditions identified by the condition aggregation operation represent a second-order condition check. The second-order condition check describes a secondary analysis performed on the result of the first-order condition check. In an example, the second-order condition check determines whether the result stored in the registers of the processing circuit system 105 satisfies the condition aggregation operation of the CBI. If satisfied, the condition aggregation circuit system 113 outputs a true indication (e.g., 1); otherwise, the condition aggregation circuit system 113 outputs a false indication (e.g., 0). The output of the condition aggregation circuit system 113 is used to control the execution of program code. For example, the program control circuit system 111 may evaluate the output of the condition aggregation circuit system 113 to determine the next program code segment to be executed. Although shown outside the program control circuit system 111, in some cases the program control circuit system includes a condition aggregation circuit system 113.

[0037] Registers 115 and 116 represent memory locations storing data and / or instructions used during the execution of program code. Registers 115 and 116 may have different architectures and / or be part of a single larger register (e.g., different bits). In an embodiment, registers 115 and 116 represent registers storing the results of a first-order condition check. For example, program control circuitry 111 may output the results of a first-order condition check to registers 115 and 116, and condition aggregation circuitry 113 may analyze the data stored in registers 115 and 116 to make a decision. Although only two registers are shown, processing circuitry 105 may contain more than two registers.

[0038] Memory 121 represents one or more volatile or non-volatile computer-readable storage media (e.g., random access memory, flash memory) containing instructions, data, etc. For example, memory 121 stores instructions 123, 124, 125, 126, and 129, and includes memory locations 143, 144, 145, 146, and 149. The instructions in memory 121 instruct the circuitry in processing circuitry system 105 to perform various operations, while the memory locations in memory 121 store data.

[0039] Instruction 123 indicates a first-order condition check, instructing arithmetic logic circuitry system 107 and program control circuitry system 111 to determine whether the data stored in memory locations 143 and 144 satisfies the first-order condition of instruction 123. When executed, arithmetic logic circuitry system 107 performs the comparison operation identified by instruction 123 (e.g., greater than, less than, equal to, etc.). Program control circuitry system 111 checks the output of arithmetic logic circuitry system 107 and stores an indication of whether the first-order condition is satisfied in register 115. For example, program control circuitry system 111 may store '1' if the condition is satisfied and '0' if the condition is not satisfied. Alternatively, arithmetic logic circuitry system 107 may write directly to register 115.

[0040] Similarly, instruction 124 also represents a first-order condition check, instructing arithmetic logic circuitry system 107 and program control circuitry system 111 to determine whether the data stored in memory locations 144 and 145 satisfies the first-order condition of instruction 124. When executed, arithmetic logic circuitry system 107 performs the comparison operation identified by instruction 124. Program control circuitry system 111 and / or arithmetic logic circuitry system 107 itself checks the output of arithmetic logic circuitry system 107 and stores an indication (e.g., 1 or 0) in register 116 indicating whether the first-order condition has been satisfied.

[0041] Instruction 125 represents a CBI, and the CBI identifies a conditional aggregation operation and multiple register locations for performing the conditional aggregation operation. When executed, instruction 125 causes the conditional aggregation circuitry 113 to determine whether the results stored in registers 115 and 116 satisfy the conditional aggregation operation of instruction 125. The program control circuitry 111 can evaluate the output of the conditional aggregation circuitry 113 to determine the next program code segment to execute. If the conditional aggregation operation is satisfied, the conditional aggregation circuitry 113 can output a one, otherwise the conditional aggregation circuitry 113 can output a zero.

[0042] Instructions 126 and 129 represent program instructions that depend on the result of instruction 125. For example, if the output of the conditional aggregation circuitry 113 indicates that the conditional aggregation operation is not satisfied, the program control circuitry 111 can instruct the instruction fetch circuitry 101 to fetch instruction 126 from the memory 121 (to continue its linear operation). Alternatively, if the output of the conditional aggregation circuitry 113 indicates that the conditional aggregation operation is satisfied, the program control circuitry 111 can instruct the instruction fetch circuitry 101 to fetch instruction 129 from the memory 121.

[0043] Figure 2 Illustrates the conditional branch aggregation (CBA) process 200 in an embodiment. The CBA process 200 can be implemented in the context of program instructions that, when executed by a suitable computing system, instruct the processing circuitry of the computing system to operate as follows, with the steps pointed to by the way of parentheses Figure 2 For purposes of explanation, the elements of Figure 1 will be used to describe the CBA process 200. This is not meant to limit the application of the CBA process 200, but rather to provide an example.

[0044] First, the program control circuitry 111 performs a set of first-order condition checks (step 201). For example, the program control circuitry 111 can execute instruction 123 and instruction 124. Instructions 123 and 124 represent instructions that instruct the arithmetic logic circuitry 107 and the program control circuitry 111 to determine whether the data stored in the identified memory locations satisfies the first-order conditions of the instructions (e.g., is a < y; is y < b; is x < y; is y < z; etc.). For example, instruction 123 instructs the arithmetic logic circuitry 107 and the program control circuitry 111 to determine whether the data stored in memory locations 143 and 144 satisfies the first-order condition of instruction 123. Similarly, instruction 124 instructs the arithmetic logic circuitry 107 and the program control circuitry 111 to determine whether the data stored in memory locations 144 and 145 satisfies the first-order condition of instruction 124.

[0045] Next, the program control circuit system 111 stores the result of the first-order condition check in multiple register locations (step 203). In an embodiment, the program control circuit system 111 stores the result of the first-order condition check in a register of the processing circuit system 105. For example, the program control circuit system 111 may store the result of instruction 123 in register 115 and the result of instruction 124 in register 116. If the comparison operation is satisfied, the program control circuit system 111 stores a "-" to indicate that the comparison operation is true; otherwise, the program control circuit system 111 stores a "-" to indicate that the comparison operation is false.

[0046] Instruction fetching circuitry 101 also fetches the CBI from memory 121 (step 205). For example, instruction fetching circuitry 101 may fetch instruction 125 from memory 121. Once fetched, instruction fetching circuitry 101 provides instruction 125 to decoder circuitry 103 (step 207). In response, decoder circuitry 103 decodes instruction 125 and routes the decoded representation of instruction 125 to conditional aggregation circuitry 113. The decoded representation of instruction 125 identifies the conditional aggregation operation and multiple register locations for performing the conditional aggregation operation.

[0047] Conditional aggregation circuit system 113 receives the decoded representation of instruction 125 and, in response, executes the conditional aggregation operation of instruction 125 (step 209). The conditional aggregation operation represents a hexadecimal value, which identifies multiple conditions to be checked. In an embodiment, the hexadecimal value of the conditional aggregation operation defines the expected output of the first-order condition check. For example, the hexadecimal value might define the output of instruction 123 as false and the output of instruction 124 as true. When determining whether the result of the first-order condition check satisfies the conditional aggregation operation, conditional aggregation circuit system 113 outputs a result. In an embodiment, conditional aggregation circuit system 113 outputs a '-' to indicate a true output and outputs a '-' to indicate a false output.

[0048] Finally, program control circuitry 111 evaluates the output of conditional aggregation circuitry 113 to determine which instruction to execute next (step 211). This may involve fetching the next instruction from memory 121, particularly when unpredictable branches are used. For example, if the output of conditional aggregation circuitry 113 indicates that the conditional aggregation operation is not satisfied, program control circuitry 111 may instruct instruction fetching circuitry 101 to fetch instruction 126 from memory 121. Alternatively, if the output of conditional aggregation circuitry 113 indicates that the conditional aggregation operation is satisfied, program control circuitry 111 may instruct instruction fetching circuitry 101 to fetch instruction 129 from memory 121.

[0049] Figure 3The implementation scheme describes operation sequence 300. Operation sequence 300 describes CBA procedure 200 regarding... Figure 1 The application of the components. Therefore, the operation sequence 300 includes register 115, register 116, memory 121, instruction fetch circuit system 101, decoder circuit system 103, arithmetic logic circuit system 107, program control circuit system 111 and condition aggregation circuit system 113.

[0050] First, instruction fetch circuitry 101 fetches an instruction from memory 121. For example, instruction fetch circuitry 101 may fetch instruction 123 from memory 121. Instruction 123 represents a first-order condition check, identifying a first comparison operation to be performed (i.e., OP1) and the memory location for performing the first comparison operation. Instruction fetch circuitry 101 provides instruction 123 to decoder circuitry 103. Decoder circuitry 103 decodes instruction 123 and provides the relevant memory locations (i.e., L1 and L2) for performing the first comparison operation to arithmetic logic circuitry 107.

[0051] Arithmetic logic circuit system 107 receives the relevant memory location and, in response, reads the values ​​stored at the relevant memory location (i.e., V1 and V2). Next, arithmetic logic circuit system 107 performs a first comparison operation. For example, arithmetic logic circuit system 107 may determine whether V1 is greater than, less than, or equal to V2. Once determined, program control circuit system 111 analyzes the output of arithmetic logic circuit system 107 to determine whether the result of the first comparison operation satisfies the first-order condition of instruction 123. If satisfied, program control circuit system 111 stores a true indicator (e.g., 1) in register 115; otherwise, program control circuit system 111 stores a false indicator (e.g., 0).

[0052] Instruction fetch circuitry 101 fetches the next instruction from memory 121. For example, instruction fetch circuitry 101 may fetch instruction 124 from memory 121. Instruction 124 represents another first-order condition check, identifying a second comparison operation to be performed (i.e., OP2) and the memory location for performing the second comparison operation. Instruction fetch circuitry 101 provides instruction 124 to decoder circuitry 103. Decoder circuitry 103 decodes instruction 124 and provides the relevant memory locations (i.e., L2 and L3) for performing the second comparison operation to arithmetic logic circuitry 107.

[0053] Arithmetic logic circuit system 107 receives the relevant memory location and, in response, reads the values ​​stored at the relevant memory location (i.e., V2 and V3). Next, arithmetic logic circuit system 107 performs a second comparison operation and outputs the result of the second comparison operation to program control circuit system 111. Program control circuit system 111 analyzes the output of arithmetic logic circuit system 107 to determine whether the result of the second comparison operation satisfies the first-order condition of instruction 124. If it does, program control circuit system 111 stores a true indicator (e.g., 1) in register 116; otherwise, program control circuit system 111 stores a false indicator (e.g., 0).

[0054] Instruction fetch circuitry 101 fetches the next instruction from memory 121. For example, instruction fetch circuitry 101 may fetch instruction 125 from memory 121. Instruction 125 represents a conditional branch instruction (CBI), which identifies a conditional aggregation operation (CAO) and multiple register locations for executing the CAO. In an embodiment, the CAO represents a hexadecimal value that defines the expected output of a first-order condition check. For example, the CAO may define that if the CBI is true, then the first comparison operation must be false and the second comparison operation must be true. Instruction fetch circuitry 101 provides instruction 125 to decoder circuitry 103. In response, decoder circuitry 103 decodes instruction 125 and provides the CAO and the relevant register locations for executing the CAO to conditional aggregation circuitry 113.

[0055] Conditional aggregation circuitry 113 receives the CAO and the location of the relevant register, and in response, reads the values ​​stored in the relevant registers (i.e., the outputs of OP1 and OP2). Next, conditional aggregation circuitry 113 determines whether the result of the first-order condition check satisfies the CAO of instruction 125. If the result of the first-order condition check satisfies the CAO, conditional aggregation circuitry 113 outputs a true indication; otherwise, it outputs a false indication. In an embodiment, conditional aggregation circuitry 113 outputs a single sign to indicate a true output and a zero sign to indicate a false output.

[0056] Finally, program control circuitry 111 evaluates the output of condition aggregation circuitry 113 and determines the next instruction to be executed. This may involve fetching the next instruction from memory 121. For example, if the output of condition aggregation circuitry 113 indicates a false output, program control circuitry 111 may cause instruction 126 to be executed. Alternatively, if the output of condition aggregation circuitry 113 indicates a true output, program control circuitry 111 may cause instruction 129 to be executed. In one embodiment, instruction fetching circuitry 101 receives the address of the next instruction to be executed from program control circuitry 111 and, in response, determines whether to fetch an instruction from memory 121. Instruction fetching circuitry 101 may fetch more than one instruction from memory 121 at a time. For example, instruction fetching circuitry 101 may fetch one or more instruction packets from memory 121.

[0057] Now please refer to the next image. Figure 4 The operating environment 400 in the implementation scheme is described. Operating environment 400 represents another instance of an operating environment configurable to execute program code such as conditional branch instructions. Operating environment 400 includes, but is not limited to, memory 401, program control circuitry 413, conditional aggregation circuitry 417, and registers 421. In some instances, the elements shown in operating environment 400 may be included within the processing system, such as a microcontroller unit (MCU) or a central processing unit (CPU). In some instances, some elements shown in operating environment 400 may be included outside the processing system.

[0058] Memory 401 refers to one or more volatile or non-volatile computer-readable storage media (e.g., random access memory, flash memory) that contain instructions, data, etc. For example, memory 401 contains instructions 403, 405, 407, 409, and 411. Memory 401 may be coupled to a circuitry configured to fetch instructions from memory 401 and provide those instructions to appropriate circuitry (e.g., instruction fetch circuitry 101). In embodiments, memory 401 represents... Figure 1 The memory 121.

[0059] Instructions 403, 405, 407, and 409 represent first-order condition checks, instructing the program control circuitry 413 to determine whether the first set of comparison operations is true or false. In an embodiment, instructions 403, 405, 407, and 409 can all be issued in parallel within a single instruction packet and executed in one execution cycle. When executed, instructions 403, 405, 407, and 409 instruct the program control circuitry 413 to determine how to compare data stored in a first memory location with data stored in a second memory location. Instructions 403, 405, 407, and 409 further instruct the program control circuitry 413 to output the result of each comparison operation to a specified destination register. For example, instruction 403 instructs the program control circuitry 413 to determine whether the data stored in register A13 is greater than the data stored in register A5 and outputs the comparison result to register TA0.

[0060] Instruction 411 indicates a second-order condition check, which instructs the condition aggregation circuit system 417 to perform a second set of comparison operations. More specifically, instruction 411 indicates a CBI, which identifies the condition aggregation operation and multiple register locations used to perform the condition aggregation operation. The multiple register locations of instruction 411 include registers storing the results of the first-order condition check. The condition aggregation operation is a hexadecimal value (i.e., "... The first-order condition check is defined as the expected output of the condition check. In this example, each bit position in the hexadecimal value represents a combination of first-order condition checks, functioning similarly to a LUT, and the bit value indicates the output of the corresponding combination of first-order condition checks. When executed, instruction 411 instructs condition aggregation circuitry 417 to determine how the result of the first-order condition check is compared with the condition aggregation operation. If the result of the first-order condition check satisfies the condition aggregation operation, condition aggregation circuitry 417 outputs a true indication (e.g., 1); otherwise, condition aggregation circuitry 417 outputs a false indication (e.g., 0).

[0061] Program control circuit system 413 represents one or more circuits (e.g., program control circuit system 111) configured to manage the execution of program code. Program control circuit system 413 further represents a circuit system configured to perform first-order condition checks. For example, program control circuit system 413 can execute instructions 403, 405, 407, and 409. In embodiments, the program control circuit system is coupled to an arithmetic logic unit (e.g., arithmetic logic circuit system 107) configured to perform arithmetic operations. For example, the arithmetic logic unit can perform comparison operations, and program control circuit system 413 can analyze the output of the arithmetic logic unit to determine whether a first-order condition has been met. Program control circuit system 413 includes program counter 415.

[0062] Program counter 415 represents a register that stores the memory location of the instruction currently being executed. For example, if program control circuitry 413 is currently executing instruction 407, then program counter 415 stores the address corresponding to the location in memory 401 where instruction 407 is stored.

[0063] Conditional aggregation circuit system 417 represents one or more circuits configured to execute conditional branch instructions. For example, conditional aggregation circuit system 417 may execute instruction 411 of memory 401. Conditional aggregation circuit system 417 may further represent a circuit system configured to perform conditional execution of a specified set of instruction packets. In embodiments, conditional aggregation circuit system 417 represents Figure 1 Conditional aggregation circuit system 113. Conditional aggregation circuit system 417 includes, but is not limited to, lookup table (LUT) circuit system 419.

[0064] LUT circuit system 419 represents a circuit system configured to determine whether the result of a first-order condition check satisfies the condition aggregation operation of a conditional branch instruction. For example, LUT circuit system 419 can determine whether the results of instructions 403, 405, 407, and 409 satisfy the condition aggregation operation of instruction 411. In an embodiment, LUT circuit system 419 outputs its determination result to program control circuit system 413. Program control circuit system 413 evaluates the output of LUT circuit system 419 to determine the next (one or more) instructions to be executed.

[0065] Register 421 represents a memory location storing data and / or instructions used during the execution of the program code. In the implementation, register 421 represents Figure 1 Registers 115 and 116. Register 421 includes, but is not limited to, data register 423 and status register 425.

[0066] Data register 423 may represent an addressing register, a fixed-point register, a floating-point register, or a combination thereof. Therefore, data register 423 may store addressing data, fixed-point data, floating-point data, or a combination of data types. In an embodiment, program control circuitry 413 performs a first-order condition check on the data stored in data register 423.

[0067] Status register 425 may represent an interrupt status register, a decoding stage status register, an execution stage status register, or a combination thereof. In an embodiment, status register 425 represents a register storing the result of a first-order condition check. For example, program control circuitry 413 may output the result of a first-order condition check to status register 425, and LUT circuitry 419 may analyze the data in status register 425 to make a decision. In an embodiment, status register 425 includes four separate registers for storing the result of a first-order condition check.

[0068] Figure 5A , 5B Sections 5C, 5D, and 5E illustrate the operational scenarios for executing program code in the implementation plan. More specifically, Figures 5A-5E Explanation about Figure 4 The element executes the stage sequence of conditional branch instructions. In the implementation scheme, Figure 5A The first operational phase is described. Figure 5B The second operational phase is described. Figure 5C The third operational phase is described. Figure 5D The fourth operational phase is described, and Figure 5E The fifth operational phase is described.

[0069] Now refer to Figure 5A Stage 500 represents the first operation stage. Stage 500 includes instruction 403, program control circuitry 413, and register 421. First, program control circuitry 413 receives instruction 403. In response, program control circuitry 413 identifies the relevant location within data register 423 for executing instruction 403. Once identified, program control circuitry 413 determines whether the data stored in register A13 is greater than the data stored in register A5. In an embodiment, an arithmetic logic unit (not shown) determines whether the data stored in register A13 is greater than the data stored in register A5 and outputs the result to program control circuitry 413. Since the data in register A13 is less than the data in register A5 (i.e., ...), ... Therefore, the program control circuit system 413 determines that the first comparison operation is false. Consequently, the program control circuit system 413 outputs zero to the status register (i.e., register TA0) corresponding to instruction 403.

[0070] Figure 5BStage 510, representing the second operation phase, is described. Stage 510 includes instruction 405, program control circuitry 413, and register 421. First, program control circuitry 413 receives instruction 405 and identifies the relevant location in data register 423 used to execute instruction 405. Once identified, program control circuitry 413 determines whether the data stored in register A4 is not equal to the data stored in register A10. Since the data in register A4 is not equal to the data in register A10 (i.e., ...), Therefore, the program control circuit system 413 determines that the second comparison operation is true. Consequently, the program control circuit system 413 outputs a '-' to register TA1.

[0071] Figure 5C Stage 520, representing the third operational phase, is described. Stage 520 includes instruction 407, program control circuitry 413, and register 421. First, program control circuitry 413 receives instruction 407 and identifies the relevant location in data register 423 used to execute instruction 407. Once identified, program control circuitry 413 determines whether the data stored in register A4 is equal to the data stored in register A5. Since the data in register A4 is equal to the data in register A5 (i.e., ...), ... Therefore, the program control circuit system 413 determines that the third comparison operation is true and outputs one to register TA2.

[0072] Figure 5D Stage 530, representing the fourth operation stage, is described. Stage 530 includes instruction 409, program control circuitry 413, and register 421. First, program control circuitry 413 receives instruction 409 and, in response, identifies the relevant location in data register 423 for executing instruction 409. Once identified, program control circuitry 413 determines whether the data stored in register A5 is less than the data stored in register A10. Since the data in register A5 is greater than the data in register A10 (i.e., ...), ... Therefore, the program control circuit system 413 determines that the fourth comparison operation is false and outputs zero to register TA3. Stages 500, 510, 520 and 530 can be executed in parallel, but for illustrative purposes, each stage has been described separately.

[0073] Figure 5EStage 540, representing the fifth operation stage, is described. Stage 540 includes instruction 411, conditional aggregation circuitry 417, status register 425, and lookup table (LUT) 430. LUT 430 represents the table specified by the conditional aggregation operation of instruction 411, which is used by LUT circuitry 419 to determine whether the results of instructions 403, 405, 407, and 409 satisfy the conditional aggregation operation. LUT 430 includes operation definition 431, register TA3 column 433, register TA2 column 435, register TA1 column 437, register TA0 column 439, and expected output column 441.

[0074] Operation definition 431 represents an alternative representation of the conditional aggregation operation in CBI. Therefore, operation definition 431 defines the expected output of the first-order conditional check. Figure 5E In the context of this operation, operation definition 431 defines register TA0 as storing zero, register TA1 as storing one, and one or both of registers TA2 and TA3 as storing one. In other words, operation definition 431 defines the first comparison operation as false, the second comparison operation as true, and at least one of the third and fourth comparison operations as true.

[0075] Register column 433 (TA3), column 435 (TA2), column 437 (TA1), and column 439 (TA0) represent columns that indicate each possible combination of inputs to the data stored in status register 425. Therefore, each register column's row represents a binary value, counted sequentially from zero to fifteen. For example, the first row of the register column corresponds to " ", and the last line corresponds to " ".

[0076] The expected output column 441 represents a column whose indicator register stores the result of the corresponding values ​​of the rows defined by the conditional aggregation operation of instruction 411. For example, rows 7, 11, and 15 of LUT 430 represent the results corresponding to the first-order condition " "", "and" The rows containing "", and in this instance, these combinations will produce the result "1". In the implementation, the data for the desired output column 441 is generated based on the conditional aggregation operation of instruction 411. For example, the conditional aggregation operation of instruction 411 can be represented by the following hexadecimal value:

[0077]

[0078] Therefore, the binary representation of conditional aggregation operations is:

[0079]

[0080] The binary representation also indicates that when writing from the most significant bit to the least significant bit, the expected output is the data in column 441.

[0081] In operation, conditional aggregation circuitry 417 receives instruction 411 and routes it to LUT circuitry 419. In response, LUT circuitry 419 determines whether the value stored in status register 425 corresponds to one of the possible combinations identified by desired output column 441. Upon determining that the value in status register 425 corresponds to the seventh row of LUT 430, LUT circuitry 419 outputs a true indication (e.g., 1). Program control circuitry 413 evaluates the output of LUT circuitry 419 and determines the next (one or more) instructions to be executed.

[0082] Figure 6 Example computer systems that can be used in various implementations are described. For example, computing system 601 represents a computing device capable of executing software consisting of program instructions having the conditional branching instructions described herein. Computing system 601 represents any system or set of systems that can employ the various operational architectures, processes, scenarios, and sequences for conditional branching described herein. Computing system 601 can be implemented as a single device, system, or apparatus, or it can be implemented as multiple devices, systems, or apparatuses in a distributed manner. Computing system 601 includes, but is not limited to, processing system 602, storage system 603, software 605, communication interface system 607, and user interface system 609 (optional). Processing system 602 is operatively coupled to storage system 603, communication interface system 607, and user interface system 609. Computing system 601 can represent a cloud computing device, a distributed computing device, etc.

[0083] Processing system 602 loads and executes software 605 from storage system 603, or alternatively, runs software 605 directly from storage system 603. Software 605 includes and implements conditional branch instructions (CBI) 606, which represent any conditional branch instructions (e.g., instructions 125 and 411) described in the foregoing figures. When executed by processing system 602, software 605 (including instructions 125 and 411) instructs processing system 602 to operate as described herein for at least the various processes, operating scenarios, and sequences described in the foregoing embodiments. Computing system 601 may optionally include additional means, features, or functions not described for brevity.

[0084] Still referencing Figure 6Processing system 602 may include a microprocessor and other circuitry that retrieves and executes software 605 from storage system 603. Processing system 602 may be implemented within a single processing unit, or it may be distributed among multiple processing units or subsystems that collaboratively execute program instructions. Examples of processing system 602 include general-purpose central processing units, graphics processing units, digital signal processing units, data processing units, dedicated processors and logic devices, and any other type of processing unit, combinations or variations thereof. Processing system 602 includes dedicated circuitry capable of performing CBI; examples of such circuitry include conditional aggregation circuitry 113, conditional aggregation circuitry 417, and LUT circuitry 419.

[0085] Storage system 603 may include any computer-readable storage medium that can be read and written by processing system 602 and is capable of storing software 605. Storage system 603 may include volatile and non-volatile media, removable and non-removable media, and variable and immutable media, implemented in any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, optical media, flash memory, virtual and non-virtual memory, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other suitable storage medium. In any case, computer-readable storage media is not for transmitting signals.

[0086] In addition to computer-readable storage media, in some embodiments, storage system 603 may also include computer-readable communication media that can be used to transmit at least some of the software 605 internally or externally. Storage system 603 may be implemented as a single storage device, but may also be implemented across multiple storage devices or subsystems located in the same location relative to each other or distributed among them. Storage system 603 may include additional elements, such as a controller, capable of communicating with processing system 602 or possibly other systems.

[0087] Software 605 (including CBI 606) can be implemented in program instructions and, among other functions, can instruct processing system 602 to operate as described herein with respect to the various operational scenarios, sequences, and procedures illustrated herein, when executed by processing system 602. For example, software 605 includes CBI for implementing conditional branching operations as described herein.

[0088] Specifically, program instructions may include various components or modules that cooperate or otherwise interact to perform the various processes and operational scenarios described herein. These components or modules may be embodied in compiled or interpreted instructions, or in some other variation or combination of instructions. These components or modules may be executed synchronously or asynchronously, serially or in parallel, in a single-threaded or multi-threaded environment, in a single-processor or multi-processor environment, in a single-host or multi-host environment, or in any other suitable execution paradigm, variation, or combination thereof. Software 605 may include additional processes, programs, or components, such as operating system software, virtualization software, or other application software. Software 605 may also include firmware or some other form of machine-readable processing instructions executable by processing system 602.

[0089] Generally, software 605, when loaded into and executed by processing system 602, can transform a suitable device, system, or apparatus (represented by computing system 601) from a general-purpose computing system into a dedicated computing system tailored to provide memory access as described herein. In practice, encoding software 605 on storage system 603 can transform the physical structure of storage system 603. In different embodiments of this specification, the specific transformation of the physical structure can depend on various factors. Examples of such factors may include, but are not limited to, the technology of the storage media used to implement storage system 603 and whether the computer storage media is characterized as a primary storage device or a secondary storage device, among other factors.

[0090] For example, if the computer-readable storage medium is implemented as a semiconductor-based memory, then software 605 can, when program instructions are encoded therein, transform the physical state of the semiconductor memory, for example, by changing the state of the transistors, capacitors, or other discrete circuit elements constituting the semiconductor memory. Similar transformations may occur relative to magnetic or optical media. Other transformations of the physical medium are possible without departing from the scope of this specification, wherein only the foregoing examples are provided to facilitate this description.

[0091] The communication interface system 607 may include communication connections and means that allow communication with other computing systems (not shown) via a communication network (not shown). Examples of connections and means that enable inter-system communication may include network interface cards, antennas, power amplifiers, radio frequency circuitry, transceivers, and other communication circuitry. The connections and means can communicate via a communication medium for exchanging communication content with other computing systems or system networks, such as metal, glass, air, or any other suitable communication medium. The aforementioned media, connections, and means are well-known and will not be described in detail here.

[0092] Communication between computing system 601 and other computing systems (not shown) can occur via a communication network and according to various communication protocols, combinations of protocols, or variations thereof. Examples include intranets, the Internet, the Internet, local area networks, wide area networks, wireless networks, wired networks, virtual networks, software-defined networks, data center buses and backplanes, or any other type of network, combination of networks, or variations thereof. The aforementioned communication networks and protocols are well known and need not be described in detail here.

[0093] As those skilled in the art will understand, aspects of this specification may be embodied as a system, method, or computer program product. Therefore, aspects of this specification may be in the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, and are generally referred to herein in the form of a “circuit,” “module,” or “system.” Furthermore, aspects of this specification may be in the form of a computer program product implemented on one or more computer-readable media having computer-readable program code embodied thereon.

[0094] In fact, the included descriptions and figures depict specific embodiments to teach those skilled in the art how to make and use the best mode. Some other aspects have been simplified or omitted for the purpose of teaching the principles of the invention. Those skilled in the art will understand from these embodiments variations that fall within the scope of this specification. Those skilled in the art will also understand that the features described above can be combined in various ways to form multiple embodiments. Therefore, this specification is not limited to the specific embodiments described above, but is limited only by the claims and their equivalents.

[0095] The above description and associated diagrams teach the preferred mode of the invention. The appended claims define the scope of the invention. It should be noted that some aspects of the preferred mode may not fall within the scope of the invention as defined by the claims. Those skilled in the art will appreciate that the features described above can be combined in various ways to form multiple variations of the invention. Therefore, the invention is not limited to the specific examples described above, but is limited only by the appended claims and their equivalents.

Claims

1. A system comprising: Instruction fetching circuitry; A decoder circuit system coupled to the instruction acquisition circuit system; as well as A conditional aggregation circuit system coupled to the decoder circuit system; The instruction acquisition circuit system is configured to: Fetch a conditional branch instruction from memory, wherein the conditional branch instruction identifies multiple register locations and a conditional aggregation operation, wherein the conditional aggregation operation includes multiple condition checks; and The conditional branch instruction is provided to the decoder circuit system; The decoder circuitry is configured such that the condition aggregation circuitry performs the multiple condition checks with respect to values ​​stored in the multiple register locations.

2. The system of claim 1, wherein the conditional aggregation circuitry is configured to perform the plurality of conditional checks with respect to the values ​​stored in the plurality of register locations, and wherein the conditional branching instruction includes an identifier defining the conditional aggregation operation of the plurality of conditional checks.

3. The system of claim 2, wherein the condition aggregation circuit system includes a lookup table (LUT) circuit system for performing the plurality of condition checks, wherein the input to the LUT circuit system includes the identifier of the condition aggregation operation and the value from the plurality of register locations, and wherein the output from the LUT circuit system includes the result of the plurality of condition checks.

4. The system of claim 3, wherein the values ​​stored in the plurality of register locations include the result of a first-order condition check, and wherein the plurality of condition checks performed by the LUT circuit system include a second-order condition check based on the result of the first-order condition check.

5. The system of claim 4, further comprising a program control circuit system, the program control circuit being configured to: Perform the first-order condition check; and Each result of the first-order condition check is stored in a different register location among the plurality of register locations.

6. The system of claim 4, wherein the second-order condition check includes a first condition check and a second condition check, and wherein the plurality of register locations includes a first register location and a second register location.

7. The system of claim 6, wherein the LUT circuit system is configured to: Determine whether the first result stored in the first register location satisfies the first condition check and whether the second result stored in the second register location satisfies the second condition check; If the first result does not meet the first condition check, a false indication is output; If the second result does not meet the second condition check, a false indication is output; and When the first result satisfies the first condition check and the second result satisfies the second condition check, output a true indication.

8. The system of claim 2, wherein the identifier of the conditional aggregation operation comprises a hexadecimal value.

9. A computing device comprising: Memory devices; as well as One or more processors operably coupled to the memory device; The one or more processors are configured to at least: A conditional branch instruction is fetched from the memory device, wherein the conditional branch instruction identifies multiple register locations and a conditional aggregation operation, wherein the conditional aggregation operation includes multiple condition checks; and Perform the multiple condition checks on the values ​​stored in the multiple register locations.

10. The computing device of claim 9, wherein the conditional branch instruction includes an identifier defining the conditional aggregation operation of the plurality of condition checks, and wherein the identifier of the conditional aggregation operation includes a hexadecimal value.

11. The computing device of claim 10, wherein, in order to perform the plurality of condition checks, the one or more processors are further configured to: Receive input, wherein the input includes the identifier of the conditional aggregation operation and the value from the plurality of register locations; and Generate output, wherein the output includes the results of the multiple condition checks.

12. The computing device of claim 11, wherein the values ​​stored in the plurality of register locations include the result of a first-order condition check, and wherein the plurality of condition checks performed by the one or more processors include a second-order condition check based on the result of the first-order condition check.

13. The computing device of claim 12, wherein the one or more processors are further configured to: Perform the first-order condition check; and Each result of the first-order condition check is stored in a different register location among the plurality of register locations.

14. The computing device of claim 12, wherein the second-order condition check includes a first condition check and a second condition check, and wherein the plurality of register locations includes a first register location and a second register location.

15. The computing device of claim 14, wherein the one or more processors are further configured to: Determine whether the first result stored in the first register location satisfies the first condition check and whether the second result stored in the second register location satisfies the second condition check; If the first result does not meet the first condition check, a false indication is output; If the second result does not meet the second condition check, a false indication is output; and When the first result satisfies the first condition check and the second result satisfies the second condition check, output a true indication.

16. One or more computer-readable storage media, comprising: The program instructions stored thereon include conditional branch instructions that identify multiple register locations and conditional aggregation operations, wherein the conditional aggregation operations include multiple condition checks, and wherein the conditional branch instructions instruct the processing circuitry system to: Perform the multiple condition checks on the values ​​stored in the multiple register locations.

17. The computer-readable storage medium of claim 16, wherein the conditional branching instruction includes an identifier defining the conditional aggregation operation of the plurality of condition checks, and wherein the identifier of the conditional aggregation operation includes a hexadecimal value.

18. The computer-readable storage medium of claim 16, wherein the value stored in the plurality of register locations includes the result of a first-order condition check, and wherein the plurality of condition checks performed by the processing circuitry system include a second-order condition check based on the result of the first-order condition check.

19. The computer-readable storage medium of claim 18, wherein the program instructions further instruct the processing circuitry system: Perform the first-order condition check; and Each result of the first-order condition check is stored in a different register location among the plurality of register locations.

20. The computer-readable storage medium of claim 18, wherein the second-order condition check includes a first condition check and a second condition check, and The plurality of register locations includes a first register location and a second register location, and the program instructions further instruct the processing circuitry: Determine whether the first result stored in the first register location satisfies the first condition check and whether the second result stored in the second register location satisfies the second condition check; If the first result does not meet the first condition check, a false indication is output; If the second result does not meet the second condition check, a false indication is output; and When the first result satisfies the first condition check and the second result satisfies the second condition check, output a true indication.

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