High-efficiency transmission system of USB2.0 controller based on DMA module

Abstract

The application discloses a kind of based on DMA module's USB2.0 controller high-efficiency transmission system, and integration DMA module in USB controller allows data to be directly transmitted between memory and peripheral, avoids CPU to participate in each data transmission operation, to improve data transmission efficiency.Integration DMA module, USB controller can directly access memory in data transmission process, reduce CPU intervention, to significantly improve data transmission rate, reduce system delay, reduce CPU burden, and optimize overall system performance.Therefore, the application solves the performance bottleneck problem of USB controller in prior art in high data volume transmission and multitasking processing.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and in particular to a high-efficiency transmission system for a USB 2.0 controller based on a DMA module. Background Technology

[0002] USB (Universal Serial Bus) interfaces are widely used in computers, embedded devices, and various electronic products for connecting external devices and transmitting data. Existing USB controllers typically rely on the CPU for data transmission control, requiring the CPU to intervene in each data transfer process, such as reading data and writing to memory. With the increasing demands for data transmission, traditional USB controllers often face bandwidth bottlenecks and excessive CPU load when handling large data volumes and high-speed transmissions, thus affecting device performance and response speed.

[0003] To optimize data transfer efficiency and reduce CPU load, an increasing number of USB controllers are integrating DMA (Direct Memory Access) modules. DMA modules can directly transfer data between memory and peripherals without CPU intervention. However, existing USB controller designs still have limitations in leveraging DMA modules to improve performance, especially when handling complex data streams and multi-task parallel transfers. Efficiently implementing DMA scheduling and data stream management remains a technical challenge. For example, the PHILIPS LPC2800 series microcontrollers integrate a DMA engine in their USB 2.0 high-speed device controller, but this engine only has four channels and is only responsible for data transfer. While the DMA engine in the XILINX Zynq-7000 series USB controller can handle different data structures in master and slave modes, transaction transfer efficiency and dynamic resource adjustment are not addressed. Summary of the Invention

[0004] This invention provides a high-efficiency transmission system for a USB 2.0 controller based on a DMA module, involving performance optimization technology for USB controllers, and in particular a method to improve the data transmission efficiency and system performance of a USB controller by integrating a DMA (Direct Memory Access) module, solving the performance bottleneck problem of USB controllers in high data volume transmission and multi-task processing in the prior art.

[0005] This invention provides a high-efficiency transmission system for a USB 2.0 controller based on a DMA module, comprising:

[0006] The UTM synchronization module is used to resynchronize the 60MHz clock domain of the transceiver unit with the system clock CLK of the USB 2.0 controller. The system clock CLK drives the other modules of the USB 2.0 controller, except for the transceiver unit and the UTM synchronization module, to the CPU interface.

[0007] The data packet encoding and decoding module is used to generate headers for data packets to be transmitted and to decode the headers of received data packets.

[0008] The endpoint control module consists of two controller state machines: one for control transmission on endpoint 0 and the other for batch / interrupt / isochronous transmission on endpoints 1 to 15.

[0009] The RAM controller provides an interface to a single synchronous single-port RAM block. The RAM block buffers data packets between the CPU and the USB controller, obtains a first-in-first-out queue pointer from the endpoint control module, translates it into an address pointer within the RAM block, and generates RAM access control signals.

[0010] A multi-channel direct memory access controller for loading and unloading endpoint first-in-first-out queues.

[0011] Optionally, in one embodiment of the present invention, the UTM synchronization module is further configured to perform a high-speed detection handshake and process host negotiation protocol and session request protocol in point-to-point communication with other USB controller devices.

[0012] Optionally, in one embodiment of the present invention, the data packet encoding and decoding module is further configured to generate a cyclic redundancy check code for the data packet to be transmitted, and check the cyclic redundancy check code of the received data packet.

[0013] Optionally, in one embodiment of the invention, the CPU interface allows access to the control / status registers and first-in-first-out queues of each endpoint to generate interrupts to the CPU when a data packet is successfully transmitted or received, and when the core enters or resumes from suspend mode.

[0014] Optionally, in one embodiment of the present invention, when multiple data transmission tasks are performed in parallel, the multi-channel direct memory access controller schedules the tasks according to priority.

[0015] Optionally, in one embodiment of the present invention, the multi-channel direct memory access controller is configured with eight channels, each channel being independently configured and performing different tasks.

[0016] The USB 2.0 controller high-efficiency transmission system based on the DMA module in this embodiment of the invention integrates the DMA module, enabling the USB controller to directly access memory during data transmission, reducing CPU intervention, thereby significantly improving data transmission rate, reducing system latency, alleviating CPU burden, and optimizing overall system performance.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 This is a schematic diagram of a high-efficiency transmission system for a USB 2.0 controller based on a DMA module, according to an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the DMA module structure according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of data flow management and scheduling of the DMA module in an embodiment of the present invention. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0023] Figure 1 This is a schematic diagram of a high-efficiency transmission system for a USB 2.0 controller based on a DMA module, according to an embodiment of the present invention.

[0024] like Figure 1 As shown, this high-efficiency transmission system for a USB 2.0 controller based on a DMA module includes:

[0025] The UTM synchronization module is used to resynchronize the 60MHz clock domain of the transceiver unit with the system clock CLK of the USB 2.0 controller. The system clock CLK drives the other modules of the USB 2.0 controller, except for the transceiver unit and the UTM synchronization module, to the CPU interface.

[0026] The data packet encoding and decoding module is used to generate headers for data packets to be transmitted and to decode the headers of received data packets.

[0027] The endpoint control module consists of two controller state machines: one for control transmission on endpoint 0 and the other for batch / interrupt / isochronous transmission on endpoints 1 to 15.

[0028] The RAM controller provides an interface to a single synchronous single-port RAM block. The RAM block buffers data packets between the CPU and the USB controller, obtains a first-in-first-out queue pointer from the endpoint control module, translates it into an address pointer within the RAM block, and generates RAM access control signals.

[0029] A multi-channel direct memory access controller for loading and unloading endpoint first-in-first-out queues.

[0030] In an embodiment of the present invention, the USB controller is a USB 2.0 controller.

[0031] The UTM synchronization module resynchronizes the transceiver unit's 60MHz clock domain with the dual-role controller's system clock CLK, which drives the rest of the core up to the CPU interface. This allows the rest of the controller to operate at CPU bus speed without further synchronization. The module also performs high-speed detection handshakes and handles HNP (Host Negotiation Protocol) and SRP (Session Request Protocol) in point-to-point communication with other USB OTG devices.

[0032] The packet encoding / decoding module generates headers for packets to be transmitted and decodes the headers of received packets. It also generates a CRC (Cyclic Redundancy Check) for packets to be transmitted and checks the CRC of received packets.

[0033] The endpoint control module uses two controller state machines: one for control transfers on endpoint 0, and the other for batch / interrupt / isochronous transfers on endpoints 1 to 15.

[0034] The RAM controller provides an interface to a single, synchronous, single-port RAM block used to buffer data packets between the CPU and USB. It obtains FIFO pointers from the endpoint controller, translates them into address pointers within the RAM block, and generates RAM access control signals.

[0035] The CPU interface allows access to the control / status registers and FIFO (First-In-First-Out queue) of each endpoint. It also generates interrupts for the CPU when a data packet is successfully transmitted or received, and when the core enters or resumes from suspend mode.

[0036] A multi-channel DMA (Direct Memory Access) controller for efficient loading / unloading of endpoint FIFOs. This DMA controller can be configured with up to 8 channels, such as... Figure 2 As shown.

[0037] DMA data stream management and scheduling, such as Figure 3 The flowchart is shown.

[0038] Priority scheduling:

[0039] When multiple data transfer tasks are performed concurrently, DMA scheduling can prioritize these tasks based on their priorities. For example, some tasks may have higher real-time requirements and need to be completed first. DMA can dynamically adjust the data transfer order based on task priorities.

[0040] Bandwidth allocation:

[0041] For different USB devices, DMA can allocate bandwidth reasonably according to the device's bandwidth requirements. For large data transfer tasks (such as external hard drives), DMA can allocate more bandwidth; for small data transfers (such as USB keyboards), less bandwidth can be allocated.

[0042] Dynamic resource management:

[0043] When system resources are limited, DMA can dynamically adjust resource allocation. For example, when memory resources are scarce, DMA can temporarily pause some low-priority data transfer tasks to free up resources for high-priority tasks, ensuring stable system operation.

[0044] Transmission rate adaptation:

[0045] DMA can dynamically adjust the transfer rate to meet different transfer rate requirements. For example, DMA can use a higher transfer rate for large file transfers, while it can adapt to a lower transfer rate for small file transfers to reduce system load.

[0046] DMA multi-task parallel data processing.

[0047] Multiple DMA channels:

[0048] Each channel can be configured independently and perform different tasks. In this way, multiple data streams can be processed in parallel, with each DMA channel focusing on a specific task. For example, one DMA channel might be responsible for reading data from a USB device. Another DMA channel might handle transferring data from memory to a USB device. Yet another DMA channel might be responsible for control transfers to different USB endpoints.

[0049] Parallelism in data transmission:

[0050] Each DMA channel can transfer data independently without waiting for other channels to complete. This parallelism allows DMA to efficiently manage multiple data streams, significantly improving data throughput. For example, a USB controller may communicate with multiple devices simultaneously, and DMA can transfer data from different devices to main memory in parallel, or send data from memory to multiple devices simultaneously.

[0051] The high-efficiency data transfer system for a USB 2.0 controller based on a DMA module proposed in this invention integrates a DMA module into the USB controller, allowing direct data transfer between memory and peripherals. This avoids CPU involvement in every data transfer operation, thereby improving data transfer efficiency. DMA data stream management: Through efficient data stream management and scheduling algorithms, the operation of the DMA module is optimized, ensuring that the USB controller can handle multiple data transfer tasks efficiently in real time, reducing data conflicts and bandwidth contention. Multi-task parallel processing: With multi-channel DMA support, the USB controller can process multiple data streams simultaneously, supporting the parallel operation of multiple USB devices, further improving system throughput and response speed.

[0052] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A high-efficiency transmission system for a USB 2.0 controller based on a DMA module, characterized in that, include: The UTM synchronization module is used to resynchronize the 60MHz clock domain of the transceiver unit with the system clock CLK of the USB 2.0 controller. The system clock CLK drives the other modules of the USB 2.0 controller, excluding the transceiver unit and the UTM synchronization module. The other modules include the packet encoding and decoding module, the endpoint control module, the RAM controller, and the multichannel direct memory access controller (DMA). The data packet encoding and decoding module is used to generate a header for the data packet to be transmitted and to decode the header of the received data packet. The endpoint control module consists of two controller state machines: one for control transmission on endpoint 0 and the other for batch, interrupt, or isochronous transmission on endpoints 1 to 15. The RAM controller is used to provide an interface to connect to a single synchronous single-port RAM block. The RAM block is used to buffer data packets between the CPU and the USB controller, obtain a first-in-first-out queue pointer from the endpoint control module, convert it into an address pointer within the RAM block, and generate RAM access control signals. The multichannel direct memory access controller (DMA) is used to load and unload endpoint first-in-first-out queues. DMA data stream management and scheduling includes: Priority scheduling: When multiple data transfer tasks are performed in parallel, DMA schedulers schedule tasks according to task priorities; Bandwidth allocation: For different USB devices, DMA allocates bandwidth reasonably according to the device's bandwidth requirements; Dynamic resource management: When system resources are limited, DMA dynamically adjusts resource allocation. When memory resources are scarce, DMA temporarily suspends low-priority data transfer tasks and allocates resources to high-priority tasks. Transmission rate adaptation: DMA dynamically adjusts the transmission rate to meet different transmission rate requirements.

2. The system according to claim 1, characterized in that, The UTM synchronization module is also used to perform high-speed detection handshakes and process host negotiation protocols and session request protocols in point-to-point communication with other USB controller devices.

3. The system according to claim 1, characterized in that, The data packet encoding and decoding module is also used to generate a cyclic redundancy check code for the data packet to be transmitted, and to check the cyclic redundancy check code of the received data packet.

4. The system according to claim 1, characterized in that, The CPU interface allows access to the control / status registers and first-in-first-out queues of each endpoint, generating interrupts to the CPU when packets are successfully transmitted or received, and when the core enters or resumes from suspend mode.

5. The system according to claim 1, characterized in that, When multiple data transfer tasks are performed in parallel, the multichannel direct memory access controller schedules the tasks according to priority.

6. The system according to claim 1, characterized in that, The multichannel direct memory access controller is configured with 8 channels, each of which is configured independently and performs different tasks.

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