An Implementation Method of SpMV Based on Adaptive Strategy on a CPU-DCU Heterogeneous Platform

Abstract

This invention belongs to the field of high-performance parallel computing, specifically relating to a method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, aiming to improve the efficiency of SpMV computation. The method includes acquiring sparse matrix data at the CPU, converting the sparse matrix data into CSR format to obtain a CSR format array. Based on the CSR format array, adaptive decomposition is performed on the sparse matrix represented by it to obtain dense blocks and sparse blocks. An RDCSR format array is constructed based on the CSR format array; the RDCSR format array contains the CSR format array, an array recording the row indices of the dense blocks, and an array recording the row indices of the sparse blocks. The RDCSR format array is transmitted to the DCU, where, after adaptive thread allocation for the dense and sparse blocks at the DCU, SpMV computation is performed in parallel to obtain a merged computation result. The merged computation result is transmitted from the DCU to the CPU, and the computational performance of SpMV is evaluated.

Description

Technical Field

[0001] This invention relates to the field of high-performance parallel computing, and in particular to a method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform. Background Technology

[0002] Sparse matrix-vector multiplication (SpMV) is a core operation in scientific computing, numerical analysis, engineering simulation, and other fields. Its computational efficiency directly affects the overall performance of large-scale data processing and complex problem solving. With the explosive growth of data scale and the continuous increase in computing demands, a single processor can no longer meet the needs of high-efficiency computing. The CPU-DCU heterogeneous platform, with the logic control capability of the CPU and the parallel computing advantage of the DCU, has become an important hardware architecture to support high-performance SpMV operations.

[0003] Traditional SpMV implementation methods generally adopt a unified matrix storage format (such as CSR format) and a static thread scheduling strategy. However, existing methods cannot effectively distinguish the differences in density and sparsity in local regions of the matrix, resulting in unreasonable allocation of storage and computing resources. At the same time, it is difficult to adapt to the different computing needs of dense and sparse blocks, which can easily lead to thread idleness or uneven load, severely restricting the computing potential of CPU-DCU heterogeneous platforms. Summary of the Invention

[0004] The purpose of this invention is to provide an implementation method of SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, aiming to improve the computational efficiency of SpMV and solve the problem of limited computational performance caused by insufficient matrix structure adaptation and inflexible thread resource allocation in traditional methods.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This invention provides a method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, comprising: S1: acquiring sparse matrix data at the CPU end, converting the sparse matrix data into CSR format, and obtaining a CSR format array; S2: performing adaptive decomposition on the sparse matrix represented by the CSR format array to obtain dense blocks and sparse blocks, and constructing an RDCSR format array based on the CSR format array; the RDCSR format array includes the CSR format array, an array recording the row indices of the dense blocks, and an array recording the row indices of the sparse blocks; S3: transmitting the RDCSR format array to the DCU, performing adaptive thread allocation on the dense blocks and sparse blocks at the DCU end, and performing SpMV calculation in parallel to obtain the merged calculation result; S4: transmitting the merged calculation result from the DCU to the CPU, and evaluating the calculation performance of SpMV.

[0007] In step S1, the CPU receives sparse matrix data stored in mtx file format; extracts basic information such as the number of rows, columns, and total number of non-zero elements of the sparse matrix; converts the sparse matrix into CSR format to obtain a CSR format array containing arrays of non-zero values, arrays of column positions, and arrays of row offsets.

[0008] In step S2, the adaptive decomposition of the sparse matrix specifically includes: shifting the non-zero elements of each row of the sparse matrix to the left and counting the number of non-zero elements in each row; using the number of threads contained in the DCU thread bundle as the partitioning threshold, dividing the non-zero elements in each row that are integer multiples of the threshold into dense blocks, and dividing the remaining non-zero elements into sparse blocks.

[0009] In step S2, a dense block row index array and a sparse block row index array are constructed to record the row indices corresponding to the dense blocks and sparse blocks, respectively; the CSR format array is merged with the dense block row index array and the sparse block row index array to form an RDCSR format array.

[0010] In step S3, based on the dense block row index array, a thread bundle is allocated to each row of the dense block, and the threads in the thread bundle correspond one-to-one with the non-zero elements of the dense block.

[0011] In step S3, adaptive thread allocation for sparse blocks specifically includes: calculating the number of threads required for each row of the sparse block based on the row index array of the sparse block and the total number of non-zero elements in the sparse block; and allocating the corresponding number of threads to each row of the sparse block according to the calculated number of threads.

[0012] In step S3, performing SpMV calculation specifically includes: threads within a thread bundle performing multiply-add operations on the non-zero elements of the dense block in parallel, reducing to obtain the dense block calculation result; threads assigned to the sparse block performing multiply-add operations on the non-zero elements of the sparse block in parallel, reducing to obtain the sparse block calculation result; merging the dense block calculation result and the sparse block calculation result and writing them into the DCU global memory.

[0013] In step S4, the merged calculation results in the DCU global memory are transferred to the CPU to complete the calculation process of SpMV.

[0014] The performance evaluation in step S4 specifically includes: using runtime as the evaluation metric, comparing and evaluating the computational performance of SpMV with that of traditional CSR format implementation methods.

[0015] The partitioning threshold is determined by using the number of threads contained in a thread bundle in the DCU as the partitioning threshold, which is used to distinguish the non-zero element limit between dense blocks and sparse blocks.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] 1. This application provides an implementation method of SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform. By adaptively decomposing a sparse matrix into dense and sparse blocks, it can accurately adapt to the local structural characteristics of the matrix. This decomposition method breaks through the limitations of the traditional unified processing mode, allowing subsequent calculations to adopt differentiated strategies based on the sparsity differences between the two types of blocks, avoiding resource waste caused by overall unified processing. The RDCSR format, built based on the CSR format extension, achieves explicit recording and fast location of the two types of block data by adding row index arrays for dense and sparse blocks. This format retains the compact storage advantages of the CSR format for sparse data, and can directly provide structured data basis for DCU-side computation scheduling, reducing the additional overhead of data parsing and improving data access efficiency.

[0018] 2. For dense blocks, a thread bundle is allocated to each row, achieving a one-to-one mapping between threads and non-zero elements. This fully leverages the parallel processing capability of the DCU thread bundles, ensuring saturated utilization of computational resources in dense regions. For sparse blocks, threads are dynamically allocated based on the number of non-zero elements, avoiding thread idleness issues caused by fixed thread allocation and achieving balanced scheduling of computational load in sparse regions. The synergistic thread allocation strategies of the two types of blocks significantly improve the utilization rate of DCU computational resources. Through the collaborative design of matrix adaptive decomposition, RDCSR format optimization, and thread adaptive allocation, the efficiency bottleneck caused by insufficient structural adaptation and inflexible resource allocation in traditional SpMV methods on heterogeneous platforms is effectively solved. Experimental verification shows that compared with traditional implementations such as hipSPARSE and CSR_scalar, this method can significantly shorten the runtime of SpMV computation, fully unleash the computational potential of CPU-DCU heterogeneous platforms, and provide an efficient solution for large-scale sparse matrix operations. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating an implementation method of SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, as provided in an embodiment of this application.

[0020] Figure 2 This is a strategy diagram for adaptive matrix decomposition provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of an RDCSR storage format provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of a SpMV calculation process provided in an embodiment of this application;

[0023] Figure 5 This is a schematic diagram of a parallel algorithm for dense block SpMV provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of a sparse block SpMV parallel algorithm provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram illustrating the basic information of a SuiteSparse matrix library provided in an embodiment of this application;

[0026] Figure 8 This is a performance evaluation experiment result diagram provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0028] Before explaining the implementation method of SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform provided in the embodiments of this application, the English terms mentioned in this application are explained as follows:

[0029] SpMV stands for Sparse Matrix-Vector Multiplication, a core operation in fields such as scientific computing, referring to the multiplication of sparse matrices and vectors.

[0030] CPU: Central Processing Unit, is the core component of a computer, responsible for data processing and logic control. In this application, as part of a heterogeneous platform, it is responsible for preprocessing and receiving computation results.

[0031] DPU: Data Processing Unit, which serves as the core component for parallel computing in this application's heterogeneous platform, possesses strong parallel computing capabilities.

[0032] CSR, or Compressed Sparse Row, is a commonly used sparse matrix storage format that compresses and stores sparse matrices using arrays of non-zero values, column positions, and row offsets.

[0033] RDCSR, or Row Decomposition Compressed Spare Row, is an extended format constructed in this application that adds dense and sparse block row index arrays to CSR.

[0034] This application provides an implementation method for an adaptive strategy SpMV on a CPU-DCU heterogeneous platform, exemplified by, for example... Figure 1 As shown. The method includes:

[0035] S1: Obtain sparse matrix data on the CPU side, convert the sparse matrix data into CSR format, and obtain a CSR format array.

[0036] More specifically, in step S1, the CPU receives sparse matrix data stored in mtx file format; extracts basic information such as the number of rows m, the number of columns n, and the total number of non-zero elements nnz of the sparse matrix; converts the sparse matrix into CSR format to obtain a CSR format array containing a non-zero value array data array, a column position array col index array, and a row offset array row pointer array.

[0037] S2: Based on the CSR format array, adaptively decompose the sparse matrix represented by it to obtain dense blocks and sparse blocks, and construct an RDCSR format array based on the CSR format array. The RDCSR format array contains the CSR format array, an array recording the row indices of the dense blocks, and an array recording the row indices of the sparse blocks.

[0038] For example, refer to Figure 2 In step S2, the adaptive decomposition of the sparse matrix specifically includes:

[0039] S21: Shift the non-zero elements of each row of the sparse matrix to the left and count the number of non-zero elements in each row.

[0040] First, shift the non-zero elements of each row of the matrix to the left. Then, iterate through the row pointer array of the sparse matrix and use the differences between adjacent elements to calculate the row pointers for each row of the sparse matrix. Number of non-zero elements . The specific calculation formula is as follows:

[0041]

[0042] in, This is a row offset array for a sparse matrix.

[0043] S22: Using the number of threads contained in the DCU thread bundle as the partitioning threshold, divide the non-zero elements in each row whose number is an integer multiple of the threshold into dense blocks, and divide the remaining non-zero elements into sparse blocks.

[0044] As one possible implementation, the partitioning threshold is determined by using the number of threads contained in a thread bundle in the DCU as the partitioning threshold to distinguish the number of non-zero elements in dense blocks and sparse blocks.

[0045] For example, the number of threads contained in the DCU thread bundle is used as the partitioning threshold. ,Right now Based on the number of non-zero elements in a row. With the dividing threshold Adaptive decomposition is performed on each row of the matrix. For each row, the first non-zero elements (multiples of k) are placed into a dense block, and the remaining non-zero elements (the remainder after subtracting multiples of k from the total number of non-zero elements) are placed into a sparse block. If the number of non-zero elements in the current row is... for Integer multiples of, i.e. If the number of non-zero elements in the current row satisfies the condition, then the entire row is divided into dense blocks. If the number of non-zero elements in the current row is [value missing], then the entire row is divided into sparse blocks. And not for Integer multiples of, i.e. Then the line before Each element is divided into a dense block, and the remaining elements are... Each element is assigned to a sparse block.

[0046] In step S2, a dense block row index array and a sparse block row index array are constructed, and the row indices corresponding to the dense blocks and sparse blocks are recorded respectively. The CSR format array is merged with the dense block row index array and the sparse block row index array to form an RDCSR format array.

[0047] For example, after completing the matrix decomposition, construct a dense block row index array and a sparse block row index array, respectively recording the row indices corresponding to the dense block and the sparse block, and simultaneously calculate the lengths of the two arrays, with the length of the dense block row index array being L1 and the length of the sparse block row index array being L2.

[0048] For example, such as Figure 3 As shown, the RDCSR format array is composed of the original CSR format array, the dense block row index array dense_indices, and the sparse block row index array sparse_indices.

[0049] S3: Transmit the RDCSR format array to the DCU. After adaptive thread allocation for dense and sparse blocks at the DCU, perform SpMV calculation in parallel to obtain the merged calculation result.

[0050] Specifically, transferring the RDCSR format array to the DCU includes transferring the row offset array, column index array, non-zero value array, dense block row index array, and sparse block row index array constructed in step S3 to the DCU.

[0051] In step S3, based on the dense block row index array, a thread bundle is allocated to each row of the dense block, and the threads in the thread bundle correspond one-to-one with the non-zero elements of the dense block.

[0052] For example, in a DCU, a thread bundle contains 64 threads. For dense blocks where the number of non-zero elements is a multiple of 64, one thread bundle is allocated to each row, implementing a one-to-one mapping between threads and non-zero elements, thereby enabling full-load parallel processing of that row and avoiding thread idleness. This depends on the thread block size. Calculate the number of thread blocks in the dense block section. , The specific calculation formula is as follows:

[0053]

[0054] in Indicates the thread bundle size. The number of rows in the dense block. The number of threads that can be accommodated in each thread block.

[0055] In step S3, adaptive thread allocation for sparse blocks specifically includes: calculating the number of threads required for each row of the sparse block based on the row index array of the sparse block and the total number of non-zero elements in the sparse block; and allocating the corresponding number of threads to each row of the sparse block according to the calculated number of threads.

[0056] For sparse blocks, the adaptive thread count is calculated according to the formula. Assign each row of the sparse block There are 10 threads, each performing the multiplication and addition operation in parallel at its corresponding position. (Number of threads per line) The calculation formula is as follows:

[0057]

[0058] in, The number of rows in the dense block. The number of rows in the sparse block. The total number of non-zero elements in the matrix.

[0059] in accordance with and The size of the sparse block is used to calculate the number of thread blocks in the sparse block portion. , The calculation formula is as follows: ;

[0060] in The number of threads allocated to each line of the sparse block. The number of rows in the sparse block.

[0061] For example, such as Figure 4 In step S3, the SpMV calculation specifically includes: threads within a thread bundle performing multiplication and addition operations on the non-zero elements of the dense block in parallel, and reducing to obtain the dense block calculation result; threads allocated to the sparse block performing multiplication and addition operations on the non-zero elements of the sparse block in parallel, and reducing to obtain the sparse block calculation result; merging the dense block calculation result and the sparse block calculation result and writing them into the DCU global memory.

[0062] For the computation of dense block SpMV, each thread obtains the row number to be processed from the dense block row index array dense_indices. Then, obtain the row start from the row_pointer_array array, based on the number of non-zero elements in the current row. Adjust the ending position This is to ensure that the number of elements is a multiple of 64. The calculation formula is as follows:

[0063] in The row index calculated for the current thread. It is a row offset array. The number of non-zero elements in the current row.

[0064] Within a thread bundle, 64 threads read data in parallel and execute corresponding multiply-accumulate operations with a step size of 64. After calculation, the intermediate product results are reduced using a shuffle instruction and integrated into the sum of products for that row of dense blocks. The parallel algorithm for dense block SpMV is as follows: Figure 5 As shown.

[0065] For the computation of sparse block SpMV, the global thread ID is calculated using blockIdx and threadIdx, and then mapped to sparse_indices to obtain the row index. Get the starting position of the current row from the row_pointer_array array. And based on the number of non-zero elements in that row Adjust the starting position This ensures that the remaining elements are processed. The adjustment calculation formula is as follows:

[0066]

[0067] in The row index calculated for the current thread. It is a row offset array. The number of non-zero elements in the current row. TpR threads read data in parallel and perform corresponding multiply-accumulate operations with a step size of TpR. After the calculation is completed, the intermediate product results of each thread are reduced by the shuffle instruction and integrated into the sum of the products of the sparse blocks in the row.

[0068] For example, the sparse block SpMV parallel algorithm is as follows: Figure 6 As shown, the first thread in each row performs an atomic operation to accumulate the two results and write them into the DCU global memory to complete the merging.

[0069] S4: Transfer the merged calculation results from the DCU to the CPU and evaluate the computational performance of SpMV.

[0070] The performance evaluation in step S4 specifically includes: using runtime as the evaluation metric, comparing and evaluating the computational performance of SpMV with that of traditional CSR format implementation methods.

[0071] To verify the actual effectiveness of the method provided in this application's embodiments, this application also compares it with traditional CSR format methods such as hipSPARSE, CSR_scalar, CSR_vector, and light_spmv, using runtime as the performance metric. Testing was conducted on the Sugon supercomputing platform, which uses Linux 3.1.0 as the operating system, ROCM heterogeneous programming version 4.0 as the rocm heterogeneous programming version, gcc / g++ 7.3.1 as the CPU compiler, and hipcc-24.04.0 as the DCU accelerator compiler. This system is equipped with a Hygon 7185 CPU processor and a Hygon DC1000 accelerator. The Hygon 7185 CPU adopts an x86 architecture, has 32 cores, and possesses high computing power, memory access performance, and I / O expansion capabilities.

[0072] To comprehensively evaluate the performance of the method of this invention, several typical sparse matrices from the SuiteSparse matrix library were selected as test objects, and their basic information is as follows: Figure 7 As shown in the figure. The performance evaluation results obtained from the experiment are shown in the figure below. Figure 8 As shown, the SpMV implementation method based on adaptive strategy proposed in this invention outperforms existing methods in terms of running efficiency on multiple sparse matrices. Compared with traditional CSR format implementation methods such as hipSPARSE, CSR_scalar, CSR_vector, and light_spmv, this method significantly shortens the execution time of sparse matrix-vector multiplication, verifying its high efficiency on CPU-DCU heterogeneous platforms.

[0073] The method provided in this application mainly comprises two stages: a CPU preprocessing stage and a DCU parallel computing stage. The CPU preprocessing stage employs an adaptive matrix factorization strategy to divide the sparse matrix into dense and sparse blocks, and establishes an RDCSR storage structure to explicitly record the data in the dense and sparse blocks. The DCU parallel computing stage employs an adaptive thread allocation strategy, using a thread bundle-level parallel scheduling method for dense blocks and a thread-level parallel scheduling method for sparse blocks, adaptively allocating thread resources based on the number of non-zero elements. By allowing dense and sparse blocks to perform SpMV computation in parallel, the computational efficiency of SpMV is improved.

[0074] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0075] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, characterized in that, include: S1: Obtain sparse matrix data on the CPU, convert the sparse matrix data into CSR format, and obtain a CSR format array; S2: Based on the CSR format array, adaptively decompose the sparse matrix represented by it to obtain dense blocks and sparse blocks, and construct an RDCSR format array based on the CSR format array; the RDCSR format array includes the CSR format array, an array recording the row indices of dense blocks, and an array recording the row indices of sparse blocks; S3: Transmit the RDCSR format array to the DCU, and after adaptive thread allocation for dense blocks and sparse blocks at the DCU, execute SpMV calculation in parallel to obtain the merged calculation result; S4: Transmit the merged calculation result from the DCU to the CPU, and evaluate the calculation performance of SpMV; In step S2, the adaptive decomposition of the sparse matrix specifically includes: shifting the non-zero elements of each row of the sparse matrix to the left and counting the number of non-zero elements in each row; using the number of threads contained in a DCU thread bundle as a partitioning threshold, dividing the non-zero elements in each row that are integer multiples of the threshold into dense blocks, and dividing the remaining non-zero elements into sparse blocks; wherein, the partitioning threshold is determined by using the number of threads contained in a thread bundle in the DCU as the partitioning threshold, which is used to distinguish the boundary of the number of non-zero elements between dense blocks and sparse blocks; In step S2, a dense block row index array and a sparse block row index array are constructed to record the row indices corresponding to the dense blocks and sparse blocks, respectively; the CSR format array is merged with the dense block row index array and the sparse block row index array to form the RDCSR format array; In step S3, based on the dense block row index array, a thread bundle is allocated to each row of the dense block, and the threads in the thread bundle correspond one-to-one with the non-zero elements of the dense block; In step S3, adaptive thread allocation for sparse blocks specifically includes: calculating the number of threads required for each row of the sparse block based on the row index array of the sparse block and the total number of non-zero elements in the sparse block; and allocating a corresponding number of threads to each row of the sparse block according to the calculated number of threads.

2. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S1, sparse matrix data stored in mtx file format is received at the CPU. Extract basic information, which includes at least the number of rows, columns, and total number of non-zero elements of the sparse matrix. Convert the sparse matrix into the CSR format to obtain a CSR format array containing an array of non-zero values, an array of column positions, and an array of row offsets.

3. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S3, performing SpMV calculation specifically includes: threads within the thread bundle performing multiply-add operations on the non-zero elements of the dense block in parallel, reducing to obtain the dense block calculation result; threads allocated to the sparse block performing multiply-add operations on the non-zero elements of the sparse block in parallel, reducing to obtain the sparse block calculation result; merging the dense block calculation result and the sparse block calculation result and writing them into the DCU global memory.

4. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that, In step S4, the merged calculation results in the DCU global memory are transferred to the CPU to complete the calculation process of SpMV.

5. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that, The performance evaluation in step S4 specifically includes: using runtime as the evaluation metric, comparing and evaluating the computational performance of the SpMV with that of the traditional CSR format implementation method.

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