Quantum bit mapping method and device, equipment and storage medium

Abstract

The embodiment of the invention discloses a quantum bit mapping method and device, equipment and a storage medium, and belongs to the technical field of quantum computing. The method comprises the following steps: acquiring a logic quantum bit sequence and a gate operation sequence corresponding to a quantum calculation task; determining a mappable physical quantum bit of the (i + 1) th logic quantum bit based on i candidate physical quantum bits corresponding to the first i logic quantum bits in the logic quantum bit sequence; based on a mapping evaluation result corresponding to the mappable physical quantum bit, screening out a candidate physical quantum bit corresponding to the (i + 1) th logic quantum bit; under the condition that a mapping evaluation result corresponding to the mappable physical quantum bit of the nth logic quantum bit is obtained, determining a target mapping evaluation result; based on a quantum bit mapping combination corresponding to the target mapping evaluation result, mapping the n logic quantum bits into n physical quantum bits; the mapping efficiency of quantum bits in a large-scale chip can be improved, and the mapping quality of the quantum bits can be optimized.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and in particular to a quantum bit mapping method, apparatus, device, and storage medium. Background Technology

[0002] During the compilation of quantum algorithms, it is necessary to map the logical qubits located in the quantum circuits to the physical qubits on the real physical quantum chip.

[0003] The mapping process of qubits can be divided into two steps. The first step is to generate an initial mapping. The second step is to perform a gate operation. If the physical qubits corresponding to the logical qubits associated with the gate operation are not connected, a controlled swap gate is added to exchange the mapping states of the two logical qubits, so that the physical qubits corresponding to the logical qubits associated with the gate operation are connected, thereby compensating for the connectivity between the logical qubits.

[0004] In related technologies, during the initial mapping process, logical qubits in quantum circuits are directly and randomly mapped to physical qubits on real physical quantum chips. This results in randomness in the connection relationships between the physical qubits corresponding to the logical qubits associated with each gate operation. Consequently, a large number of swap gates are required during the execution of gate operations, leading to resource waste. Summary of the Invention

[0005] This application provides a quantum bit mapping method, apparatus, device, and storage medium, the technical solution of which is as follows:

[0006] On one hand, embodiments of this application provide a quantum bit mapping method, the method comprising:

[0007] Obtain the logical qubit sequence and gate operation sequence corresponding to the quantum computing task, wherein the logical qubit sequence includes n logical qubits;

[0008] Based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence, determine the mappable physical qubit of the (i+1)th logical qubit in the physical hardware resources;

[0009] Based on the mapping evaluation result corresponding to the mappable physical qubit, candidate physical qubits corresponding to the (i+1)th logical qubit are selected from the mappable physical qubits of the (i+1)th logical qubit. The mapping evaluation result characterizes the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit on the execution of the gate operation sequence. The degree of influence is related to the number of new gate operations required to execute the gate operation sequence.

[0010] Given the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit, a target mapping evaluation result is determined from the mapping evaluation result, and the target mapping evaluation result is superior to other mapping evaluation results;

[0011] Based on the quantum bit mapping combination corresponding to the target mapping evaluation result, the n logical quantum bits are mapped to n physical quantum bits in the physical hardware resources.

[0012] On the other hand, embodiments of this application provide a qubit mapping device, the device comprising:

[0013] The acquisition module is used to acquire the logical qubit sequence and gate operation sequence corresponding to the quantum computing task, wherein the logical qubit sequence includes n logical qubits;

[0014] The bit determination module is used to determine the mappable physical qubit of the (i+1)th logical qubit in physical hardware resources based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence;

[0015] A bit filtering module is used to filter candidate physical qubits corresponding to the (i+1)th logical qubit from the mappable physical qubits based on the mapping evaluation result corresponding to the mappable physical qubit. The mapping evaluation result characterizes the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit on the execution of the gate operation sequence. The degree of influence is related to the number of new gate operations required to execute the gate operation sequence.

[0016] The result determination module is used to determine a target mapping evaluation result from the mapping evaluation result when the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit is obtained. The target mapping evaluation result is superior to other mapping evaluation results.

[0017] The bit mapping module is used to map the n logical qubits to n physical qubits in the physical hardware resources based on the qubit mapping combination corresponding to the target mapping evaluation result.

[0018] On the other hand, embodiments of this application provide a computer device including a processor and a memory, wherein the memory stores at least one instruction, which is loaded and executed by the processor to implement the quantum bit mapping method as described above.

[0019] On the other hand, embodiments of this application provide a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the quantum bit mapping method as described above.

[0020] On the other hand, embodiments of this application provide a computer program product comprising at least one instruction stored in a computer-readable storage medium. A processor of a computer device reads the at least one instruction from the computer-readable storage medium and executes the at least one instruction, causing the computer device to perform the qubit mapping method described above.

[0021] In this embodiment, after obtaining the logical qubits and gate operation sequence corresponding to the quantum computing task, the logical qubits are not directly mapped to physical qubits in physical hardware resources. Instead, based on the logical qubit sequence, starting from the first logical qubit, the mappable physical qubits of each logical qubit are determined. By calculating the mapping evaluation results corresponding to each mappable physical qubit, candidate physical qubits are selected from the mappable physical qubits. Through a progressive selection process, after determining the mapping evaluation results corresponding to the mappable physical qubit of the nth logical qubit, the optimal mapping evaluation result is selected as the target mapping evaluation result. Based on the qubit mapping combination corresponding to the target mapping evaluation result, the logical qubits are mapped to physical qubits in physical hardware resources. Compared to direct random qubit mapping, the qubit mapping method provided in this embodiment, which performs qubit mapping based on the qubit mapping combination corresponding to the optimal mapping evaluation result, can minimize the number of new gate operations required during gate operation execution, thereby improving the accuracy of qubit mapping and optimizing the mapping quality of qubits. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This application shows a structural block diagram of a quantum computing system provided in an exemplary embodiment.

[0024] Figure 2 A flowchart of a quantum bit mapping method provided in an exemplary embodiment of this application is shown;

[0025] Figure 3 A schematic diagram of a quantum bit mapping combination provided in an exemplary embodiment of this application is shown;

[0026] Figure 4 A flowchart illustrating a process for obtaining a sequence of logical qubits according to an exemplary embodiment of this application is shown;

[0027] Figure 5 This application illustrates a logical quantum circuit corresponding to a quantum computing task provided in an exemplary embodiment.

[0028] Figure 6 It shows Figure 5 Gate operation dependency graph corresponding to quantum logic circuits;

[0029] Figure 7 A flowchart illustrating the process of screening candidate qubits provided in an exemplary embodiment of this application is shown;

[0030] Figure 8 A schematic diagram of a combination of qubit mappings provided in another exemplary embodiment of this application is shown;

[0031] Figure 9 A flowchart illustrating the process of calculating the mapping evaluation result for each combination of qubit mappings provided in an exemplary embodiment of this application is shown.

[0032] Figure 10 This application illustrates a logical quantum circuit corresponding to a quantum computing task provided in another exemplary embodiment.

[0033] Figure 11 It shows Figure 10 Gate operation dependency graph corresponding to quantum logic circuits;

[0034] Figure 12 An exemplary embodiment of this application is shown. Figure 10A combination of qubit mappings corresponding to logical qubits;

[0035] Figure 13 A schematic diagram illustrating the screening of candidate qubits provided in an exemplary embodiment of this application is shown;

[0036] Figure 14 A schematic diagram of a globally screened candidate qubit provided in an exemplary embodiment of this application is shown;

[0037] Figure 15 A schematic diagram of a partition-based candidate qubit selection method provided in another exemplary embodiment of this application is shown;

[0038] Figure 16 This illustration shows a schematic diagram of global and partition-based candidate qubit selection provided by another exemplary embodiment of this application;

[0039] Figure 17 A structural block diagram of a quantum bit mapping device provided in an exemplary embodiment of this application is shown;

[0040] Figure 18 A schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0043] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0044] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0045] First, a brief introduction to the terms used in the embodiments of this application:

[0046] Quantum bit: a unit of measurement in quantum information science. Traditional computers use 0 and 1, and quantum computers also use 0 and 1 to represent information. However, unlike traditional computers, quantum bits can be both 0 and 1 simultaneously. This effect is called quantum superposition, a unique characteristic of quantum computers. The superposition state of quantum bits greatly improves the processing speed of quantum computers.

[0047] Quantum bit mapping: When designing quantum circuits, users typically design them according to their algorithm requirements. However, current quantum chips often struggle to achieve coupling between all qubits. Therefore, when executing quantum circuits on quantum computing hardware, it is necessary to rearrange the qubits used in the quantum algorithm or add SWAP gates for state exchange to compensate for the topological limitations of the chip, thereby achieving the adaptation of the quantum program between the logic circuit and the physical circuit. This rearrangement process of mapping logical qubits in the logic circuit to physical qubits in the physical chip is called quantum mapping.

[0048] Quantum gates: Quantum circuits that operate on qubits, and can be represented by unitary matrices. Compared to traditional logic gates, quantum gates are reversible. Based on the number of active qubits, they can be classified into single-qubit gates, two-qubit gates, and multi-qubit gates.

[0049] Please refer to Figure 1 The diagram illustrates the architecture of a quantum computing system to which the qubit mapping method of an exemplary embodiment of this application is applied. The quantum computing system includes a browser, client, quantum applications, a quantum operating system (QOS), quantum hardware resources, etc.

[0050] Optionally, the browser and client are executable programs used to generate quantum computing tasks, and they typically run on a terminal. The terminal can be a smartphone, tablet, laptop, desktop computer, smart TV, wearable device, or in-vehicle terminal, etc.

[0051] The quantum applications are deployed on top of the quantum operating system. The application programming interface (API) in the quantum applications receives quantum computing tasks, the task distribution system distributes these tasks to the quantum operating system, and the quantum simulator within the applications simulates the quantum computation of the tasks.

[0052] Optionally, the quantum operating system is deployed in the cloud, typically installed on top of quantum hardware resources. The quantum operating system includes an intermediate representation, a quantum just-in-time (JIT) compiler, a quantum module, resource allocation, isolation and security, and resource checks. The intermediate representation serves as a universal interface between quantum applications and the quantum operating system, acting as an abstract representation of quantum computing tasks. The JIT compiler includes a task scheduling model and a topology compilation model. The task scheduling model performs task scheduling, and the topology compilation model compiles the scheduled tasks to obtain the qubit unit topology. The quantum module includes an inspector and a database. The inspector checks the quantum computing tasks, and the database stores the data for the quantum computing tasks, such as the qubit unit topology corresponding to each task. Resource allocation is used to allocate virtualized resources for quantum computing tasks. Isolation and security are used for data isolation and security between the quantum operating system and quantum hardware resources. Resource checks are used by quantum computing tasks to check quantum hardware resources.

[0053] Quantum hardware resources are the physical space where quantum computing resides. They are typically deployed in the cloud. Quantum hardware resources can include physical QPU1 and physical QPU2, which refer to quantum processing units.

[0054] The quantum processing unit includes a large number of physical qubits, and adjacent physical qubits are connected by radio frequency beams to form an overall qubit network.

[0055] When a browser or client generates a task that is a quantum computing task, the computer device first distributes the task to the task scheduling model of the quantum operating system through the task distribution system in the quantum application. The quantum simulator in the quantum application can simulate the quantum computing of the task. Then, the task is scheduled in the quantum operating system by the task scheduling model and compiled by the topology compilation model to obtain a quantum bit topology suitable for executing the quantum computing task.

[0056] Please refer to Figure 2 This document illustrates a flowchart of a quantum bit mapping method provided in an exemplary embodiment of this application. This embodiment uses the method applied to a computer device as an example for illustration. The method includes the following steps:

[0057] Step 201: Obtain the logical qubit sequence and gate operation sequence corresponding to the quantum computing task. The logical qubit sequence includes n logical qubits.

[0058] Optionally, quantum computing tasks refer to tasks that use qubits instead of binary bits and perform computations based on quantum mechanical principles (such as quantum superposition and quantum entanglement). Examples include quantum communication, quantum sensing, and quantum imaging.

[0059] Optionally, a logical qubit is a concept in quantum computing that represents a valid qubit in a quantum computer. It is composed of physical qubits combined using quantum error-correcting codes (QECCs). Considering that individual physical qubits are easily affected by external environmental disturbances, logical qubits are introduced to improve the stability and reliability of quantum computers.

[0060] Optionally, the gate operation sequence includes a series of gate operations that need to be executed sequentially for performing quantum computing tasks. Optionally, the gate operations can be single-qubit gate operations or two-qubit gate operations. The gate operations involved in this embodiment are two-qubit gate operations, with each gate operation applied to two logical qubits out of a plurality of logical qubits. Examples include controlled-NOT (CNOT) gates and SWAP gates.

[0061] In some embodiments, when a quantum computing task exists, the computer device first parses the quantum computing task and generates the corresponding qubit topology structure through topological compilation. The qubit topology structure represents the connection relationships between logical qubits. Simultaneously, the computer device generates a gate operation sequence corresponding to the quantum computing task based on the execution order of the various gate operations involved in the task. Further, the computer device sorts the logical qubits according to the qubit topology structure and the gate operation sequence to obtain the logical qubit sequence corresponding to the quantum computing task.

[0062] Optionally, the logical qubit sequence includes n logical qubits. For example, the logical qubit sequence can be represented as [q1, q2, q3, ..., q...]. n ].

[0063] In one possible implementation, the quantum computing task includes multiple quantum computing subtasks. The computer device first determines the qubit topology corresponding to each quantum computing subtask, and then obtains a general qubit topology capable of performing the quantum computing task by taking the union of the multiple qubit topologies.

[0064] Optionally, the gate operation sequence and logic qubits are typically pre-constructed by the quantum computing platform using quantum error correction codes and stored in a pre-defined storage space. When a quantum computing task needs to be performed, the computer device can directly retrieve the pre-defined gate operation sequence and logic qubits from the pre-defined storage space.

[0065] Step 202: Based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence, determine the mappable physical qubit of the (i+1)th logical qubit in the physical hardware resources.

[0066] Optionally, physical hardware resources refer to physical quantum chips, quantum computers, etc., which contain a large number of physical qubits.

[0067] Optionally, a physical qubit is a real, existing physical hardware resource used to store and process quantum information. For example, a physical qubit can be a Josephson junction in a superconducting circuit, an ion in an ion trap, and so on. Physical qubits possess properties such as quantum superposition and quantum entanglement, making them the information carriers in quantum computing.

[0068] In some embodiments, in order to map logical qubits to physical qubits in physical hardware resources and to make a one-to-one mapping relationship between logical qubits and physical qubits, a computer device can determine the candidate physical qubits corresponding to each logical qubit in turn based on the bit number of each logical qubit in the logical qubit sequence.

[0069] In one possible implementation, if the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence have been determined, the computer device can determine the other physical qubits in the physical hardware resources, excluding the aforementioned i candidate physical qubits, as the mappable physical qubits corresponding to the (i+1)th logical qubit.

[0070] Optionally, a physical qubit can be represented as Q, and the physical hardware resources include n physical qubits Q1 to Q2. n In an illustrative combination of qubit maps, the logical qubit sequence is [q1, q2, q3, ..., q...]. nIf the first logical qubit q1 corresponds to candidate physical qubit Q3, and the second logical qubit q2 corresponds to candidate physical qubit Q4, then the mappable physical qubits corresponding to the third logical qubit q3 are Q1, Q2, Q5, ..., Q6. n .

[0071] Step 203: Based on the mapping evaluation results corresponding to the mappable physical qubits, candidate physical qubits corresponding to the (i+1)th logical qubit are selected from the mappable physical qubits of the (i+1)th logical qubit. The mapping evaluation results characterize the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to a mappable physical qubit on the execution gate operation sequence. The degree of influence is related to the number of new gate operations required for the execution gate operation sequence.

[0072] In some embodiments, when sequentially determining the mappable physical qubits corresponding to each logical qubit in a logical qubit sequence, each logical qubit corresponds to multiple possible qubit mapping combinations. Therefore, the number of qubit mapping combinations increases exponentially during the layer-by-layer qubit mapping process. Furthermore, when there are a large number of physical qubits in the physical hardware resources, the number of qubit mapping combinations is even greater, resulting in high computational complexity in determining a single qubit mapping combination from multiple combinations.

[0073] For example, if the physical hardware resources contain 20 physical qubits, then the first logical qubit corresponds to 20 qubit mapping methods, and under each qubit mapping method of the first logical qubit, the second logical qubit corresponds to 19 qubit mapping methods. Furthermore, under each qubit mapping method of the second logical qubit, the third logical qubit corresponds to 18 qubit mapping methods, and so on, resulting in 20×19×18... qubit mapping combinations.

[0074] In this embodiment of the application, in order to reduce the computational complexity and reduce the consumption of computing resources in the process of determining the physical qubits corresponding to logical qubits layer by layer, the mapping evaluation results corresponding to each mappable physical qubit are calculated, and the mappable physical qubits are screened. The mappable physical qubits with relatively better mapping evaluation results are retained as candidate physical qubits corresponding to the logical qubits of that layer. The number of bits of the candidate physical qubits is significantly less than the number of bits of the mappable physical qubits.

[0075] Optionally, the mapping evaluation result characterizes the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to a mappable physical qubit on the execution gate operation sequence. The degree of influence is related to the number of additional gate operations required for the execution gate operation sequence.

[0076] In one possible implementation, given that multiple qubit mapping combinations corresponding to the first i logical qubits have been determined, the computer device can determine the mappable physical qubit corresponding to the (i+1)th logical qubit in the next layer of each qubit mapping combination based on the i candidate physical qubits corresponding to the first i logical qubits in each qubit mapping combination. This updates the qubit mapping combination corresponding to each mappable physical qubit. Then, the computer device calculates the mapping evaluation result for each qubit mapping combination corresponding to each mappable physical qubit, and determines the mappable physical qubit corresponding to the relatively better qubit mapping combination as the candidate physical qubit corresponding to the (i+1)th logical qubit based on the mapping evaluation result.

[0077] For example, such as Figure 3 As shown, the physical hardware resources include 20 physical qubits Q1 to Q2. 20 In the case where the logical qubit sequence is [q1,q2,q3,……q], n First, the mappable physical qubits corresponding to the first logical qubit q1 are Q1 to Q2. 20 After calculating the mapping valuation results, we can filter out q1 corresponding to Q1, q1 corresponding to Q4, and q1 corresponding to Q. 10 With three qubit mapping combinations, in the qubit mapping combination where q1 corresponds to Q1, the mappable physical qubits corresponding to the second logical qubit q2 are Q1 to Q2. 20 The system contains 19 physical qubits excluding Q1; under the qubit mapping combination where q1 corresponds to Q4, the mappable physical qubits corresponding to the second logical qubit q2 are Q1 to Q4. 20 It contains 19 physical qubits excluding Q4; in q1, Q is the corresponding qubit. 10 Under this qubit mapping combination, the mappable physical qubits corresponding to the second logical qubit q2 are Q1 to Q2. 20 Except Q 10 The 19 physical qubits other than [q1,q2] correspond to a total of 57 qubit mapping combinations. Therefore, the computer can calculate the mapping evaluation results corresponding to each of the 57 qubit mapping combinations. For example, [q1,q2] corresponds to [Q1,Q5], [q1,q2] corresponds to [Q1,Q9], and [q1,q2] corresponds to [Q...]. 10If the mapping evaluation results of the three qubit mapping combinations [Q8] are better than the other mapping evaluation results, then it can be determined that under the qubit mapping combination where q1 corresponds to Q1, the candidate physical qubits corresponding to the second logical qubit q2 are Q5 and Q9; under the qubit mapping combination where q1 corresponds to Q4, the second logical qubit q2 has no candidate physical qubits; under the qubit mapping combination where q1 corresponds to Q... 10 Under this combination of qubit mappings, the candidate physical qubit corresponding to the second logical qubit q2 is Q8.

[0078] Step 204: Given the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit, determine the target mapping evaluation result from the mapping evaluation results. The target mapping evaluation result is superior to other mapping evaluation results.

[0079] In some embodiments, after sequentially determining the candidate physical qubits corresponding to the first n-1 logical qubits in the logical qubit sequence and obtaining multiple qubit mapping combinations, the computer device can determine the mappable physical qubit corresponding to the nth logical qubit under each qubit mapping combination, and calculate the mapping evaluation result corresponding to each mappable physical qubit respectively, thereby determining the optimal one among the multiple mapping evaluation results as the target mapping evaluation result.

[0080] Among them, the target mapping evaluation result is better than other mapping evaluation results. The target mapping evaluation result indicates that when the nth logical qubit is mapped to a mappable physical qubit, the resulting qubit mapping combination has the best impact on each gate operation in the execution gate operation sequence.

[0081] Step 205: Based on the quantum bit mapping combination corresponding to the target mapping evaluation result, map n logical quantum bits to n physical quantum bits in physical hardware resources.

[0082] In some embodiments, after determining the target mapping evaluation result from the mapping evaluation results corresponding to the mappable physical qubits of the nth logical qubit, the computer device can map the n logical qubits one by one to the n physical qubits in the physical hardware resources according to the qubit mapping combination corresponding to the target mapping evaluation result.

[0083] In summary, in this embodiment, after obtaining the logical qubits and gate operation sequence corresponding to the quantum computing task, the logical qubits are not directly mapped to physical qubits in physical hardware resources. Instead, based on the logical qubit sequence, starting from the first logical qubit, the mappable physical qubits of each logical qubit are determined. By calculating the mapping evaluation results corresponding to each mappable physical qubit, candidate physical qubits are selected from the mappable physical qubits. Through a progressive selection process, after determining the mapping evaluation results corresponding to the mappable physical qubit of the nth logical qubit, the optimal mapping evaluation result is selected as the target mapping evaluation result. Based on the qubit mapping combination corresponding to the target mapping evaluation result, the logical qubits are mapped to physical qubits in physical hardware resources. Compared to direct random qubit mapping, the qubit mapping method provided in this embodiment, which performs qubit mapping based on the qubit mapping combination corresponding to the optimal mapping evaluation result, can minimize the number of new gate operations required during gate operation execution, thereby improving the accuracy of qubit mapping and optimizing the mapping quality of qubits.

[0084] In some embodiments, considering that there is a one-to-one mapping relationship between logical qubits and physical qubits, i.e., the mapping physical qubit corresponding to the (i+1)th logical qubit is determined by the influence of the candidate physical qubits corresponding to the first i logical qubits, i.e., the order of the candidate physical qubits corresponding to each logical qubit is different, thus generating a variety of different qubit mapping combinations. Therefore, in order to improve the efficiency of determining the target mapping evaluation result, the computer device can first sort the logical qubits according to the bit importance of the logical qubits to obtain the logical qubit sequence.

[0085] Please refer to Figure 4 This document illustrates a flowchart of a process for obtaining a sequence of logical qubits according to an exemplary embodiment of this application. This embodiment uses the method applied to a computer device as an example for illustration. The method includes the following steps:

[0086] Step 401: Analyze the quantum computing task to obtain the gate operation sequence and n logical qubits.

[0087] In one possible implementation, when a quantum computing task exists, the computer device first analyzes the quantum computing task, determines the logical quantum circuit corresponding to the quantum computing task, obtains the n logical qubits corresponding to the quantum computing task, and generates the gate operation sequence corresponding to the quantum computing task according to the execution order of each gate operation involved in the quantum computing task.

[0088] Indicative, such as Figure 5As shown, it illustrates a logical quantum circuit corresponding to a quantum computing task provided in an exemplary embodiment of this application. This logical quantum circuit includes logical qubits q0, q1, q2, q3, q4 and gate operations g0, g1, g2, g3, g4.

[0089] Step 402: Determine the gate operations associated with each logical qubit and the execution sequence number of each gate operation.

[0090] In one possible implementation, considering that the earlier the gate operation is executed in the logical quantum circuit, the greater its impact on the qubit mapping, the computer device needs to sequentially traverse each logical qubit according to the execution order of each gate operation in the logical quantum circuit and the two logical qubits corresponding to each gate operation to determine the gate operation associated with each logical qubit.

[0091] In this context, the gate operation associated with a logical qubit is the gate operation that applies the operation to that logical qubit. For example, if gate operation g1 is applied to logical qubits q1 and q2, then the gate operation associated with logical qubit q1 includes gate operation g1.

[0092] Indicative, such as Figure 5 As shown, gate operation g0 is applied to logical qubits q0 and q2, gate operation g1 is applied to logical qubits q3 and q4, gate operation g2 is applied to logical qubits q0 and q1, gate operation g3 is applied to logical qubits q1 and q2, and gate operation g4 is applied to logical qubits q2 and q3. Therefore, the gate operations associated with logical qubit q0 are g0 and g2, the gate operations associated with logical qubit q1 are g2 and g3, the gate operations associated with logical qubit q2 are g0, g3 and g4, the gate operations associated with logical qubit q3 are g1 and g4, and the gate operation associated with logical qubit q4 is g1.

[0093] Optionally, the execution sequence number of each gate operation can be determined based on the gate operation dependency graph corresponding to the logical quantum circuit. Regarding the generation of the gate operation dependency graph corresponding to the logical quantum circuit, in one possible implementation, the computer device uses each gate operation as a node in the gate operation dependency graph, determines the directed edges between the nodes according to the execution order of each gate operation, and thus generates the gate operation dependency graph corresponding to the logical quantum circuit based on the nodes and the directed edges between them.

[0094] Furthermore, the computer device determines the execution sequence number of the gate operation corresponding to each node based on the depth of the dependency graph in the gate operation dependency graph. For example, if a node is located at the first level of the gate operation dependency graph, the execution sequence number of the gate operation corresponding to that node is 0; if a node is located at the second level of the gate operation dependency graph, the execution sequence number of the gate operation corresponding to that node is 1, and so on, thereby determining the execution sequence number of each gate operation.

[0095] Indicative, such as Figure 6 As shown, the computer device uses gate operations g0, g1, g2, g3, and g4 as nodes, and determines the directed edges between the nodes according to the execution order of each gate operation. Specifically, gate operations g0 and g1 are executed first, gate operation g2 is executed after gate operation g0, gate operation g3 is executed after gate operations g0 and g2, and gate operation g4 is executed after gate operations g1 and g3, thus generating... Figure 5 The gate operation dependency graph corresponding to the logic quantum circuit is shown. Furthermore, based on this gate operation dependency graph, the computer device can determine that the execution sequence number of gate operations g0 and g1 is 0 (dep = 0), the execution sequence number of gate operation g2 is 1 (dep = 1), the execution sequence number of gate operation g3 is 2 (dep = 2), and the execution sequence number of gate operation g4 is 3 (dep = 3).

[0096] Step 403: Determine the bit importance of each logical qubit based on preset parameters and the execution sequence number of each gate operation associated with the logical qubit.

[0097] In one possible implementation, after determining the gate operations associated with each logical qubit and the execution sequence number of each gate operation, the computer device can calculate the operational importance of each gate operation to the logical qubit based on the execution sequence number of each gate operation associated with the logical qubit and preset parameters. Then, by summing the operational importance of each gate operation associated with the logical qubit, the bit importance of the logical qubit can be determined.

[0098] Optionally, preset parameters are parameter values ​​set according to actual business needs, typically taking any value between 0 and 1. For example, the preset parameter α can be set to 0.5.

[0099] Optionally, the importance of a gate operation characterizes the degree of influence of the gate operation in determining the importance of a logical qubit. The higher the importance of the gate operation, the greater its influence on the importance of the qubit.

[0100] Optionally, the importance of a gate operation can be expressed as a parameter α, with a preset parameter as the base and the execution sequence number of the gate operation as the exponent. dep(g) Therefore, the bit importance of a logical qubit can be expressed as wei(q) = ∑ g∈gate[q]α dep(g) Where wei(q) represents the bit importance of logical qubit q, gate[q] represents the set of all gate operations associated with logical qubit q, g is the gate operation, dep(g) is the execution sequence number of the gate operation, and α is the preset parameter.

[0101] Indicative, such as Figure 5 and Figure 6 As shown, with α = 0.5, the bit importance of a logical qubit q0 is wei(q0) = 0.5. 0 +0.5 1 =1.5; for logical qubit q1, its qubit importance is wei(q1) = 0.5. 1 +0.5 2 =0.75; for logical qubit q2, its qubit importance is wei(q2) = 0.5 0 +0.5 2 +0.5 3 =1.375; for logical qubit q3, its qubit importance is wei(q3) = 0.5 0 +0.5 3 =1.125; for logical qubit q4, its qubit importance is wei(q4) = 0.5 0 =1.

[0102] Step 404: Sort the n logical qubits according to their importance to obtain a logical qubit sequence.

[0103] In one possible implementation, after determining the bit importance of each logical qubit, the computer device can sort the n logical qubits in descending order of bit importance to obtain the logical qubit sequence corresponding to the quantum computing task.

[0104] Indicative, such as Figure 5 and Figure 6 As shown, after calculating the bit importance of logical qubits q0, q1, q2, q3, and q4 respectively, the logical qubit sequence [q0, q2, q3, q4, q1] can be obtained.

[0105] In the above embodiments, based on the logical quantum circuit corresponding to the quantum computing task, the gate operations associated with each logical qubit are determined, and the bit importance of each logical qubit is determined by combining the execution sequence number of each gate operation, thereby generating a logical qubit sequence. The logical qubits in the logical qubit sequence are sorted from high to low bit importance, which facilitates the subsequent determination of the candidate physical qubits corresponding to each logical qubit based on the logical qubit sequence, and helps to improve the mapping quality of qubits.

[0106] In some embodiments, after determining the sequence of logical qubits corresponding to a quantum computing task, the computer device can determine the candidate physical qubits corresponding to each logical qubit by sequentially traversing each logical qubit according to its bit number in the logical qubit sequence, based on a one-to-one mapping between logical qubits and physical qubits.

[0107] Optionally, for the first logical qubit in the logical qubit sequence, since the mapping relationship of other logical qubits has not yet been determined, the computer device can identify each physical qubit in the physical hardware resources as a mappable physical qubit corresponding to the first logical qubit. Then, by calculating the mapping evaluation results of each mappable physical qubit, candidate physical qubits corresponding to the first logical qubit are selected from the mappable physical qubits.

[0108] Optionally, for the i-th logical qubit in the logical qubit sequence, since the candidate qubits corresponding to the first i-1 logical qubits have been determined, the computer device can only determine the remaining physical qubits in the physical hardware resources other than the candidate physical qubits corresponding to the first i logical qubits as the mappable physical qubits corresponding to the i-th logical qubit.

[0109] Indicatively, there exist physical hardware resources including physical qubits Q1 to Q2. 20 For a logical qubit sequence [q3,q2,q4,q0,q1,q5], firstly, the mappable physical qubits corresponding to the first logical qubit q3 are Q1 to Q5. 20 After screening, the candidate physical qubits corresponding to the first logical qubit q3 were determined to be Q6, Q7, and Q... 12 Q 20 Then, for the second logical qubit q2, under the qubit mapping combination where q3 corresponds to Q6, the mappable physical qubits corresponding to the second logical qubit q2 are Q1 to Q6. 20 It contains 19 physical qubits excluding Q6; Q3 corresponds to Q 12 Under this qubit mapping combination, the mappable physical qubits corresponding to the second logical qubit q2 are Q1 to Q2. 20 Except Q 12 In addition to the 19 physical qubits, the others follow the same pattern.

[0110] To improve the efficiency of qubit mapping and avoid calculating all qubit mapping combinations consisting of logical and physical qubits, for each logical qubit, the computer device needs to calculate the mapping evaluation result corresponding to each mappable physical qubit, and then select the corresponding candidate physical qubits based on the mapping evaluation results. (Illustrative example, such as...) Figure 7 As shown, the process may specifically include the following steps:

[0111] Step 701: Based on the i candidate physical qubits corresponding to the first i logical qubits and the mappable physical qubits of the (i+1)th logical qubit, determine the mapping evaluation result corresponding to each mappable physical qubit.

[0112] In some embodiments, after determining the i candidate physical qubits corresponding to the first i logical qubits and obtaining multiple sets of qubit mapping combinations, the computer device needs to determine the mappable physical qubits of the (i+1)th logical qubit under each set of qubit mapping combinations, and then combine the i candidate physical qubits corresponding to the first i logical qubits and the mappable physical qubits of the (i+1)th logical qubit to determine the mapping evaluation result corresponding to each mappable physical qubit.

[0113] For example, such as Figure 8 As shown, there exists physical hardware resources containing physical qubits Q0 to Q5. For the logical qubit sequence [q3,q2,q4,q0,q1,q5], firstly, the mappable physical qubits corresponding to the first logical qubit q3 are Q0 to Q5. After screening and determining that the candidate physical qubits corresponding to the first logical qubit q3 are Q1, Q3, and Q5, for the second logical qubit q2, under the qubit mapping combination where q3 corresponds to Q1, the mappable physical qubits corresponding to the second logical qubit q2 are Q0, Q2, Q3, Q4, and Q5; under the qubit mapping combination where q3 corresponds to Q3, the mappable physical qubits corresponding to the second logical qubit q2 are Q0, Q1, Q2, Q4, and Q5; under the qubit mapping combination where q3 corresponds to Q5, the mappable physical qubits corresponding to the second logical qubit q2 are Q0, Q1, Q2, Q3, and Q4. Therefore, the computer equipment needs to calculate the mapping evaluation results corresponding to the fifteen qubit mapping combinations: Q1+Q0, Q1+Q2, Q1+Q3, Q1+Q4, Q1+Q5, Q3+Q0, Q3+Q1, Q3+Q2, Q3+Q4, Q3+Q5, Q5+Q0, Q5+Q1, Q5+Q2, Q5+Q3, and Q5+Q4.

[0114] Indicative, Figure 9A flowchart illustrating the specific process for calculating the mapping evaluation result for each combination of qubit mappings is shown, which may include the following steps:

[0115] Step 7011: Based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to a mappable physical qubit, determine the executable gate operations and non-executable gate operations in the gate operation sequence. Executing an executable gate operation does not require adding a new gate operation, while executing a non-executable gate operation requires adding a new gate operation.

[0116] In one possible implementation, the computer device first divides the gate operations in the gate operation sequence according to the quantum bit mapping combination formed when mapping the (i+1)th logical quantum bit to a mappable physical quantum bit, and divides the gate operations into executable gate operations and non-executable gate operations. Executing an executable gate operation does not require adding a new gate operation, while executing a non-executable gate operation requires adding a new gate operation.

[0117] Optionally, the computer device, based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to a mappable physical qubit, sequentially traverses the gate operations according to the execution order of each gate operation in the gate operation sequence. Thus, if the bit distance between the gate operations is 1, the gate operation is determined to be an executable gate operation; if the bit distance between the gate operations is greater than 1, the gate operation and other gate operations executed after the gate operation are determined to be non-executable gate operations.

[0118] Optionally, a gate operation can be represented as g = (q, q′), and the process of mapping logical qubits to physical qubits can be represented as mapping π. Then, the bit distance between the candidate physical qubits corresponding to the gate operation can be represented as dist(g, π) = dist AG (π(q),π(q′)), where π(q) represents mapping logical qubit q to physical qubit on physical hardware resource AG, dist AG (π(q),π(q′)) represents the physical distance between the physical qubit corresponding to logical qubit q and the physical qubit corresponding to logical qubit q′.

[0119] Specifically, if the physical qubit corresponding to logical qubit q is adjacent to the physical qubit corresponding to logical qubit q′, then the bit distance corresponding to the gate operation g=(q,q′) is considered to be 1; if the physical qubit corresponding to logical qubit q is not adjacent to the physical qubit corresponding to logical qubit q′, then the bit distance corresponding to the gate operation g=(q,q′) is considered to be greater than 1.

[0120] Indicative, such as Figure 10The illustrated logic quantum circuit includes logic qubits q0, q1, q2, q3 and gate operations g0, g1, g2, g3, g4, g5, g6. Specifically, gate operation g0 corresponds to logic qubits q0 and q2, gate operation g1 corresponds to logic qubits q2 and q3, gate operation g2 corresponds to logic qubits q0 and q3, gate operation g3 corresponds to logic qubits q0 and q2, gate operation g4 corresponds to logic qubits q2 and q3, gate operation g5 corresponds to logic qubits q0 and q3, and gate operation g6 corresponds to logic qubits q1 and q3.

[0121] Indicative, such as Figure 11 As shown, according to Figure 10 The execution order of each gate operation in a logical quantum circuit can be used to obtain the gate operation dependency graph corresponding to that logical quantum circuit.

[0122] Indicative, such as Figure 12 As shown, it illustrates a combination of qubit mappings corresponding to logical qubits q0, q1, q2, and q3, where logical qubit q0 is mapped to physical qubit Q0, logical qubit q1 is mapped to physical qubit Q1, logical qubit q2 is mapped to physical qubit Q2, and logical qubit q3 is mapped to physical qubit Q3.

[0123] Furthermore, combined with Figures 10-12 As shown, for gate operation g0, logical qubits q0 and q2 correspond to physical qubits Q0 and Q2, respectively. Since physical qubits Q0 and Q2 are adjacent in physical hardware resources, the bit distance of gate operation g0 is 1, and gate operation g0 is an executable gate operation. For gate operation g1, logical qubits q2 and q3 correspond to physical qubits Q2 and Q3, respectively. Since physical qubits Q2 and Q3 are adjacent in physical hardware resources, the bit distance of gate operation g1 is 1, and gate operation g1 is an executable gate operation. For gate operation g2, logical qubits q0 and q3 correspond to physical qubits Q0 and Q3, respectively. Since the distance between physical qubits Q0 and Q3 in physical hardware resources is 2, which is greater than 1, gate operation g2 is a non-executable gate operation. Gate operations g3, g4, g5, and g6 are all executed after gate operation g2, therefore gate operations g3, g4, g5, and g6 are also non-executable gate operations.

[0124] In one possible implementation of the process for determining the bit distance of a non-executable gate operation, if all logical qubits corresponding to the non-executable gate operation have candidate physical qubits, the computer device can determine the distance between two candidate physical qubits as the bit distance of the non-executable gate operation; if any logical qubit among the logical qubits corresponding to the non-executable gate operation does not have candidate physical qubits, the computer device can determine the maximum distance between physical qubits in the physical hardware resources as the bit distance of the non-executable gate operation.

[0125] Among them, the maximum distance between physical qubits in physical hardware resources refers to the maximum physical distance between any two physical qubits in physical hardware resources.

[0126] Step 7012: Determine the number of the first gate operations required to add gate operations to the gate operation sequence based on the qubit mapping combination.

[0127] In one possible implementation, for a qubit mapping combination formed when mapping the (i+1)th logical qubit to a mappable physical qubit, after determining the executable and non-executable gate operations, the computer device can simulate the gate operation execution process and add gate operations to the qubit mapping combination during the simulation execution process to transform the non-executable gate operations into executable gate operations, thereby counting the first gate operation number required to add gate operations based on the gate operation sequence executed based on the qubit mapping combination.

[0128] Optionally, the computer device can transform an inoperable gate operation into an executable gate operation by adding a SWAP gate to swap the mapping relationship between two logical qubits and physical qubits, thereby making the physical qubits corresponding to the two logical qubits to which the inoperable gate operation is applied adjacent.

[0129] Indicative, such as Figures 10-12 As shown, for gate operation g2, logical qubits q0 and q3 correspond to physical qubits Q0 and Q3, respectively. The distance between physical qubits Q0 and Q3 in the physical hardware resources is 2, and physical qubit Q3 is adjacent to physical qubits Q1 and Q2 in the physical hardware resources. Therefore, the computer device can use a SWAP gate to exchange the mapping relationship between logical qubit q0 and physical qubit Q0, and logical qubit q2 and physical qubit Q2, so that logical qubits q0 and q3 of gate operation g2 correspond to physical qubits Q2 and Q3, respectively, thus transforming gate operation g2 into an executable gate operation.

[0130] Step 7013: Determine the first mapping estimate result based on the number of second gate operations of the executable gate operations and the total number of bits that can be mapped in the physical hardware resources.

[0131] In one possible implementation, for an executable gate operation, the computer device can count the number of second gate operations in the sequence of executable gate operations, and then determine the first mapping estimate result based on the number of second gate operations and the total number of bits that can be mapped to physical qubits in the physical hardware resources.

[0132] The first mapping estimate result can be expressed as cost1(π)=P×n×β, where P represents the number of second gate operations that can be executed, n represents the total number of physical qubits that can be mapped in the physical hardware resources, and β is an adjustable parameter value set according to actual business needs.

[0133] Step 7014: Determine the second mapping valuation result based on the total number of bits, the bit distance of non-executable gate operations, and the hardware diameter of physical hardware resources.

[0134] In one possible implementation, for non-executable gate operations, the computer device needs to determine the second mapping estimator result based on the bit distance of each non-executable gate operation, the hardware diameter of the physical hardware resources, and the total number of mappable physical qubits in the physical hardware resources.

[0135] Optionally, to facilitate the evaluation of each non-executable gate operation separately, the computer device can first determine the non-executable gate operations associated with each logical qubit in the qubit mapping combination, thereby generating a sequence of non-executable gate operations corresponding to each logical qubit. Then, for each non-executable gate operation, the computer device determines the gate operation evaluation result based on the gate operation number, hardware diameter, and bit distance of the current non-executable gate operation in the non-executable gate operation sequence.

[0136] Optionally, the gate evaluation result characterizes the degree to which non-executable gates affect the quality of the gate sequence. The gate evaluation result can be expressed as α. i ×(γ diam -dist(gate x [i],π)), where gate x Represents the logical qubit q x The sequence of non-executable gate operations formed by associated non-executable gate operations, where i represents the gate operation number of the current non-executable gate operation in the sequence, dist(gate) x[i],π) represents the bit distance of the currently non-executable gate operation, diam represents the hardware diameter of the physical hardware resource, and γ diam α is an adjustable parameter related to the hardware diameter, and is an adjustable parameter value set according to actual business needs.

[0137] Furthermore, the computer device, based on the total number of bits and the number of third gate operations in the non-executable gate operation sequence, sequentially sums the gate operation evaluation results of each non-executable gate operation according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation, to obtain the second mapping evaluation result.

[0138] Optionally, the second mapping valuation sub-result can be represented as Where len(gate) x ) represents the number of third gate operations in the non-executable gate operation sequence, and n represents the total number of bits.

[0139] Considering that the number of operations in the third gate is sufficiently large, i.e., the value of i continuously increases, while α takes a value between 0 and 1, therefore α i The value will also decrease exponentially, and the gate operation valuation result α i ×(γ diam -dist(gate x The values ​​of [i] and π) will also decrease, and their weight in the second mapping estimator will also decrease. That is, when the value of i is large enough, the influence of the gate operation estimator on the second mapping estimator can be ignored. Therefore, in order to optimize the calculation process of the estimator and reduce the consumption of computing resources, the computer device can add an accumulation summation condition during the process of accumulating and summing the gate operation estimators of each non-executable gate operation. This accumulation summation condition is used to determine whether to continue to perform accumulation summation on the gate operation estimators.

[0140] In one possible implementation, the computer device sums the gate operation evaluation results of each non-executable gate operation according to the total number of bits and the number of third gate operations in the non-executable gate operation sequence, based on the bit index of the logical qubit and the gate operation index of the non-executable gate operation. Simultaneously, a truncation parameter is set, and the gate operation evaluation results of each non-executable gate operation are compared with the truncation parameter. If the gate operation evaluation result of the current non-executable gate operation is not less than the truncation parameter, it indicates that the influence of the gate operation evaluation result on the second mapping evaluation sub-result is not negligible, and therefore the gate operation evaluation results need to be summed. If the gate operation evaluation result of the current non-executable gate operation is less than the truncation parameter, it indicates that the influence of the gate operation evaluation result on the second mapping evaluation sub-result is negligible, thus stopping the summation and obtaining the second mapping evaluation sub-result.

[0141] For example, at α = 0.55, γ diam When α = 1, 30 =1.6e -8 α 40 =4e -11 These are all extremely small values, negligible in the calculation process; therefore, the computer can set the truncation parameter to 1e. -6 Thus, the gate operation evaluation result α i ×(γ diam -dist(gate x [i],π)) is less than 1e -6 In this case, the computer equipment will stop summing the results of the gate operation evaluation.

[0142] In another possible implementation, the computer device sums the gate operation evaluation results of each non-executable gate operation according to the total number of bits and the number of third gate operations in the non-executable gate operation sequence, based on the bit index of the logical qubit and the gate operation index of the non-executable gate operation. Simultaneously, an index threshold is set, and the gate operation index of each non-executable gate operation is compared with the index threshold. If the current gate operation index is not greater than the index threshold, it indicates that the influence of the gate operation evaluation result on the second mapping evaluation sub-result is not negligible, and therefore the gate operation evaluation result needs to be summed. If the current gate operation index is greater than the index threshold, it indicates that the influence of the gate operation evaluation result on the second mapping evaluation sub-result is negligible, thus stopping the summation and obtaining the second mapping evaluation sub-result.

[0143] For example, at α = 0.55, γ diam When α = 1, 30 =1.6e -8 α 40 =4e -11 These are all extremely small values ​​that can be ignored during the calculation process. Therefore, the computer device can set the threshold value to 40. Thus, if the gate operation number that is currently not executable is greater than 40, the computer device will stop summing up the gate operation evaluation results.

[0144] Step 7015: Based on the summation of the first mapping estimator result, the second mapping estimator result, and the number of first gate operations, the mapping estimator result corresponding to the mappable physical qubit is obtained.

[0145] In one possible implementation, after obtaining the first mapping estimator result corresponding to the executable gate operation and the second mapping estimator result corresponding to the non-executable gate operation, the computer device can obtain the mapping estimator result corresponding to the mappable physical qubit by summing the first mapping estimator result, the second mapping estimator result, and the number of the first gate operation.

[0146] Optionally, the mapping valuation result is expressed as Where m represents the number of the first gate operations required to perform the gate operation sequence based on the combination of qubit mapping.

[0147] Step 702: Select a first number of candidate mapping valuation results from the mapping valuation results. The candidate mapping valuation results are better than other mapping valuation results.

[0148] In some embodiments, after determining the mapping evaluation result corresponding to the combination of qubit mappings generated by each mappable physical qubit of the (i+1)th logical qubit, the computer device can compare the various mapping evaluation results and select a first number of candidate mapping evaluation results from the mapping evaluation results, wherein the candidate mapping evaluation results are better than other mapping evaluation results.

[0149] In one possible implementation, the computer device can group each candidate physical qubit corresponding to the i-th logical qubit into a group, and in each group, select candidate mapping evaluation results from the mapping evaluation results corresponding to multiple mappable physical qubits of the i+1-th logical qubit.

[0150] Indicative, such as Figure 13 As shown, taking a logical qubit sequence of [q0, q1, q2...] and physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, Q5 as an example, for the mappable physical qubits corresponding to logical qubit q0, Q0, Q1, Q2, Q3, Q4, Q5, after mapping evaluation, candidate physical qubits Q1 and Q5 are obtained. Based on the candidate physical qubits Q1 and Q5 corresponding to logical qubit q0, the computer device determines the mappable physical qubit corresponding to logical qubit q1, and the mapping evaluation results of each mappable physical qubit. Then, taking the candidate physical qubits Q1 and Q5 corresponding to logical qubit q0 as two branches, two more candidate physical qubits are selected from each group, and so on. Therefore, the number of candidate physical qubits selected in the third layer is 2×2×2, and the number of candidate physical qubits selected in the nth layer is 2... n .

[0151] Clearly, in the above screening method, the number of candidate physical qubits in each screening layer is constantly increasing, resulting in a factorial increase in algorithm complexity.

[0152] Therefore, in order to reduce the number of candidate physical qubits corresponding to each logical qubit while ensuring the quality of mapping optimization and controlling the algorithm complexity, in one possible implementation, the computer device can directly select the first number of candidate mapping evaluation results from the qubit mapping combinations generated by each mappable physical qubit of the (i+1)th logical qubit in a global screening manner.

[0153] Indicative, such as Figure 14 As shown, taking a logical qubit sequence of [q0, q1, q2...] and physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, and Q5 as an example, for logical qubit q0, the mappable physical qubits corresponding to it are Q0, Q1, Q2, Q3, Q4, and Q5. After mapping evaluation, candidate physical qubits Q1 and Q5 are obtained. Therefore, based on the candidate physical qubits Q1 and Q5 corresponding to logical qubit q0, the computer device determines the mappable physical qubit corresponding to logical qubit q1, and obtains... Ten qubit mapping combinations are obtained: Q1+Q0, Q1+Q2, Q1+Q3, Q1+Q4, Q1+Q5, Q5+Q0, Q5+Q1, Q5+Q2, Q5+Q3, and Q5+Q4. The computer device then uses a global screening method to directly select Q1+Q2 and Q1+Q4 from these ten qubit mapping combinations. That is, the number of candidate physical qubits in the second layer of screening is 2. This process continues, with 2 candidate physical qubits for every three layers of screening, and the number of candidate physical qubits for the nth layer of screening is also 2.

[0154] It is evident that by adopting a global screening approach, the number of candidate physical qubits corresponding to each layer of logical qubits can be kept at the highest level, thereby achieving control over the algorithm's complexity.

[0155] Optionally, to more evenly consider the mapping evaluation results of different mappable physical qubits, the computer device can also group the mapping evaluation results corresponding to the mappable physical qubits and filter candidate mapping evaluation results by partitioning. In one possible implementation, the computer device first sorts the mapping evaluation results corresponding to the mappable physical qubits according to the bit index of the candidate physical qubits corresponding to the i-th logical qubit and the bit index of the mappable physical qubits of the (i+1)-th logical qubit. Then, based on the sorting results and the number of the first group, the mapping evaluation results corresponding to the mappable physical qubits are grouped, and a second number of candidate mapping evaluation results are selected from each group, wherein the candidate mapping evaluation results are superior to other mapping evaluation results in the same group.

[0156] Indicative, such as Figure 15 As shown, taking the logical qubit sequence as [q0, q1, q2...] and the physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, Q5 as an example, the mappable physical qubits corresponding to logical qubit q0 are Q0, Q1, Q2, Q3, Q4, Q5. The computer device divides them into two groups and selects a candidate mapping evaluation result in each group, thereby obtaining the candidate physical qubits Q1 and Q5 corresponding to logical qubit q0. Then, based on the candidate physical qubits Q1 and Q5 corresponding to the logical qubit q0, the computer device determines the mappable physical qubits corresponding to the logical qubit q1, resulting in ten qubit mapping combinations: Q1+Q0, Q1+Q2, Q1+Q3, Q1+Q4, Q1+Q5, Q5+Q0, Q5+Q1, Q5+Q2, Q5+Q3, and Q5+Q4. The computer device then continues to select one candidate mapping evaluation result from each of the two sets of mapping evaluation results using a partitioned screening method, resulting in two sets of qubit mapping combinations: Q1+Q2 and Q5+Q1. That is, the number of candidate physical qubits in the second layer of screening is 2×1. Similarly, the number of candidate physical qubits in every three layers of screening is 2×1, and the number of candidate physical qubits in the nth layer of screening is also 2×1.

[0157] It is evident that by using a partitioned selection method, the number of candidate physical qubits corresponding to each layer of logical qubits can be kept at the number of the first group × the number of the second group, thereby controlling the complexity of the algorithm.

[0158] Optionally, the computer device can also combine the above two screening methods to screen candidate mapping evaluation results. In one possible implementation, the computer device first screens a third number of first candidate mapping evaluation results from the mapping evaluation results using a global screening method, where the first candidate mapping evaluation results are superior to other mapping evaluation results. Simultaneously, based on the bit index of the candidate physical qubit corresponding to the i-th logical qubit and the bit index of the mappable physical qubit of the (i+1)-th logical qubit, the mapping evaluation results corresponding to the mappable physical qubits are sorted. Then, based on the sorting results and the second grouping quantity, the mapping evaluation results corresponding to the mappable physical qubits are grouped. Finally, using a partitioned screening method, a fourth number of second candidate mapping evaluation results are screened from each group of mapping evaluation results, where the second candidate mapping evaluation results are superior to other mapping evaluation results in the same group except for the first candidate mapping evaluation results.

[0159] Indicative, such as Figure 16 As shown, taking a logical qubit sequence of [q0, q1, q2...] and physical hardware resources including physical qubits Q0, Q1, Q2, Q3, Q4, and Q5 as an example, for the logical qubit q0, the mappable physical qubits corresponding to the physical qubits are Q0, Q1, Q2, Q3, Q4, and Q5. First, the computer device uses a global screening method to select one candidate physical qubit Q2 from the six qubit mapping combinations. Simultaneously, it uses a partitioned screening method to divide the six qubit mapping combinations into two groups, and selects candidate physical qubits Q1 and Q5 from each group respectively. Then, the computer device uses logical quantities... For the candidate physical qubits Q1, Q2, and Q5 corresponding to the logical qubit q0, the global screening and partitioned screening methods are determined respectively. From the 15 mappable physical qubits corresponding to the logical qubit q1, one candidate mapping evaluation result is selected globally, corresponding to the qubit mapping combination Q1+Q2. At the same time, one candidate mapping evaluation result is selected from each of the two groups, corresponding to the qubit mapping combination Q2+Q1 and the corresponding qubit mapping combination Q5+Q1. And so on. The number of candidate physical qubits selected in every three layers is 1+2×1, and the number of candidate physical qubits selected in the nth layer is also 1+2×1.

[0160] It is evident that by employing a combined global and partitioned screening method, the number of candidate physical qubits corresponding to each layer of logical qubits can be maintained at the third number + the second group number × the fourth number, thereby achieving control over the algorithm's complexity.

[0161] Step 703: The mappable physical qubits corresponding to the candidate mapping evaluation results are determined as the candidate physical qubits corresponding to the (i+1)th logical qubit.

[0162] In one possible implementation, the computer device can determine the mappable physical qubits corresponding to each candidate mapping evaluation result as the candidate physical qubits corresponding to the (i+1)th logical qubit, thereby obtaining multiple qubit mapping combinations corresponding to the first (i+1)th logical qubits in the logical qubit sequence.

[0163] Furthermore, for each qubit mapping combination, the computer device can determine the mappable physical qubit of the (i+2)th logical qubit in the physical hardware resources based on the (i+1)th candidate physical qubits corresponding to the first (i+1)th logical qubits. This process is repeated until the mappable physical qubit of the nth logical qubit in the physical hardware resources is determined. By evaluating and screening the qubit mapping combinations corresponding to each mappable physical qubit, the qubit mapping combination corresponding to the target mapping evaluation result is determined.

[0164] In the above embodiments, during the process of screening candidate physical qubits corresponding to the (i+1)th logical qubit, the number of candidate physical qubits corresponding to each layer of logical qubits is effectively controlled by two screening methods: global screening and partitioned screening. This reduces the algorithm complexity and is beneficial to improving the efficiency of performing qubit mapping in large-scale physical quantum chips.

[0165] Furthermore, in the process of screening physical qubits, the mapping combinations of qubits corresponding to each mappable physical qubit are evaluated, thereby selecting the mappable physical qubits corresponding to the relatively better mapping evaluation results as candidate physical qubits corresponding to the (i+1)th logical qubit, which improves the screening quality of candidate physical qubits.

[0166] Furthermore, in the process of calculating the mapping evaluation result, when the number of gate operations is large, in order to avoid the computational complexity from increasing indefinitely with the increase of the number of gate operations, by setting a truncation parameter or an ordinal threshold, the cumulative calculation is stopped when the impact of the gate operation evaluation result on the overall mapping evaluation result is negligible. This effectively reduces the computational complexity and the consumption of computing resources.

[0167] Please refer to Figure 17 The diagram illustrates a structural block diagram of a quantum bit mapping device provided in an exemplary embodiment of this application, the device comprising:

[0168] The acquisition module 1701 is used to acquire the logical qubit sequence and gate operation sequence corresponding to the quantum computing task, wherein the logical qubit sequence includes n logical qubits;

[0169] Bit determination module 1702 is used to determine the mappable physical qubit of the (i+1)th logical qubit in physical hardware resources based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence;

[0170] The bit filtering module 1703 is used to filter out candidate physical qubits corresponding to the (i+1)th logical qubit from the mappable physical qubits based on the mapping evaluation result corresponding to the mappable physical qubit. The mapping evaluation result characterizes the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit on the execution of the gate operation sequence. The degree of influence is related to the number of new gate operations required to execute the gate operation sequence.

[0171] The result determination module 1704 is used to determine a target mapping evaluation result from the mapping evaluation result when the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit is obtained. The target mapping evaluation result is superior to other mapping evaluation results.

[0172] The bit mapping module 1705 is used to map the n logical qubits to n physical qubits in the physical hardware resources based on the qubit mapping combination corresponding to the target mapping evaluation result.

[0173] Optionally, the bit filtering module 1703 includes:

[0174] The result determination unit is used to determine the mapping evaluation result corresponding to each mappable physical qubit based on the i candidate physical qubits corresponding to the first i logical qubits and the mappable physical qubits of the (i+1)th logical qubit.

[0175] The result filtering unit is used to filter out a first number of candidate mapping valuation results from the mapping valuation results, wherein the candidate mapping valuation results are better than other mapping valuation results;

[0176] The bit determination unit is used to determine the mappable physical qubit corresponding to the candidate mapping evaluation result as the candidate physical qubit corresponding to the (i+1)th logical qubit.

[0177] Optionally, the result filtering unit is used for:

[0178] Based on the bit index of the candidate physical qubit corresponding to the i-th logical qubit and the bit index of the mappable physical qubit of the (i+1)-th logical qubit, the mapping evaluation results corresponding to the mappable physical qubit are sorted.

[0179] Based on the sorting results and the number of the first group, the mapping evaluation results corresponding to the mappable physical qubits are grouped.

[0180] A second number of candidate mapping valuation results are selected from each group of mapping valuation results, and the candidate mapping valuation results are superior to other mapping valuation results in the same group.

[0181] Optionally, the result filtering unit is further configured to:

[0182] A third number of first candidate mapping valuation results are selected from the mapping valuation results, and the first candidate mapping valuation results are better than the other mapping valuation results;

[0183] Based on the bit index of the candidate physical qubit corresponding to the i-th logical qubit and the bit index of the mappable physical qubit of the (i+1)-th logical qubit, the mapping evaluation results corresponding to the mappable physical qubit are sorted.

[0184] Based on the sorting results and the number of the second grouping, the mapping evaluation results corresponding to the mappable physical qubits are grouped.

[0185] From each group of mapping valuation results, a fourth number of second candidate mapping valuation results are selected, and the second candidate mapping valuation results are better than other mapping valuation results in the same group except for the first candidate mapping valuation results.

[0186] Optionally, the result determining unit is used for:

[0187] Based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit, the executable gate operations and non-executable gate operations in the gate operation sequence are determined, wherein executing the executable gate operation does not require adding a new gate operation, while executing the non-executable gate operation requires adding a new gate operation;

[0188] Determine the first number of additional gate operations required to execute the gate operation sequence based on the quantum bit mapping combination;

[0189] Based on the number of second gate operations of the executable gate operations and the total number of mappable physical qubits in the physical hardware resources, the first mapping estimate result is determined;

[0190] Based on the total number of bits, the bit distance of the non-executable gate operation, and the hardware diameter of the physical hardware resources, the second mapping valuation result is determined;

[0191] Based on the sum of the first mapping estimator result, the second mapping estimator result, and the number of the first gate operations, the mapping estimator result corresponding to the mappable physical qubit is obtained.

[0192] Optionally, the result determining unit is further configured to:

[0193] Based on the non-executable gate operations associated with each logical qubit in the aforementioned qubit mapping combination, a sequence of non-executable gate operations corresponding to each logical qubit is generated;

[0194] Based on the gate operation number in the non-executable gate operation sequence, the hardware diameter, and the bit distance of the current non-executable gate operation, the gate operation evaluation result of the current non-executable gate operation is determined, and the gate operation evaluation result characterizes the degree of influence of the non-executable gate operation on the gate operation sequence.

[0195] Based on the total number of bits and the number of third gate operations in the non-executable gate operation sequence, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation to obtain the second mapping evaluation result.

[0196] Optionally, the result determining unit is used for:

[0197] Based on the total number of bits and the number of the third non-executable gate operations in the non-executable gate operation sequence, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation.

[0198] If the gate operation evaluation result of the current non-executable gate operation is less than the truncation parameter, stop the summation and obtain the second mapping evaluation sub-result.

[0199] Optionally, the result determining unit is used for:

[0200] Based on the total number of bits and the number of the third non-executable gate operations in the non-executable gate operation sequence, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation.

[0201] If the gate operation number of the non-executable gate operation is greater than the number threshold, the summation is stopped, and the second mapping estimate result is obtained.

[0202] Optionally, the result determining unit is used for:

[0203] Based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit, the gate operations are traversed sequentially according to the execution order of each gate operation in the gate operation sequence;

[0204] When the bit distance of the gate operation is 1, the gate operation is determined to be the executable gate operation;

[0205] If the bit distance of the gate operation is greater than 1, the gate operation and other gate operations performed after the gate operation are determined to be non-executable gate operations.

[0206] Optionally, the device further includes:

[0207] The first bit distance determination module is used to determine the distance between the candidate physical qubits as the bit distance of the non-executable gate operation when there are candidate physical qubits for the logical qubits corresponding to the non-executable gate operation.

[0208] The second bit distance determination module is used to determine the maximum distance between the physical qubits in the physical hardware resources as the bit distance of the non-executable gate operation when the logical qubit corresponding to the non-executable gate operation does not have the candidate physical qubit.

[0209] Optionally, the acquisition module 1701 is used for:

[0210] The quantum computing task is analyzed to obtain the gate operation sequence and the n logical qubits;

[0211] Determine the gate operations associated with each logical qubit, and the execution sequence number of each gate operation;

[0212] The importance of each logical qubit is determined based on preset parameters and the execution sequence number of each gate operation associated with the logical qubit.

[0213] Based on the bit importance, the n logical qubits are sorted to obtain the logical qubit sequence.

[0214] Optionally, the bit determination module 1702 is used for:

[0215] For the first logical qubit in the logical qubit sequence, each physical qubit in the physical hardware resources is determined as the mappable physical qubit corresponding to the first logical qubit;

[0216] For the i-th logical qubit in the logical qubit sequence, the remaining physical qubits in the physical hardware resources, excluding the candidate physical qubits corresponding to the first i logical qubits, are determined as the mappable physical qubits corresponding to the i-th logical qubit.

[0217] In summary, in this embodiment, after obtaining the logical qubits and gate operation sequence corresponding to the quantum computing task, the logical qubits are not directly mapped to physical qubits in physical hardware resources. Instead, based on the logical qubit sequence, starting from the first logical qubit, the mappable physical qubits of each logical qubit are determined. By calculating the mapping evaluation results corresponding to each mappable physical qubit, candidate physical qubits are selected from the mappable physical qubits. Through a progressive selection process, after determining the mapping evaluation results corresponding to the mappable physical qubit of the nth logical qubit, the optimal mapping evaluation result is selected as the target mapping evaluation result. Based on the qubit mapping combination corresponding to the target mapping evaluation result, the logical qubits are mapped to physical qubits in physical hardware resources. Compared to direct random qubit mapping, the qubit mapping method provided in this embodiment, which performs qubit mapping based on the qubit mapping combination corresponding to the optimal mapping evaluation result, can minimize the number of new gate operations required during gate operation execution, thereby improving the accuracy of qubit mapping and optimizing the mapping quality of qubits.

[0218] It should be noted that the apparatus provided in the above embodiments is only an example of the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the apparatus can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and their implementation process can be found in the method embodiments, which will not be repeated here.

[0219] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the acquisition of relevant user data. These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their relevant data is being collected. This ensures that the application only begins the steps for acquiring user data after receiving confirmation from the user regarding the prompt interface or pop-up. Otherwise (i.e., without receiving confirmation from the user), the steps for acquiring user data are terminated, meaning no user data is acquired. In other words, all information involved in this application (including but not limited to user device information, user personal information, and corresponding user operation data), data (including but not limited to data used for analysis, stored data, and displayed data), and signals are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0220] Please refer to Figure 18 This illustration shows a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application. Specifically, the computer device 1800 includes a Central Processing Unit (CPU) 1801, a system memory 1804 including a random access memory 1802 and a read-only memory 1803, and a system bus 1805 connecting the system memory 1804 and the CPU 1801. The computer device 1800 may also include a basic input / output system (I / O system) 1806 to facilitate the transfer of information between various devices within the computer, and a mass storage device 1807 for storing the operating system 1813, application programs 1814, and other program modules 1815.

[0221] In some embodiments, the basic input / output system 1806 includes a display 1808 for displaying information and an input device 1809 for user input, such as a mouse or keyboard. Both the display 1808 and the input device 1809 are connected to the central processing unit 1801 via an input / output controller 1810 connected to the system bus 1805. The basic input / output system 1806 may also include the input / output controller 1810 for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 1810 also provides output to a display screen, printer, or other types of output devices.

[0222] The mass storage device 1807 is connected to the central processing unit 1801 via a mass storage controller (not shown) connected to the system bus 1805. The mass storage device 1807 and its associated computer-readable media provide non-volatile storage for the computer device 1800. That is, the mass storage device 1807 may include computer-readable media (not shown) such as a hard disk or drive.

[0223] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The system memory 1804 and mass storage device 1807 described above can be collectively referred to as memory.

[0224] The memory stores one or more programs, which are configured to be executed by one or more central processing units 1801. The one or more programs contain instructions for implementing the methods described above. The central processing unit 1801 executes the one or more programs to implement the quantum bit mapping methods provided in the various method embodiments described above.

[0225] According to various embodiments of this application, the computer device 1800 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 1800 can be connected to the network 1811 via the network interface unit 1812 connected to the system bus 1805, or the network interface unit 1812 can be used to connect to other types of networks or remote computer systems (not shown).

[0226] This application also provides a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the quantum bit mapping method described in the above embodiments.

[0227] Optionally, the computer-readable storage medium may include ROM, RAM, solid-state drives (SSDs), or optical discs, etc. The RAM may include resistive random access memory (ReRAM) and dynamic random access memory (DRAM).

[0228] This application provides a computer program product including at least one instruction stored in a computer-readable storage medium. A processor of a computer device reads the at least one instruction from the computer-readable storage medium and executes the at least one instruction, causing the computer device to perform the quantum bit mapping method described in the above embodiments.

[0229] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0230] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A quantum bit mapping method, characterized in that, The method includes: Obtain the logical qubit sequence and gate operation sequence corresponding to the quantum computing task, wherein the logical qubit sequence includes n logical qubits; Based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence, determine the mappable physical qubit of the (i+1)th logical qubit in the physical hardware resources; Based on the mapping evaluation result corresponding to the mappable physical qubit, candidate physical qubits corresponding to the (i+1)th logical qubit are selected from the mappable physical qubits of the (i+1)th logical qubit. The mapping evaluation result characterizes the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit on the execution of the gate operation sequence. The degree of influence is related to the number of new gate operations required to execute the gate operation sequence. Given the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit, a target mapping evaluation result is determined from the mapping evaluation result, and the target mapping evaluation result is superior to other mapping evaluation results; Based on the quantum bit mapping combination corresponding to the target mapping evaluation result, the n logical quantum bits are mapped to n physical quantum bits in the physical hardware resources.

2. The method according to claim 1, characterized in that, The process of selecting candidate physical qubits corresponding to the (i+1)th logical qubit from the mappable physical qubits based on the mapping evaluation result of the mappable physical qubit includes: Based on the i candidate physical qubits corresponding to the first i logical qubits, and the mappable physical qubits of the (i+1)th logical qubit, determine the mapping evaluation result corresponding to each mappable physical qubit; A first number of candidate mapping valuation results are selected from the mapping valuation results, and the candidate mapping valuation results are superior to the other mapping valuation results; The mappable physical qubits corresponding to the candidate mapping evaluation results are determined as the candidate physical qubits corresponding to the (i+1)th logical qubit.

3. The method according to claim 2, characterized in that, The step of selecting a first number of candidate mapping valuation results from the mapping valuation results includes: Based on the bit index of the candidate physical qubit corresponding to the i-th logical qubit and the bit index of the mappable physical qubit of the (i+1)-th logical qubit, the mapping evaluation results corresponding to the mappable physical qubit are sorted. Based on the sorting results and the number of the first group, the mapping evaluation results corresponding to the mappable physical qubits are grouped. A second number of candidate mapping valuation results are selected from each group of mapping valuation results, and the candidate mapping valuation results are superior to other mapping valuation results in the same group.

4. The method according to claim 2, characterized in that, The step of selecting a first number of candidate mapping valuation results from the mapping valuation results further includes: A third number of first candidate mapping valuation results are selected from the mapping valuation results, and the first candidate mapping valuation results are better than the other mapping valuation results; Based on the bit index of the candidate physical qubit corresponding to the i-th logical qubit and the bit index of the mappable physical qubit of the (i+1)-th logical qubit, the mapping evaluation results corresponding to the mappable physical qubit are sorted. Based on the sorting results and the number of the second grouping, the mapping evaluation results corresponding to the mappable physical qubits are grouped. From each group of mapping valuation results, a fourth number of second candidate mapping valuation results are selected, and the second candidate mapping valuation results are better than other mapping valuation results in the same group except for the first candidate mapping valuation results.

5. The method according to claim 2, characterized in that, The determination of the mapping evaluation result corresponding to each mappable physical qubit based on the i candidate physical qubits corresponding to the first i logical qubits and the mappable physical qubit of the (i+1)th logical qubit includes: Based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit, the executable gate operations and non-executable gate operations in the gate operation sequence are determined, wherein executing the executable gate operation does not require adding a new gate operation, while executing the non-executable gate operation requires adding a new gate operation; Determine the first number of additional gate operations required to execute the gate operation sequence based on the quantum bit mapping combination; Based on the number of second gate operations of the executable gate operations and the total number of mappable physical qubits in the physical hardware resources, the first mapping estimate result is determined; Based on the total number of bits, the bit distance of the non-executable gate operation, and the hardware diameter of the physical hardware resources, the second mapping valuation result is determined; Based on the sum of the first mapping estimator result, the second mapping estimator result, and the number of the first gate operations, the mapping estimator result corresponding to the mappable physical qubit is obtained.

6. The method according to claim 5, characterized in that, The determination of the second mapping estimation sub-result based on the total number of bits, the bit distance of the non-executable gate operation, and the hardware diameter of the physical hardware resources includes: Based on the non-executable gate operations associated with each logical qubit in the aforementioned qubit mapping combination, a sequence of non-executable gate operations corresponding to each logical qubit is generated; Based on the gate operation number in the non-executable gate operation sequence, the hardware diameter, and the bit distance of the current non-executable gate operation, the gate operation evaluation result of the current non-executable gate operation is determined, and the gate operation evaluation result characterizes the degree of influence of the non-executable gate operation on the gate operation sequence. Based on the total number of bits and the number of third gate operations in the non-executable gate operation sequence, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation to obtain the second mapping evaluation result.

7. The method according to claim 6, characterized in that, Based on the total number of bits and the number of third gate operations in the sequence of non-executable gate operations, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation to obtain the second mapping evaluation sub-result, including: Based on the total number of bits and the number of the third non-executable gate operations in the non-executable gate operation sequence, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation. If the gate operation evaluation result of the current non-executable gate operation is less than the truncation parameter, stop the summation and obtain the second mapping evaluation sub-result.

8. The method according to claim 6, characterized in that, Based on the total number of bits and the number of third gate operations in the sequence of non-executable gate operations, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation to obtain the second mapping evaluation sub-result, including: Based on the total number of bits and the number of the third non-executable gate operations in the non-executable gate operation sequence, the gate operation evaluation results of each non-executable gate operation are summed according to the bit index of the logical qubit and the gate operation index of the non-executable gate operation. If the gate operation number of the non-executable gate operation is greater than the number threshold, the summation is stopped, and the second mapping estimate result is obtained.

9. The method according to claim 5, characterized in that, The step of determining the executable and non-executable gate operations in the gate operation sequence based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit includes: Based on the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit, the gate operations are traversed sequentially according to the execution order of each gate operation in the gate operation sequence; When the bit distance of the gate operation is 1, the gate operation is determined to be the executable gate operation; If the bit distance of the gate operation is greater than 1, the gate operation and other gate operations performed after the gate operation are determined to be non-executable gate operations.

10. The method according to claim 9, characterized in that, The method further includes: When there are candidate physical qubits for the logical qubits corresponding to the non-executable gate operation, the distance between the candidate physical qubits is determined as the bit distance of the non-executable gate operation; If the candidate physical qubit does not exist for the logical qubit corresponding to the non-executable gate operation, the maximum distance between the physical qubits in the physical hardware resources is determined as the bit distance of the non-executable gate operation.

11. The method according to claim 1, characterized in that, The acquisition of the logical qubit sequence and gate operation sequence corresponding to the quantum computing task includes: The quantum computing task is analyzed to obtain the gate operation sequence and the n logical qubits; Determine the gate operations associated with each logical qubit, and the execution sequence number of each gate operation; The importance of each logical qubit is determined based on preset parameters and the execution sequence number of each gate operation associated with the logical qubit. Based on the bit importance, the n logical qubits are sorted to obtain the logical qubit sequence.

12. The method according to claim 1, characterized in that, The step of determining the mappable physical qubit of the (i+1)th logical qubit in physical hardware resources based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence includes: For the first logical qubit in the logical qubit sequence, each physical qubit in the physical hardware resources is determined as the mappable physical qubit corresponding to the first logical qubit; For the i-th logical qubit in the logical qubit sequence, the remaining physical qubits in the physical hardware resources, excluding the candidate physical qubits corresponding to the first i logical qubits, are determined as the mappable physical qubits corresponding to the i-th logical qubit.

13. A quantum bit mapping device, characterized in that, The device includes: The acquisition module is used to acquire the logical qubit sequence and gate operation sequence corresponding to the quantum computing task, wherein the logical qubit sequence includes n logical qubits; The bit determination module is used to determine the mappable physical qubit of the (i+1)th logical qubit in physical hardware resources based on the i candidate physical qubits corresponding to the first i logical qubits in the logical qubit sequence; A bit filtering module is used to filter candidate physical qubits corresponding to the (i+1)th logical qubit from the mappable physical qubits based on the mapping evaluation result corresponding to the mappable physical qubit. The mapping evaluation result characterizes the degree of influence of the qubit mapping combination formed when mapping the (i+1)th logical qubit to the mappable physical qubit on the execution of the gate operation sequence. The degree of influence is related to the number of new gate operations required to execute the gate operation sequence. The result determination module is used to determine a target mapping evaluation result from the mapping evaluation result when the mapping evaluation result corresponding to the mappable physical qubit of the nth logical qubit is obtained. The target mapping evaluation result is superior to other mapping evaluation results. The bit mapping module is used to map the n logical qubits to n physical qubits in the physical hardware resources based on the qubit mapping combination corresponding to the target mapping evaluation result.

14. A computer device, characterized in that, The computer device includes a processor and a memory; the memory stores at least one instruction, which is executed by the processor to implement the quantum bit mapping method as described in any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is executed by a processor to implement the quantum bit mapping method as described in any one of claims 1 to 12.

16. A computer program product, characterized in that, The computer program product includes at least one instruction stored in a computer-readable storage medium; a processor of a computer device reads the at least one instruction from the computer-readable storage medium and executes the at least one instruction to cause the computer device to implement the quantum bit mapping method as described in any one of claims 1 to 12.

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