A method, system, and medium for magnetic tape storage three-dimensional interleaving hardware acceleration

Abstract

The application discloses a magnetic tape storage three-dimensional interlaced hardware acceleration method, system and medium, relates to the magnetic tape storage technical field, and the acceleration method is specifically as follows: the logical block obtained is split into N sub-blocks through a cross switch network, and is scattered and mapped to a plurality of physical tracks according to a maximum track spacing rule; a pseudo-random sequence generated by a shift register chain is used to dynamically allocate a physical frame address; logically continuous sub-blocks are inserted into physically non-continuous physical frames; a redundant generation network generates a check block using a variable dynamic strategy; the cross switch network distributes the check block to a physical track with the highest track health index based on check block routing logic; a dynamic redundancy control module compares the average track health index of the physical track with a preset threshold value, generates a current optimal redundancy ratio, and converts the current optimal redundancy ratio into a configuration instruction of the variable dynamic strategy; the acceleration method eliminates data transfer overhead, realizes ultra-low delay and high energy efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of magnetic tape storage technology, and in particular to a magnetic tape storage three-dimensional interleaving hardware acceleration method, system and medium. BACKGROUND

[0002] Magnetic tape storage is still the core solution for cold data storage due to its high capacity, low cost and long-term preservation advantages, but its linear access characteristics and physical medium vulnerability (such as track scratches, local pollution) lead to frequent long burst errors. Traditional error correction coding (such as RS code, LDPC) can correct random short errors, but it is difficult to deal with long burst errors that span multiple tracks or continuous storage areas. Therefore, three-dimensional interleaving technology is introduced: by rearranging data in the spatial dimension (distributing data across tracks), the time dimension (dispersing multiple frame read-write timing) and the logical dimension (dispersing redundant block mapping), long burst errors are dispersed into correctable short errors, thereby improving reliability. However, three-dimensional interleaving involves dynamic permutation of massive data in multiple dimensions, and the computational complexity grows exponentially.

[0003] Traditional systems based on the von Neumann architecture separate storage and computation, requiring frequent data movement from the tape controller cache to the processor, resulting in high latency and energy consumption (data movement energy consumption accounts for more than 70%). The low power and high real-time requirements of tape systems further exacerbate the contradiction: for example, if the real-time interleaving / deinterleaving of linear read-write is delayed too high, it will slow down the overall throughput. Existing hardware acceleration solutions (such as FPGA, GPU) have improved computing speed, but still rely on off-chip storage interaction and cannot avoid the data movement bottleneck; at the same time, their parallel architecture is difficult to adapt to the irregular access mode of tape data in three-dimensional mapping. In addition, although the memory computing technology reduces data movement through near-memory computing, current research focuses on regular operations (such as matrix multiplication), and lacks native support for high-dimensional dynamic data permutation required by three-dimensional interleaving, resulting in a technical gap in the industry in the field of efficient error correction hardware design for tape media.

[0004] Existing solutions solidify three-dimensional interleaving algorithm logic in FPGA, and achieve long burst error protection through data permutation in spatial dimension, time dimension and logical dimension. The core implementation includes: 1) in the spatial dimension, the data blocks are split and mapped to multiple tracks, and the FPGA multi-channel I / O is used for parallel writing; 2) in the time dimension, the data frames are arranged in non-continuous timing through a shift register chain, breaking the continuity of physical storage; 3) in the logical dimension, RS check blocks are inserted according to a fixed rule and allocated to independent tracks. The parallel pipeline structure of FPGA can partially improve the processing speed (typical throughput 3-5 Gbps). However, the parallel computing unit is difficult to adapt to the irregular data access mode, and the energy efficiency is low.

[0005] In addition, some solutions utilize the near-memory computing capabilities of in-memory computing architectures, integrating computing circuits near storage units to support single-dimensional (spatial track) data rearrangement. The core logic is to directly map the data to be written to the in-memory computing array, and then perform single-dimensional permutations (such as matrix transpose) through the computing units within the array, distributing the same logical block across different physical tracks, reducing data interaction between DRAM and the processor. However, these solutions have significant limitations: 1) They only support regular one-dimensional mapping, lacking cross-temporal and logical dimension collaborative processing capabilities, resulting in limited effectiveness against long-term burst errors; 2) They do not integrate redundancy check generation functionality, requiring additional hardware support for the error correction process.

[0006] Therefore, the existing technology has the following drawbacks:

[0007] (1) High data transfer costs:

[0008] FPGA solutions require frequent interaction with off-chip memory (such as DDR) to complete 3D data replacement, resulting in data transfer energy consumption accounting for more than 60% of the total system power consumption, and high latency (>100μs) affecting real-time performance. Although in-memory computing solutions reduce some data transfer, cross-dimensional processing still requires interaction with external modules, and cannot completely eliminate the data transfer bottleneck.

[0009] (2) Insufficient multi-dimensional synergy:

[0010] FPGA solutions achieve 3D interleaving through a fixed pipeline, but the computing units are only adapted to regular data flows (such as continuous track mapping). The hardware utilization rate for irregular access modes (such as random recovery across tracks) is less than 50%, making it difficult to cope with complex error scenarios. In-memory computing solutions only support fixed-interval mapping in the spatial dimension (such as matrix transpose), lacking the ability to handle nonlinear timing jumps in the time dimension (such as pseudo-random frame distribution) and dynamic redundancy generation in the logical dimension, resulting in low efficiency in resisting multi-dimensional coupling errors.

[0011] (3) Redundant generation and distribution rigidity:

[0012] Existing solutions (such as RS verification for FPGAs) use static redundancy rules, with a fixed ratio of verification blocks (e.g., 1:8) and preset positions (e.g., fixed track groups). They cannot be dynamically adjusted according to tape media aging or sudden error modes, and the error correction efficiency decreases by 30%-40% over time.

[0013] (4) The contradiction between energy efficiency and real-time performance is prominent:

[0014] FPGA solutions improve throughput through parallelism, but high off-chip data interaction leads to poor energy efficiency; in-memory computing solutions have higher energy efficiency, but their single function cannot meet the requirements of 3D real-time performance. Summary of the Invention

[0015] Based on the technical problems existing in the background technology, this invention proposes a hardware acceleration method, system and medium for three-dimensional interleaving of magnetic tape storage, which eliminates data transfer overhead and achieves ultra-low latency and high energy efficiency.

[0016] This invention proposes a hardware acceleration method for three-dimensional interleaving of magnetic tape storage, which achieves acceleration through an in-memory computing array, a three-dimensional permutation engine and a dynamic redundancy control module. The three-dimensional permutation engine is integrated inside the in-memory computing array and includes a cross-switching network, a redundancy generation network and a shift register chain.

[0017] The specific acceleration method is as follows:

[0018] The obtained logical block is split into N sub-blocks by a cross-connect network and mapped to multiple physical tracks according to the maximum track spacing rule. The physical frame address is dynamically allocated using a pseudo-random sequence generated by the shift register chain, and logically continuous sub-blocks are inserted into physically non-contiguous physical frames.

[0019] The redundancy generation network uses a variable dynamic strategy to generate check blocks, and the cross-switch network allocates the check blocks to the physical track with the highest track health index based on the check block routing logic.

[0020] The dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, and converts the current optimal redundancy ratio into the configuration command of the variable dynamic strategy. At the same time, it sorts the real-time track health index of all physical tracks in descending order to obtain a track health ranking list, and creates a check block routing table based on it. The check block routing table is fed back to the cross switch network to control the check block routing logic of the cross switch network.

[0021] Furthermore, the cross-switch network includes an N×M switch matrix, where N represents the number of sub-blocks and M represents the number of physical tracks. Each intersection of the switch matrix is ​​a programmable switch used to establish arbitrary connections between the sub-blocks and physical tracks.

[0022] Furthermore, the dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, as follows:

[0023] The read failure rate of each physical track is periodically acquired and converted into a normalized track health index, from which the average track health index is calculated. ;

[0024] Preset multi-level health thresholds: High health threshold Medium health threshold and moderate health threshold At the same time, the redundancy ratio corresponding to each threshold level is preset: low redundancy ratio Standard redundancy ratio High redundancy ratio Redundancy ratio upper limit ;

[0025] when When the magnetic tape medium is in its best condition, the current optimal redundancy ratio is achieved. ;

[0026] when When the magnetic tape medium is in good condition, the optimal redundancy ratio is achieved. ;

[0027] when When this occurs, it indicates that the magnetic tape medium is in poor condition. At this point, the current optimal redundancy ratio is... ;

[0028] when When this occurs, it indicates that the magnetic tape medium is in a dangerous condition. At this point, the current optimal redundancy ratio is... And set a threshold to trigger an alarm.

[0029] Furthermore, the verification block routing table is fed back to the cross-connect network to control the routing logic of the cross-connect network, specifically as follows:

[0030] Start searching from the front end of the check block routing table and select the physical track of the first free physical frame as the target track;

[0031] Create a new entry in the check block routing table to map the address of the check block generated by the redundancy generation network and to be allocated to an idle physical frame on the target track;

[0032] The new entry is sent as a control command to the crossbar network, thereby establishing a connection between the check block and the idle physical frame.

[0033] Furthermore, the cross-switch network, shift register chain, and redundancy generation network constitute a three-dimensional permutation engine and are integrated into the storage unit of the in-memory computing architecture.

[0034] Furthermore, the specific process of tape de-interleaving is as follows:

[0035] After reading a physical block containing multiple sub-blocks and a check block from the tape, the in-memory computing array detects the error location and locates the data error within it;

[0036] The cross switch network aggregates the sub-blocks from different physical tracks based on the original mapping table that records the physical storage locations of each sub-block and the parity block;

[0037] The shift register chain performs a reverse operation to restore the original order of the sub-blocks in the logic block;

[0038] The redundancy generation network uses verification blocks to reconstruct the located damaged data;

[0039] The recovered complete logic block is output to the host via the tape read / write interface to realize data reading.

[0040] Furthermore, a timing controller is set up to control the scheduling of various modules in the 3D displacement engine. Specific steps include:

[0041] Command issuance and path establishment: The timing controller issues commands to enable the cross switch network to complete the path connection from the sub-block and the check block to the target physical track according to the check block routing table;

[0042] Synchronous Triggering and Parallel Computation: After the routing connection is stable, the timing controller synchronously triggers the shift register chain and the redundancy generation network; the shift register chain calculates the non-contiguous physical frame address within a single clock cycle, while the redundancy generation network begins to perform check block encoding calculations spanning one or more clock cycles.

[0043] Waiting and Synchronous Latching: After the timing controller receives the "operation complete" signal from all modules in the 3D displacement engine, it issues a global "latch" signal when it confirms that all sub-blocks, the corresponding physical frame addresses, and the generated check blocks are ready, ensuring that all outputs are ready for physical writing in the same clock cycle.

[0044] A hardware acceleration system for three-dimensional interleaving of magnetic tape storage includes an in-memory computing storage array, a three-dimensional displacement engine, and a dynamic redundancy control module, wherein the three-dimensional displacement engine is integrated inside the in-memory computing storage array.

[0045] The three-dimensional permutation engine includes a cross-switching network, a redundancy generation network, and a shift register chain;

[0046] The cross-connect network is used to split the acquired logic block into N sub-blocks and scatter them to multiple physical tracks according to the maximum track spacing rule, and to allocate the check blocks generated by the redundancy generation network to the physical tracks with the highest track health index based on the check block routing logic.

[0047] Redundant generation networks utilize variable dynamic strategies to generate check blocks;

[0048] The dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, and converts the current optimal redundancy ratio into the configuration command of the variable dynamic strategy. At the same time, it sorts the real-time track health index of all physical tracks in descending order to obtain a track health ranking list, and creates a check block routing table based on it. The check block routing table is fed back to the cross switch network to control the check block routing logic of the cross switch network.

[0049] Furthermore, it also includes an interface and a controller, which are responsible for;

[0050] The interface and controller include a configuration register, a tape read / write interface, and a timing register;

[0051] Configuration registers are used to configure system parameters;

[0052] The tape read / write interface is used for communication with external systems;

[0053] The timing register is used to control the scheduling of various modules in the 3D displacement engine, specifically:

[0054] Command issuance and path establishment: The timing controller issues commands to enable the cross switch network to complete the path connection from the sub-block and the check block to the target physical track according to the check block routing table;

[0055] Synchronous Triggering and Parallel Computation: After the routing connection is stable, the timing controller synchronously triggers the shift register chain and the redundancy generation network; the shift register chain calculates the non-contiguous physical frame address within a single clock cycle, while the redundancy generation network begins to perform check block encoding calculations spanning one or more clock cycles.

[0056] Waiting and Synchronous Latching: When a pause is required, the timing controller sends a pause command to the 3D displacement engine. After waiting to receive the "operation complete" signal from all modules in the 3D displacement engine, the timing controller sends a global "latch" signal when it confirms that all sub-blocks, the corresponding physical frame addresses, and the generated check blocks are ready. This ensures that all outputs are ready in the same clock cycle for physical writing.

[0057] A computer-readable storage medium storing a plurality of classification programs, the plurality of classification programs being invoked by a processor to execute the method described above.

[0058] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0059] The advantages of the 3D interleaving hardware acceleration method, system, and medium for magnetic tape storage provided by this invention are as follows: Through a 3D displacement engine within the in-memory computing array, and through a 3D collaborative protection mechanism encompassing spatial (cross-track distribution), temporal (non-contiguous frame storage), and logical (dynamic redundancy) aspects, long burst errors (such as track scratches and contiguous frame contamination) are dispersed into independent, correctable short errors, reducing data movement by over 90%, eliminating data movement bottlenecks, and achieving ultra-low latency and high energy efficiency. Compared to 2D interleaving schemes, error correction coverage is improved by 40%, and data integrity is still guaranteed even under magnetic tape media aging or extreme environments (such as high humidity and strong magnetic fields), extending the lifespan of the magnetic tape storage system. Attached Figure Description

[0060] Fig. 1 This is a schematic diagram of the structure of the present invention;

[0061] Fig. 2 A block diagram of 3D interleaving / deinterleaving based on a memory computing architecture;

[0062] Fig. 3 This is a schematic diagram of the three-dimensional data rearrangement and redundancy generation process, which corresponds to the three-dimensional interleaving writing flowchart of the logical block. Detailed Implementation

[0063] The technical solution of the present invention will now be described in detail through specific embodiments. Many specific details are set forth in the following description to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0064] This embodiment addresses a key technical challenge faced by magnetic tape storage systems in resisting long burst errors: Traditional three-dimensional interleaving / deinterleaving schemes rely on the von Neumann architecture, requiring repeated transfer of batch data across tracks and time sequences between storage and computing units, resulting in high latency and high energy consumption; the linear access characteristics of magnetic tape media and its susceptibility to physical damage (such as track scratches and local contamination) require interleaving algorithms to achieve real-time and efficient rearrangement in three dimensions: spatial (multi-track distribution), temporal (multi-frame read / write), and logical (data block redundancy). However, traditional serial computing and hardware accelerators (such as FPGAs) are limited by data movement bottlenecks and low parallelism, making it difficult to meet the stringent requirements of magnetic tape systems for high reliability, low power consumption, and strong real-time performance.

[0065] like Figs. 1 to 3 As shown, the present invention proposes a hardware acceleration method for three-dimensional interleaving of magnetic tape storage, including an in-memory computing storage array, a three-dimensional permutation engine and a dynamic redundancy control module. The three-dimensional permutation engine is integrated inside the in-memory computing storage array and includes a cross-switching network, a redundancy generation network and a shift register chain.

[0066] The specific acceleration method is as follows:

[0067] The obtained logical block is split into N sub-blocks by a cross-connect network and mapped to multiple physical tracks according to the maximum track spacing rule. The physical frame address is dynamically allocated using a pseudo-random sequence generated by the shift register chain, and logically continuous sub-blocks are inserted into physically non-contiguous physical frames.

[0068] The redundancy generation network uses a variable dynamic strategy to generate check blocks, and the cross-switch network allocates the check blocks to the physical track with the highest track health index based on the check block routing logic.

[0069] The dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, and converts the current optimal redundancy ratio into the configuration command of the variable dynamic strategy. At the same time, it sorts the real-time track health index of all physical tracks in descending order to obtain a track health ranking list, and creates a check block routing table based on it. The check block routing table is fed back to the cross switch network to control the check block routing logic of the cross switch network.

[0070] This embodiment utilizes a three-dimensional displacement engine within the in-memory computing array. Through a three-dimensional collaborative protection mechanism encompassing spatial (cross-track distribution), temporal (non-contiguous frame storage), and logical (dynamic redundancy) aspects, it disperses long burst errors (such as track scratches and contiguous frame contamination) into independent, correctable short errors, reducing data movement by over 90%, eliminating data movement bottlenecks, and achieving ultra-low latency and high energy efficiency. Compared to two-dimensional interleaving schemes, error correction coverage is improved by 40%, and data integrity is still guaranteed even under tape media aging or extreme environments (such as high humidity and strong magnetic fields), extending the lifespan of the tape storage system.

[0071] This embodiment designs a multi-granularity parallel computing unit: in the spatial dimension, it utilizes the physical distribution characteristics of the cross-switch network to synchronously map multiple tracks; in the temporal dimension, it supports nonlinear timing transitions through a configurable shift register chain; and in the logical dimension, it integrates a dynamic redundancy generation module to insert adaptive check blocks in situ. It supports irregular data access (such as cross-track contamination recovery), and improves hardware utilization to over 85%.

[0072] Meanwhile, this embodiment achieves real-time sensing of the magnetic tape media status through a dynamic redundancy control module. The track error rate monitoring unit integrated within this module is responsible for real-time monitoring of the error rate of each physical track and comprehensively evaluating the aging degree of the magnetic tape media. Based on the monitoring results, the dynamic redundancy control module can dynamically adjust the redundancy ratio in the redundancy generation network (ranging from 5% to 20%) and optimize the parity block routing logic of the cross-connect network (i.e., prioritizing the allocation of parity blocks to the physical tracks with the highest track health index), thereby improving error correction efficiency by 50% compared to the static solution.

[0073] The acceleration process is explained below according to the system workflow:

[0074] I. Data Input and Initial Storage Stage;

[0075] The raw data is input into the system through the tape read / write interface. The interface parses the LTO or enterprise-grade tape protocol and adapts to the transmission rate (e.g., 10Gbps). After dividing the data into fixed-length (e.g., 1KB) logical blocks, it is transmitted to the in-memory computing array. The storage units in the storage array directly store the logical blocks, with each storage unit corresponding to a physical track. At the same time, the embedded computing unit (PIM) performs preliminary verification (e.g., CRC calculation) to detect data integrity and provide a basis for subsequent processing.

[0076] II. Three-dimensional data rearrangement and redundancy generation stage;

[0077] The in-memory computing array serves as the foundation of the system, consisting of memory cells and embedded computing units (PIMs). It not only stores data but also provides a physical platform for in-situ computing. Furthermore, it integrates a 3D displacement engine within the memory cells, eliminating data transfer overhead and achieving ultra-low latency and high energy efficiency.

[0078] The 3D permutation engine is key to achieving efficient, low-power data rearrangement. It is a distributed circuit module integrated within the storage array, specifically including a crossbar switch network, a redundancy generation network, and a shift register chain.

[0079] 2-1. Cross switch network;

[0080] A crossbar switch network consists of an N×M switch matrix, where N represents the number of sub-blocks and M represents the number of physical tracks. Each crossbar in the switch matrix is ​​a programmable switch used to establish arbitrary connections between sub-blocks (inputs) and physical tracks (outputs). Its routing logic is controlled by a dynamically updatable check block routing table.

[0081] Functions and working principles:

[0082] (a1) Spatial Dimension Mapping: When writing data, the crossbar switch network is responsible for mapping multiple sub-blocks of a logical data block into multiple physical tracks in parallel and non-adjacent manner, according to a preset maximum track spacing rule. For example, mapping the 16 sub-blocks of logical block A... Dispersed writing to tracks that are far apart This transforms potential continuous physical scratches into dispersed, correctable individual errors.

[0083] (a2) Check block routing: According to the instructions of the dynamic redundancy control module, the check blocks (such as RS check blocks) generated by the redundancy generation network are preferentially routed to the physical track with the best health status (i.e. the lowest error rate) to realize intelligent allocation of resources.

[0084] (a3) Data aggregation: When reading data (deinterleaving), the cross switch network performs reverse operation based on the records of the original mapping table to accurately aggregate the sub-blocks read from different tracks back to the original logic block.

[0085] 2-2. Shift Register Chain;

[0086] A shift register chain consists of multiple cascaded shift registers and feedback logic, with a linear feedback shift register (LFSR) at its core. The generator polynomial of the LFSR is configurable, allowing it to produce pseudo-random sequences with different characteristics.

[0087] Functions and working principle:

[0088] (b1) Nonlinear jumps in the time dimension: The shift register chain dynamically generates non-contiguous physical frame addresses for the written data sub-blocks. Specifically, it uses a pseudo-random sequence generated by the LFSR to scramble the addresses of logical frames, breaking the physical continuity of data in the time dimension. For example, logically contiguous sub-blocks... It may be mapped to physically non-adjacent frames. It can effectively prevent the loss of multiple consecutive frames of data due to magnetic tape contamination or head failure. For sub-block index, It is a random number.

[0089] (b2) Timing recovery: When reading data (deinterleaving), the shift register chain can perform the reverse operation using the same generator polynomial and initial seed to accurately recover the original sub-block order.

[0090] 2-3. Redundancy Generator.

[0091] The redundancy generation network consists of a dedicated hardware encoder and decoder array, natively supporting efficient error correction code (ECC) operations, such as Reed-Solomon codes (RS) or low-density parity-check codes (LDPC).

[0092] Functions and working principle:

[0093] (c1) Dynamic Redundancy Generation: This circuit does not employ a fixed redundancy strategy, but rather operates based on real-time instructions (such as redundancy ratio and encoding type) provided by the dynamic redundancy control module. For example, when the magnetic tape medium is in good condition, it may use RS encoding of (239, 223) (approximately 7% redundancy); when magnetic tape medium aging and error rate increases are detected, it automatically switches to RS encoding of (255, 223) (approximately 14% redundancy), thereby maximizing storage density while ensuring reliability.

[0094] (c2) In-situ computation: Since the redundancy generation network is tightly integrated in the storage array, it can directly encode and perform operations on the data in the storage unit to generate check blocks without having to move the data to an external processor, thus completely eliminating the associated latency and power consumption.

[0095] (c3) Error correction: When reading data (deinterleaving), the redundancy generation network uses check blocks to decode and reconstruct the damaged data, thus completing the final error recovery.

[0096] This embodiment achieves high processing efficiency by directly integrating a 3D displacement engine into an in-memory computing storage array. This efficiency improvement stems from multi-dimensional in-situ collaborative processing capabilities, specifically manifested in the following aspects:

[0097] Spatial dimension processing (implemented via a cross-connect network): When a logic block is written, the cross-connect network can complete the parallel, non-proximity mapping of sub-blocks within a single clock cycle, based on predetermined mapping rules and dynamically generated routing logic. Specifically, the network distributes data sub-blocks to multiple physical tracks according to the "maximum track spacing rule," while simultaneously allocating check blocks precisely to the physical track with the highest current health index according to the "check block routing table."

[0098] Compared to traditional solutions where data needs to be transferred serially or in batches between the CPU / FPGA and external memory via a bus, this embodiment eliminates cross-chip data movement, fundamentally removing the main source of latency. Therefore, the spatial dimension of data transfer is transformed from millisecond-level data movement operations to nanosecond-level on-chip routing switching, resulting in an order-of-magnitude improvement in efficiency.

[0099] Time-dimensional processing (implemented via a shift register chain): While the data is spatially mapped, the integrated shift register chain generates non-contiguous physical frame addresses for each sub-block in parallel. Because the shift register chain is adjacent to the memory cells, it can directly apply the calculated addresses to write operations without requiring time-consuming data exchange with the central processing unit or timing controller. This allows the non-linear rearrangement operations in the time dimension to be completed completely synchronously and with zero latency with the mapping operations in the spatial dimension.

[0100] Logical dimension processing (achieved through a redundancy generation network): Similarly, the redundancy generation network directly performs real-time RS / LDPC encoding on the data to be written within the storage array to generate parity blocks. These newly generated parity blocks do not need to go through the traditional "read-transfer-calculation-transfer-writeback" process; instead, they are immediately injected into the crossbar switch network and allocated to the optimal track. This "computation as storage" model simplifies the originally complex redundancy generation process, which requires multiple bus interactions, into a single in-situ calculation.

[0101] This embodiment's 3D permutation engine transforms the processing operations in the spatial, temporal, and logical dimensions from a serial, discrete, and high-latency process under traditional architectures into a parallel, collaborative, and low-latency in-situ processing mode. Since data does not need to leave the storage array, it completely avoids the "memory wall" bottleneck of the von Neumann architecture. This architectural advantage enables the invention not only to perform exceptionally well when processing regular data streams but also to efficiently support irregular data access (such as random recovery across tracks due to local errors), ultimately achieving a more than 3x speedup in 3D interleaving and fully meeting the stringent real-time requirements of high-density magnetic tape storage.

[0102] III. Dynamic Redundancy Control and Closed-Loop Optimization Stage;

[0103] The track error rate monitoring unit of the dynamic redundancy control module counts the read failure rate (such as the number of CRC check errors) of each physical track in real time and converts it into a normalized health index (range 0-1, 1 represents the optimal state); for example, if the error rate of track 3 is 0.15, its track health index can be calculated as 0.85.

[0104] Subsequently, the core of the dynamic redundancy control module is the dynamic redundancy ratio adjustment algorithm and the check block priority allocation rule, which aim to dynamically optimize the error correction strategy based on the real-time health status of the magnetic tape media. Therefore, the dynamic redundancy control module performs two key decisions based on these track health indices from the track error rate monitoring unit:

[0105] Dynamic Redundancy Ratio Adjustment Algorithm: This module incorporates a multi-level threshold-based decision framework. It compares the average health index of the tracks with preset thresholds (e.g., 0.95, 0.8, 0.7) to dynamically adjust the global redundancy ratio. For example, when the average health index drops from 0.9 to below 0.8, the redundancy generation network automatically increases the redundancy strategy from 10% (e.g., 2 parity blocks per 18 data blocks) to 15% (e.g., 3 parity blocks per 17 data blocks) to address the increased error risk.

[0106] Checksum block priority allocation rule: This module generates a list of tracks ranked from highest to lowest health based on the real-time health index of all tracks. Based on this list, it creates a checksum block routing table—a precise set of mapping instructions that assigns the currently healthiest physical track as the storage location for each checksum block to be written.

[0107] Finally, the routing table is sent to the crossbar switch network. Based on the table's instructions, the crossbar switch network precisely routes the parity blocks to the designated "optimal" track. This closed-loop "monitor-feedback-adjust" control ensures that the system's error correction efficiency can be intelligently and adaptively optimized in real time according to the lifecycle status of the magnetic tape media.

[0108] 3-1. Algorithm for dynamic adjustment of redundancy ratio;

[0109] This algorithm is a multi-level threshold-based decision framework used to automatically adjust redundancy during data writing. Its aim is to maximize storage space utilization while ensuring data reliability.

[0110] As an example of the execution process of the redundancy ratio dynamic adjustment algorithm, the specific steps are as follows:

[0111] (d1) Health index monitoring and calculation;

[0112] Data acquisition: The track error rate monitoring unit in the dynamic redundancy control module counts the read failure rate of each physical track in real time (such as the number of CRC check errors) and converts it into a normalized track health index (range 0-1, 1 represents the optimal state).

[0113] Average value calculation: Before performing a write operation, the system periodically obtains the health index of all active physical tracks from the track error rate monitoring unit. It also calculates the average track health index of the physical tracks involved in the current write operation. The calculation formula is:

[0114] ;

[0115] Where M represents the number of physical tracks involved in this data write operation. For the first The health index of a physical track is a property of the physical medium and is independent of sub-blocks.

[0116] (d2) Algorithm input parameters and threshold presets:

[0117] Preset multi-level health thresholds: High health threshold Medium health threshold and low health threshold At the same time, the redundancy ratio corresponding to each threshold level is preset: low redundancy ratio Standard redundancy ratio and high redundancy ratio and the upper limit of redundancy ratio .

[0118] Input parameters for this embodiment:

[0119] A collection of magnetic health indices for all physical magnetic tracks. ,in For the first The magnetic health index corresponding to each physical magnetic track;

[0120] Preset multi-level health thresholds, for example , , ;

[0121] Redundancy ratios corresponding to each threshold level, for example , , , .

[0122] (d3) Compare the calculated average track health index with the preset threshold to generate the current optimal redundancy ratio. Specifically:

[0123] when When the magnetic tape medium is in its best condition, the lowest redundancy ratio should be used to save space; at this point, the current optimal redundancy ratio is... ;

[0124] when When this occurs, it indicates that the magnetic tape medium is in good condition and the standard redundancy ratio is used. At this point, the current optimal redundancy ratio is... ;

[0125] when When this occurs, it indicates that the magnetic tape medium is in poor condition. The redundancy ratio should be increased to ensure safety. At this point, the current optimal redundancy ratio is... ;

[0126] when When this occurs, it indicates that the magnetic tape media is in a dangerous condition, the highest redundancy ratio should be used, and an alarm may be triggered. At this point, the current optimal redundancy ratio is... .

[0127] (d4) Select the optimal redundancy ratio This translates into specific configuration instructions for the redundancy generation network, such as instructing it to use specific RS encoding parameters (e.g., switching from (239, 223) to (255, 223) to generate the corresponding number of parity blocks.

[0128] In steps (d1) to (d4), the redundancy generation network generates RS / LDPC check blocks according to a variable dynamic strategy generated by the dynamic redundancy control module. This dynamic strategy is adjusted by the dynamic redundancy control module based on the real-time monitored "track health index." For example, when the magnetic tape media is in good condition, the dynamic strategy may insert one check block every 15 sub-blocks (redundancy of approximately 6.7%); while when magnetic tape media aging or an increase in error rate is detected, the strategy automatically switches to inserting two check blocks every 14 sub-blocks (redundancy of approximately 14.3%). The generated check blocks are then combined with track error rate feedback and preferentially allocated to the healthiest physical tracks, thereby completing the adaptive reconstruction of the 3D data.

[0129] 3-2. Check block priority allocation rules;

[0130] The dynamic redundancy control module generates a list of tracks ranked from highest to lowest health based on the real-time track health index of all tracks. Based on this list, a parity block routing table is created. This table is a precise set of mapping instructions that assigns the currently healthiest (lowest error rate) physical track as the storage location for each parity block to be written, maximizing its survival probability. This ensures that the parity block, crucial for data recovery, is always stored in the most reliable physical location.

[0131] The execution process of the check block priority allocation rule:

[0132] (e1) Input parameters;

[0133] A collection of magnetic health indices for all physical magnetic tracks. ,in For the first The magnetic health index corresponding to each physical magnetic track;

[0134] A newly generated, unallocated check block .

[0135] (e2) Health Ranking: Sort the health index of all physical tracks in descending order to generate a health ranking list from healthiest to unhealthiest. ;

[0136] (e3) Optimal track selection: sorted from track health list The search begins at the very beginning (i.e., the healthiest track), selecting the first free physical frame (with available storage space) as the target track. ;

[0137] (e4) Routing table update: Create a new entry in the check block routing table to include check blocks generated by the redundant generation network and awaiting allocation. Address mapping to target track On the idle physical frames.

[0138] (e5) Allocation execution: The routing table entry (i.e., the new entry) is sent as a control instruction to the cross-connect network, which is responsible for establishing a physical connection and writing the parity block precisely to the specified optimal location, thereby establishing a connection between the parity block and the idle physical frame.

[0139] This embodiment achieves a complete dynamic redundancy control method that can perform real-time intelligent optimization based on the life cycle status of the magnetic tape medium by working together with the redundancy ratio dynamic adjustment algorithm and the check block priority allocation rule.

[0140] The dynamic redundancy control module monitors track load status and track health index in real time, dynamically adjusting the redundancy ratio (adjustable from 5% to 20%) and parity block distribution strategy. When a high error rate is detected in a local track, the parity block is automatically rerouted to a low-load track, and the sub-block mapping path is optimized through a cross-connect network to avoid idle storage and computing resources. Hardware utilization is increased to over 85%, and error correction resource allocation efficiency is improved by 50% compared to traditional solutions.

[0141] IV. Timing Synchronization and Physical Writing Stage;

[0142] The core of this phase is ensuring precise temporal coordination of the operations of all hardware modules. This is led by a timing controller (typically implemented as a finite state machine, FSM). This timing controller uses a global clock signal (e.g., 200MHz) as a base clock and precisely schedules the various modules of the 3D displacement engine through a specific, step-by-step coordination process:

[0143] (f1) Instruction issuance and path establishment: The timing controller issues an instruction to enable the cross switch network to complete the path connection from the sub-block and the check block to the target physical track according to the check block routing table.

[0144] (f2) Synchronous triggering and parallel computing: After the routing connection is stable, the timing controller synchronously triggers the shift register chain and the redundancy generation network; the shift register chain calculates the non-contiguous physical frame address within a single clock cycle, while the redundancy generation network begins to perform check block encoding calculations spanning one or more clock cycles.

[0145] (f3) Waiting and Synchronous Latching: After the timing controller waits to receive the "operation complete" signal returned by all modules in the 3D displacement engine, it issues a global "latch" signal when it confirms that all sub-blocks, the corresponding physical frame addresses and the generated check blocks are ready, to ensure that all outputs are ready in the same clock cycle for physical writing.

[0146] Through this series of strictly synchronized and coordinated actions, the system ensures the logical consistency and timing determinism of multi-dimensional operations. Finally, according to the established track-frame mapping relationship, the system writes the sub-block and parity block as a complete, three-dimensionally interleaved data unit to the magnetic tape medium. For example, sub-block A1 is written to physical frame 5 of track 1, while its associated parity block P1 is written to physical frame 8 of track 17, which has a better health condition, thus completing a highly reliable data storage operation resistant to long burst errors.

[0147] V. Uninterruption and Error Recovery Phase;

[0148] After reading a physical block containing multiple sub-blocks and a parity block from the tape, the in-memory computing array detects and locates data errors (i.e., the PIM unit of the in-memory computing array quickly detects the error location (such as ECC decoding)). The cross-switch network aggregates sub-blocks from different physical tracks based on the original mapping table that records the physical storage locations of each sub-block and the parity block. The shift register chain performs reverse operations to restore the original order of the sub-blocks in the logic block. The redundancy generation network uses the parity block to reconstruct the located damaged data. Finally, the restored complete logic block is output to the host through the tape read / write interface, achieving highly reliable data reading.

[0149] This embodiment is based on a storage-computing integrated architecture. It achieves coordinated processing of space (across tracks), time (non-continuous frames), and logic (adaptive redundancy) through a three-dimensional displacement engine within the storage unit. It eliminates data transfer overhead by utilizing hardware-level parallelism of cross-connect network, shift register chain, and redundancy generation network. The dynamic redundancy module optimizes the error correction strategy in real time through closed-loop control, and the timing register ensures strict synchronization of multi-dimensional operations, providing a highly reliable solution for tape storage to resist long burst errors.

[0150] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A hardware acceleration method for three-dimensional interleaving of magnetic tape storage, characterized in that, Acceleration is achieved through an in-memory computing storage array, a three-dimensional permutation engine, and a dynamic redundancy control module. The three-dimensional permutation engine is integrated inside the in-memory computing storage array and includes a cross-switch network, a redundancy generation network, and a shift register chain. The acceleration method is specifically as follows: The obtained logical block is split into N sub-blocks by a cross-connect network and mapped to multiple physical tracks according to the maximum track spacing rule. The physical frame address is dynamically allocated using a pseudo-random sequence generated by the shift register chain, and logically continuous sub-blocks are inserted into physically non-contiguous physical frames. The redundancy generation network uses a variable dynamic strategy to generate check blocks, and the cross-switch network allocates the check blocks to the physical track with the highest track health index based on the check block routing logic. The dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, and converts the current optimal redundancy ratio into the configuration command of the variable dynamic strategy. At the same time, it sorts the real-time track health index of all physical tracks in descending order to obtain a track health ranking list, and creates a check block routing table based on it. The check block routing table is fed back to the cross switch network to control the check block routing logic of the cross switch network.

2. The acceleration method according to claim 1, characterized in that, The cross-switch network includes an N×M switch matrix, where N represents the number of sub-blocks and M represents the number of physical tracks. Each intersection of the switch matrix is ​​a programmable switch used to establish arbitrary connections between the sub-blocks and physical tracks.

3. The acceleration method according to claim 1, characterized in that, The dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, as follows: The read failure rate of each physical track is periodically acquired and converted into a normalized track health index, from which the average track health index is calculated. ; Preset multi-level health thresholds: High health threshold Medium health threshold and low health threshold At the same time, the redundancy ratio corresponding to each threshold level is preset: low redundancy ratio Standard redundancy ratio High redundancy ratio and the upper limit of redundancy ratio ; when When the magnetic tape medium is in its best condition, the current optimal redundancy ratio is achieved. ; when When the magnetic tape medium is in good condition, the optimal redundancy ratio is achieved. ; when When this occurs, it indicates that the magnetic tape medium is in poor condition. At this point, the current optimal redundancy ratio is... ; when When this occurs, it indicates that the magnetic tape medium is in a dangerous condition. At this point, the current optimal redundancy ratio is... And set a threshold to trigger an alarm.

4. The acceleration method according to claim 1, characterized in that, The parity block routing table is fed back to the cross-connect network to control the parity block routing logic of the cross-connect network, specifically as follows: Start searching from the front end of the check block routing table and select the physical track of the first free physical frame as the target track; Create a new entry in the check block routing table to map the address of the check block generated by the redundancy generation network and to be allocated to an idle physical frame on the target track; The new entry is sent as a control command to the crossbar network, thereby establishing a connection between the check block and the idle physical frame.

5. The acceleration method according to claim 1, characterized in that, The specific process of tape deinterleaving is as follows: After reading a physical block containing multiple sub-blocks and a check block from the tape, the in-memory computing array detects and locates data errors within it; The cross switch network aggregates the sub-blocks from different physical tracks based on the original mapping table that records the physical storage locations of each sub-block and the parity block; The shift register chain performs a reverse operation to restore the original order of the sub-blocks in the logic block; The redundancy generation network uses verification blocks to reconstruct the located damaged data; The recovered complete logic block is output to the host via the tape read / write interface to realize data reading.

6. The acceleration method according to claim 1, characterized in that, Setting up a timing controller is used to control the scheduling of various modules in the 3D displacement engine. The specific steps include: Command issuance and path establishment: The timing controller issues commands to enable the cross switch network to complete the routing connection from the sub-block and the check block to the target physical track according to the check block routing table; Synchronous Triggering and Parallel Computation: After the routing connection is stable, the timing controller synchronously triggers the shift register chain and the redundancy generation network; the shift register chain calculates the non-contiguous physical frame address within a single clock cycle, while the redundancy generation network begins to perform check block encoding calculations spanning one or more clock cycles. Waiting and Synchronous Latching: After the timing controller waits to receive the "operation complete" signal returned by all modules in the 3D displacement engine, it issues a global "latch" signal when it confirms that all sub-blocks, the corresponding physical frame addresses, and the generated check blocks are ready, ensuring that all outputs are ready in the same clock cycle for physical writing.

7. A hardware acceleration system for three-dimensional interleaving of magnetic tape storage, characterized in that, It includes an in-memory computing storage array, a 3D displacement engine, and a dynamic redundancy control module. The 3D displacement engine is integrated inside the in-memory computing storage array. The three-dimensional permutation engine includes a cross-switching network, a redundancy generation network, and a shift register chain; The cross-connect network is used to split the acquired logic block into N sub-blocks and scatter them to multiple physical tracks according to the maximum track spacing rule, and to allocate the check blocks generated by the redundancy generation network to the physical tracks with the highest track health index based on the check block routing logic. Redundant generation networks utilize variable dynamic strategies to generate check blocks; The dynamic redundancy control module compares the average track health index of the physical tracks with a preset threshold to generate the current optimal redundancy ratio, and converts the current optimal redundancy ratio into the configuration command of the variable dynamic strategy. At the same time, it sorts the real-time track health index of all physical tracks in descending order to obtain a track health ranking list, and creates a check block routing table based on it. The check block routing table is fed back to the cross switch network to control the check block routing logic of the cross switch network.

8. The acceleration system according to claim 7, characterized in that, It also includes an interface and a controller, which includes a configuration register, a tape read / write interface, and a timing register; Configuration registers are used to configure system parameters; The tape read / write interface is used for communication with external systems; Command issuance and path establishment: The timing controller issues commands to enable the cross switch network to complete the routing connection from the sub-block and the check block to the target physical track according to the check block routing table; Synchronous Triggering and Parallel Computation: After the routing connection is stable, the timing controller synchronously triggers the shift register chain and the redundancy generation network; the shift register chain calculates the non-contiguous physical frame address within a single clock cycle, while the redundancy generation network begins to perform check block encoding calculations spanning one or more clock cycles. Waiting and Synchronous Latching: After the timing controller waits to receive the "operation complete" signal returned by all modules in the 3D displacement engine, it issues a global "latch" signal when it confirms that all sub-blocks, the corresponding physical frame addresses, and the generated check blocks are ready, ensuring that all outputs are ready in the same clock cycle for physical writing.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a plurality of classification programs, which are used by a processor to execute the method as described in any one of claims 1-6.

Images