Chip and system architecture for accelerating neural network computation

The semiconductor device with a hierarchical NoC and 2D mesh network addresses inefficiencies in conventional chip architectures by optimizing PE utilization and communication, enabling high-throughput and low-latency neural network operations.

WO2026067588A1 Publication Date: 2026-04-02MOFFETT TECH CO LTD
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Patent Information

Application Number
PCT/CN2025/124215
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-04-24
Filing Date
2025-09-26
Publication Date
2026-04-02

AI Technical Summary

Technical Problem

Conventional chip architectures for neural network processing suffer from underutilization of compute resources, inefficient data movement, and inflexible communication topologies, leading to latency overhead and difficulty in scaling and supporting diverse neural network operations.

Method used

A semiconductor device with a hierarchical architecture featuring a ring-shaped network-on-chip (NoC) and 2D mesh network interconnects, combined with software and hardware schedulers at different levels, to optimize PE utilization, instruction/data throughput, and parallel scalability, including specialized computing engines and dynamic control logic.

Benefits of technology

The architecture achieves high-throughput, low-latency execution of neural network operations by maximizing PE utilization, supporting flexible and efficient communication, and enabling scalable computation across large neural network models.

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Abstract

A chip architecture and system design for accelerating neural network computation is disclosed. The chip includes a plurality of cores interconnected via a ring-shaped network-on-chip (NoC), each core comprising a 2D mesh of processing elements (PEs) with hierarchical software-and hardware-based schedulers. Each PE includes specialized compute engines, local memory, and dynamic precision conversion logic. The architecture supports flexible instruction dispatch, scalable memory access, and runtime scheduling optimization. The chip can be deployed in chiplet-based configurations, PCIe cards with paired chips, or modular OAM cards with single-chip packaging. Multi-card systems utilize crossbar switch fabrics and direct inter-card links to enable efficient, low-latency communication and high-bandwidth scalability.
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