Heterogeneous computing internet of things for a software radio system

Abstract

This application discloses a heterogeneous computing power gateway for a software-defined radio system, comprising: a multi-protocol conversion module for detecting the interface types of various heterogeneous units and RF front-end modules, loading protocol controllers of corresponding interface types, and realizing data forwarding between multiple protocol controllers and multiple heterogeneous units through on-chip crossbar routing; a storage module; a synchronization module for sending clock signals to multiple heterogeneous units through a clock unit, detecting the clock phase of multiple clock signals through multiple phase detection units, and calibrating multiple clock signals according to preset phase deviations and multiple clock phases through multiple phase calibration units; clock signals and data signals use independent routing; and a control module for identifying the target task characteristics of target data to generate a scheduling plan for the target data. This application is compatible with multiple protocols, has high synchronization accuracy among heterogeneous units, and isolates clock signals and data signals, thus ensuring processing accuracy.

Description

Technical Field

[0001] This application relates to the field of wireless communication network technology, and in particular to a heterogeneous computing power Internet gateway for a software radio system. Background Technology

[0002] The core of software-defined radio (SDR) is to achieve flexible signal processing by loading waveform software onto a standardized hardware and software architecture. Its computing power requirements are evolving towards "high speed + miniaturization" in scenarios such as 5G / 6G communication, portable phased array radar, and vehicle-mounted communication. The core advantage of SDR lies in enabling multi-band, multi-mode signal processing through standardized hardware architecture and flexible waveform software. Its development is moving towards "multi-heterogeneous computing power integration + embedded deployment." Currently, the gateway design of SDR systems (such as USRP and EttusResearch series) has significant technical bottlenecks and cannot meet the high-efficiency collaborative requirements of multiple heterogeneous computing powers (FPGA + GPU + DSP + APU). Specific problems are as follows:

[0003] 1. Lack of multi-protocol compatibility: Existing gateways mostly use a single bus protocol, which only supports interconnection of two or fewer heterogeneous units. When facing the high-speed serial interface of FPGA, the PCIe interface of GPU, and the SRIO interface of DSP, multiple protocol conversion chips need to be deployed, resulting in complex on-board wiring and superimposed transmission delays, which cannot meet the real-time transmission requirements of multi-channel high-speed streaming data.

[0004] 2. Inefficient bandwidth scheduling: Traditional gateways use a static bandwidth allocation mechanism. When radar beamforming (FPGA-intensive), interference classification (GPU-intensive), and signal decoding (DSP-intensive) tasks are performed concurrently, a single unit may consume a large amount of bandwidth while other units have insufficient bandwidth, resulting in a significant decrease in system throughput.

[0005] 3. Synchronization and transmission coupling conflict: In multi-channel coherent processing scenarios, the clock signal is affected by data transmission interference, resulting in phase jitter, which directly leads to a decrease in the signal-to-noise ratio of the synthesized signal and seriously affects the target detection accuracy;

[0006] 4. Insufficient embedded compatibility: Mainstream gateways rely on general-purpose CPUs and desktop-level operating systems to implement protocol parsing, resulting in long startup times and high standby power consumption, making them unsuitable for low-power, fast-start scenarios such as portable and automotive applications. Summary of the Invention

[0007] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a heterogeneous computing power gateway for a software-defined radio system, which is compatible with multiple protocols, has high synchronization accuracy among heterogeneous units, and isolates clock signals and data signals to ensure processing accuracy.

[0008] According to an embodiment of this application, a heterogeneous computing power gateway for a software-defined radio system is applied to an external interconnection unit, the external interconnection unit including a radio frequency front-end module and multiple different heterogeneous units, and the heterogeneous computing power gateway of the software-defined radio system includes:

[0009] The multi-protocol conversion module includes an interface detection unit, a firmware management unit, an on-chip crossover switch router, and multiple different protocol controllers. The interface detection unit is used to detect the interface types of each heterogeneous unit and the RF front-end module. The firmware management unit loads the protocol controller with the corresponding interface type to complete the hardware-level connection between the multiple heterogeneous units and the RF front-end module. The on-chip crossover switch router is used to realize data forwarding between the multiple protocol controllers and the multiple heterogeneous units.

[0010] The storage module is connected to multiple protocol controllers and multiple heterogeneous units, respectively;

[0011] The synchronization module includes a clock unit, multiple phase detection units, and multiple phase calibration units. The clock unit is used to send clock signals to multiple heterogeneous units one-to-one through multiple clock distribution channels. The multiple phase detection units are used to detect the clock phase of multiple clock signals one-to-one. The multiple phase calibration units are used to calibrate multiple clock signals one-to-one according to a preset phase deviation and multiple clock phases. The clock signal and data signal are isolated by using independent PCB traces.

[0012] The control module is connected to the multi-protocol conversion module, the storage module, and the synchronization module, respectively. The control module is used to identify the target task characteristics of the target data and generate a scheduling plan for the target data based on the target task characteristics. The scheduling plan represents the protocol conversion and data forwarding processing path of the target data among multiple protocol controllers and multiple heterogeneous units. The target data is obtained by parsing the raw baseband signal sent by the radio frequency front-end module through the target protocol controller, which is one of the multiple protocol controllers.

[0013] The heterogeneous computing power gateway of the software-defined radio system according to the embodiments of this application has at least the following beneficial effects:

[0014] This application adopts a hardware-level multi-protocol controller integrated design, which reduces the number of on-board components and significantly reduces transmission latency compared to the traditional "multiple adapter chips + software parsing" solution, and solves the "protocol island" problem of multiple heterogeneous units. This application also effectively controls clock phase jitter through physical layer isolation and closed-loop calibration design of clock signals. Compared with the traditional clock signal and data signal multiplexing link solution, the signal synthesis signal-to-noise ratio of this application is significantly improved, which can meet the high-precision processing requirements of phased array radar and other applications.

[0015] According to some embodiments of this application, the control module includes:

[0016] The task feature recognition unit is used to identify the target task features of the target data.

[0017] A scheduling plan determination unit is used to generate a scheduling plan for the target data based on the target task characteristics;

[0018] A bandwidth requirement determination unit is used to determine the target bandwidth requirement based on the target task characteristics, so that the on-chip cross-connect switch routing can dynamically adjust the bandwidth allocation and priority of data transmission based on the target bandwidth requirement.

[0019] According to some embodiments of this application, when the task feature identification unit is used to identify the target task features of the target data, it is specifically configured to distinguish the task type by the frame header identifier of the target data in order to determine the target task features of the target data.

[0020] According to some embodiments of this application, when the bandwidth requirement determination unit determines the target bandwidth requirement based on the target task characteristics, it is specifically configured to match the target bandwidth requirement of the target task characteristics based on a pre-stored feature library, wherein the pre-stored feature library is used to store different bandwidth requirements corresponding to different task characteristics.

[0021] According to some embodiments of this application, when the on-chip crossover switch routing dynamically adjusts the bandwidth allocation and priority of data transmission based on the target bandwidth requirement, the specific configuration is to allocate bandwidth and priority based on the target bandwidth requirement using a weighted fair queue algorithm.

[0022] According to some embodiments of this application, the plurality of protocol controllers include a NoC controller, a PCIe controller, an SRIO controller, and a high-speed serial transceiver.

[0023] According to some embodiments of this application, the plurality of heterogeneous units include FPGA units, GPU units, DSP units, and APU units.

[0024] According to some embodiments of this application, the clock unit employs a temperature-controlled crystal oscillator.

[0025] According to some embodiments of this application, the control module is an embedded control module.

[0026] According to some embodiments of this application, the storage module employs a shared memory pool.

[0027] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0028] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0029] Figure 1 This is a system block diagram of a heterogeneous computing power gateway for a software radio system according to an embodiment of this application.

[0030] Figure label:

[0031] RF front-end module 100;

[0032] Multi-protocol conversion module 200;

[0033] Storage module 300;

[0034] Synchronization module 400;

[0035] Control module 500;

[0036] FPGA Unit 600;

[0037] GPU Unit 700;

[0038] DSP Unit 800;

[0039] APU Unit 900. Detailed Implementation

[0040] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0041] In the description of this application, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0042] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0043] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0044] The following will combine Figure 1 The heterogeneous computing power gateway of the software radio system according to the embodiments of this application will be clearly and completely described. Obviously, the embodiments described below are some embodiments of this application, not all embodiments.

[0045] refer to Figure 1 , Figure 1 This is a system block diagram of a heterogeneous computing power gateway for a software radio system according to an embodiment of this application.

[0046] According to an embodiment of this application, a heterogeneous computing power gateway of a software radio system is applied to an external interconnection unit. The external interconnection unit includes a radio frequency front-end module 100 and multiple different heterogeneous units. The heterogeneous computing power gateway of the software radio system includes a multi-protocol conversion module 200, a storage module 300, a synchronization module 400, and a control module 500.

[0047] The multi-protocol conversion module 200 includes an interface detection unit, a firmware management unit, an on-chip crossover switch router, and multiple different protocol controllers. The interface detection unit is used to detect the interface type of each heterogeneous unit and the RF front-end module 100. The firmware management unit loads the protocol controller of the corresponding interface type to complete the hardware-level connection between multiple heterogeneous units and the RF front-end module 100. The on-chip crossover switch router is used to realize data forwarding between multiple protocol controllers and multiple heterogeneous units.

[0048] The storage module 300 is connected to multiple protocol controllers and multiple heterogeneous units, respectively;

[0049] The synchronization module 400 includes a clock unit, multiple phase detection units, and multiple phase calibration units. The clock unit is used to send clock signals to multiple heterogeneous units one-to-one through multiple clock distribution channels. The multiple phase detection units are used to detect the clock phase of multiple clock signals one-to-one. The multiple phase calibration units are used to calibrate multiple clock signals one-to-one according to a preset phase deviation and multiple clock phases. The clock signal and data signal are isolated by using independent PCB traces.

[0050] The control module 500 is connected to the multi-protocol conversion module 200, the storage module 300, and the synchronization module 400, respectively. The control module 500 is used to identify the target task characteristics of the target data and generate a scheduling plan for the target data based on the target task characteristics. The scheduling plan represents the protocol conversion and data forwarding processing path of the target data among multiple protocol controllers and multiple heterogeneous units. The target data is obtained by parsing the original baseband signal sent by the radio frequency front-end module 100 through the target protocol controller. The target protocol controller is one of the multiple protocol controllers.

[0051] This application adopts a "single-chip multi-core + hardware acceleration" architecture, selects an embedded high-speed protocol controller chip (integrating multiple independent processing cores), and implements protocol conversion and scheduling through on-chip hardware logic to avoid software parsing delay.

[0052] Multiple protocol controllers include a NoC controller, a PCIe controller, an SRIO controller, and a high-speed serial transceiver. Multiple heterogeneous units include an FPGA unit 600, a GPU unit 700, a DSP unit 800, and an APU unit 900. The NoC controller and FPGA unit 600 achieve low-latency, high-bandwidth interconnection via an on-chip network; the PCIe controller interfaces with the GPU unit 700, supporting the offloading of large-scale parallel computing tasks; the SRIO controller connects to the DSP unit 800, meeting the deterministic latency requirements of real-time signal processing; and the high-speed serial transceiver is directly connected to the RF front-end module 100, ensuring lossless sampling and low-jitter transmission of baseband signals.

[0053] In some embodiments, the protocol controllers are interconnected via an on-chip crossbar router. The on-chip crossbar router is the core hub for high-speed data transmission within the gateway hardware architecture. It supports multiple hardware communication protocols such as NoC, PCIe, and SRIO, and can accurately receive various signals from the protocol controller cluster. Based on the signal's protocol attributes and the target heterogeneous unit (FPGA unit 600 / GPU unit 700 / DSP unit 800 / RF front-end module 100, etc.), it performs efficient forwarding. Simultaneously, it can adjust the bandwidth allocation and priority of data transmission based on the real-time operating status of the hardware unit. With the low-latency characteristics of hardware-level forwarding, it ensures efficient, stable, and unblocked data interaction between units during concurrent execution of multiple intensive tasks such as radar beamforming, interference classification, signal decoding, and task collaborative scheduling (APU intensive), avoiding impacts on the overall system throughput due to data transmission link congestion.

[0054] This application employs an "automatic interface identification + dynamic firmware loading" strategy. After the gateway powers on, the interface detection unit detects the interface types of each heterogeneous unit and RF front-end module 100 (such as the NoC signal of the FPGA unit 600 and the PCIe signal of the GPU unit 700). The firmware management unit loads the corresponding interface type protocol controller to complete the hardware-level connection of multiple heterogeneous units and RF front-end modules 100, achieving "plug-and-play" interconnection. This application supports hardware-level conversion of protocol frame formats, such as converting the AXI4-Stream frame of the FPGA unit 600 into the PCIeTLP frame compatible with the GPU unit 700, significantly reducing conversion latency.

[0055] In some embodiments of this application, the clock unit employs a temperature-controlled crystal oscillator. The temperature-controlled crystal oscillator provides a 100MHz main frequency reference clock with a temperature stability of ±0.1ppm. The phase calibration unit uses a PLL (phase-locked loop) to achieve precise phase alignment of multiple clocks, ensuring microsecond-level synchronization between heterogeneous buses such as NoC, PCIe, and SRIO. This application adopts a "physical isolation + phase closed-loop calibration" design: ① Clock signals and data signals use independent PCB trace layers (clock layer located in the middle layer, data layer located on the surface layer) to avoid crosstalk; ② The temperature-controlled crystal oscillator generates a reference clock, which is sent to each heterogeneous unit via a clock distribution channel. Each heterogeneous unit is equipped with an independent PLL calibration unit to compensate for phase deviations caused by temperature drift in real time; ③ The gateway collects the clock phase of each heterogeneous unit through a synchronization monitoring channel (i.e., multiple phase detection units). When the deviation reaches a set threshold, it triggers PLL recalibration to ensure that the clock phase consistency of the entire system meets the requirements.

[0056] In some embodiments of this application, the storage module 300 employs a shared memory pool. In interconnection scenarios involving multiple protocol controllers and multiple heterogeneous units, the shared memory pool architecture avoids the bandwidth waste and latency overhead associated with traditional DMA copying, ensuring high read and write speeds.

[0057] In some embodiments of this application, the control module 500 adopts an embedded control module. The embedded control module integrates an embedded microcontroller, multiple sensor interfaces (temperature, voltage), and a USB debugging interface in its hardware configuration, along with firmware stored in Flash memory. In terms of software configuration, it runs a FreeRTOS real-time operating system and lightweight management firmware (code size ≤ 500KB). The embedded control module in this application can achieve: ① Fast startup: Employing firmware pre-loading technology, it enables fast gateway startup; ② Power consumption management: When the load on heterogeneous units is low, it automatically reduces the clock frequency of the corresponding protocol controller to achieve low standby power consumption; ③ Fault diagnosis: It monitors the temperature of each interface in real time through sensors, triggering bandwidth derating and sending alarm signals when the temperature exceeds the limit. The firmware design based on the real-time operating system in this application significantly shortens startup time and reduces standby power consumption, making it more suitable for resource-constrained scenarios such as portable and vehicle-mounted applications compared to desktop-level management solutions. This application integrates fault self-diagnosis and derating protection functions, exhibiting excellent MTBF performance and significantly reducing maintenance frequency compared to existing solutions, making it suitable for harsh environments such as outdoor and vehicle-mounted environments.

[0058] In some embodiments of this application, the control module 500 includes a task feature identification unit, a scheduling plan determination unit, and a bandwidth requirement determination unit.

[0059] The task feature recognition unit is used to identify the target task features of the target data.

[0060] The scheduling plan determination unit is used to generate a scheduling plan for target data based on the characteristics of the target task.

[0061] The bandwidth requirement determination unit is used to determine the target bandwidth requirement based on the characteristics of the target task, so that the on-chip cross switch routing can dynamically adjust the bandwidth allocation and priority of data transmission based on the target bandwidth requirement.

[0062] In some embodiments of this application, when the task feature identification unit is used to identify the target task features of the target data, it is specifically configured to distinguish the task type by the frame header identifier of the target data in order to determine the target task features of the target data.

[0063] In some embodiments of this application, when the bandwidth requirement determination unit determines the target bandwidth requirement based on the target task characteristics, it is specifically configured to match the target bandwidth requirement of the target task characteristics based on a pre-stored feature library, which is used to store different bandwidth requirements corresponding to different task characteristics.

[0064] In some embodiments of this application, when the on-chip cross-connect switch routing dynamically adjusts the bandwidth allocation and priority of data transmission based on the target bandwidth requirement, the specific configuration is to allocate bandwidth and priority based on the target bandwidth requirement using a weighted fair queue algorithm.

[0065] Understandably, the task feature recognition unit can distinguish task types through the frame header identifier of the target data (e.g., radar beamforming frames are identified by a specific value, and interference classification frames are identified by a specific value). The bandwidth requirement determination unit matches the target bandwidth requirement of the target task features based on a pre-stored feature library (the pre-stored feature library stores different bandwidth requirements corresponding to different task features, such as beamforming, interference classification, and signal decoding, each with corresponding bandwidth requirement levels). The on-chip cross-switch routing uses a weighted fair queue algorithm to allocate bandwidth and priority, with high-priority tasks (such as target tracking) having a weight several times that of ordinary tasks. When a unit's bandwidth is idle, redundant bandwidth is automatically allocated to the load unit, ensuring a significant improvement in overall bandwidth utilization. This application significantly improves bandwidth utilization during multi-task concurrency through dynamic bandwidth scheduling, greatly increasing system throughput compared to static allocation schemes, and solving the problem of bandwidth conflicts in concurrent tasks, especially suitable for dynamic multi-task scenarios such as radar and communication.

[0066] In system integration and deployment, this application adopts a multi-layer PCB design, with the gateway located in the central area of ​​the board, the RF front-end module 100 located on the left side (connected to the gateway via high-speed differential traces), and the FPGA unit 600, GPU unit 700, DSP unit 800, and APU unit 900 located around the gateway.

[0067] (1) The FPGA unit 600 is connected to the gateway through the NoC interface, with the trace length adapted to the requirements and the impedance matching conforming to the standard;

[0068] (2) The GPU unit 700 is connected to the gateway via a PCIe 4.0 x8 interface, using a PCIe Express standard slot;

[0069] (3) The DSP unit 800 is connected to the gateway through the SRIO interface. The differential traces adopt an equal length design to ensure signal integrity.

[0070] (4) The clock signal and data signal are routed in layers. The clock layer is located on the 3rd layer, the data layer is located on the 1st and 6th layers, and the middle layer is the power supply and ground to achieve electromagnetic shielding.

[0071] The heterogeneous computing power gateway of the software radio system of this application will now be described in detail with a specific embodiment.

[0072] System initialization process:

[0073] 1. Power-on startup: The embedded power module outputs DC voltage, the gateway starts first, the embedded microcontroller loads the real-time operating system firmware, then each protocol controller performs self-tests and initializes each interface, and finally each heterogeneous unit completes handshake through the gateway to achieve fast startup;

[0074] 2. Protocol Adaptation: The interface detection unit scans each connection port and identifies the NoC signal of the FPGA unit 600, the PCIe signal of the GPU unit 700, and the SRIO signal of the DSP unit 800. The firmware management unit loads the corresponding protocol firmware within 100ms and establishes a hardware-level connection.

[0075] 3. Synchronous calibration: After the thermostatic crystal oscillator is started and stabilized, the clock distribution chip sends the reference clock to each heterogeneous unit through multiple clock distribution channels. The PLL calibration unit automatically compensates for the phase deviation. After the phase detection unit confirms that the phase deviation of each heterogeneous unit meets the requirements, it sends a "synchronization ready" signal to the APU unit 900.

[0076] 4. System Ready: The APU unit 900 loads radar waveform software and sends initialization parameters (such as beamforming parameters of the FPGA unit 600 and interference classification model of the GPU unit 700) to each heterogeneous unit through the gateway. After each heterogeneous unit responds with "ready", the system enters standby mode.

[0077] Workflow (Portable Phased Array Radar Signal Processing):

[0078] 1. Signal Input and Preprocessing: The radio frequency signal received by the phased array antenna is input to the radio frequency front-end module 100, where it is converted into a digital signal by the AD converter, down-converted to the original baseband signal by the DDC, and then transmitted to the gateway through a high-speed serial interface after preliminary filtering. The transmission delay meets the design requirements.

[0079] 2. Dynamic bandwidth scheduling: The gateway's task feature identification unit extracts the frame header identifier and matches it as a beamforming task. The bandwidth requirement determination unit estimates high bandwidth requirements. At the same time, it detects the interference classification task (medium bandwidth requirement) of GPU unit 700 and the signal decoding task (low bandwidth requirement) of DSP unit 800. The on-chip cross-switch routing uses the WFQ algorithm to allocate bandwidth to ensure the needs of high-priority tasks and to allocate the remaining bandwidth reasonably.

[0080] 3. Multi-computing power collaborative processing: The raw baseband signal first enters the multi-protocol conversion module 200. The control module 500 extracts the frame header identifier and matches it with the feature library, marking the signal as "beamforming task data". Subsequently, the data is encapsulated into NoC protocol format by the protocol controller cluster and forwarded to the FPGA unit 600 via an on-chip crossbar switch. After beamforming is completed by the FPGA unit 600, the data is converted to a shared memory pool compatible format and written to the shared memory pool. The protocol controller cluster monitors the beamforming result data in the shared memory pool, encapsulates it into PCIe protocol format, and forwards it to the GPU unit 700 via an on-chip crossbar switch. After interference classification by the GPU unit 700, the data is converted to a shared memory pool compatible format and written to the shared memory pool. The protocol controller cluster monitors the shared memory pool... The interference classification results data are encapsulated into the SRIO protocol format and forwarded to the DSP unit 800 again through the on-chip crossover switch routing. After the DSP completes signal decoding, the data is converted into a shared memory pool compatible format and written to the shared memory pool. The protocol controller cluster monitors the signal decoding results data in the shared memory pool, converts it into a display and control terminal adapted format, and finally uploads it to the display and control terminal through the hardware conversion of the on-chip crossover switch routing and the format conversion engine. At the same time, the on-chip crossover switch routing collects the bandwidth utilization data of each unit in real time throughout the process and feeds it back to the protocol controller cluster. In conjunction with the scheduling process (task feature identification → bandwidth requirement estimation → weight allocation → WFQ algorithm allocation → dynamic adjustment), the bandwidth and priority of data forwarding are adjusted to ensure unblocked data transmission in each stage.

[0081] 4. Synchronization and Status Monitoring: The synchronization module 400 monitors the clock phase of each heterogeneous unit in real time. When the temperature of a heterogeneous unit rises to a set threshold (detected by a sensor), it automatically reduces the interface bandwidth of that heterogeneous unit and allocates the redundant bandwidth to other load units to ensure stable system operation.

[0082] 5. Task completion: After a single probe task is completed, the gateway controls each heterogeneous unit to enter a low-power mode to achieve low standby power consumption, waiting for the next task to be triggered.

[0083] Test and verification methods:

[0084] 1. Transmission delay test: The time difference between the output signal of the RF front-end module 100 and the received signal of the FPGA unit 600 was collected using a logic analyzer. The test results meet the design requirements.

[0085] 2. Synchronization accuracy test: The phase difference between the clock signals of FPGA unit 600 and DSP unit 800 was measured with an oscilloscope. The test results meet the design requirements.

[0086] 3. Bandwidth scheduling test: High-speed streaming data was generated by a signal generator, and three types of tasks were run concurrently. The utilization rate of each interface was monitored using a bandwidth tester. The results showed that the total bandwidth utilization rate met the design requirements and there was no bandwidth conflict.

[0087] 4. Embedded performance testing: Standby power consumption was measured using a power meter, and the results met the design requirements; startup time was recorded, meeting the fast startup requirements; multiple sets of task commands were issued through the debug interface to verify the real-time performance of embedded management;

[0088] 5. Reliability test: The system operates continuously under wide temperature and humidity conditions without downtime or performance degradation, and its MTBF performance meets the requirements.

[0089] Through the above implementation methods, this application can fully realize the efficient interconnection of multiple heterogeneous computing powers in software radio systems, meet the core requirements of embedded scenarios such as portable phased array radar and vehicle communication, and has reproducibility, stability and engineering feasibility.

[0090] It should be noted that the specific protocol controller types, heterogeneous unit types, and clock unit selections mentioned above are all illustrative examples. In actual applications, they can be replaced with other models according to specific needs and should not be regarded as limitations on this application.

[0091] According to the heterogeneous computing power gateway of the software radio system according to the embodiments of this application, this application adopts a hardware-level multi-protocol controller integrated design. Compared with the traditional "multiple adapter chips + software parsing" scheme, it reduces the number of on-board components, significantly reduces transmission latency, and solves the "protocol island" problem of multiple heterogeneous units. This application also effectively controls clock phase jitter through physical layer isolation and closed-loop calibration design of clock signals. Compared with the traditional clock signal and data signal multiplexing link scheme, the signal synthesis signal-to-noise ratio of this application is significantly improved, which can meet the high-precision processing requirements of phased array radar, etc.

[0092] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0093] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A heterogeneous computing power gateway for a software-defined radio system, characterized in that, Applied to an external interconnect unit, the external interconnect unit including a radio frequency front-end module and multiple different heterogeneous units, the heterogeneous computing power internet gateway of the software radio system includes: The multi-protocol conversion module includes an interface detection unit, a firmware management unit, an on-chip crossover switch router, and multiple different protocol controllers. The interface detection unit is used to detect the interface types of each heterogeneous unit and the RF front-end module. The firmware management unit loads the protocol controller with the corresponding interface type to complete the hardware-level connection between the multiple heterogeneous units and the RF front-end module. The on-chip crossover switch router is used to realize data forwarding between the multiple protocol controllers and the multiple heterogeneous units. The storage module is connected to multiple protocol controllers and multiple heterogeneous units, respectively; The synchronization module includes a clock unit, multiple phase detection units, and multiple phase calibration units. The clock unit is used to send clock signals to multiple heterogeneous units one-to-one through multiple clock distribution channels. The multiple phase detection units are used to detect the clock phase of multiple clock signals one-to-one. The multiple phase calibration units are used to calibrate multiple clock signals one-to-one according to a preset phase deviation and multiple clock phases. The clock signal and data signal are isolated by using independent PCB traces. The control module is connected to the multi-protocol conversion module, the storage module, and the synchronization module, respectively. The control module is used to identify the target task characteristics of the target data and generate a scheduling plan for the target data based on the target task characteristics. The scheduling plan represents the protocol conversion and data forwarding processing path of the target data among multiple protocol controllers and multiple heterogeneous units. The target data is obtained by parsing the raw baseband signal sent by the radio frequency front-end module through the target protocol controller, which is one of the multiple protocol controllers. The control module includes: The task feature recognition unit is used to identify the target task features of the target data. A scheduling plan determination unit is used to generate a scheduling plan for the target data based on the target task characteristics; A bandwidth requirement determination unit is used to determine the target bandwidth requirement based on the target task characteristics, so that the on-chip cross-connect switch routing can dynamically adjust the bandwidth allocation and priority of data transmission based on the target bandwidth requirement.

2. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, When the task feature identification unit is used to identify the target task features of the target data, it is specifically configured to distinguish the task type by the frame header identifier of the target data in order to determine the target task features of the target data.

3. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, When the bandwidth requirement determination unit determines the target bandwidth requirement based on the target task characteristics, it is specifically configured to match the target bandwidth requirement of the target task characteristics based on a pre-stored feature library, wherein the pre-stored feature library is used to store different bandwidth requirements corresponding to different task characteristics.

4. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, When the intra-chip cross-connect switch routing dynamically adjusts the bandwidth allocation and priority of data transmission based on the target bandwidth requirement, the specific configuration is to allocate bandwidth and priority using a weighted fair queue algorithm based on the target bandwidth requirement.

5. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, The plurality of protocol controllers include a NoC controller, a PCIe controller, an SRIO controller, and a high-speed serial transceiver.

6. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, The heterogeneous units include FPGA units, GPU units, DSP units, and APU units.

7. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, The clock unit uses a temperature-controlled crystal oscillator.

8. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, The control module is an embedded control module.

9. The heterogeneous computing power gateway of the software-defined radio system according to claim 1, characterized in that, The storage module uses a shared memory pool.

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