Memory system and repair operation method of memory system

Abstract

A memory system and a repair operation method of the memory system are provided. The memory system includes: a memory cell array including a memory cell group having a plurality of memory cells and a redundant memory cell group having a plurality of redundant memory cells, each of the plurality of memory cells having a retention time equal to or greater than a preset refresh cycle for the memory cell array; a test circuit determining a hold time of each of the plurality of memory cells and the plurality of redundant memory cells, and determining whether each of the plurality of memory cells satisfies a repair condition based on the determined hold time; and a repair circuit that, in response to the test circuit determining that the first memory cell satisfies a repair condition, uses one of the plurality of redundant memory cells to repair the first memory cell having a minimum retention time among the plurality of memory cells.

Description

Technical Field

[0001] This disclosure relates to a memory system and a method for repairing a memory system, and more specifically to a memory system and a method for repairing a memory system by using redundant memory cells to repair memory cells when it is determined that the memory cells meet the repair conditions. Background Technology

[0002] Semiconductor memory is a key component for storing data in computer systems and consists of multiple memory cells. Each memory cell has a physical location where data bits can be stored. The performance of some memory cells can be degraded due to defects in the manufacturing process, physical damage, etc.

[0003] Refresh operations on a memory cell array can be performed on memory cells with degraded performance, but these operations may be unnecessary for other memory cells in the array. Therefore, there is a need for memory devices and repair methods that can address these issues.

[0004] The information described above is intended to enhance understanding of the background of this disclosure and may include information that does not constitute related technology. Summary of the Invention

[0005] To address one or more of the problems described above and / or other problems not explicitly described herein, some example embodiments of this disclosure provide a memory system and a method for repairing a memory system.

[0006] The problems to be solved by this disclosure are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description of the disclosure.

[0007] Some exemplary embodiments of the inventive concept provide a memory system comprising: a memory cell array and a redundant memory cell group, the memory cell group comprising a plurality of memory cells and the redundant memory cell group comprising a plurality of redundant memory cells, each of the plurality of memory cells having a hold time equal to or greater than a preset refresh cycle for the memory cell array; a test circuit for determining the hold time of each of the plurality of memory cells and the hold time of the plurality of redundant memory cells, and determining, based on the determined hold time, whether each of the plurality of memory cells meets a repair condition; and a repair circuit for repairing the first memory cell using one of the plurality of redundant memory cells, in response to the test circuit determining that a first memory cell from the plurality of memory cells having a first hold time meets the repair condition, the first hold time being a minimum hold time.

[0008] Some example embodiments also provide a memory system comprising: a memory cell array including a group of memory cells and a redundant group of memory cells, the group of memory cells including a plurality of memory cells and the redundant group of memory cells including a plurality of redundant memory cells; a repair circuit that uses at least a portion of the plurality of redundant memory cells to repair at least a portion of the plurality of memory cells, such that weak cells in the plurality of memory cells having a hold time less than a minimum period are repaired, and each of the plurality of memory cells has a hold time equal to or greater than a preset refresh period for the memory cell array; and a test circuit that determines the hold time of each of the plurality of memory cells and the hold time of each of the plurality of redundant memory cells, and determines whether each of the plurality of memory cells meets a repair condition based on the determined hold time. In response to determining that one or more memory cells in the plurality of memory cells meet a repair condition and that the hold time of at least a portion of the available redundant memory cells in the redundant group of memory cells is longer than the hold time of each of the one or more memory cells, the repair circuit uses the at least a portion of the available redundant memory cells to repair the one or more memory cells, the one or more memory cells including a memory cell from the plurality of memory cells having a minimum hold time. The repair condition is that the retention time of each of the one or more memory cells is less than a threshold time, which is longer than the minimum period.

[0009] Some example embodiments also provide a method for repairing a memory system, the method comprising: using a test circuit to determine a hold time for each of a plurality of memory cells in a memory cell array, each of the plurality of memory cells having a hold time equal to or greater than a preset refresh cycle for the memory cell array; using the test circuit to determine, based on the determined hold time, whether a memory cell having the minimum hold time among the plurality of memory cells meets a repair condition; and in response to determining that the memory cell meets the repair condition, using a repair circuit to repair the memory cell with one of a plurality of redundant memory cells included in the memory cell array.

[0010] According to some example embodiments of this disclosure, in a memory cell array comprising multiple memory cells including repaired weak cells, one or more memory cells that meet the repair conditions can be repaired, thereby increasing the refresh cycle of the memory cell array. Therefore, the service time for performing read and write operations in the memory device can be increased. That is, the data bandwidth provided from the memory device can be improved.

[0011] Memory devices that have reached a threshold temperature should be operated with a refresh cycle shorter than the existing refresh cycle to ensure data integrity. However, according to some disclosed example embodiments, the threshold temperature can be increased by repairing one or more memory cells in a memory cell array that meet the repair conditions, including repaired weak cells. In other words, the memory device can be used at a threshold temperature higher than a preset threshold temperature without adjusting the refresh cycle of the memory device.

[0012] The effects achievable through this disclosure are not limited to those described above. Those skilled in the art will clearly understand from the description of this disclosure below that any technical effects not mentioned will be present. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments of the inventive concept.

[0014] Figure 2 This is a diagram showing the test circuit and repair circuit connected to the memory device.

[0015] Figure 3 This is a diagram showing the memory interface.

[0016] Figure 4 This is a diagram showing the internal structure of a storage bank.

[0017] Figure 5 This is a diagram showing the detailed configuration of the memory cell array.

[0018] Figure 6 It provides a diagram for explaining the repairs between memory cell groups.

[0019] Figure 7 It provides a diagram for explaining the repairs between bit lines.

[0020] Figure 8 It provides a diagram for explaining the repairs between parts of the bit line.

[0021] Figure 9 It provides a diagram for explaining the repairs between memory cells.

[0022] Figure 10 The diagram shows a graph that provides the processing used to explain the retention time of the memory cell.

[0023] Figure 11 This is a flowchart illustrating a method for calculating the hold time of a memory cell.

[0024] Figure 12This illustrates an example of how bits written to each of multiple memory cells change over time.

[0025] Figure 13 This is a diagram showing the hold time calculated for multiple memory cells in a group of memory cells.

[0026] Figure 14 It shows the order in time. Figure 13 A graph showing the retention time.

[0027] Figure 15 It shows the basis Figure 13 and Figure 14 A diagram illustrating the operation of repairing weak units.

[0028] Figure 16 It shows the basis Figure 13 and Figure 14 A diagram illustrating the operation of repairing memory cells that meet the repair conditions.

[0029] Figure 17 This is a flowchart illustrating the repair operation method for a memory system.

[0030] Figure 18 This is a diagram illustrating an example of an implementation of a semiconductor package.

[0031] Figure 19 This is a cross-sectional view of a semiconductor package. Detailed Implementation

[0032] In this disclosure, "memory cell" and "cell" may refer to the same object and are used interchangeably. For example, "redundant cell" may refer to a redundant memory cell, and "weak cell" may refer to a weak memory cell.

[0033] In the following text, reference will be made to Figures 1 to 19 Some exemplary embodiments of this disclosure are described. Throughout the description, the same reference numerals may refer to the same components.

[0034] Figure 1 This is a block diagram illustrating the memory system. (See reference...) Figure 1 The memory system 100 may include a memory device 110 and a memory controller 120.

[0035] The memory device 110 can be implemented using DRAM, but is not limited to it. For example, the memory device 110 can correspond to Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate (LPDDR) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), etc. Alternatively, the memory device 110 can also be implemented using Static DRAM (SDRAM), High Bandwidth Memory (HBM), or Processor in Memory (PIM).

[0036] The memory device 110 may also be implemented using a non-volatile memory device. For example, the memory device 110 may be implemented using flash memory or resistive memory such as phase-change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (RRAM).

[0037] The memory device 110 may include a memory cell array 111, a row decoder 112, a refresh control circuit 113, and a temperature sensor 114.

[0038] The memory cell array 111 may include multiple word lines, multiple bit lines, and multiple memory cells. The multiple memory cells may be connected to each of the multiple word lines and multiple bit lines, and may be defined by multiple rows and multiple columns. In some example embodiments, rows may be defined by word lines, and columns by bit lines. The multiple memory cells may be implemented using non-volatile memory capable of storing data regardless of power supply or volatile memory capable of storing data when powered, and may be stored by physical fuse-cutting with a laser or by electrical programming.

[0039] The refresh control circuit 113 can send the address of the row to be refreshed from multiple rows to the row decoder 112. The row decoder 112 can perform a refresh operation on the row to be refreshed.

[0040] Temperature sensor 114 can measure the temperature of at least a portion of memory device 110. For example, temperature sensor 114 can measure the temperature of memory cell array 111. The temperature information measured by temperature sensor 114 can be sent to memory controller 120.

[0041] The memory controller 120 may provide signals to the memory device 110 to control the operation of the memory device 110. These signals may include a command CMD and an address ADDR. In some example embodiments, the memory controller 120 may provide the command CMD and address ADDR to the memory device 110 to access the memory cell array 111 and control memory operations (such as reads and writes). Data may be sent from the memory cell array 111 to the memory controller 120 in response to a read operation, and data may be sent from the memory controller 120 to the memory cell array 111 in response to a write operation.

[0042] The command CMD may include activation commands, read and write commands, and refresh commands. In some example embodiments, the command CMD may also include a precharge command. The refresh command may be a command for performing a refresh operation in the memory cell array 111.

[0043] In response to receiving a refresh command, the memory device 110 can perform a refresh operation in the memory cell array 111 for each preset refresh cycle.

[0044] The refresh period of memory cell array 111 can be determined based on the minimum hold time among the hold times of memory cells used for actual memory operations (e.g., excluding memory cells repaired using redundant cells) in memory cell array 111. For example, the refresh period can be determined to be equal to or less than the minimum hold time among the hold times of memory cells used for actual memory operations in memory cell array 111. In response to repairing a memory cell with the minimum hold time among the memory cells used for actual memory operations, memory controller 120 can set the refresh period of memory cell array 111 to a refresh period longer than a preset refresh period.

[0045] The memory controller 120 can determine the refresh cycle of the memory cell array 111 based on the temperature measured by the temperature sensor 114. For example, in response to an increase in the temperature measured by the temperature sensor 114, the memory controller 120 can set the refresh cycle of the memory cell array to a refresh cycle shorter than a preset refresh cycle. For example, if it is determined that the temperature measured by the temperature sensor is equal to or greater than a threshold temperature, the memory controller 120 can set the refresh cycle of the memory cell array 111 to a refresh cycle shorter than a preset refresh cycle. If the temperature of the memory cell array 111 increases, the charge retention capacity of the memory cell array 111 decreases, thereby increasing the risk of data loss, and therefore, refresh operations can be performed more frequently than the existing refresh cycle to ensure data integrity. The memory controller 120 can raise the threshold temperature in response to repairing the memory cell in the memory cell array 111 that has the minimum retention time for actual memory operation.

[0046] In some example embodiments, the memory controller 120 may access the memory device 110 in response to a request from a host outside the memory system 100. The memory controller 120 may communicate with the host using various protocols.

[0047] Figure 2 This is a diagram showing a test circuit 140 and a repair circuit 150 connected to a memory device 110. The test circuit 140 and the repair circuit 150 can be implemented in hardware and / or software.

[0048] Test circuit 140 can perform test operations on memory device 110. For example, test circuit 140 can perform test operations on memory cells included in memory cell array 111. Test circuit 140 can store specific data in memory cell array 111 and read data, and determine whether the test operation passes or fails based on whether the read data is the same as the specific data.

[0049] Test circuit 140 can test memory device 110 via channel 42. Channel 142 may include a bus that physically or electrically connects test circuit 140 to memory device 110, and clock CK, command and address CA, and data DQ can be transmitted and received between test circuit 140 and memory device 110 via the bus.

[0050] The test circuit 140 can measure voltage, current, frequency and other variations under various driving conditions of the memory device 110, and test whether the range of variations falls within the expected (and / or optionally predetermined) acceptable range.

[0051] Test circuit 140 can provide commands to memory device 110 to test memory operations. Non-limiting examples of memory commands may include, for example, timing commands for controlling the timing of various operations, access commands for accessing memory, read commands for performing read operations and write commands for performing write operations, mode register write and read commands for performing mode register write and read operations, post-packaging repair (PPR) commands, etc.

[0052] During testing, if test circuit 140 provides a write command and a related address to memory device 110, memory device 110 can receive the write command and the related address, and perform a write operation to write the data received from test circuit 140 to the memory location corresponding to the related address. Similarly, if test circuit 140 provides a read command and a related address to memory device 110, memory device 110 can receive the read command and the related address, and perform a read operation to output the read data from the memory location corresponding to the related address.

[0053] Repair circuit 150 can use redundant cells to repair faulty cells (e.g., weak cells) in memory cell array 111. For example, repair circuit 150 can repair weak cells detected by EDS (Electronic Die Sorting) testing and / or packaging / module / mounting testing of memory device 110 after the semiconductor manufacturing process of memory device 110. Repair circuit 150 can repair memory cells that exhibit unstable voltage values ​​when voltage is applied, or memory cells that are physically damaged or detected as faulty on connected data paths. Repair circuit 150 may cause the address of a redundant cell to be selected instead of the address of the detected weak cell in memory cell array 111.

[0054] Repair circuit 150 can repair weak cells in memory cell array 111 so that the minimum specifications required by memory cell array 111 (e.g., JEDEC specifications, etc.) can be met. For example, weak cells with a hold time shorter than a preset refresh period can be repaired so that memory cell array 111 can be refreshed at the minimum refresh period required by memory cell array 111 (e.g., 64 ms) or a longer refresh period. The preset refresh period can be equal to or greater than the minimum refresh period.

[0055] Repair circuit 150 can repair memory cells having a hold time equal to or greater than a preset refresh cycle for memory cell array 111 (e.g., the minimum refresh cycle required for memory cell array 111). For example, if test circuit 140 determines that a specific memory cell in memory cell array 111 (e.g., the memory cell with the minimum hold time among the memory cells in memory cell array 111 used for actual memory operation) meets the repair conditions, repair circuit 150 can repair the specific memory cell using redundant cells. Test circuit 140 can calculate (e.g., determine) the hold time of a specific memory cell and determine whether the corresponding memory cell meets the repair conditions based on the calculated (e.g., determined) hold time. In this way, the refresh cycle of memory cell array 111 can be increased, thereby improving the performance of memory device 110. This will be referred to below. Figures 10 to 15 Let me describe it in detail.

[0056] The repair circuit 150 can store redundancy mapping information, which indicates the address (e.g., row address and / or column address) of the repaired memory cell that has been repaired with redundant addresses (e.g., redundant row address and / or redundant column address).

[0057] Test circuit 140 and repair circuit 150 are shown as being connected to memory device 110 from outside the memory device 110, but some example embodiments are not limited thereto. For example, test circuit 140 and / or repair circuit 150 may be included in memory device 110.

[0058] Figure 3 This is a diagram showing a memory interface 200. The memory interface 200 may include a memory controller 120, test and repair circuitry 210, a multiplexer (MUX) 220, and a physical layer 230. The memory interface 200 can be connected to the memory device 110 via the physical layer 230.

[0059] Test and repair circuit 210 can be used with Figure 2 The test circuit 140 and the repair circuit 150 correspond. For example, it can be achieved by... Figure 2 The test circuit 140 and the repair circuit 150 are combined into a single circuit to implement the test and repair circuit 210.

[0060] The memory controller 120 or the test and repair circuitry 210 selected by the multiplexer 220 can be connected to the memory device 110 via the physical layer 230. That is, the memory device 110 can perform either the general memory operations performed by the memory controller 120 or the test and repair operations performed by the test and repair circuitry 210.

[0061] Test controller 300 can send signals to multiplexer 220 to select memory controller 120 or test and repair circuit 210 as the configuration to be connected to memory device 110.

[0062] The test and repair circuitry 210 is shown in a configuration separate from the memory controller 120, but some example embodiments are not limited to this. For example, the test and repair circuitry 210 may be included in the memory controller 120, and the multiplexer 220 may be omitted from the memory interface 200. Alternatively, the test and repair circuitry 210 may be configured separately. Figure 2 The test circuit 140 and the repair circuit 150 are included, and either the test circuit 140 or the repair circuit 150 may be included in the memory controller 120.

[0063] Figure 4 This is a diagram showing the internal structure of the memory bank 400, and Figure 5 This is a diagram showing a detailed configuration of the memory cell array 111. The memory bank 400 may include the memory cell array 111, a row decoder 112, a column decoder 410, a write driver 420, and an input / output (I / O) sense amplifier 430.

[0064] Reference Figure 5The memory cell array 111 may include a first memory cell group (or memory cell group_1) 510_1 to an nth memory cell group (or memory cell group_n) 510_n, each containing multiple memory cells (where n is a natural number of 2 or greater), and a redundant cell group (or redundant memory cell group) 520 containing multiple redundant cells. Optionally, the memory cell array 111 may include one memory cell group or multiple redundant cell groups.

[0065] The first memory cell group 510_1 to the nth memory cell group 510_n can be configured in the same or similar arrangement as each other. The redundant cell group 520 can be configured in the same or similar arrangement as any one of the first memory cell groups 510_1 to the nth memory cell group 510_n. Although Figure 5 The first memory cell group 510_1 to the nth memory cell group 510_n and the redundant cell group 520 are shown to include the same number (q, where q is any natural number greater than 0) of word lines and the same number (p, where p is any natural number greater than 0) of bit lines, but this is for ease of description and some example embodiments are not limited thereto. Each of the first memory cell group 510_1 to the nth memory cell group 510_n and the redundant cell group 520 may include any number of word lines and bit lines. Individual word lines WL[1] to word lines WL[q], word lines RWL[1] to word lines RWL[q] and bit lines BL[1] to bit lines BL[p], bit lines RBL[1] to bit lines RBL[p] are shown for each group of the memory cell array 111, but some example embodiments are not limited thereto, and two or more groups may share word lines and / or bit lines with each other.

[0066] The memory cells and redundant cells in the memory cell array 111 can be connected to the row decoder 112 via multiple word lines arranged along the row direction, and can be connected to the column decoder 410 via bit lines arranged along the column direction.

[0067] The writing or reading of the first memory cell group 510_1 to the nth memory cell group 510_n and the redundant cell group 520 can be performed using the writing or reading methods of a general semiconductor memory device.

[0068] For example, the row decoder 112, which is connected to the memory cell and the redundant cell via multiple word lines, can decode the row address signal input from the address controller, and the decoded row address signal can activate word lines WL[1] to WL[q] and word lines RWL[1] to RWL[q] of the memory cell array.

[0069] Similarly, the column decoder 410, which is connected to the memory cell and the redundant cell via multiple bit lines, can decode the column address signal. The decoded column address signal can be used to select the bit lines BL[1] to BL[p] and bit lines RBL[1] to RBL[p] of the memory cell array via the column select lines.

[0070] During a write operation, the write driver 420 and the I / O sense amplifier 430 can send write data to the memory cell selected by the row decoder 112 and the column decoder 410. Similarly, during a read operation, the write driver 420 and the I / O sense amplifier 430 can detect data stored in the memory cell selected by the row decoder 112 and the column decoder 410.

[0071] The memory bank 400 may also include control logic (e.g., control logic circuitry). The control logic can control external (e.g., Figure 1 The memory controller 120 receives commands and decodes them.

[0072] The memory cell array 111 can be refreshed in response to the control logic decoding a refresh command. While the memory cell array 111 is being refreshed, the memory bank 400 can be in an inactive state. Therefore, as the refresh cycle of the memory cell array 111 is increased, the activation time of the memory bank 400 can be increased, thereby improving the efficiency of the memory device.

[0073] Parts of the memory cells in the first memory cell group 510_1 to the nth memory cell group 510_n can be repaired using the corresponding redundant cells in the redundant cell group 520. Data to be written to or read from the repaired memory cell can be written to the redundant cell or read from the redundant cell. The following will refer to... Figures 6 to 9 A detailed description of an example of using redundant units to repair memory cells.

[0074] Figures 6 to 9 This diagram illustrates a method for repairing portions of a memory cell using redundant units. For ease of description, an example of repairing memory cells in the first memory cell group 510_1 is shown and described, but some example embodiments are not limited thereto. See also... Figures 6 to 9 The described repair operation can use a repair circuit (e.g., Figure 2 The repair circuit 150 is used to perform the operation.

[0075] Figure 6This provides a diagram for interpreting repairs between memory cell groups. For example, if there is a memory cell CELL[1,3] to be repaired in the first memory cell group 510_1, then the first memory cell group 510_1 can be repaired using the redundant cell group 520. That is, if there is a memory cell CELL[1,3] to be repaired in the first memory cell group 510_1, then the address signal of the first memory cell group 510_1 including the memory cell CELL[1,3] to be repaired can be determined as the address signal for the redundant cell group 520 and processed accordingly.

[0076] Figure 7 This provides a diagram for interpreting the repair between bit lines. For example, if the memory cell CELL[1,3] to be repaired in the first memory cell group 510_1 is connected to the third bit line BL[3], then the memory cell connected to the third bit line BL[3] can be repaired by a cell connected to a bit line RBL[3], which is connected to the redundant cell group 520. That is, the column address signal for the third bit line BL[3] can be determined as the column address signal for a bit line connected to the redundant cell group 520 and processed accordingly.

[0077] Additionally or alternatively, if the memory cell CELL[1,3] to be repaired is connected to the first word line WL[1], the memory cell connected to the first word line WL[1] can be repaired by a cell connected to one of the word lines RWL[1], which is connected to the redundant cell group 520.

[0078] Figure 8 This provides a diagram for interpreting repairs between portions (e.g., segments) of a bit line. A bit line may be divided into two or more segments, and at least one memory cell is connected to two or more segments. For example, if the memory cell CELL[1,3] to be repaired in the first memory cell group 510_1 is connected to a third bit line BL[3], then a portion of the cell including the memory cell CELL[1,3] to be repaired connected to the third bit line BL[3] can be repaired using a portion of the cell connected to one of the bit lines connected to the redundant cell group 520. That is, the column address signal for the third bit line BL[3] can be determined as the column address signal of one of the bit lines connected to the redundant cell group 520, and at least some bits of the row address can be determined as the row address signal of the word line connected to the redundant cell group 520, such that repairs between segments can be performed.

[0079] Additionally or optionally, if the memory cell CELL[1,3] to be repaired is connected to the first word line WL[1], a portion of the memory cell including the memory cell CELL[1,3] to be repaired connected to the first word line WL[1] may be repaired to a portion of the cell connected to a word line RWL[1] connected to the redundant cell group 520.

[0080] Figure 9 This provides a diagram for explaining the repair between memory cells. For example, if there is a memory cell CELL[1,3] to be repaired in the first memory cell group 510_1, then the memory cell CELL[1,3] to be repaired can be repaired using a redundant cell. That is, the column address signal and row address signal for the memory cell CELL[1,3] to be repaired can be determined as the column address signal and row address signal for the redundant cell and processed accordingly, so that the repair operation can be processed on a unit of memory cell.

[0081] Unlike Figures 5 to 9 The example shown may provide an internal redundant unit group in each memory cell group for performing repairs within each memory cell group. For example, a first memory cell group 510_1 may include an internal redundant unit group, and multiple redundant bit lines corresponding to the internal redundant unit group may be arranged. In some example embodiments, the memory cell to be repaired in each memory cell group may be repaired first using the internal redundant unit group provided therein, and if another memory cell to be repaired exists, subsequent repairs may be performed using the redundant unit group 520.

[0082] The retention time of leakage characteristics of multiple memory cells in the first memory cell group 510_1 and multiple redundant cells in the redundant cell group 520 can be used to determine whether each of the multiple memory cells in the first memory cell group 510_1 meets the repair conditions, and memory cells that meet the repair conditions can be repaired. (Refer to...) Figures 10 to 14 Provide a detailed example of calculating (e.g., determining) the hold time of memory cells and redundant cells.

[0083] Figure 10 Graphs 1010 and 1020 are shown to provide a process for interpreting (e.g., determining) the hold time of a memory cell. The hold time of the memory cell can be determined using a test circuit (e.g., Figure 2 The test circuit 140 is used to calculate.

[0084] The first curve 1010 and the second curve 1020 can represent the leakage characteristics of a specific memory cell (or redundant cell) in the memory cell array.

[0085] The first graph 1010 and the second graph 1020 represent the change of voltage (Vstorage) stored in the memory cell over time. For example, the first graph 1010 represents the voltage change after a bit "1" is written to the memory cell, and the second graph 1020 represents the voltage change after a bit "0" is written to the memory cell. The reference voltage Vref is a voltage used for comparison with the voltage stored in the memory cell, wherein if the voltage stored in the memory cell is higher than the reference voltage Vref, a bit "1" can be stored in the memory cell, and if the voltage stored in the memory cell is lower than the reference voltage Vref, a bit "0" can be stored in the memory cell.

[0086] The first time point t1 in the first curve 1010 can represent the time at which the write operation of writing bit "1" is performed. After the first time point t1, the voltage stored in the memory cell may decrease over time due to the generation of leakage current.

[0087] To calculate the hold time of a memory cell, a read operation can be performed at a second time point t2. Since the read value at the second time point t2 is the same as the bit "1" written at the first time point t1, the hold time of the memory cell can be calculated to be longer than the time elapsed from the first time point t1 to the second time point t2. The second time point t2 can be a time point at least after a preset refresh cycle of the memory cell array from the first time point t1. The preset refresh cycle can be equal to or greater than the minimum cycle required by the memory cell array.

[0088] A read operation can be performed at a third time point t3 in response to the read value at the second time point t2 being the same as the bit "1" written at the first time point t1. Since the read value at the third time point t3 is the same as the bit "1" written at the first time point t1, the retention time of the memory cell can be calculated to be longer than the time elapsed from the first time point t1 to the third time point t3.

[0089] A read operation can be performed at a fourth time point t4 in response to the read value at the third time point t3 being the same as the bit "1" written at the first time point t1, or in response to the read value at the third time point t3 being the same as the read value at a previous read time point (i.e., the second time point t2). Since the read value at the fourth time point t4 is different from the bit "1" written at the first time point t1 and different from the read value at the previous time point (i.e., the third time point t3), the retention time of the memory cell can be calculated to be shorter than the time elapsed from the first time point t1 to the fourth time point t4. In other words, the retention time of the memory cell can be calculated (e.g., determined) as the time between (t3 to t1) and (t4 to t1).

[0090] Similarly, the hold time of a memory cell can be calculated by writing a bit "0" into the memory cell and performing a read operation.

[0091] In the second graph 1020, the fifth time point t5 represents the time at which the write operation to write bit "0" is performed. After the fifth time point t5, the voltage stored in the memory cell can increase over time.

[0092] A read operation of a memory cell can be performed at time point t6 to calculate the hold time of the memory cell. Since the read value at time point t6 is the same as the bit "0" written at time point t5, the hold time of the memory cell can be calculated to be longer than the time elapsed from time point t5 to time point t6. Time point t6 can be a point in time after at least a preset refresh cycle of the memory cell array from time point t5. The preset refresh cycle can be equal to or greater than the minimum cycle required by the memory cell array.

[0093] A read operation can be performed at time point t7 in response to the read value at time point t6 being the same as the bit "1" written at time point t5. Since the read value at time point t7 differs from either the bit "0" written at time point t5 or the read value at time point t6, the hold time of the memory cell can be calculated to be shorter than the time elapsed from time point t5 to time point t7. In other words, the hold time of the memory cell can be calculated (e.g., determined) as the time between (t6 to t5) and (t7 to t5).

[0094] Optionally, read operations for calculating the hold time of memory cells can be performed sequentially starting from the most recent point in time since the write operation. For example, in the first graph 1010, a write operation to write a bit "1" can be performed at the first time point t1, and a read operation of the memory cell can be performed at the fourth time point t4. Because the read value at the fourth time point t4 is different from the bit "1" written at the first time point t1, the hold time of the memory cell can be calculated to be shorter than the time elapsed from the first time point t1 to the fourth time point t4.

[0095] A read operation can be performed at a third time point t3 in response to the read value at the fourth time point t4 being different from the bit "1" written at the first time point t1. In response to the read value at the third time point t3 being the same as the bit "1" written at the first time point t1 or different from the read value at a previous read time point (i.e., the fourth time point t4), the retention time of the memory cell can be calculated to be longer than the time elapsed from the first time point t1 to the third time point t3.

[0096] Similarly, in the second graph 1020, a write operation to write bit "0" can be performed at the fifth time point t5, and a read operation of the memory cell can be performed at the seventh time point t7. Because the read value at the seventh time point t7 is different from the bit "0" written at the fifth time point t5, the retention time of the memory cell can be calculated to be shorter than the time elapsed from the fifth time point t5 to the seventh time point t7.

[0097] A read operation can be performed at time point t6 in response to the read value at time point t7 being different from the bit "0" written at time point t5. The retention time of the memory cell can be calculated to be longer than the time elapsed from time point t5 to time point t6, in response to the read value at time point t6 being the same as the bit "0" written at time point t5 or different from the read value at a previous read time point (i.e., time point t7).

[0098] For the same memory cell, leakage characteristics can differ between when bit "0" is written and when bit "1" is written. That is, the trend of charge change over time in the memory cell can differ between when bit "0" is written and when bit "1" is written, and therefore the retention time can be calculated differently.

[0099] The first time point t1 and the fifth time point t5 can represent the time points at which the write operation is performed, rather than fixed time points. For example, the write operation can be performed again before the read operation is performed, after increasing or decreasing the interval between the write and read operations. In some example embodiments, the corresponding time points can be set back to the first time point t1 or the fifth time point t5. For example, the read operation at the third time point t3 can not be performed immediately after the read operation at the second time point t2. Instead, the write operation at the first time point t1 can be performed again, and then the read operation at the third time point t3 can be performed.

[0100] Figure 11 This is a flowchart illustrating a method 1100 for calculating (e.g., determining) the hold time of a memory cell. A test circuit (e.g., Figure 2 The test circuit 140) is used to execute method 1100. Method 1100 can be executed on memory cells and redundant cells.

[0101] At operation S1110, the test circuit can perform a first write operation to write the first bit (e.g., bit "1") to a memory cell whose retention time is to be calculated (e.g., determined), and perform a first read operation on the memory cell after a first time has elapsed since the first write operation. The first time may be longer than a preset refresh period (e.g., 64 ms) of the memory cell array including the memory cell.

[0102] At operation S1120, the test circuit can perform a second write operation to write the first bit to a memory cell, and perform a second read operation to the memory cell after a second time has elapsed since the second write operation. The second time can be longer than a preset refresh cycle of the memory cell array including the memory cell. For example, the second time can be longer or shorter than the first time by a unit time (e.g., 1 ms or 2 ms).

[0103] At operation S1130, if it is determined that the first read value of the memory cell according to the first read operation is different from the second read value of the memory cell according to the second read operation, the test circuit can acquire (e.g., determine) a third time between the first time and the second time. For example, if the first read value is different from the first bit and the second read value is the same as the first bit, or if the first read value is the same as the first bit and the second read value is different from the first bit, the test circuit can acquire (e.g., determine) the third time between the first time and the second time as the hold time of the memory cell or as a candidate hold time of the memory cell.

[0104] At operation S1140, the test circuit can perform a third write operation to write the second bit to a memory cell, and a third read operation to the memory cell after a fourth time interval following the third write operation. The second bit can be the opposite of the first bit (e.g., bit "0"). The fourth time interval can be any time longer than a preset refresh period of the memory cell array including the memory cells.

[0105] Similarly, at operation S1150, the test circuit can perform a fourth write operation to write the second bit to a memory cell, and a fourth read operation to the memory cell after a fifth time interval following the fourth write operation. The fifth time interval can be longer than a preset refresh cycle of the memory cell array including the memory cells. For example, the fifth time interval can be longer or shorter than the fourth time interval by a unit of time.

[0106] At operation S1160, if it is determined that the third read value of the memory cell according to the third read operation is different from the fourth read value of the memory cell according to the fourth read operation, the test circuit can acquire (e.g., determine) a sixth time between the fourth and fifth times. For example, if the third read value is different from the second bit and the fourth read value is the same as the second bit, or if the third read value is the same as the second bit and the fourth read value is different from the second bit, the test circuit can acquire (e.g., determine) the sixth time between the fourth and fifth times as the hold time of the memory cell or as a candidate hold time of the memory cell.

[0107] At operation S1170, the test circuit can calculate (e.g., determine) the shorter of the acquired third time and the acquired sixth time as the hold time of the memory cell.

[0108] Figure 11 The flowcharts shown and the descriptions above are merely examples and can be implemented differently in some examples. For example, one or more operations in the flowchart can be omitted, the order of operations can be changed, one or more operations can be executed in parallel, or one or more operations can be executed multiple times.

[0109] Figure 12 This illustrates an example of how bits written to each of multiple memory cells change over time. Figure 12 The memory cell group can represent Figure 5 Each of the first memory cell group 510_1 to the nth memory cell group 510_n or the redundant cell group 520, but some example embodiments are not limited thereto.

[0110] For each of the multiple memory cells in a group of memory cells, refer to the above. Figure 10 and Figure 11The described method calculates the hold time. The hold time can be calculated sequentially for the entire array (or bank) of memory cells in the memory device, on a unit basis, as a memory cell, bit line, word line, memory cell group, or memory cell array, or the hold time can be calculated in parallel for one or more memory cells.

[0111] The first operation 1210 illustrates an example of performing a specific write operation on each of a plurality of memory cells in a group of memory cells. For example... Figure 12 As shown, different bits can be written to each of multiple memory cells. Alternatively, the same bit ("0" or "1") can be written to all of multiple memory cells.

[0112] The second operation 1220 illustrates an example of performing a read operation on each of a plurality of memory cells in a group of memory cells after a desired (and / or optionally predetermined) time has elapsed since the write operation. It can be seen that the bits written to some memory cells CELL[3,2] and CELL[3,p] are toggled over time. The retention time of the memory cells with the toggled bits can be calculated as equal to or less than the time elapsed from the write operation to the read operation. On the other hand, the retention time of other memory cells without the toggled bits can be calculated as exceeding the time elapsed from the write operation to the read operation.

[0113] Figure 13 This is a diagram showing the hold time calculated for multiple memory cells in the first memory cell group 510_1, and Figure 14 It shows the order in time. Figure 13 A graph showing the retention time. For example, the retention time of memory cell CELL[i,j] at the point where the i-th word line and the j-th bit line intersect each other is represented as rt[i,j] (where i is from 1 to q, j is from 1 to p, (where p and q are natural numbers of 2 or greater)).

[0114] Reference Figure 14 Memory cells CELL[1,1] and CELL[2,1] with hold times rt[1,1] and rt[2,1] that are less than the preset refresh period (Tset) or minimum period (e.g., minimum refresh period (Tmin)) required by the memory cell array are weak cells, and major repairs can be performed using redundant cells.

[0115] The refresh cycle of the memory cell array can be set to be equal to or less than the minimum hold time of the memory cells in the memory cell array used for actual memory operations. Therefore, in the case of a weak cell being repaired, the redundant cell corresponding to the weak cell is operated instead, and thus the minimum hold time of the memory cells in the memory cell array used for actual memory operations can be increased, and the refresh cycle (Tset) of the memory cell array can be set to be equal to or greater than the minimum cycle (Tmin) required by the memory cell array.

[0116] Secondary repairs can be performed on memory cells that meet the repair conditions. Memory cells with poor leakage characteristics can be further repaired. For example, memory cells CELL[2,2], CELL[1,3], and CELL[2,3] with hold times less than the threshold time (Tthr) can be further repaired. That is, by also repairing memory cells other than the weak cells, the minimum hold time of the memory cells used for actual memory operations in the memory cell array can be increased to the threshold time (Tthr) or greater, and the refresh cycle of the memory cell array can be set to the threshold time (Tthr) or greater.

[0117] Figure 15 It shows the basis Figure 13 and Figure 14 A diagram illustrating the operation of repairing the weak unit 1510, and Figure 16 It shows the basis Figure 13 and Figure 14 A diagram illustrating the operation of memory cell 1610 that meets the repair conditions. Figure 15 and Figure 16 The repair operation can use a repair circuit (e.g., Figure 2 The repair circuit 150 is used to perform the operation.

[0118] The available redundant units 1520 and 1620 in the redundant unit group 520 can be used to repair the weak units 1510 and memory units 1610 in the first memory unit group 510_1. The retention time of each of the available redundant units 1520 and 1620 can be longer than the retention time of the unit to be repaired.

[0119] Optionally, weak cell 1510 and memory cell 1610 may be repaired according to some example embodiments and referenced. Figures 6 to 8 To describe. According to Figures 6 to 8The shortest of the retention times of the redundant cells used to repair the memory cell may be longer than the shortest of the retention times of the memory cell to be repaired. For example, if bit line BL[1] connected to weak cell 1510 is replaced by bit line RBL[1] in redundant cell group 520, then the shortest of the retention times of the redundant cells on bit line RBL[1] of redundant cell group 520 may be longer than the shortest of the retention times of the memory cell on bit line BL[1] connected to weak cell 1510.

[0120] Figure 17 This is a flowchart illustrating a repair operation method 1700 for a memory system. Repair operation method 1700 can be used... Figure 2 The repair operation method 1700 is executed by the test circuit 140 and the repair circuit 150. The repair operation method 1700 can be executed on a unit basis, such as memory cell arrays or memory banks. For example, when the repair operation method 1700 executed on one memory cell array or memory bank is terminated, the repair operation method 1700 can be executed on another memory cell array or memory bank, and the repair operation method 1700 can be repeatedly executed on all memory cell arrays in the memory device. Optionally, the repair operation method 1700 can be executed in parallel for multiple memory cell arrays.

[0121] At operation S1710, the test circuit can calculate (e.g., determine) the hold time of each of the plurality of memory cells included in the memory cell array. The test circuit can also calculate (e.g., determine) the hold time of each of the plurality of redundant cells included in the memory cell array.

[0122] At operation S1720, the repair circuit can repair at least one weak cell among a plurality of memory cells that has a hold time shorter than a preset refresh period by using at least one of a plurality of redundant cells. The preset refresh period may be equal to or greater than the minimum period required for the memory cell array.

[0123] At operation S1730, the test circuit can determine whether the memory cell meets the repair condition. For example, the repair condition could be that the memory cell's retention time is less than a threshold time longer than a preset refresh cycle.

[0124] The threshold time can be set based on a preset refresh cycle of the memory cell array. For example, a longer threshold time can be set as the preset refresh cycle increases, allowing for an increase in the number of memory cells to be repaired and an increase in the refresh cycle of the memory cell array. If no memory cell in the memory cell array meets the repair conditions, the repair operation method 1700 for the corresponding memory cell array can be terminated.

[0125] At operation S1740, if a specific memory cell is determined to meet the repair conditions, the test circuit can determine whether a usable redundant cell exists. A usable redundant cell can refer to a redundant cell that has not yet been used to repair other memory cells. A search can be performed within the redundant cell group included in the corresponding memory cell array to find out if a usable redundant cell exists. If a usable redundant cell is determined to exist, the repair circuit can use the usable redundant cell to repair the memory cell. If no usable redundant cell is determined to exist, the repair operation method 1700 for the corresponding memory cell array can be terminated.

[0126] At operation S1750, if it is determined that a usable redundant cell exists, the test circuit can determine whether the hold time of the usable redundant cell is longer than the hold time of the memory cell. If it is determined that the hold time of the usable redundant cell is longer than the hold time of the first memory cell, the repair circuit can use the usable redundant cell to repair the memory cell. That is, a redundant cell with better leakage characteristics than the memory cell can be used to perform the repair operation. On the other hand, if the hold time of the usable redundant cell is shorter than the shortest hold time of the memory cell that meets the repair conditions, the repair operation method 1700 for the memory cell array can be terminated because even if the repair is performed, the minimum hold time of the memory cell in the corresponding memory cell array used for actual memory operation is shortened.

[0127] Optionally, at operation S1760, if there are available redundant units with a hold time longer than the hold time of the memory cells that meet the repair conditions, the repair circuit can use the available redundant units to repair the memory cells. In operations S1740 and S1750, if the number of available redundant units is less than the number of memory cells that meet the repair conditions, the memory cells that meet the repair conditions can be repaired in order of shorter hold times. For example, after a memory cell is repaired using available redundant memory units at operation S1760, the memory controller 120 can control the memory device 110 to write data into the repaired memory cell. This improves the accuracy of the stored data and increases the refresh cycle of the memory cell array, thereby improving the performance and reliability of the memory device 110.

[0128] Figure 17The flowcharts shown and the description above are merely examples and may be implemented differently in some other example embodiments. For example, one or more operations in the flowchart may be omitted, the order of operations may be changed, one or more operations may be performed in parallel, or one or more operations may be performed repeatedly. For example, the repair circuit may repair at least one weak cell in a plurality of memory cells having a hold time less than a preset refresh period by using at least one of a plurality of redundant cells before determining the hold time of each of the plurality of memory cells.

[0129] Figure 18 This is a diagram illustrating an example of an embodiment of the semiconductor package 1800.

[0130] Reference Figure 18 The semiconductor package 1800 may include a stacked memory device 1830 and a host die 1840. The stacked memory device 1830 and the host die 1840 may be stacked on an interpolator 1820, and the interpolator 1820 may be stacked on a package substrate 1810. The semiconductor package 1800 may transmit signals to and receive signals from other external packages or semiconductor devices via solder balls (not shown) attached to the lower part of the package substrate 1810.

[0131] Each of the stacked memory devices 1830 may be implemented based on the High Bandwidth Memory (HBM) standard. However, the aspects are not limited to this, and each of the stacked memory devices 1830 may be implemented based on Graphics Double Data Rate (GDDR), Hybrid Memory Cube (HMC), or Wide I / O standards.

[0132] The stacked memory device 1830 may include a plurality of core dies and buffer dies. At least one of the plurality of core dies may include a memory device (e.g., as previously illustrated and described) Figure 1 (Memory device 110).

[0133] The host die 1840 may include at least one processor (such as a central processing unit (CPU), application processor (AP), graphics processor (GPU), neural processor (NPU), system-on-a-chip (SoC), tensor processor (TPU), vision processor (VPU), image signal processor (ISP), and digital signal processor (DSP)).

[0134] The host die 1840 may include a memory controller (e.g., for controlling the stacked memory device 1830) Figure 1The host die 1840 can send signals to and receive signals from the corresponding stacked memory device via the memory controller 120. Optionally, the memory controller may be included in the stacked memory device 1830.

[0135] The memory controller controls all operations of the stacked memory device 1830. The memory controller can send signals for controlling the stacked memory device 1830 through the physical layer.

[0136] Figure 19 This is a cross-sectional view of the semiconductor package 2000. Figure 19 The semiconductor package 2000 may include a stacked memory device 2100, a host die 2200, an interpolator 2300, and a package substrate 2400. Figure 19 The stacked memory device 2100, host die 2200, interposer 2300, and package substrate 2400 can be respectively connected to Figure 18 The stacked memory device 1830, host die 1840, interpolator 1820, and package substrate 1810 correspond to each other. Although Figure 19 The host die 2200 is shown positioned adjacent to the side surface of the stacked memory device 2100, but some example embodiments are not limited to this. For example, the host die 2200 may be positioned below the stacked memory device 2100.

[0137] Core dies 2120 through 2150 may each include an array of memory cells. Buffer die 2110 may include a physical layer (PHY) 2111 and a direct access area (DAB) 2122. Physical layer 2111 is electrically connected to physical layer 2210 of host die 2200 via interpolator 2300. Stacked memory device 2100 may receive signals from or send signals to host die 2200 via physical layer 2111. Physical layer 2111 may include interface circuitry for buffer die 2110.

[0138] Direct access region 2122 provides an access path for testing stacked memory device 2100 without going through host die 2200. Direct access region 2122 may include conductive means (e.g., ports or pins) capable of direct communication with external test and / or repair equipment. Test signals and data received through direct access region 2122 can be transmitted to core dies 2120 to 2150 via through-silicon vias (TSVs, also known as through-silicon vias) 2101. Data read from core dies 2120 to 2150 for testing core dies 2120 can be transmitted to test equipment via TSV 2101 and direct access region 2122. Therefore, direct access testing and repair can be performed on core dies 2120 to 2150.

[0139] Buffer die 2110 and core dies 2120 to 2150 are electrically connected to each other via TSV 2101 and bump 2102. Buffer die 2110 can receive signals provided for each channel from host die 2200 via bump 2102 assigned to each channel. For example, bump 2102 may be a microbump.

[0140] The host die 2200 can use the stacked memory device 2100 to execute applications supported by the semiconductor package 2000.

[0141] The host die 2200 may include a physical layer 2210 and a memory controller 2220. Optionally, the memory controller 2220 may be disposed separately outside the host die 2200, or may be included in the buffer die 2110.

[0142] Physical layer 2210 may include physical layer 2111 for sending signals to and receiving signals from physical layer 2111 of stacked memory device 2100. Host die 2200 may provide various signals to physical layer 2111 via physical layer 2210. Signals provided to physical layer 2111 may be sent to core dies 2120 to core dies 2150 via interface circuitry between TSV 2101 and physical layer 2111. Host die 2200 may include test and repair circuitry (e.g., test and repair circuitry 210). Figure 3 Similarly, a multiplexer may be included in the host die 2200, such that the memory controller 2220 or test and repair circuitry may be connected to the physical layer 2210 of the host die 2200 according to control signals.

[0143] The memory controller 2220 controls all operations of the stacked memory device 2100. The memory controller 2220 can send signals for controlling the stacked memory device 2100 to the stacked memory device 2100 via the physical layer 2210. The memory controller 2220 can interact with... Figure 1 The memory controller 120 corresponds to this.

[0144] Intercalator 2300 connects stacked memory device 2100 to host die 2200. Intercalator 2300 connects physical layer 2111 of stacked memory device 2100 to physical layer 2210 of host die 2200 and provides a physical path formed of conductive material. Therefore, stacked memory device 2100 and host die 2200 can be stacked on intercalator 2300 to send signals to and receive signals from each other.

[0145] Bump 2103 may be attached to the upper part of package substrate 2400, and solder ball 2104 may be attached to the lower part of package substrate 2400. For example, bump 2103 may be a flip chip bump. Intercalator 2300 may be stacked on package substrate 2400 via bump 2103. Semiconductor package 2000 may transmit signals to and receive signals from other external packages or semiconductor devices via solder ball 2104. For example, package substrate 2400 may be a printed circuit board (PCB).

[0146] One or more of the elements disclosed above may include or be implemented in a processing circuitry system (such as hardware including logic circuitry; a hardware / software combination (such as a processor executing software); or a combination thereof). For example, the processing circuitry system may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

Claims

1. A memory system, comprising: A memory cell array includes a group of memory cells and a redundant group of memory cells. The group of memory cells includes a plurality of memory cells and the redundant group of memory cells includes a plurality of redundant memory cells, wherein each of the plurality of memory cells has a hold time equal to or greater than a preset refresh cycle for the memory cell array. A test circuit is configured to determine the hold time of each of the plurality of memory cells and the hold time of each of the plurality of redundant memory cells, and based on the determined hold times, to determine whether each of the plurality of memory cells meets the repair conditions; and The repair circuit is configured to repair the first memory cell using one of the plurality of redundant memory cells in response to a test circuit determining that a first memory cell with a first hold time from the plurality of memory cells meets the repair conditions, wherein the first hold time is a minimum hold time.

2. The memory system as claimed in claim 1, wherein, The preset refresh cycle is equal to or greater than the minimum refresh cycle required by the memory cell array, and The repair circuit is also configured to repair weak cells from the memory cell array that have a hold time shorter than a preset refresh cycle.

3. The memory system as claimed in claim 1, wherein, The test circuit is also configured to determine whether there are available redundant memory cells in the redundant memory cell group, and The repair circuit is also configured to repair the first memory cell using the available redundant memory cells in response to the test circuit determining that a redundant memory cell is available in the redundant memory cell group.

4. The memory system of claim 3, wherein, The test circuit is also configured to determine whether the hold time of the available redundant memory cell is longer than the first hold time of the first memory cell, and The repair circuit is also configured to repair the first memory cell using the available redundant memory cell in response to the test circuit determining that the hold time of the available redundant memory cell is longer than the first hold time of the first memory cell.

5. The memory system of claim 1, wherein, The repair condition is: the first hold time of the first memory cell is less than the threshold time, and the threshold time is longer than the preset refresh cycle.

6. The memory system of claim 5, wherein, The threshold time is set based on the preset refresh cycle of the memory cell array.

7. The memory system of claim 1, wherein, The test circuit and the repair circuit are implemented as a single circuit.

8. The memory system of claim 1, further comprising: A temperature sensor is configured to measure the temperature of at least a portion of a memory device comprising an array of memory cells; as well as The memory controller is configured to control the memory device, wherein... In response to determining that the temperature measured by the temperature sensor is equal to or greater than a first threshold temperature, the memory controller is configured to set the refresh period of the memory cell array to be shorter than a preset refresh period, and In response to the repair circuit repairing the first memory cell, the memory controller is configured to set a first threshold temperature to a second threshold temperature, the second threshold temperature being greater than the first threshold temperature.

9. The memory system of claim 1, further comprising: A memory controller is configured to control a memory device comprising an array of memory cells, wherein, The memory controller is configured to set the refresh period of the memory cell array to be longer than a preset refresh period in response to the repair circuit repairing the first memory cell.

10. The memory system of claim 1, wherein, The repair circuit is also configured to repair portions of the plurality of memory cells, including the first memory cell, in response to determining that the first memory cell meets the repair conditions.

11. The memory system of claim 10, wherein, The portion of the plurality of memory cells includes a second memory cell on the same bit line or word line as the first memory cell.

12. The memory system of claim 10, wherein, The shortest hold time of the redundant memory cell used to repair the portion of the multiple redundant memory cells is longer than the first hold time of the first memory cell.

13. The memory system according to any one of claims 1 to 12, wherein, The test circuit is also configured as follows: Perform the first write operation, which writes the first bit to the first memory cell. A first read operation of the first memory cell is performed after a first time has elapsed since the first write operation; Perform a second write operation to write the first bit to the first memory cell; A second read operation of the first memory cell is performed after a second time has elapsed since the second write operation, wherein the first time and the second time are longer than a preset refresh cycle, and the second time is longer or shorter than the first time by a unit time. In response to determining that a first read value from a first memory cell based on a first read operation is different from a second read value from a first memory cell based on a second read operation, a third time between the first time and the second time is obtained; and The first hold time of the first memory cell is determined based on the third time.

14. The memory system of claim 13, wherein, The test circuit is configured as follows: Perform a third write operation to write the second bit to the first memory cell, where the second bit is the opposite of the first bit; The third read operation of the first memory cell is performed after a fourth time interval following the third write operation; Perform a fourth write operation to write the second bit to the first memory cell; A fourth read operation of the first memory cell is performed after a fifth time interval following the fourth write operation, wherein the fourth and fifth times are longer than a preset refresh cycle, and the fifth time is longer or shorter than the fourth time by the unit time. In response to determining that the third read value of the first memory cell according to the third read operation is different from the fourth read value of the first memory cell according to the fourth read operation, a sixth time between the fourth time and the fifth time is obtained; and The first hold time of the first memory cell is determined based on the third and sixth times.

15. The memory system of claim 14, wherein, The test circuit is configured to determine the shorter of the third and sixth times as the first hold time of the first memory cell.

16. A memory system, comprising: A memory cell array includes a group of memory cells and a redundant group of memory cells, wherein the group of memory cells includes multiple memory cells and the redundant group of memory cells includes multiple redundant memory cells. The repair circuit is configured to repair at least a portion of the plurality of redundant memory cells using at least a portion of the plurality of memory cells, such that weak cells in the plurality of memory cells having a hold time less than a minimum refresh period are repaired, and each of the plurality of memory cells has a hold time equal to or greater than a preset refresh period for the memory cell array. as well as A test circuit is configured to determine the hold time of each of the plurality of memory cells and the hold time of each of the plurality of redundant memory cells, and to determine whether each of the plurality of memory cells meets the repair conditions based on the determined hold times, wherein, In response to determining that one or more memory cells among the plurality of memory cells meet the repair conditions and that at least a portion of the available redundant memory cells in the redundant memory cell group has a hold time longer than the hold time of each of the one or more memory cells, the repair circuit is configured to repair the one or more memory cells using the at least portion of the available redundant memory cells, wherein the one or more memory cells include the memory cell with the minimum hold time from among the plurality of memory cells, and The repair condition is that the retention time of each of the one or more memory cells is less than a threshold time, and the threshold time is longer than the minimum refresh cycle.

17. A method for repairing a memory system, comprising: A test circuit is used to determine the hold time of each of a plurality of memory cells in a memory cell array, wherein each of the plurality of memory cells has a hold time equal to or greater than a preset refresh cycle for the memory cell array. The test circuit uses a determined hold time to determine whether the memory cell with the shortest hold time from the plurality of memory cells meets the repair conditions; and In response to determining that the memory cell meets the repair conditions, the repair circuit uses one of the multiple redundant memory cells in the memory cell array to repair the memory cell.

18. The repair operation method as described in claim 17, further comprising: Before determining the hold time for each of the plurality of memory cells, at least one of the plurality of redundant memory cells is used to repair at least one weak cell among the plurality of memory cells, wherein the at least one weak cell has a hold time less than a preset refresh cycle, and The preset refresh cycle is equal to or greater than the minimum refresh cycle required by the memory cell array.

19. The repair operation method as described in claim 17, wherein, The steps for repairing the memory cell include: Determine whether any of the plurality of redundant memory cells are available; and In response to determining that there are available redundant memory cells among the plurality of redundant memory cells, the available redundant memory cells are used to repair the memory cells.

20. The repair operation method as described in claim 19, wherein, The steps of repairing the memory cell using available redundant memory cells include: Determine whether the hold time of the available redundant memory cells is longer than the hold time of the memory cells; and In response to determining that the retention time of an available redundant memory cell is longer than the retention time of the memory cell, the available redundant memory cell is used to repair the memory cell.

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