Battery equalization circuit, battery equalization system and method

Abstract

The invention discloses a battery equalization circuit, a battery equalization system and a battery equalization method for a battery pack. The battery pack includes n series-connected cells (n > = 4). The battery equalization circuit comprises m bridge arms, each bridge arm comprises a high-side switch tube and a low-side switch tube, and an intermediate node of each bridge arm is coupled to a first end of an inductor. Wherein one of the m high-side switching tubes and one of the m low-side switching tubes are selected as working switching tube pairs for alternate conduction, so that the first end of the inductor is alternately coupled to the positive electrode of the first target battery or the negative electrode of the second target battery. When n is an even number, the first target battery is one of the (n / 2) + 1 battery to the n battery, the second target battery is one of the 1 battery to the n / 2 battery, and the second end of the inductor is coupled to the positive electrode of the n / 2 battery.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic circuits, and more specifically, to battery balancing circuits, battery balancing systems, and balancing methods. Background Technology

[0002] Battery packs typically consist of several individual cells connected in series. Differences in charging state, impedance, and temperature characteristics among these cells can lead to imbalances. This imbalance reduces the overall capacity and shortens the lifespan of the battery pack. Therefore, battery balancing circuits are needed to regulate this imbalance, maintaining the pack's capacity and extending its lifespan.

[0003] Common battery balancing circuits in the prior art include passive resistor balancing circuits and active balancing circuits that include capacitors, inductors, or transformers. Passive resistor balancing circuits dissipate excess energy through resistors, resulting in low efficiency and high heat generation. Active balancing circuits that include capacitors, inductors, or transformers suffer from problems such as circuit complexity, large size, and lack of stability. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a battery balancing circuit, battery balancing system, and method for battery packs, which improves balancing efficiency while saving circuit cost and size.

[0005] According to an embodiment of the present invention, a battery balancing circuit for a battery pack is proposed. The battery pack includes batteries 1, 2, ..., n connected in series, where n is an integer greater than or equal to 4. The battery balancing circuit includes m bridge arms, each of which includes a high-side switch and a low-side switch connected in series. The intermediate node between the high-side and low-side switches in each bridge arm is coupled to the first terminal of an inductor. One of the m high-side switches and one of the m low-side switches are selected as a working switch pair. This working switch pair is alternately turned on, causing the first terminal of the inductor to be alternately coupled to the positive terminal of a first target battery or the negative terminal of a second target battery to meet the balancing requirements. When n is even, m = n / 2, the first target battery is one of (n / 2) + 1 to n, the second target battery is one of 1 to n / 2, and the second terminal of the inductor is coupled to the positive terminal of the n / 2 battery. When n is odd, m = (n-1) / 2. The first target battery is one of batteries from [(n+1) / 2]+1 to n. The second target battery is one of batteries from 1 to [(n+1) / 2]-1. The second terminal of the inductor is time-divisionally coupled to the positive or negative terminal of battery (n+1) / 2.

[0006] According to an embodiment of the present invention, a battery balancing system is also proposed, including a battery pack and a battery balancing circuit as described above. The battery pack includes batteries numbered 1, 2, ..., n, connected in series, where n is an integer greater than or equal to 4.

[0007] According to an embodiment of the present invention, a method for balancing a battery pack is also proposed, the battery pack comprising batteries 1, 2, ..., n connected in series, where n is an integer greater than or equal to 4. The method includes: coupling the intermediate nodes of m bridge arms to the first end of an inductor, wherein each of the m bridge arms includes a high-side switch and a low-side switch connected in series; selecting one of the m high-side switches and one of the m low-side switches as a working switch pair; alternately turning on the working switch pair to couple the first end of the inductor to the positive terminal of a first target battery or the negative terminal of a second target battery; and wherein when n is even, m = n / 2, and the first target battery is (n / 2) + 1. The first target battery is one of batteries from size n to n / 2, and the second target battery is one of batteries from size 1 to n / 2. The second terminal of the inductor is coupled to the positive terminal of battery n / 2. When n is odd, m = (n-1) / 2, the first target battery is one of batteries from [(n+1) / 2]+1 to n, and the second target battery is one of batteries from size 1 to [(n+1) / 2]-1. The second terminal of the inductor is coupled to the positive or negative terminal of battery (n+1) / 2 in a time-sharing manner. Attached Figure Description

[0008] To better understand this invention, it will be described in detail with reference to the following figures:

[0009] Figure 1 An existing passive resistor equalization circuit 10 is shown;

[0010] Figure 2 An existing active equalization circuit 20 containing capacitors is shown;

[0011] Figure 3 An existing active equalization circuit 30 including a transformer is shown;

[0012] Figure 4 This is a schematic diagram of a battery balancing circuit 41 for a battery pack 40 according to an embodiment of the present invention.

[0013] Figure 5 This is a schematic diagram of a battery balancing circuit 51 for a battery pack 50 according to an embodiment of the present invention.

[0014] Figure 6 A schematic diagram of a battery balancing circuit 61 for a four-cell series-connected battery pack is shown according to an embodiment of the present invention.

[0015] Figures 7A-7D Each of the embodiments of the present invention is shown as follows: Figure 6 The diagram shows the battery equalization circuit 61 operating in four modes.

[0016] Figure 8 A schematic diagram of a battery balancing circuit 81 for a five-cell series battery pack according to an embodiment of the present invention is shown.

[0017] Figures 9A-9D Each of the embodiments of the present invention is shown as follows: Figure 8 The diagram shown illustrates the battery balancing circuit 81 operating in four modes.

[0018] Figure 10 A schematic diagram of a battery balancing system 900 according to an embodiment of the present invention is shown;

[0019] Figure 11 This is a flowchart illustrating a method 1000 for balancing a battery pack according to an embodiment of the present invention. Detailed Implementation

[0020] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0021] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Figure 1 This is an existing passive resistor equalization circuit 10. For example... Figure 1 As shown, the passive resistor equalization circuit 10 includes a bypass resistor and a bypass field-effect transistor (FET) connected in parallel with the battery. In the passive resistor equalization circuit 10, the bypass resistor and bypass FET are used to discharge the battery cells with higher voltage, thereby equalizing the voltage between the battery cells in the battery pack. Although this technical solution is simple, it can only regulate the battery cells with higher voltage, and the excess energy can only be dissipated as heat, resulting in low equalization efficiency.

[0023] Figure 2 This refers to an existing active equalization circuit 20 that includes capacitors. For example... Figure 2 As shown, in the active equalization circuit 20, the capacitor continuously charges and discharges between two adjacent battery cells to balance the capacity of each battery cell in the battery pack. Compared with the passive resistor equalization circuit, this technical solution has improved efficiency, but a large amount of energy is still dissipated during the charging and discharging process of the capacitor, and the energy can only be transferred between adjacent battery cells.

[0024] Figure 3 This refers to an existing active equalization circuit 30 that includes a transformer. For example... Figure 3 As shown, in the active equalization circuit 30, energy can be transferred between the individual battery cells in the battery pack. This technical solution offers fast equalization speed, but the use of a transformer increases circuit cost and size.

[0025] To address the above problems, embodiments of the present invention provide a battery balancing circuit, a battery balancing system, and a method, which can not only improve balancing efficiency but also reduce circuit cost and size.

[0026] Figure 4 This is a schematic diagram of a battery balancing circuit 41 for a battery pack 40 according to an embodiment of the present invention. Figure 4 As shown, the battery pack 40 has several individual cells connected in series between the battery pack terminals V+ and V-, including battery C1 (size 1), battery C2 (size 2), ..., battery Cn (size n), where n is an even number greater than or equal to 4. Figure 4 In this embodiment, the battery balancing circuit 41 includes m bridge arms B1 to Bm and an inductor L1, where m = n / 2. Each bridge arm includes a high-side switch QH and a low-side switch QL connected in series, and the intermediate nodes of the high-side switch QH and the low-side switch QL in each bridge arm are coupled to the first end of the inductor L1. Figure 4As shown, the first high-side switch QH1 of the first bridge arm B1 is coupled to the positive terminal of battery Cn (i.e., battery pack terminal V+), and the first low-side switch QL1 is coupled to the negative terminal of battery C1 (i.e., battery pack terminal V-). The second high-side switch QH2 of the second bridge arm is coupled to the positive terminal of battery Cn-1 (n-1), and the second low-side switch QL2 is coupled to the negative terminal of battery C2; ...; and the second high-side switch QHn / 2 of the m-th bridge arm is coupled to the positive terminal of battery C(n / 2)+1 (n / 2)+1, and the second low-side switch QLn / 2 (n / 2)-2 is coupled to the negative terminal of battery Cn / 2 (n / 2). Simultaneously, the second terminal of inductor L1 is coupled to the positive terminal of battery Cn / 2 (n / 2).

[0027] In an embodiment of the present invention, the battery balancing circuit 41 can select one of m high-side switching transistors QH1 to QHn / 2 and one of m low-side switching transistors QL1 to QLn / 2 as a working switching pair according to the energy transfer requirements between individual batteries, and alternately turn them on, so that the first end of the inductor L1 is alternately coupled to the positive terminal of the first target battery or the negative terminal of the second target battery, thereby realizing energy transfer between batteries. Figure 4 In one embodiment, the first target battery is one of (n / 2)+1 battery C(n / 2)+1 to n battery Cn, and the second target battery is one of (n / 2)+1 battery C1 to n / 2 battery Cn / 2. In one embodiment, the first target battery or the second target battery is the single cell with the highest voltage in the battery pack 40. In another embodiment, the first target battery or the second target battery is the single cell with the lowest voltage in the battery pack 40.

[0028] exist Figure 4 In this embodiment, the battery equalization circuit 41 further includes m-1 high-side blocking switches SH1 to SH(n / 2)-1 and m-1 low-side blocking switches SL1 to SL(n / 2)-1. Specifically, the m-1 high-side blocking switches SH1 to SH(n / 2)-1 are connected in reverse series with the high-side switches QH2 to QHn / 2 in the second bridge arm B2 to the m-th bridge arm Bm, respectively, and the m-1 low-side blocking switches SL1 to SL(n / 2)-1 are connected in reverse series with the low-side switches QL2 to QLn / 2 in the second bridge arm B2 to the m-th bridge arm Bm, respectively.

[0029] like Figure 4As shown, the second high-side switch QH2 of the second bridge arm B2 is coupled to the positive terminal of battery Cn-1 (n-1) through the first high-side blocking switch SH1, the second low-side switch QL2 is coupled to the negative terminal of battery C2 (2) through the first low-side blocking switch SL1, and so on. The second high-side switch QHn / 2 of the m-th bridge arm Bm is coupled to the positive terminal of battery C(n / 2)+1 (n / 2)+1 (n / 2)- ...

[0030] In some embodiments, the high-side blocking switch SH, which is connected in series with the high-side switch QH in the working switch pair, remains on, and the low-side blocking switch SL, which is connected in series with the low-side switch QL in the working switch pair, remains on.

[0031] For example, when battery C1 (size 1) is the second target battery (i.e., the single cell with the highest or lowest voltage in battery pack 40), the first low-side switch QL1 is selected as the operating switch, thereby coupling the first terminal of inductor L1 to the negative terminal of battery C1. When battery Cn-1 (size n-1) is the first target battery (i.e., the single cell with the highest or lowest voltage in battery pack 40), the second high-side switch QH2 is selected as the operating switch, and the first high-side blocking switch SH1, which is connected in series with the second high-side switch QH2, remains on, thereby coupling the first terminal of inductor L1 to the positive terminal of battery Cn-1 (size n-1).

[0032] In one embodiment, when the first high-side switch QH1 and the first low-side switch QL1 form a working switch pair, the energy transfer between the C1~Cn / 2 batteries and the C(n / 2)+1~Cn batteries is realized by the alternating conduction of the first high-side switch QH1 and the first low-side switch QL1.

[0033] In one embodiment, when the second high-side switch QH2 and the second low-side switch QL2 form a working switch pair, the first high-side blocking switch SH1 and the first low-side blocking switch SL1 remain on. Through the alternating on and off of the second high-side switch QH2 and the second low-side switch QL2, energy transfer between the C2~Cn / 2 batteries and the C(n / 2)+1~Cn-1 batteries is realized.

[0034] In one embodiment, when the first high-side switch QH1 and the n / 2 low-side switch QLn / 2 form a working switch pair, the n / 2 low-side blocking switch SL(n / 2)-1 remains on. Through the alternating conduction of the first high-side switch QH1 and the n / 2 low-side switch QLn / 2, energy transfer between the Cn / 2 battery and the C(n / 2)+1 to Cn batteries is realized.

[0035] Figure 5 This is a schematic diagram of a battery balancing circuit 51 for a battery pack 50 according to an embodiment of the present invention. Figure 5 In the battery pack 50, there are batteries C1, C2, ..., Cn connected in series, where n is an odd number greater than 4.

[0036] exist Figure 5 In this embodiment, the battery balancing circuit 51 includes m bridge arms B1 to Bm and an inductor L2, where m = (n-1) / 2. Each bridge arm includes a high-side switch QH and a low-side switch QL connected in series, and the intermediate nodes of the high-side switch QH and the low-side switch QL in each bridge arm are coupled to the first end of the inductor L2. Figure 5 As shown, the first high-side switch QH1 of the first bridge arm B1 is coupled to the positive terminal of battery Cn (i.e., battery pack terminal V+), and the first low-side switch QL1 is coupled to the negative terminal of battery C1 (i.e., battery pack terminal V-); the second high-side switch QH2 of the second bridge arm B2 is coupled to the positive terminal of battery Cn-1 (n-1), and the second low-side switch QL2 is coupled to the negative terminal of battery C2 (2); ... and the (n-1) / 2 high-side switch QH(n-1) / 2 of the m-th bridge arm is coupled to the positive terminal of battery C[(n+1) / 2]+1 (n+1) / 2]+1 (n+1) / 2), and the (n-1) / 2 low-side switch QL(n-1) / 2 is coupled to the negative terminal of battery C[(n+1) / 2]-1 (n+1) / 2 (n+1) / 2). Simultaneously, the second terminal of inductor L2 is time-divisionally coupled to either the positive or negative terminal of battery C(n+1) / 2. Figure 5 In one embodiment, the battery balancing circuit 51 further includes a first gating switch Sm1 and a second gating switch Sm2, used to time-divisionally couple the second terminal of the inductor L2 to the positive and negative terminals of the (n+1) / 2 battery C(n+1) / 2.

[0037] and Figure 4 The embodiments are similar, Figure 5 The battery balancing circuit 51 can also select one of the m high-side switching transistors QH1~QH(n-1) / 2 and one of the m low-side switching transistors QL1~QL(n-1) / 2 as the working switching transistor pair according to the energy transfer requirements between individual batteries, and alternately turn them on, so that the first end of the inductor L2 is alternately coupled to the positive terminal of the first target battery or the negative terminal of the second target battery, thereby realizing the energy transfer between batteries. Figure 5In one embodiment, the first target battery is one of batteries from [(n+1) / 2]+1 to n, and the second target battery is one of batteries from 1 to [(n+1) / 2]-1. In one embodiment, the first target battery or the second target battery is the single cell with the highest voltage in the battery pack 50. In another embodiment, the first target battery or the second target battery is the single cell with the lowest voltage in the battery pack 50.

[0038] For example, when battery C1 (size 1) is the second target battery (i.e., the single cell with the highest or lowest voltage in battery pack 50), the first low-side switch QL1 is selected as the operating switch, thereby coupling the first terminal of inductor L2 to the negative terminal of battery C1. When battery Cn-1 (size n-1) is the first target battery (i.e., the single cell with the highest or lowest voltage in battery pack 50), the second high-side switch QH2 is selected as the operating switch, thereby coupling the first terminal of inductor L2 to the positive terminal of battery Cn-1.

[0039] exist Figure 5 In this embodiment, the battery equalization circuit 51 further includes m-1 high-side blocking switches SH1~SH[(n-1) / 2]-1 and m-1 low-side blocking switches SL1~SL[(n-1) / 2]-1. Specifically, the m-1 high-side blocking switches SH1~SH[(n-1) / 2]-1 are connected in reverse series with the high-side switches QH2~QH(n-1) / 2 in the second bridge arm B2 to the m-th bridge arm Bm, respectively, and the m-1 low-side blocking switches SL1~SL[(n-1) / 2]-1 are connected in reverse series with the low-side switches QL2~QL(n-1) / 2 in the second bridge arm B2 to the m-th bridge arm Bm, respectively.

[0040] like Figure 5 As shown, the second high-side switch QH2 of the second bridge arm B2 is coupled to the positive terminal of battery Cn-1 (n-1) through the first high-side blocking switch SH1, and the second low-side switch QL2 is coupled to the negative terminal of battery C2 (2) through the first low-side blocking switch SL1, ..., and the (n-1) / 2 high-side switch QH(n-1) / 2 of the m-th bridge arm Bm is coupled to the positive terminal of battery C[(n-1) / 2]+1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2)-1 ((n-1) / 2)-1 ((n-1) / 2)-2 ((n-1) / 2)-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2]-1 ((n-1) / 2) ...

[0041] In some embodiments, the high-side blocking switch SH, which is connected in series with the high-side switch QH in the working switch pair, remains on, and the low-side blocking switch SL, which is connected in series with the low-side switch QL in the working switch pair, remains on.

[0042] For example, when battery C1 (size 1) is the second target battery (i.e., the single cell with the highest or lowest voltage in battery pack 50), the first low-side switch QL1 is selected as the operating switch, thereby coupling the first terminal of inductor L2 to the negative terminal of battery C1. When battery Cn-1 (size n-1) is the first target battery (i.e., the single cell with the highest or lowest voltage in battery pack 50), the second high-side switch QH2 is selected as the operating switch, and the first high-side blocking switch SH1, which is connected in series with the second high-side switch QH2, remains on, thereby coupling the first terminal of inductor L2 to the positive terminal of battery Cn-1 (size n-1).

[0043] Figure 6 A schematic diagram of a battery balancing circuit 61 for a four-cell series-connected battery pack 60 according to an embodiment of the present invention is shown. Figure 6 As shown, the battery pack 60 has four individual cells C1 to C4 connected in series (i.e., n = 4). The battery balancing circuit 61 includes a first bridge arm B1, a second bridge arm B2, and an inductor L3. The first bridge arm B1 includes a first high-side switch QH1 and a first low-side switch QL1 connected in series, and the second bridge arm B2 includes a second high-side switch QH2 and a second low-side switch QL2 connected in series. The midpoint between the first high-side switch QH1 and the first low-side switch QL1, and the midpoint between the second high-side switch QH2 and the second low-side switch QL2, are all coupled to the first terminal of the inductor L3. Simultaneously, the second terminal of the inductor L3 is coupled to the positive terminal of battery C2 (number 2). Figure 6 In this embodiment, the battery balancing circuit 61 further includes a first high-side blocking switch SH1 and a first low-side blocking switch SL1, which are connected in reverse series with the second high-side switch QH2 and the second low-side switch QL2, respectively. The first high-side switch QH1 of the first bridge arm B1 is coupled to the positive terminal (i.e., battery pack terminal V+) of battery C4, and the first low-side switch QL1 is coupled to the negative terminal (i.e., battery pack terminal V-) of battery C1. The second high-side switch QH2 of the second bridge arm B2 is coupled to the positive terminal of battery C3 through the first high-side blocking switch SH1, and the second low-side switch QL2 is coupled to the negative terminal of battery C2 through the first low-side blocking switch SL1.

[0044] Figures 7A-7D Each of the embodiments of the present invention is shown as follows: Figure 6 The diagram shows the battery balancing circuit 61 operating in four modes. The following section will use the battery balancing circuit 61 for a four-cell series-connected battery pack 60 as an example, combined with... Figures 7A-7D The four operating modes of the battery balancing circuit 61 will be explained in detail.

[0045] Figure 7A This is a schematic diagram of the battery balancing circuit 61 operating in the first operating mode. When the battery balancing circuit 61 operates in the first operating mode, the first high-side switch QH1 and the first low-side switch QL1 of the first bridge arm B1 are selected as the working switch pair and are alternately turned on, while the second high-side switch QH2 and the second low-side switch QL2 of the second bridge arm B2, along with the first blocking switch pair SH1 and SL1, remain off. Specifically, when the first high-side switch QH1 is on and the first low-side switch QL1 is off, the first high-side switch QH1, inductor L3, and batteries C3 and C4 form a discharge circuit, that is, C3 and C4 discharge to inductor L3, and inductor L3 stores the released electrical energy. Subsequently, the first high-side switch QH1 is turned off and the first low-side switch QL1 is turned on. The first low-side switch QL1, batteries C1 and C2, and inductor L3 form a charging circuit. Inductor L3 charges batteries C1 and C2, transferring stored energy to them. Conversely, if the first low-side switch QL1 is turned on first and the first high-side switch QH1 is turned off, batteries C1 and C2 discharge into inductor L3. Then, the first low-side switch QL1 is turned off again and the first high-side switch QH1 is turned on, transferring stored energy from inductor L3 to batteries C3 and C4. Therefore, when the battery balancing circuit 61 operates in the first working mode, the alternating on / off state of the first high-side switch QH1 and the first low-side switch QL1 enables energy transfer between batteries C1 and C2 and batteries C3 and C4.

[0046] Figure 7BThis is a schematic diagram of the battery balancing circuit 61 operating in the second working mode. When the battery balancing circuit 61 operates in the second working mode, the second high-side switch QH2 and the second low-side switch QL2 of the second bridge arm B2 are selected as the working switch pairs and are alternately turned on, while the first high-side blocking switch pair SH1 and the second low-side blocking switch pair SL1 remain on, and the first high-side switch QH1 and the first low-side switch QL1 of the first bridge arm B1 remain off. Specifically, when the second high-side switch QH2 is on and the second low-side switch QL2 is off, the second high-side switch QH2, the inductor L3, and the battery C3 form a discharge circuit, that is, the battery C3 discharges to the inductor L3, and the inductor L3 converts the released electrical energy into energy storage. Subsequently, the second high-side switch QH2 is turned off and the second low-side switch QL2 is turned on. The second low-side switch QL2, battery C2, and inductor L3 form a charging circuit, and inductor L3 charges battery C2, transferring the stored electrical energy to battery C2. Conversely, if the second low-side switch QL2 is turned on first and the second high-side switch QH2 is turned off, battery C2 is in a discharging state, and inductor L3 stores the electrical energy released by battery C2. Then, the second low-side switch QL2 is turned off and the second high-side switch QH2 is turned on, and inductor L3 transfers the stored electrical energy to battery C3. Therefore, when the battery balancing circuit 61 operates in the second operating mode, energy transfer between battery C2 and battery C3 can be achieved through the alternating conduction of the second high-side switch QH2 and the second low-side switch QL2.

[0047] Figure 7CA schematic diagram of the battery balancing circuit 61 operating in the third operating mode is shown. When the battery balancing circuit 61 operates in the third operating mode, the first high-side switch QH1 of the first bridge arm B1 and the second low-side switch QL2 of the second bridge arm B2 are selected as the working switch pair and are alternately turned on, while the first low-side blocking switch SL1 remains on, and the first low-side switch QL1, the second high-side switch QH2, and the first high-side blocking switch SH1 remain off. Specifically, when the first high-side switch QH1 is on and the second low-side switch QL2 is off, the first high-side switch QH1, the inductor L3, and the batteries C3 and C4 form a discharge circuit, that is, the batteries C3 and C4 discharge to the inductor L3, and the inductor L3 converts the released electrical energy into energy storage. Subsequently, the first high-side switch QH1 is turned off and the second low-side switch QL2 is turned on. The second low-side switch QL2, battery C2, and inductor L3 form a charging circuit, and inductor L3 charges battery C2, transferring the stored electrical energy to battery C2. Conversely, if the second low-side switch QL2 is turned on first and the first high-side switch QH1 is turned off, battery C2 is in a discharging state, and inductor L3 stores the electrical energy released by battery C2. Then, the second low-side switch QL2 is turned off and the first high-side switch QH1 is turned on, and inductor L3 transfers the stored electrical energy to batteries C3 and C4. Therefore, when the battery balancing circuit 61 operates in the third operating mode, the energy transfer between battery C2 and batteries C3 and C4 can be achieved through the alternating conduction of the first high-side switch QH1 and the second low-side switch QL2.

[0048] Figure 7DA schematic diagram of the battery balancing circuit 61 operating in the fourth operating mode is shown. When the battery balancing circuit 61 operates in the fourth operating mode, the first low-side switch QL1 of the first bridge arm B1 and the second high-side switch QH2 of the second bridge arm B2 are selected as the working switch pair and are alternately turned on, while the first high-side blocking switch SH1 remains on, and the first high-side switch QH1, the first low-side blocking switch SL1, and the second low-side switch QL2 remain off. Specifically, when the second high-side switch QH2 is on and the first low-side switch QL1 is off, the second high-side switch QH2, the inductor L3, and the battery C3 form a discharge circuit, that is, the battery C3 discharges to the inductor L3, and the inductor L3 converts the released electrical energy into energy storage. Subsequently, the second high-side switch QH2 is turned off and the first low-side switch QL1 is turned on. The first low-side switch QL1, batteries C1 and C2, and inductor L3 form a charging circuit. Inductor L3 charges batteries C1 and C2, transferring the stored electrical energy to batteries C1 and C2. Conversely, if the first low-side switch QL1 is turned on first and the second high-side switch QH2 is turned off, batteries C1 and C2 are in a discharging state, and inductor L3 stores the electrical energy released by batteries C1 and C2. Then, the first low-side switch QL1 is turned off and the second high-side switch QH2 is turned on, and inductor L3 transfers the stored electrical energy to battery C3. Therefore, when the battery balancing circuit 61 operates in the fourth operating mode, the energy transfer between batteries C1 and C2 and battery C3 can be achieved through the alternating conduction of the second high-side switch QH2 and the first low-side switch QL1.

[0049] Table 1 summarizes the individual cells that enable energy transfer in four operating modes using the battery balancing circuit 61 for the four-cell series battery pack 60.

[0050] Table 1 Battery balancing circuit 61 realizes energy transfer in a single cell

[0051]

[0052] In summary, the battery balancing circuit of this invention can select appropriate high-side switching transistors QH and low-side switching transistors QL to form a working switch pair based on the individual cells with the highest / lowest voltage within the battery pack. By alternately turning on the selected working switch pairs, energy transfer within the battery pack is achieved, ultimately causing the voltage of each individual cell to converge towards the target average voltage. Compared with existing technologies, the battery balancing circuit provided by this invention not only has a simple topology and low cost, but also enables rapid voltage balancing of each cell within the battery pack, effectively improving balancing efficiency.

[0053] Figure 8 A schematic diagram of a battery balancing circuit 81 for a five-cell series-connected battery pack 80 according to an embodiment of the present invention is shown. Figure 8As shown, the battery pack 80 has five individual cells C1 to C5 connected in series (i.e., n = 5). The battery balancing circuit 81 includes a first bridge arm B1, a second bridge arm B2, and an inductor L4. The first bridge arm B1 includes a first high-side switch QH1 and a first low-side switch QL1 connected in series, and the second bridge arm B2 includes a second high-side switch QH2 and a second low-side switch QL2 connected in series. The intermediate node of the first high-side switch QH1 and the first low-side switch QL1, as well as the intermediate node of the second high-side switch QH2 and the second low-side switch QL2, are all coupled to the first terminal of the inductor L3. Figure 8 In this embodiment, the battery balancing circuit 81 further includes a first high-side blocking switch SH1 and a first low-side blocking switch SL1, which are connected in reverse series with the second high-side switch QH2 and the second low-side switch QL2, respectively. The first high-side switch QH1 of the first bridge arm B1 is coupled to the positive terminal (i.e., battery pack terminal V+) of battery C5, and the first low-side switch QL1 is coupled to the negative terminal (i.e., battery pack terminal V-) of battery C1. The second high-side switch QH2 of the second bridge arm B2 is connected in series with the positive terminal of battery C4 through the first high-side blocking switch SH1, and the second low-side switch QL2 is connected in series with the negative terminal of battery C2 through the first low-side blocking switch SL1. Figure 8 In this embodiment, the second terminal of inductor L4 is coupled to the positive terminal of battery C3 via a first selector switch Sm1 or to the negative terminal of battery C3 via a second selector switch Sm2. In other words, the second terminal of inductor L4 can be coupled to either the positive or negative terminal of battery C3 according to the energy transfer requirements of battery pack 80.

[0054] and Figure 6 Similar to the battery equalization circuit 61, the battery equalization circuit 81 also has four operating modes. Figures 9A-9D Each of the embodiments of the present invention is shown as follows: Figure 8 The diagram shows the battery balancing circuit 81 operating in four modes.

[0055] like Figure 9A As shown, when the battery equalization circuit 81 is in the first working mode, the first high-side switch QH1 and the first low-side switch QL1 of the first bridge arm B1 are selected as the working switch pair and are alternately turned on, while the second high-side switch QH2 and the second low-side switch QL2 of the second bridge arm B2, as well as the first blocking switch pair SH1 and SL1, remain off.

[0056] like Figure 9BAs shown, when the battery balancing circuit 81 operates in the second operating mode, the second high-side switch QH2 and the second low-side switch QL2 of the second bridge arm B2 are selected as the working switch pairs and are alternately turned on. At the same time, the first high-side blocking switch pair SH1 and the second low-side blocking switch pair SL1 remain on, while the first high-side switch QH1 and the first low-side switch QL1 of the first bridge arm B1 remain off.

[0057] like Figure 9C As shown, when the battery balancing circuit 81 is operating in the third operating mode, the first high-side switch QH1 of the first bridge arm B1 and the second low-side switch QL2 of the second bridge arm B2 are selected as the working switch pair and are alternately turned on, while the first low-side blocking switch SL1 remains on, and the first low-side switch QL1, the second high-side switch QH2 and the first high-side blocking switch SH1 remain off.

[0058] like Figure 9D As shown, when the battery balancing circuit 81 is in the fourth working mode, the first low-side switch QL1 of the first bridge arm B1 and the second high-side switch QH2 of the second bridge arm B2 are selected as the working switch pair and are alternately turned on, while the first high-side blocking switch SH1 remains on, and the first high-side switch QH1, the first low-side blocking switch SL1 and the second low-side switch QL2 remain off.

[0059] It should be understood that, under the same operating mode, the first selector switch Sm1 and the second selector switch Sm2 are configured to be turned on in a time-sharing manner according to energy transfer requirements. In other words, under the same operating mode, the second terminal of inductor L4 can be time-sharingly coupled to the positive or negative terminal of battery C3 according to the energy transfer requirements of battery pack 80.

[0060] For example, when the battery balancing circuit 81 operates in the second working mode, if the second terminal of inductor L4 is first connected to the negative terminal of battery C3 (i.e., the second selector switch Sm2 is turned on), and the second low-side switch QL2 is turned on, battery C2, inductor L4, the second low-side switch QL2, and the second low-side blocking switch SL1 form a discharge circuit, and inductor L4 stores the electrical energy released by battery C2. Subsequently, the second terminal of inductor L4 is connected to the positive terminal of battery C3 (i.e., the first selector switch Sm1 is turned on), and the second low-side switch QL2 is turned off, while the second high-side switch QH2 is turned on. Battery C4, inductor L4, the second high-side switch QH2, and the first high-side blocking switch SH1 form a charging circuit, and inductor L4 transfers the stored electrical energy to battery C4, thereby realizing the energy transfer between battery C2 and battery C4.

[0061] Table 2 summarizes the individual cells that enable energy transfer in four operating modes using the battery balancing circuit 81 for the five-cell series battery pack 80.

[0062] Table 2 Battery balancing circuit 81 realizes energy transfer in individual cells

[0063]

[0064] Except that the second terminal of inductor L4 can be connected to the positive and negative terminals of battery 3 in a time-sharing manner according to the battery balancing requirements, the working principle of battery balancing circuit 81 in different working modes is the same as that of battery balancing circuit 61, and will not be described again here.

[0065] Figure 10 A schematic diagram of a battery balancing system 900 according to an embodiment of the present invention is shown. Figure 10 As shown, the battery balancing system 900 includes a battery pack 90, a battery balancing circuit 91, a sampling circuit 92, and a control circuit 93. The battery pack 90 has n individual cells connected in series between the battery pack terminals V+ and V-, including cell 1 C1, cell 2 C2, ..., cell n Cn, where n is an integer greater than or equal to 4. The sampling circuit 92 is connected to each individual cell in the battery pack 90 to collect the voltage of each individual cell and output the sampled data. The control circuit 93 receives the sampled data from the sampling circuit 92, determines the state of each individual cell within the entire battery pack 90, identifies the target cell with the highest or lowest voltage, and then determines whether the battery pack balancing start-up conditions are met. When the battery pack balancing start-up conditions are met, the control circuit 93 controls the battery balancing circuit 91 to transfer the electrical energy from the higher-voltage individual cells in the battery pack 90 to the lower-voltage individual cells, thereby achieving voltage balancing among the individual cells in the battery pack 90.

[0066] In one embodiment, the method for the control circuit 93 to initiate battery pack equalization is as follows: calculate the total average voltage of the entire battery pack 90, and calculate the difference between the highest / lowest voltage of a single cell and the total average voltage. When this difference exceeds a preset equalization threshold, it is determined that the equalization requirement for a single cell has been triggered.

[0067] exist Figure 10In this embodiment, the battery pack 90 includes five individual batteries C1 to C5 connected in series. The battery balancing circuit 91 includes a first bridge arm B1 and a second bridge arm B2. Specifically, the first high-side switch QH1 of the first bridge arm B1 is coupled to the positive terminal of battery C5 (i.e., battery pack terminal V+), and the first low-side switch QL1 is coupled to the negative terminal of battery C1 (i.e., battery pack terminal V-). The second high-side switch QH2 of the second bridge arm B2 is coupled to the positive terminal of battery C4, and the second low-side switch QL2 is coupled to the negative terminal of battery C2. The intermediate node between the first high-side switch QH1 and the low-side switch QL1, and the intermediate node between the second high-side switch QH2 and the second low-side switch QL2, are both coupled to the first terminal of inductor L5.

[0068] The battery balancing circuit 91 also includes a first selection switch Sm1 and a second selection switch Sm2, used to time-division multiplex the second terminal of inductor L5 to either the positive or negative terminal of battery C3. It should be understood that when n is even, the second terminal of inductor L5 can be directly coupled to the positive terminal of battery Cn / 2 (size n / 2). In other words, when n is even, the first selection switch Sm1 and the second selection switch Sm2 are not necessary components.

[0069] exist Figure 10 In this embodiment, when the balancing requirement arises, one of the first high-side switch QH1 and the second high-side switch QH2, along with one of the first low-side switch QL1 and the second low-side switch QL2, is selected as the operating switch pair. By alternately turning on the operating switch pair, the first terminal of the inductor L5 is alternately coupled to the positive terminal of the first target battery (i.e., battery C4 or battery C5) or the negative terminal of the second target battery (i.e., battery C1 or battery C2) to meet the balancing requirement.

[0070] like Figure 10 As shown, the battery balancing circuit 91 further includes a first high-side blocking switch SH1 and a first low-side blocking switch SL1, which are connected in reverse series with the second high-side switch QH2 and the second low-side switch QL2, respectively. Specifically, the second high-side switch QH2 of the second bridge arm B2 is coupled to the positive terminal of battery C4 (size 4) through the first high-side blocking switch SH1, and the second low-side switch QL2 is coupled to the negative terminal of battery C2 (size 2) through the first low-side blocking switch SL1. In one embodiment, when the second high-side switch QH2 is selected as the operating switch, the first high-side blocking switch SH1 remains on. In another embodiment, when the second low-side switch QL2 is selected as the operating switch, the first low-side blocking switch SL1 remains on.

[0071] exist Figure 10 In this embodiment, the battery balancing circuit 91 further includes a drive circuit 910. When an balancing demand occurs, the control circuit 93 outputs a switch control signal S.G To drive circuit 910. Responding to switch control signal S G The drive circuit 910 outputs a high-side drive signal GH and a low-side drive signal GL to control the alternating conduction of the working switch pair, respectively. Simultaneously, the control circuit 93 also outputs a first control signal MUX1 and a second control signal MUX2. The first control signal MUX1 controls the high-side blocking switch SH, connected in series with the high-side switch QH in the working switch pair, and the low-side blocking switch SL, connected in series with the low-side switch QL in the working switch pair, to remain on. The second control signal MUX2 controls the first gating switch Sm1 and the second gating switch Sm2 to conduct in a time-division multiplexing manner. It should be understood that when n is even, the control circuit 93 may not output the second control signal MUX2.

[0072] In one embodiment, the method for determining whether the control circuit 93 has ended battery pack equalization is as follows: After equalization is completed, the total average voltage of the entire battery pack 90 is recalculated, and the difference between the highest / lowest voltage individual cell and the total average voltage is calculated. When the difference is less than a preset equalization threshold, the equalization termination condition is met. The control circuit 93 then stops outputting the switch control signal S. G The first control signal MUX1 and the second control signal MUX2.

[0073] exist Figure 10 In the embodiments described, the switching transistors QH, QL, SH, SL, and Sm are all N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). It should be understood that in the embodiments of the present invention, the aforementioned switching transistors can also be other suitable switching transistors, such as insulated-gate bipolar transistors (IGBTs), and the present invention is not limited to the selection of devices.

[0074] Figure 11 This is a flowchart of a method 1000 for balancing a battery pack according to an embodiment of the present invention. The battery pack includes batteries 1, 2, ..., n connected in series, where n is an integer greater than or equal to 4. The method 1000 includes steps 1001 to 1005.

[0075] Step 1001: Couple the intermediate nodes of the m bridge arms to the first end of an inductor, wherein each of the m bridge arms includes a high-side switch and a low-side switch connected in series.

[0076] Step 1002: Select one of the m high-side switching transistors and one of the m low-side switching transistors as the working switching pair.

[0077] Step 1003: Alternately turn on the working switch pair to couple the first end of an inductor to the positive terminal of the first target battery or the negative terminal of the second target battery.

[0078] Step 1004: When n is even, m = n / 2. The first target battery is one of (n / 2) + 1 batteries to n batteries, and the second target battery is one of 1 batteries to n / 2 batteries. The second end of the inductor is coupled to the positive terminal of the n / 2 battery.

[0079] Step 1005: When n is odd, m = (n-1) / 2. The first target battery is one of batteries from [(n+1) / 2]+1 to n. The second target battery is one of batteries from 1 to [(n+1) / 2]-1. The second terminal of the inductor is time-divisionally coupled to the positive or negative terminal of battery (n+1) / 2.

[0080] In step 1003, the first target battery or the second target battery is the single cell with the highest or lowest voltage in the battery pack.

[0081] In one embodiment, the m bridge arms include a first bridge arm, a second bridge arm, ..., and an m-th bridge arm. The first bridge arm is coupled between the positive terminal of battery n and the negative terminal of battery 1; the second bridge arm is coupled between the positive terminal of battery n-1 and the negative terminal of battery 2; and when n is even, the m-th bridge arm is coupled between the positive terminal of battery (n / 2)+1 and the negative terminal of battery n / 2; when n is odd, the m-th bridge arm is coupled between the positive terminal of battery [(n+1) / 2]+1 and the negative terminal of battery [(n+1) / 2]-1.

[0082] In one embodiment, m-1 high-side blocking switches are connected in reverse series with the high-side switches in the second to the m-th bridge arms, respectively; and m-1 low-side blocking switches are connected in reverse series with the low-side switches in the second to the m-th bridge arms, respectively.

[0083] Note that in the flowchart described above, the functions marked in the boxes may occur in a different order than shown in the flowchart. For example, two boxes shown consecutively may actually be executed in essentially parallel order, or they may be executed in reverse order, depending on the specific functions involved.

[0084] It should be understood that, in the embodiments of the present invention, one or more operating modes can be combined to achieve energy transfer between individual battery cells. The energy transfer implementation processes listed in the present invention are merely illustrative. In the specification, related terms such as "first" and "second" are merely used to distinguish one entity or action from another, and do not necessarily imply any relationship or order between these entities or actions. "High side" and "low side" in the specification do not indicate the actual physical arrangement of the circuit. Numerical orders such as "first," "second," and "third" merely refer to different individuals among a plurality, and do not imply any order or sequence, unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in a temporary or logical order according to such order, unless specifically specified in the language of the claims. Without departing from the scope of the present invention, these processing steps can be interchanged in any order, as long as such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0085] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A battery balancing circuit for a battery pack, the battery pack comprising batteries 1, 2, ..., n connected in series, where n is an integer greater than or equal to 4, the battery balancing circuit comprising: The bridge comprises m arms, each including a high-side switch and a low-side switch connected in series. The midpoint between the high-side and low-side switches in each arm is coupled to the first terminal of an inductor. One of the m high-side switches and one of the m low-side switches are selected as a working switch pair. This working switch pair alternately conducts, causing the first terminal of the inductor to be alternately coupled to the positive terminal of a first target battery or the negative terminal of a second target battery to meet balancing requirements. When n is even, m = n / 2, the first target battery is one of batteries (n / 2) + 1 to n, the second target battery is one of batteries (n / 2) + 1 to n / 2, and the second terminal of the inductor is coupled to the positive terminal of battery n / 2; and When n is odd, m = (n-1) / 2. The first target battery is one of batteries from [(n+1) / 2]+1 to n. The second target battery is one of batteries from 1 to [(n+1) / 2]-1. The second terminal of the inductor is time-divisionally coupled to the positive or negative terminal of battery (n+1) / 2.

2. The battery balancing circuit as described in claim 1, wherein: The first target battery or the second target battery is the single cell with the highest voltage in the battery pack.

3. The battery balancing circuit as described in claim 1, wherein: The first target battery or the second target battery is the single cell with the lowest voltage in the battery pack.

4. The battery balancing circuit as described in claim 1, wherein the m bridge arms include a first bridge arm, a second bridge arm, ..., and an m-th bridge arm, wherein: The first bridge arm is coupled between the positive terminal of battery n and the negative terminal of battery 1; The second bridge arm is coupled between the positive terminal of battery n-1 and the negative terminal of battery 2; as well as When n is even, the m-th bridge arm is coupled between the positive terminal of battery (n / 2)+1 and the negative terminal of battery n / 2. When n is odd, the m-th bridge arm is coupled between the positive terminal of battery [(n+1) / 2]+1 and the negative terminal of battery [(n+1) / 2]-1.

5. The battery balancing circuit as described in claim 4, further comprising: m-1 high-side blocking switches are connected in reverse series with the high-side switches in the second to the m-th bridge arms, respectively. as well as m-1 low-side blocking switches are connected in reverse series with the low-side switches in the second to the m-th bridge arms, respectively.

6. The battery balancing circuit as described in claim 5, wherein: The high-side blocking switch, connected in series with the high-side switching transistor in the working switch pair, remains on; and The low-side blocking switch connected in series with the low-side switch in the working switch pair remains on.

7. The battery balancing circuit as described in claim 4, wherein: When the battery equalization circuit is operating in the first operating mode, the first high-side switch and the first low-side switch of the first bridge arm are selected to form a working switch pair and are alternately turned on. When the battery equalization circuit is operating in the second operating mode, the second high-side switch and the second low-side switch of the second bridge arm are selected to form a working switch pair and are alternately turned on. When the battery balancing circuit is operating in the third operating mode, the second low-side switch of the second bridge arm and the first high-side switch of the first bridge arm are selected to form a working switch pair and are alternately turned on. as well as When the battery balancing circuit operates in the fourth operating mode, the first low-side switch of the first bridge arm and the second high-side switch of the second bridge arm are selected to form a working switch pair and are alternately turned on.

8. The battery balancing circuit as described in claim 7, wherein when n = 4: In the first working mode, energy transfer is realized between batteries 1 and 2 and batteries 3 and 4; In the second working mode, energy transfer between battery No. 2 and battery No. 3 is realized; In the third working mode, energy transfer is realized between battery 2 and batteries 3 and 4; as well as In the fourth operating mode, energy transfer between battery 1, battery 2 and battery 3 is realized.

9. The battery balancing circuit as described in claim 7, wherein when n = 5: In the first working mode, energy transfer is realized between batteries 1-3 and batteries 4 and 5, energy transfer between batteries 1 and 2 and batteries 3-5, and energy transfer between batteries 1 and 2 and batteries 4 and 5. In the second working mode, energy transfer is realized between battery 2, battery 3 and battery 4, energy transfer between battery 2 and battery 3 and battery 4, and energy transfer between battery 2 and battery 4. In the third working mode, energy transfer is realized between batteries 2 and 3 and batteries 4 and 5, energy transfer between battery 2 and batteries 3 to 5, and energy transfer between battery 2 and batteries 4 and 5. as well as In the fourth working mode, energy transfer is realized between batteries 1-3 and battery 4, between batteries 1 and 2 and batteries 3 and 4, and between batteries 1, 2 and 4.

10. The battery balancing circuit as described in claim 1, wherein when n is an even number, the battery balancing circuit further comprises: The first selection switch connects the second end of the inductor to the positive terminal of the (n+1) / 2 battery. as well as The second selector switch connects the second end of the inductor to the negative terminal of the (n+1) / 2 battery.

11. A battery balancing system, comprising: A battery pack, comprising battery 1, battery 2, ..., battery n connected in series, where n is an integer greater than or equal to 4; as well as The battery balancing circuit as described in any one of claims 1 to 10.

12. A method for balancing a battery pack, the battery pack comprising batteries 1, 2, ..., n connected in series, where n is an integer greater than or equal to 4, the method comprising: The intermediate nodes of m bridge arms are all coupled to the first end of an inductor, wherein each of the m bridge arms includes a high-side switch and a low-side switch connected in series. Select one of the m high-side switching transistors and one of the m low-side switching transistors as the working switching transistor pair; Alternating switching pairs couple the inductor to couple the first terminal of the inductor to the positive terminal of the first target battery or the negative terminal of the second target battery; and When n is even, m = n / 2, the first target battery is one of batteries (n / 2) + 1 to n, the second target battery is one of batteries (n / 2) + 1 to n / 2, and the second terminal of the inductor is coupled to the positive terminal of battery n / 2; and When n is odd, m = (n-1) / 2, the first target battery is one of batteries from [(n+1) / 2]+1 to n, the second target battery is one of batteries from 1 to [(n+1) / 2]-1, and the second end of the inductor is time-divisionally coupled to the positive or negative terminal of battery (n+1) / 2.

13. The method of claim 12, wherein: The first target battery or the second target battery is the single cell with the highest voltage in the battery pack.

14. The method of claim 12, wherein: The first target battery or the second target battery is the single cell with the lowest voltage in the battery pack.

15. The method of claim 12, wherein the m bridge arms comprise a first bridge arm, a second bridge arm, ..., and an m-th bridge arm, wherein: The first bridge arm is coupled between the positive terminal of battery n and the negative terminal of battery 1; The second bridge arm is coupled between the positive terminal of battery n-1 and the negative terminal of battery 2; as well as When n is even, the m-th bridge arm is coupled between the positive terminal of battery (n / 2)+1 and the negative terminal of battery n / 2. When n is odd, the m-th bridge arm is coupled between the positive terminal of battery [(n+1) / 2]+1 and the negative terminal of battery [(n+1) / 2]-1.

16. The method of claim 15, further comprising: Connect the m-1 high-side blocking switches in reverse series with the high-side switches in the second to the m-th bridge arms, respectively. as well as The m-1 low-side blocking switches are connected in reverse series with the low-side switches in the second to the m-th bridge arms, respectively.

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