Clock circuit

Abstract

A clock circuit includes a voltage controlled oscillator having an input coupled to an output of an amplifier and an output outputting an output clock signal. The clock circuit additionally includes a reference branch and a feedback branch, both including a first switch coupled to an input via an inverter and a second switch coupled to the input. The branch also includes both a variable capacitor coupled to a reference potential and to the first switch and a variable resistor coupled to the first switch. Both branches include a supply voltage coupled to the variable resistor, and an output node, with the second switch coupled to the variable capacitor and to a node. The reference branch input is an input clock signal and the output is a reference voltage, and the feedback branch input is an output clock signal and the output is a feedback voltage.

Description

Technical Field

[0001] This invention relates to a clock circuit. Background Technology

[0002] In modern microcontroller units (MCUs) and microprocessor units (MPUs), clocks with various frequencies are required. Typically, depending on programmable variables, the generated output clock frequency is proportional to a reference clock frequency. Previously, clocks were affected by variables such as process, voltage, and temperature variations, causing them to fail to produce the desired frequency. Summary of the Invention

[0003] Various aspects of the invention are set forth in the appended independent and supplementary claims. Combinations of features from the supplementary claims may be combined with features of the independent claims as needed, and not merely as expressly stated in the claims.

[0004] According to one aspect, a clock circuit is provided, comprising:

[0005] An amplifier having a first input, a second input, and an output;

[0006] A voltage-controlled oscillator having an input coupled to the output of the amplifier and an output for outputting an output clock signal of the clock circuit;

[0007] Reference branches, the reference branches include:

[0008] Input, the input being used to receive a frequency f in The input reference clock signal;

[0009] A first switch, coupled to the input via an inverter, is used to control the first switch via the input reference clock signal;

[0010] A second switch, coupled to the input, is used to control the second switch via the input reference clock signal;

[0011] A variable capacitor having a first terminal coupled to a reference potential and a second terminal coupled to a first terminal of the first switch;

[0012] A variable resistor having a first end coupled to a second end of the first switch;

[0013] A power supply voltage node, said power supply voltage node being coupled to a second terminal of the variable resistor; and

[0014] An output node, coupled between the first terminal of the variable resistor and the second terminal of the first switch, outputs the reference voltage of the reference branch to the first input of the amplifier;

[0015] The second switch has a first end coupled to the first terminal of the variable capacitor, and a second end coupled to a node between the second terminal of the variable capacitor and the first terminal of the first switch; and

[0016] Feedback branches, the feedback branches including:

[0017] A feedback input, coupled to the output of the voltage-controlled oscillator, is used to receive the output clock signal of the clock circuit;

[0018] A first switch, coupled to the feedback input via an inverter, is used to control the first switch via the output clock signal of the clock circuit.

[0019] A second switch, coupled to the feedback input, is used to control the second switch via the output clock signal of the clock circuit;

[0020] A variable capacitor having a first terminal coupled to the reference potential and a second terminal coupled to the first terminal of the first switch of the feedback branch;

[0021] A variable resistor having a first terminal coupled to a second terminal of the first switch in the feedback branch;

[0022] A power supply voltage node, the power supply voltage node being coupled to the second terminal of the variable resistor in the feedback branch; and

[0023] An output node, coupled between the first terminal of the variable resistor of the feedback branch and the second terminal of the first switch of the feedback branch, to output the feedback voltage of the feedback branch to the second input of the amplifier;

[0024] The second switch of the feedback branch has a first end coupled to the first end of the variable capacitor of the feedback branch, and a second end coupled to the node between the second end of the variable capacitor of the feedback branch and the first end of the first switch of the feedback branch.

[0025] According to an embodiment, a clock circuit is provided that uses a frequency-to-voltage converter structure constructed from variable resistors and variable capacitors to form an analog frequency-locked loop. Using this arrangement allows for flexibility in the ratio between the output clock signal and the input reference clock signal. Variations caused by process, temperature, supply voltage, or aging effects can be eliminated.

[0026] In one embodiment, the reference branch further includes a filter capacitor having a first terminal coupled to a reference potential of the reference branch and a second terminal coupled to an output node of the reference branch. The function of this filter capacitor is to suppress voltage ripple at the output node of the reference branch.

[0027] In some embodiments, the feedback branch includes a filter capacitor having a first terminal coupled to a reference potential of the feedback branch and a second terminal coupled to the output node of the feedback branch. The function of this filter capacitor is to suppress voltage ripple at the output node of the feedback branch.

[0028] In one embodiment, the reference branch further includes an N-divider coupled between the input of the reference branch and a first and second switch of the reference branch. The function of the N-divider is to compensate for large frequency differences when the desired output frequency is much higher than the input reference frequency.

[0029] In one embodiment, the feedback branch further includes an M-divider coupled between the feedback input and the output of the voltage-controlled oscillator. The M-divider compensates for large frequency differences when the desired output frequency is much lower than the input reference frequency.

[0030] According to an embodiment, the M-divider and N-divider are programmable and are used to compensate for the frequency difference between the input reference clock signal and the output clock signal.

[0031] In one embodiment, the clock circuit includes a low-dropout regulator (LDO) coupled to the amplifier for supplying power to the amplifier and suppressing noise from the supply voltage.

[0032] In one embodiment, the clock circuit includes a chopper coupled to the input of the amplifier to eliminate main output frequency errors and drift contributing factors.

[0033] According to an embodiment, the clock circuit includes a third branch, the third branch comprising:

[0034] Nodes, the nodes being coupled between the output node of the reference branch and the first input of the amplifier; and

[0035] A resistor, the first end of which is coupled to the node;

[0036] A switch, the first end of which is coupled to the second end of the resistor; and a power supply voltage, the first end of which is coupled to the second end of the switch.

[0037] In one embodiment, the clock circuit further includes a first multiplexer having a first input coupled to an input reference clock signal, a second input coupled to the output of a voltage-controlled oscillator, and outputs coupled to a first switch and a second switch of a reference branch.

[0038] In one embodiment, the clock circuit further includes a second multiplexer having a first input coupled to the output of a voltage-controlled oscillator, a second input coupled to an input reference clock signal, and outputs coupled to a first switch and a second switch of a reference branch.

[0039] In some embodiments, the variable resistors of the reference branch and the feedback branch are programmable and are used to compensate for the frequency difference between the input reference clock signal and the output clock signal.

[0040] According to an embodiment, the variable capacitor of the reference branch and the variable resistor of the feedback branch are programmable for compensating for the resistance difference between the variable resistor of the reference branch and the variable resistor of the feedback branch.

[0041] According to another aspect, a microcontroller unit (MCU) is provided, including a clock circuit of the type described above.

[0042] According to another aspect, a microprocessor unit (MPU) is provided, including a clock circuit of the type described above. Attached Figure Description

[0043] Embodiments of this disclosure will be described below by way of example only with reference to the accompanying drawings, in which similar reference numerals denote similar elements, and in the drawings:

[0044] Figure 1 A clock circuit according to an embodiment is shown; and

[0045] Figure 2 A clock circuit according to another embodiment is shown. Detailed Implementation

[0046] Embodiments of this disclosure are described below with reference to the accompanying drawings.

[0047] Figure 1A clock circuit 100 according to an embodiment is shown. The clock circuit 100 includes an amplifier 140. In this example, the amplifier 140 includes a first input 141, a second input 143, and an output 145, as will be described in more detail below. The output 145 of the amplifier 140 is coupled to a voltage-controlled oscillator (VCO) 144, which has an output for outputting an output clock signal 146 of the clock circuit 100.

[0048] like Figure 1 As shown, the clock circuit 100 includes a reference branch 101. The reference branch 101 receives signals having a frequency f. in The input reference clock signal 102 (clkin) can be transmitted through an N-divider 104, which divides the frequency f in Divide by N (where N is an integer). The value of N divider 104 can be programmable, for reasons described in more detail below. The input reference clock signal 102 output from N divider 104 can be used to control the first switch 112 (S1) and the second switch 120 (S2) of reference branch 101, wherein the input to the first switch 112 is coupled to the input reference clock signal 102 (and optionally N divider 104) via inverter 106. Inverter 106 is operable to provide alternating signals to the first switch 112 and the second switch 120 such that when the first switch 112 is open, the second switch 120 is closed, or vice versa.

[0049] In this example, reference branch 101 includes a variable capacitor 116 (C1) having a first terminal coupled to a reference potential 118 and a second terminal coupled to a first terminal of a first switch 112. For example, the reference potential 118 may be ground. Reference branch 101 also includes a variable resistor 110 (R1) having a first terminal coupled to a second terminal of the first switch 112 and a second terminal coupled to a power supply voltage 108. The variable resistor 110 and the variable capacitor 116 may be programmable, for reasons described in more detail below.

[0050] In this embodiment, reference branch 101 includes output node 107. Output node 107 is coupled between a first terminal of variable resistor 110 and a second terminal of first switch 112. Output node 107 is configured to transmit the reference voltage V of reference branch 101. ref The output is to the first input 141 of amplifier 140. Notably, the second switch 120 has a first end coupled to a first terminal of variable capacitor 116, and a second end coupled to a node 113 between the second terminal of variable capacitor 116 and the first terminal of first switch 112.

[0051] In this embodiment, the function of reference branch 101 is to convert the frequency signal (i.e., the input reference clock signal 102) into a reference voltage V. ref This is provided to amplifier 140. As noted above, the first switch 112 and the second switch 120 are controlled by the input reference clock signal 102. When the second switch 120 is closed (thereby opening the first switch 112), the variable capacitor 116 discharges to the reference potential 118 (e.g., ground). On the other hand, when the second switch 120 is open (thereby closing the first switch 112), the variable capacitor 116 begins to charge. This process creates a switching capacitor resistor between the reference potential 118 and the output node 107. The equivalent resistance R of the switching capacitor resistor in reference branch 101... ref It has the following values:

[0052] R ref =N / (C1*f in (Equation 1)

[0053] in:

[0054] C1 = the capacitance of variable capacitor 116.

[0055] N = N divider 104 (integer value), and

[0056] f in = The frequency of the input reference clock signal 102.

[0057] Refer to branch 101 for the switching capacitor and resistor, and variable resistor 110 for dividing the power supply voltage to 108V. supply This provides a reference voltage V with the following value at output node 107. ref :

[0058]

[0059] in:

[0060] R1 = the resistance of variable resistor 110.

[0061] like Figure 1 As shown, the clock circuit 100 also includes a feedback branch 103. The feedback branch 103 receives a feedback input 147 coupled to the output of the VCO 144 for receiving the output clock signal 146 (clkout, having a frequency f) of the clock circuit 100. out Feedback input 147 can be transmitted through M-divider 142, which can divide the frequency f. outDividing by a programmable (integer) value M, the reason for which will be described in more detail below (note that M and N may have different values ​​or may be the same value). The output clock signal 146 from the M divider 142 can be used to control the first switch 130 (S3) and the second switch 128 (S4) of the feedback branch 103, wherein the input to the first switch 130 is coupled to the feedback input 147 via the inverter 126 (and optionally the M divider 142). The inverter 126 is operable to provide alternating signals to the first switch 130 and the second switch 128 such that when the first switch 130 is open, the second switch 128 is closed, or vice versa.

[0062] In this example, feedback branch 103 includes a variable capacitor 134 (C2) having a first terminal coupled to a reference potential 136 and a second terminal coupled to a first terminal of a first switch 130. For example, the reference potential 136 may be ground. Feedback branch 103 also includes a variable resistor 124 (R2) having a first terminal coupled to a second terminal of the first switch 130 and a second terminal coupled to a power supply voltage 122. The variable resistor 124 and the variable capacitor 134 may be programmable, for reasons described in more detail below.

[0063] In this embodiment, feedback branch 103 includes output node 123. Output node 123 is coupled between a first terminal of variable resistor 124 and a second terminal of first switch 130. Output node 123 is configured to receive the feedback voltage V of feedback branch 103. fb The output is given to the second input 143 of amplifier 140. Notably, the second switch 128 has a first end coupled to the first terminal of variable capacitor 134, and a second end coupled to the node between the second terminal of variable capacitor 134 and the first terminal of first switch 130.

[0064] In this embodiment, the function of feedback branch 103 is to convert the frequency signal (i.e., the output clock signal 146) into a feedback voltage V. fb This is provided to amplifier 140. As noted above, the first switch 130 and the second switch 128 are controlled by feedback input 147. When the second switch 128 is closed (thereby opening the first switch 130), the variable capacitor 134 discharges to a reference potential 136 (e.g., ground). Conversely, when the second switch 128 is open (thereby closing the first switch 130), the variable capacitor 134 begins to charge. This process creates a switching capacitor resistor between the reference potential 136 and the output node 123. The equivalent resistance R of the switching capacitor resistor in feedback branch 103 is... out It has the following values:

[0065] R out =M / (C2*fout (Equation 3)

[0066] in:

[0067] C2 = the capacitance of variable capacitor 134.

[0068] M = M divider 142 (integer value), and

[0069] f out = The frequency of the output clock signal 146.

[0070] Feedback branch 103 switches the capacitor and resistor, and variable resistor 124 divides the power supply voltage to 122V. supply This provides a feedback voltage V with the following value at output node 123. fb :

[0071]

[0072] in:

[0073] R2 = the resistance of variable resistor 124.

[0074] In this example, the reference voltage V ref and feedback voltage V fb The signals are sent to inputs 141 and 143 of amplifier 140 to generate a control voltage (V) at output 145 of amplifier 140. cntl As previously mentioned, the output 145 of amplifier 140 is coupled to VCO 144, which in turn decouples V... cntl It is converted into a frequency value to generate the output clock signal (clkout).

[0075] In addition to forming the output clock signal 146, the output of VCO 144 forms the beginning of the feedback loop through feedback branch 103, as described above. Therefore, V ref and V fb Operable to control amplifier 140 and VCO 144 to lock the output clock signal 146 to a desired value (e.g., clkin or a multiple / fraction thereof).

[0076] To achieve V fb =V ref ,need:

[0077]

[0078] Equations 1 and 3 are used to solve for the frequency f of the output clock signal. out The equation is:

[0079]

[0080] According to this equation, the frequency ratio between the input reference clock signal 102 and the output clock signal 146 is independent of the process, temperature coefficient, or power supply voltage, and therefore the output clock signal 146 can be made independent of temperature changes, manufacturing process changes, etc.

[0081] As mentioned above, the M-divider 142 and N-divider 104 are individually programmable. The M-divider 142 and N-divider 104 can be used to compensate for large frequency differences between the input reference clock signal 102 and the output clock signal 146. Optionally, the large frequency difference that the M-divider 142 and N-divider 104 can compensate for can be greater than or equal to 8 times or less than or equal to 0.125 times. Therefore, the accuracy of the clock circuit 100 can be improved.

[0082] As previously highlighted, the variable resistors 110 / 124 are individually programmable. The variable resistors 110 / 124 in reference branch 101 and feedback branch 103 can be used to compensate for small frequency differences between the input reference clock signal 102 and the output clock signal 146. Optionally, the small frequency differences that the variable resistors 110 / 124 can compensate for are in the range of 0.25 to 4 times. As noted above, the variable capacitors 116 / 134 are also individually programmable. The variable capacitors 116 / 134 in reference branch 101 and feedback branch 103 can be used to compensate for mismatches between the variable resistor 110 in reference branch 101 and the variable resistor 124 in feedback branch 103. Examples of different scenarios where programming may be required can be seen below:

[0083]

[0084]

[0085] Table 1 - Programming and Tuning Strategies for Programmable Component Output Frequency

[0086] like Figure 1 As shown, reference branch 101 may further include a filter capacitor 114 having a first terminal coupled to a reference potential 118 of reference branch 101 and a second terminal coupled to an output node 107 of reference branch 101. Feedback branch 103 may further include a filter capacitor 132 having a first terminal coupled to a reference potential 136 of feedback branch 103 and a second terminal coupled to an output node 123 of feedback branch 103. Filter capacitors 114 / 132 can be used to suppress voltage ripple in their respective output nodes 107 / 123.

[0087] Figure 2 Show Figure 1The clock circuit 200 of the type shown has some additional optional features, such as a low-dropout regulator 212 (LDO). The LDO 212 may be coupled to amplifier 140 to power amplifier 140 and suppress noise from the power supply voltage 108 of reference branch 101 and the power supply voltage 122 of feedback branch 103. Clock circuit 200 may additionally include a chopper 214 coupled to the input of amplifier 140 to eliminate main output frequency errors such as offset and drift contributing factors.

[0088] In this embodiment, Figure 2 The clock circuit 200 includes another branch 205. This other branch 205 can be coupled to the clock circuit 200 via node 211, which is coupled between the output node 107 of the reference branch 101 and the first input 141 of the amplifier 140. The other branch 205 includes: a resistor 210 (R3), with its first end coupled to node 211; a switch 208, with its first end coupled to the second end of the resistor 210; and a power supply voltage 206, with its first end coupled to the second end of the switch 208. The other branch 205 can be used when the input reference clock signal 102 is unavailable, thereby allowing the clock circuit 200 to maintain the oscillation of its feedback loop. The output clock signal 146 when the input reference clock signal 102 is unavailable is equal to:

[0089]

[0090] in:

[0091] R3 = the resistance of the 210 resistor in the other branch.

[0092] In this embodiment, Figure 2 The clock circuit 200 may include a first multiplexer 202 having a first input coupled (optionally via an N divider 104) to an input reference clock signal 102, a second input coupled (optionally via an M divider 142) to an output of a VCO 144, and outputs coupled to a first switch 112 and a second switch 120 of a reference branch 101, as described above. In this embodiment, Figure 2The clock circuit 200 may also include a second multiplexer 204 having a first input coupled (optionally via N divider 104) to the input reference clock signal 102, a second input coupled (optionally via M divider 142) to the output of VCO 144, and outputs coupled to a first switch 130 and a second switch 128 of the feedback branch 103, as described above. The first multiplexer 202 and the second multiplexer 204 allow the user to ensure that the reference branch 101 operates at a higher frequency than the feedback branch 103. This allows for the avoidance of complex rail-to-rail inputs to the amplifier 140.

[0093] Therefore, a clock circuit has been described, including a voltage-controlled oscillator (VCO) having an input coupled to the output of an amplifier and an output of a clock signal. The clock circuit further includes a reference branch and a feedback branch, both of which include a first switch coupled to the input via an inverter and a second switch coupled to the input. Each branch also includes a variable capacitor coupled to a reference potential and coupled to the first switch, and a variable resistor coupled to the first switch. Both branches include a power supply voltage coupled to the variable resistor, and an output node, wherein the second switch is coupled to the variable capacitor and coupled to the node. The reference branch input is the input clock signal and the output is the reference voltage, and the feedback branch input is the output clock signal and the output is the feedback voltage.

[0094] Although specific embodiments of the invention have been described, it should be understood that many modifications / additions and / or substitutions may be made within the scope of the claimed invention.

Claims

1. A clock circuit, characterized in that, include: An amplifier having a first input, a second input, and an output; A voltage-controlled oscillator having an input coupled to the output of the amplifier and an output for outputting an output clock signal of the clock circuit; Reference branches, the reference branches include: Input, the input being used to receive a frequency f in The input reference clock signal; A first switch, coupled to the input via an inverter, is used to control the first switch via the input reference clock signal; A second switch, coupled to the input, is used to control the second switch via the input reference clock signal; A variable capacitor having a first terminal coupled to a reference potential and a second terminal coupled to a first terminal of the first switch; A variable resistor having a first end coupled to a second end of the first switch; A power supply voltage node, said power supply voltage node being coupled to a second terminal of the variable resistor; and An output node, coupled between the first terminal of the variable resistor and the second terminal of the first switch, outputs the reference voltage of the reference branch to the first input of the amplifier; The second switch has a first end coupled to the first terminal of the variable capacitor, and a second end coupled to a node between the second terminal of the variable capacitor and the first terminal of the first switch; and Feedback branches, the feedback branches including: A feedback input, coupled to the output of the voltage-controlled oscillator, is used to receive the output clock signal of the clock circuit; A first switch, coupled to the feedback input via an inverter, is used to control the first switch via the output clock signal of the clock circuit. A second switch, coupled to the feedback input, is used to control the second switch via the output clock signal of the clock circuit; A variable capacitor having a first terminal coupled to the reference potential and a second terminal coupled to the first terminal of the first switch of the feedback branch; A variable resistor having a first terminal coupled to a second terminal of the first switch in the feedback branch; A power supply voltage node, the power supply voltage node being coupled to the second terminal of the variable resistor in the feedback branch; and An output node, coupled between the first terminal of the variable resistor of the feedback branch and the second terminal of the first switch of the feedback branch, to output the feedback voltage of the feedback branch to the second input of the amplifier; The second switch of the feedback branch has a first end coupled to the first end of the variable capacitor of the feedback branch, and a second end coupled to the node between the second end of the variable capacitor of the feedback branch and the first end of the first switch of the feedback branch.

2. The clock circuit according to claim 1, characterized in that, The reference branch includes a filter capacitor having a first end coupled to the reference potential of the reference branch and a second end coupled to the output node of the reference branch.

3. The clock circuit according to claim 1 or 2, characterized in that, The feedback branch includes a filter capacitor having a first end coupled to the reference potential of the feedback branch and a second end coupled to the output node of the feedback branch.

4. The clock circuit according to any one of the preceding claims, characterized in that, The reference branch further includes an N-divider coupled between the input of the reference branch and the first and second switches of the reference branch.

5. The clock circuit according to any one of the preceding claims, characterized in that, The feedback branch further includes an M-divider coupled between the feedback input and the output of the voltage-controlled oscillator.

6. The clock circuit according to claim 5, when attached to claim 4, is characterized in that, The M-divider and the N-divider are programmable and are used to compensate for the frequency difference between the input reference clock signal and the output clock signal.

7. The clock circuit according to any one of the preceding claims, characterized in that, The clock circuit includes a low-dropout regulator (LDO) coupled to the amplifier for supplying power to the amplifier and suppressing noise from the power supply voltage.

8. The clock circuit according to any one of the preceding claims, characterized in that, The clock circuit includes a chopper coupled to the input of the amplifier to eliminate main output frequency errors such as offset and drift contributing factors.

9. A microcontroller unit (MCU), characterized in that, Includes the clock circuit as described in any of the preceding claims.

10. A microprocessor unit (MPU), characterized in that, Includes a clock circuit according to any one of claims 1 to 8.

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