Ultra-wideband multimode frequency divider and frequency source chip

Abstract

The invention relates to an ultra-wideband multimode frequency divider, which belongs to the technical field of integrated circuit design, and comprises a radio frequency amplification circuit module, a preposed 2-dividing circuit module, a multiplexer module, a multimode frequency divider module and a CML logic gate circuit module, the output end of the radio frequency amplification circuit module is connected with the input end of the preposed 2-dividing circuit module; the output end of the front-end 2-dividing circuit module is connected with the input end of the multiplexer module; the output end of the multiplexer module is connected with the input end of the multimode frequency divider module; and the CML logic gate circuit module is deployed on a high-frequency signal path and a key control node of the multimode frequency divider in a distributed manner. The invention provides a frequency source chip integrated with an ultra-wideband multimode frequency divider.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to an ultra-wideband multimode frequency divider and frequency source chip. Background Technology

[0002] As a core component of a communication system, the performance of the signal source directly determines the communication quality. Current communication technologies place higher demands on signal sources, including higher precision, faster switching, and wider frequency ranges. High-performance signal sources largely rely on frequency synthesis technology. From direct analog synthesis to direct digital synthesis and phase-locked loop (PLL) frequency synthesis, continuous innovation in these technologies has driven the development of frequency synthesizers towards monolithic integration. Among these, PLL frequency synthesizers, with their stability and integration advantages, have become the mainstream application solution.

[0003] With the evolution of communication technology towards higher frequencies and the innovation of semiconductor processes, PLL frequency synthesizers are developing towards digitalization, high integration, low cost, and wide bandwidth. As a key module for PLLs to achieve frequency synthesis, the frequency divider is also facing higher demands due to the development trend of PLL frequency synthesizers. Traditional frequency dividers are limited by gate delay and parasitic effects, making it difficult to operate normally in the millimeter-wave band. Furthermore, the accumulated digital jitter caused by cascaded structures significantly degrades phase noise. Meanwhile, existing dual-mode prescalers combined with MA counters cannot meet the flexible frequency division requirements of ultra-wide bandwidths (e.g., 1GHz to 30GHz) due to the division ratio being limited by the number of counter bits. Therefore, how to achieve a high-speed, low-noise, wide-bandwidth frequency divider architecture has become a core technical bottleneck in the current engineering applications of PLL frequency synthesizers. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide an ultra-wideband multimode frequency divider and frequency source chip to solve the three major technical bottlenecks of frequency dividers in ultra-wideband applications: "high-frequency operation failure, limited division ratio range, and phase noise degradation", and adapt to the needs of wideband and low-noise frequency synthesis in scenarios such as 5G communication and broadband radar.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] On one hand, the present invention provides an ultra-wideband multimode divider, comprising: an RF amplifier circuit module, a pre-divider-by-2 circuit module, a multiplexer module, a multimode divider module, and a CML logic gate circuit module; the output terminal of the RF amplifier circuit module is connected to the input terminal of the pre-divider-by-2 circuit module; the output terminal of the pre-divider-by-2 circuit module is connected to the input terminal of the multiplexer module; the output terminal of the multiplexer module is connected to the input terminal of the multimode divider module; the CML logic gate circuit modules are distributed and deployed in the high-frequency signal path and key control nodes of the multimode divider.

[0007] Furthermore, the RF amplifier circuit module employs a pre-buffered amplifier circuit with a tail inductor, and uses a common-emitter and common-base two-stage amplifier to amplify the RF input signal. The tail inductor suppresses crosstalk from noise on the RF ground to the RF input terminal.

[0008] Furthermore, the differential input pair of the pre-dividend-by-two circuit module adopts a transistor structure, and its tail current bias adopts a self-biasing structure.

[0009] Furthermore, the multiplexer module includes two differential input pairs. The two differential input pairs share the tail current and resistive load. When the common-emitter MOS switch of one differential pair is turned on, the differential pair works normally, amplifies the input signal and outputs it through the source follower. When the common-emitter MOS switch of the other differential pair is turned off, the differential input pair has no current bias, so its input signal is shielded.

[0010] Furthermore, the multi-mode frequency divider module includes an RF DIV1 / DIV2 module, a 4-level / 2 / 3-level analog frequency divider module, a DIGCOUNTER module, a RETIMER circuit module, and a 15-bit digital frequency divider module;

[0011] The RF DIV1 / DIV2 module is responsible for performing preliminary frequency division on the input high-frequency radio frequency signal, providing the basic frequency division signal for the subsequent 4-stage / 2 / 3-stage analog frequency division module;

[0012] The 4-stage / 2 / 3 analog frequency divider module is cascaded with the 15-bit digital frequency divider module to achieve coarse and fine adjustment of the division ratio. The output of the 4-stage / 2 / 3 analog frequency divider module is connected to the input of the DIG COUNTER module, allowing the DIG COUNTER module to obtain the signal state after the initial frequency division, so as to further cooperate with the 15-bit digital frequency divider module for more precise frequency ratio control. The output of the DIG COUNTER module is cascaded with the input of the 15-bit digital frequency divider module.

[0013] The control signal output terminal of the DIG COUNTER module is connected to the D... of the 4-level / 2 / 3 analog frequency divider module. <0> ~D <3> The control terminal is connected to form a coarse adjustment range of 16 to 81 in a cascaded product manner;

[0014] The control signal output terminal of the DIG COUNTER module is connected to the D of the 15-bit digital frequency divider module. <4> ~D <18> The control terminal is connected, and the frequency division ratio from 1 to 32767 can be finely adjusted through binary control words;

[0015] The RETIMER circuit is connected to the RF DIV1 / DIV2 module and ultimately outputs the frequency division signal; at the same time, the timing feedback of the DIGCOUNTER module works in conjunction with the RETIMER circuit to calibrate the frequency division timing.

[0016] Furthermore, in the 15-bit digital frequency divider module, the CML logic gate circuit module embeds the D flip-flop unit of the 15-bit digital counter, shortening the signal transmission path;

[0017] In the 4-level / 2 / 3 analog frequency divider module, CML logic gates form the differential input pairs and cascaded buffer nodes of the / 2 / 3 circuit, supporting high-frequency signal processing;

[0018] In the control path, the DIG COUNTER module outputs D in differential form through CML logic gates. <0> ~D <3> Control signals are sent to the 4-level / 2 / 3-level analog frequency divider module;

[0019] The RETIMER circuit module uses the CML interface to receive the VCO clock and resamples the first-stage frequency division signal;

[0020] The differential input pairs of the multiplexer and the source follower output stage in the multiplexer module are both based on the CML structure design to achieve high-frequency signal switching.

[0021] On the other hand, the present invention provides a frequency source chip integrating an ultra-wideband multimode divider, including a reference divider, a frequency and phase detector, a low-pass filter, a VCO, and a feedback multimode divider; the feedback multimode divider is the ultra-wideband multimode divider described above; the input terminal of the reference divider receives a reference frequency, and its output terminal is connected to the first input terminal of the frequency and phase detector; the second input terminal of the frequency and phase detector is connected to the output terminal of the feedback multimode divider; the output terminal of the frequency and phase detector is connected to the input terminal of the low-pass filter; the output terminal of the low-pass filter is connected to the input terminal of the VCO; the output terminal of the VCO is connected to the input terminal of the feedback multimode divider and outputs... The final signal; the reference frequency divider is used to divide the reference frequency, flexibly configuring the reference operating frequency of the frequency and phase detector; the frequency and phase detector is used to compare the output frequency of the reference branch and the output frequency of the feedback multi-mode frequency divider, and convert the difference between the two signals into charging current or discharging current, and then convert it into a voltage signal to control the VCO frequency through a low-pass filter; the feedback multi-mode frequency divider divides the frequency signal of the VCO and generates a feedback signal, which is provided to the frequency and phase detector to form a closed-loop feedback system; through repeated phase detection and adjustment, the output signal and input signal frequencies of the VCO finally reach the desired ratio, at which point the frequency source chip enters the locked state.

[0022] The beneficial effects of this invention are as follows:

[0023] (1) Ultra-wide bandwidth and high-precision frequency division: The architecture of “tail inductor pre-buffer amplifier circuit + 4-stage / 2 / 3-stage analog frequency division cascade + 15-bit digital frequency division” is adopted to achieve an ultra-wide operating frequency of 1GHz to 30GHz; the total frequency division ratio reaches 16 to 2654208, and supports odd frequency division and fine adjustment of frequency division ratio.

[0024] (2) Excellent high-frequency low-noise performance: Through the RETIMER circuit and distributed CML logic gate optimization, phase noise and signal delay are effectively suppressed; the pre-dividend circuit adopts a transistor differential input pair and self-biased structure to ensure stable operation under 30GHz high-frequency input and excellent phase noise performance in the high-frequency band.

[0025] (3) High integration and strong compatibility: It can be highly integrated into the frequency source chip, seamlessly cooperate with various types of VCOs, and adapt to multiple application scenarios such as 5G communication and millimeter-wave radar.

[0026] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0028] Figure 1 This is a schematic diagram of the overall structure of the ultra-wideband multimode frequency divider provided by the present invention;

[0029] Figure 2 This is a circuit diagram of an RF amplifier;

[0030] Figure 3 This is a diagram of a high-frequency divide-by-2 circuit.

[0031] Figure 4 This is a structural diagram of an RF multiplexer;

[0032] Figure 5 The improved CML logic gate circuit diagram;

[0033] Figure 6 This is a schematic diagram of the overall structure of the frequency source chip. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0037] Example 1:

[0038] like Figure 1As shown, this invention provides an ultra-wideband multimode divider architecture, including an RF amplifier circuit module, a pre-dividend-by-2 circuit module, a multiplexer module, a multimode divider module, and a CML logic gate circuit module. In practical applications, this ultra-wideband multimode divider can be applied to millimeter-wave frequency source chips, paired with various types of VCOs, covering a frequency range of 1GHz-30GHz, to meet the needs of 5G communication and other scenarios.

[0039] The output of the RF amplifier circuit module is connected to the input of the preamplifier divide-by-two circuit module; the output of the preamplifier divide-by-two circuit module is connected to the input of the multiplexer module; the output of the multiplexer module is connected to the input of the multimode divider module; and the output of the multimode divider module is connected to the phase-locked loop module of the millimeter-wave frequency source chip. CML logic gate circuit modules are distributed along the high-frequency signal path and key control nodes of the multimode divider to effectively reduce parasitic parameters on the RF divider's transmission path and improve the RF divider's operating frequency.

[0040] like Figure 2 As shown, the RF amplifier circuit module employs a pre-buffered amplifier circuit with a tail inductor to achieve an ultra-wide operating frequency range of 1GHz to 30GHz. This module effectively processes the RF input signal, and the tail inductor design effectively suppresses crosstalk from noise on the RF ground to the RF input terminal. A common-emitter, common-base two-stage amplifier circuit structure is used to effectively amplify the RF input signal to obtain good drive capability for subsequent loads.

[0041] like Figure 3 As shown, the pre-divide-by-2 circuit module is designed to reduce noise generated during logic switching. Its differential input pair uses a transistor structure, and its tail current bias uses a self-biased structure. Since the feedback signal of the standalone divide-by-2 circuit module comes from its own output and is not delayed by other logic gates, it can still operate normally at an input frequency of 30GHz.

[0042] like Figure 4 As shown, the multiplexer module is essentially an input signal buffer, with two differential input pairs sharing the tail current and resistive load. When the common-emitter MOS switch of one differential pair is on, that differential pair operates normally, amplifying the input signal and outputting it via a source follower. Conversely, when the common-emitter MOS switch of the other differential pair is off, that differential input pair has no current bias, thus its input signal is shielded. This structure allows for a direct output signal to a multimode divider when the RF input frequency is 1–15 GHz, and a divided-by-2 output signal to a multimode divider when the input frequency is 15 GHz–30 GHz. This design ensures that the minimum division ratio can still be reduced to 16 at low input frequencies, while also enabling odd division ratios.

[0043] The multimode divider module includes an RF DIV1 / DIV2 module, a 4-stage / 2 / 3 analog divider module, a DIG COUNTER module, a RETIMER module, and a 15-bit digital divider module. The RF DIV1 / DIV2 module performs initial frequency division on the input high-frequency RF signal, providing the base division signal for the subsequent 4-stage / 2 / 3 divider unit. The cascaded architecture of the 4-stage / 2 / 3 analog divider module and the 15-bit digital divider module enables coarse and fine adjustments to the division ratio.

[0044] The output of the 4-stage / 2 / 3 analog frequency divider module is connected to the input of the DIG COUNTER module, allowing the DIG COUNTER module to obtain the signal state after initial frequency division. This enables further coordination with the 15-bit digital frequency divider module for more precise frequency division ratio control. The output of the DIG COUNTER module is cascaded with the input of the 15-bit digital frequency divider module; the control signal output of the DIG COUNTER module is connected to the D... <0> ~D <3> The control terminals are connected to form a coarse adjustment range of 16 to 81 using a cascaded product method; the control signal output of the DIG COUNTER module is connected to the D... <4> ~D <18> The control terminal is connected, and fine-tuning of the division ratio from 1 to 32767 is achieved through binary control words. After cascading, the total division ratio can reach 16 to 2654208. During coarse-tuning, the more cascaded units there are, the greater the accumulated jitter in the divider, and the more significant the deterioration of the closed-loop phase noise. To reduce jitter accumulation, a RETIMER circuit is added between the input and output of the feedback divider. Therefore, the timing feedback of the DIG COUNTER module and the RETIMER circuit are used to calibrate the division timing simultaneously, achieving precise adjustment of the division ratio while ensuring wide bandwidth coverage.

[0045] CML logic gate modules are distributed across the high-frequency signal path and key control nodes of the multi-mode divider to effectively reduce parasitic parameters on the RF divider's transmission path and improve the RF divider's operating frequency. For example... Figure 5 As shown, in the digital frequency divider module, CML logic gates embed the D flip-flop units of a 15-bit digital counter, shortening the signal transmission path; in the analog frequency divider module, CML logic gate circuits form differential input pairs and cascaded buffer nodes of a 2 / 3 circuit, supporting high-frequency signal processing; in the control path, the DIG COUNTER module outputs D flip-flops in differential form through CML logic gates. <0> ~D <3> The control signal is sent to the analog frequency divider module; the RETIMER circuit uses the CML interface to receive the VCO clock and resamples the first-stage frequency divider signal; the differential input pair of the multiplexer and the source follower output stage are both designed based on the CML structure to achieve high-frequency signal switching.

[0046] Example 2:

[0047] like Figure 6 As shown, this embodiment deeply integrates the ultra-wideband multimode frequency divider of Embodiment 1 into a millimeter-wave frequency source chip. Its core modules include: a reference frequency divider, a frequency and phase detector, a low-pass filter, a VCO, and a feedback multimode frequency divider. The reference frequency divider is used to divide the reference frequency and can flexibly configure the reference operating frequency of the frequency and phase detector. The frequency and phase detector compares the output frequency of the reference branch with the output frequency of the feedback multimode divider and converts the difference between the two signals into charging current or discharging current, which is then converted into a voltage signal to control the VCO frequency through a filter. The feedback multimode frequency divider divides the frequency signal of the VCO and generates a feedback signal, which is provided to the frequency and phase detector to form a closed-loop feedback system. Through repeated phase detection and adjustment, the output signal and input signal frequencies of the VCO finally reach the desired ratio, at which point the frequency source chip enters a locked state.

[0048] In practical engineering applications, millimeter-wave frequency source chips that deeply integrate ultra-wideband multi-mode frequency dividers can be used to construct high-frequency, precise frequency synthesis systems for scenarios such as 5G communication, broadband radar, and satellite communication. This millimeter-wave frequency source chip, through flexible adaptation to various VCO models, utilizes the ultra-wideband frequency division capability and low phase noise characteristics of the multi-mode frequency divider of this invention, combined with a chip-level PLL architecture, to achieve continuous coverage across the entire frequency band from 1GHz to 30GHz, meeting the stringent requirements of communication for a "wideband, high stability, and low noise" frequency source.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An ultra-wideband multimode frequency divider, characterized in that: include: RF amplifier circuit module, preamplifier divide-by-2 circuit module, multiplexer module, multimode divider module, CML logic gate circuit module; The output of the RF amplifier circuit module is connected to the input of the pre-divider-by-2 circuit module; the output of the pre-divider-by-2 circuit module is connected to the input of the multiplexer module; the output of the multiplexer module is connected to the input of the multimode divider module; the CML logic gate circuit modules are distributed along the high-frequency signal path and key control nodes of the multimode divider.

2. The ultra-wideband multimode divider according to claim 1, characterized in that: The radio frequency amplifier circuit module uses a pre-buffered amplifier circuit with a tail inductor and a common-emitter, common-base two-stage amplifier to amplify the radio frequency input signal. The tail inductor suppresses crosstalk from noise on the radio frequency ground to the radio frequency input terminal.

3. The ultra-wideband multimode divider according to claim 1, characterized in that: The differential input pair of the pre-dividend-by-two circuit module adopts a transistor structure, and its tail current bias adopts a self-biasing structure.

4. The ultra-wideband multimode divider according to claim 1, characterized in that: The multiplexer module includes two differential input pairs. The two differential input pairs share the tail current and resistive load. When the common-emitter MOS switch of one differential pair is turned on, the differential pair works normally, amplifies the input signal and outputs it through the source follower. When the common-emitter MOS switch of the other differential pair is turned off, the differential input pair has no current bias, so its input signal is shielded.

5. The ultra-wideband multimode divider according to claim 1, characterized in that: The multi-mode frequency divider module includes an RF DIV1 / DIV2 module, a 4-level / 2 / 3-level analog frequency divider module, a DIG COUNTER module, a RETIMER circuit module, and a 15-bit digital frequency divider module; The RF DIV1 / DIV2 module is responsible for performing preliminary frequency division on the input high-frequency radio frequency signal, providing the basic frequency division signal for the subsequent 4-stage / 2 / 3-stage analog frequency division module; The 4-stage / 2 / 3 analog frequency divider module is cascaded with the 15-bit digital frequency divider module to achieve coarse and fine adjustment of the division ratio; the output of the 4-stage / 2 / 3 analog frequency divider module is connected to the input of the DIG COUNTER module, so that the DIG COUNTER module can obtain the signal state after the initial frequency division; the output of the DIG COUNTER module is cascaded with the input of the 15-bit digital frequency divider module. The control signal output terminal of the DIG COUNTER module is connected to the D... of the 4-level / 2 / 3 analog frequency divider module. <0> ~D <3> The control terminal is connected to form a coarse adjustment range of 16 to 81 in a cascaded product manner; The control signal output terminal of the DIG COUNTER module is connected to the D of the 15-bit digital frequency divider module. <4> ~D <18> The control terminal is connected, and the frequency division ratio from 1 to 32767 can be finely adjusted through binary control words; The RETIMER circuit is connected to the RF DIV1 / DIV2 module and ultimately outputs the frequency division signal; at the same time, the timing feedback of the DIGCOUNTER module works in conjunction with the RETIMER circuit to calibrate the frequency division timing.

6. The ultra-wideband multimode divider according to claim 5, characterized in that: In the 15-bit digital frequency divider module, the CML logic gate circuit module embeds the D flip-flop unit of the 15-bit digital counter, shortening the signal transmission path; In the 4-level / 2 / 3 analog frequency divider module, CML logic gates form the differential input pairs and cascaded buffer nodes of the / 2 / 3 circuit, supporting high-frequency signal processing; In the control path, the DIG COUNTER module outputs D in differential form through CML logic gates. <0> ~D <3> Control signals are sent to the 4-level / 2 / 3-level analog frequency divider module; The RETIMER circuit module uses the CML interface to receive the VCO clock from the voltage-controlled oscillator and resamples the first-stage frequency division signal; The differential input pairs of the multiplexer and the source follower output stage in the multiplexer module are both based on the CML structure design to achieve high-frequency signal switching.

7. A frequency source chip integrating an ultra-wideband multi-mode frequency divider, characterized in that: The system includes a reference frequency divider, a frequency and phase detector, a low-pass filter, a VCO, and a feedback multimode frequency divider; the feedback multimode frequency divider is the ultra-wideband multimode frequency divider as described in any one of claims 1-6; the input of the reference frequency divider receives a reference frequency, and its output is connected to the first input of the frequency and phase detector; the second input of the frequency and phase detector is connected to the output of the feedback multimode frequency divider; the output of the frequency and phase detector is connected to the input of the low-pass filter; the output of the low-pass filter is connected to the input of the VCO; the output of the VCO is connected to the input of the feedback multimode frequency divider, and outputs the final signal; the reference frequency divider is used for... The reference frequency is divided to flexibly configure the base operating frequency of the frequency and phase detector. The frequency and phase detector compares the output frequency of the reference branch with the output frequency of the feedback multimode divider, and converts the difference between the two signals into charging current or discharging current, which is then converted into a voltage signal to control the VCO frequency through a low-pass filter. The feedback multimode divider divides the frequency signal of the VCO and generates a feedback signal, which is provided to the frequency and phase detector to form a closed-loop feedback system. Through repeated phase detection and adjustment, the output signal and input signal frequency of the feedback multimode divider finally reach the desired ratio, at which point the frequency source chip enters a locked state.

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