Equalizer, serializer / deserializer, data transmission chip and electronic equipment

Abstract

The invention discloses an equalizer, a serializer / deserializer, a data transmission chip and electronic equipment, relates to the technical field of electronics, and is used for improving the performance of an existing equalizer so as to improve the performance of SerDes. The device equalizer comprises a detection control circuit and an equalization circuit, and the detection control circuit is used for detecting rising edge change and falling edge change of a sending signal of a serializer / deserializer of a sending end and outputting a first control signal to the equalization circuit based on the rising edge change. Outputting a second control signal to the equalization circuit based on the falling edge change; and the equalization circuit is used for loading a first pulse to the signal channel bearing the sending signal in the process of changing the rising edge based on the first control signal, and loading a second pulse to the signal channel bearing the sending signal in the process of changing the falling edge based on the second control signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to an equalizer, a serializer / deserializer, a data transmission chip and an electronic device. BACKGROUND

[0002] A serializer / deserializer (SerDes) is an interface circuit used to realize high-speed data communication between chips, and is widely used in fields such as data centers, communications, consumer electronics, etc. In the process of transmitting data signals by the SerDes, the SerDes will perform real-time processing and adjustment on the transmitted data signals to ensure that the data signals can be correctly transmitted. The higher the transmission rate of the data signals, the greater the challenge to the SerDes. As a core module in the SerDes, the equalizer determines the performance of the entire SerDes in terms of the equalization capability of the data signals in the SerDes. At present, the equalization capability of the existing equalizer for data signals is limited.

[0003] Therefore, how to improve the performance of the equalizer and thus improve the performance of the SerDes has become a technical problem to be solved. SUMMARY

[0004] The present application provides an equalizer, a serializer / deserializer, a data transmission chip and an electronic device, which are used to improve the performance of the existing equalizer and thus improve the performance of the SerDes.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an equalizer is provided, which includes a detection control circuit and an equalization circuit. The detection control circuit is configured to detect rising edge changes and falling edge changes of a transmission signal of a transmitter of a SerDes, and output a first control signal to the equalization circuit based on the rising edge changes and output a second control signal to the equalization circuit based on the falling edge changes. The equalization circuit is configured to load a first pulse to a signal channel carrying the transmission signal during the process of the rising edge changes based on the first control signal, and load a second pulse to the signal channel carrying the transmission signal during the process of the falling edge changes based on the second control signal. The first pulse and the second pulse can be current pulses.

[0007] In the above technical solution, the detection and control circuit can output a corresponding first control signal or a second control signal to the equalization circuit based on the rising edge and falling edge changes of the transmitted signal. The equalization circuit can, based on the first or second control signal, apply a first pulse to the signal channel carrying the transmitted signal during the rising edge change and a second pulse to the signal channel carrying the transmitted signal during the falling edge change. Since the first pulse applied by the equalization circuit can accelerate the rising edge change rate, and the second pulse can accelerate the falling edge change rate, the transmitted signal can reach the required level as quickly as possible, reducing the rising edge change time or falling edge change time of the transmitted signal. This effectively avoids inter-symbol interference to signals at other times, thus achieving a better equalization effect. Furthermore, since the equalization circuit achieves signal equalization by applying pulses, there is no need to set up multiple multipliers, multiple delay units, and adders in the equalizer. The circuit structure of the equalizer is relatively simple, and it can improve equalization performance while reducing power consumption.

[0008] In any possible implementation of the first aspect, the first control signal includes a first direction control signal for indicating that the first pulse is a pull-up additional current; the second control signal includes a second direction control signal for indicating that the second pulse is a pull-down additional current. In the above possible implementations, under the instruction of the first direction control signal, the equalization circuit can apply the pull-up additional current to the signal channel carrying the transmitted signal to inject charge into the rising edge of the transmitted signal, thereby accelerating the rate of change of the rising edge; under the instruction of the second direction control signal, the equalization circuit can apply the pull-down additional current to the signal channel carrying the transmitted signal to extract charge from the falling edge of the transmitted signal, thereby accelerating the rate of change of the falling edge.

[0009] In any possible implementation of the first aspect, the first control signal further includes: a first time control signal and a first duration control signal; the second control signal further includes a second time control signal and a second duration control signal; wherein the first time control signal is used to indicate that the start time of the first pulse is delayed by a first duration compared to the start time of the rising edge change, and the first duration control signal is used to indicate that the duration of the first pulse is a second duration; the second time control signal is used to indicate that the start time of the second pulse is delayed by a third duration compared to the start time of the falling edge change, and the second duration control signal is used to indicate that the duration of the second pulse is a fourth duration; the equalization circuit is used to load the first pulse of the second duration onto the signal channel after the first duration following the change of the rising edge of the transmitted signal, based on the first time control signal and the first duration control signal, and to load the second pulse of the fourth duration onto the signal channel after the third duration following the change of the falling edge of the transmitted signal, based on the second time control signal and the second duration control signal. In the above possible implementation, the detection and control circuit can flexibly control the loading time and loading duration of the first pulse based on the first moment control signal and the first duration control signal, and flexibly control the loading time and loading duration of the second pulse based on the second moment control signal and the second duration control signal, which can effectively improve the application flexibility of the equalizer and ensure that the equalizer can meet the needs of different application scenarios.

[0010] In any possible implementation of the first aspect, the first control signal further includes a first intensity control signal, which indicates the amplitude of the first pulse, the amplitude of which is positively correlated with the amplitude of the rising edge change; the second control signal further includes a second intensity control signal, which indicates the amplitude of the second pulse, the amplitude of which is positively correlated with the amplitude of the falling edge change. In the above possible implementations, the amplitude of the first pulse is positively correlated with the amplitude of the rising edge change, and the amplitude of the second pulse is positively correlated with the amplitude of the falling edge change. This ensures that the first pulse can effectively increase the rate of change of the rising edge, and the second pulse can effectively increase the rate of change of the falling edge, further improving the equalization performance of the equalizer.

[0011] In any possible implementation of the first aspect, the detection and control circuit includes: an edge detection circuit and a timing control circuit; the edge detection circuit is used to: detect the rising edge change and falling edge change of the transmitted signal, and output the first direction control signal and the first intensity control signal to the equalization circuit based on the rising edge change, and output the second direction control signal and the second intensity control signal to the equalization circuit based on the falling edge change; the timing control circuit is used to: output the first moment control signal, the first duration control signal, the second moment control signal, and the second duration control signal to the equalization circuit. In the above possible implementations, the edge detection circuit and the timing control circuit can be a single circuit unit, which controls the intensity, direction, loading moment, and loading duration of the first pulse (or the second pulse); or the edge detection circuit and the timing control circuit can be implemented by two separate circuits, which respectively control the intensity and direction of the first pulse (or the second pulse), and control the loading moment and loading duration of the first pulse (or the second pulse).

[0012] In any possible implementation of the first aspect, the edge detection circuit includes a subtractor and a converter; the subtractor is configured to: during the rising edge change or the falling edge change, compare a first level of the transmitted signal at a first moment and a second level at a second moment, output the level difference between the second level and the first level to the converter, and output a borrow signal to the equalization circuit, the borrow signal being the first direction control signal or the second direction control signal; the converter is configured to: convert the level difference into the first intensity control signal or the second intensity control signal, and output the first intensity control signal or the second intensity control signal to the equalization circuit. In the above possible implementations, the borrow signal output by the subtractor can characterize whether the level change of the transmitted signal is a rising edge change or a falling edge change, therefore the borrow signal can be used as a direction control signal, and the level difference output by the subtractor can characterize the magnitude of the rising edge change or the magnitude of the falling edge change. The converter can convert the level difference into a first intensity control signal that can be recognized and processed by the equalization circuit to control the amplitude of the first pulse, or convert the level difference into a second intensity control signal that can be recognized and processed by the equalization circuit to control the amplitude of the second pulse.

[0013] In any possible implementation of the first aspect, the converter is a decoder used to decode the level difference to obtain the first intensity control signal or the second intensity control signal. The above possible implementations enable the decoded first intensity control signal or second intensity control signal to be recognized by the equalization circuit, thereby controlling the amplitude of the first pulse or the second pulse output by the equalization circuit.

[0014] In any possible implementation of the first aspect, the level difference output by the subtractor is a binary code; the decoder is a thermometer code decoder, and the first intensity control signal or the second intensity control signal is the thermometer code output by the thermometer code decoder after decoding the binary code. Based on the working principle of the thermometer code decoder, the larger the level difference output by the subtractor, the more 1s are contained in the thermometer code output by the thermometer code decoder. Based on the number of 1s contained in the thermometer code, the amplitude of the first pulse or the amplitude of the second pulse output by the equalization circuit can be controlled.

[0015] In any possible implementation of the first aspect, the edge detection circuit includes: a first edge detection sub-circuit and a second edge detection sub-circuit; the first edge detection sub-circuit is configured to: detect the rising edge change of the transmitted signal, and output the first direction control signal and the first intensity control signal to the equalization circuit based on the rising edge change; the second edge detection sub-circuit is configured to: detect the falling edge change of the transmitted signal, and output the second direction control signal and the second intensity control signal to the equalization circuit based on the falling edge change. In the above possible implementation, the first edge detection sub-circuit can detect and identify the rising edge change of the transmitted signal to output the first direction control signal and the first intensity control signal to the equalization circuit to indicate the direction of the first pulse and flexibly control the amplitude and direction of the first pulse; the second edge detection sub-circuit can detect and identify the falling edge change of the transmitted signal to output the second direction control signal and the second intensity control signal to the equalization circuit to indicate the direction of the second pulse and flexibly control the amplitude of the second pulse.

[0016] In any possible implementation of the first aspect, the equalization circuit includes: a plurality of sub-equalizers; the intensity control signal, either the first intensity control signal or the second intensity control signal, used to indicate the amplitude of the corresponding pulse includes: indicating at least one target sub-equalizer enabled among the plurality of sub-equalizers, and the number of the at least one target sub-equalizer is positively correlated with the amplitude of the rising edge change or the falling edge change; the equalization circuit is used to: load the first pulse or the second pulse onto the signal channel through the at least one target sub-equalizer based on the first intensity control signal or the second intensity control signal. In the above possible implementations, the more at least one target sub-equalizer enabled in the equalization circuit, the greater the amplitude of the first pulse or the second pulse loaded by the at least one target sub-equalizer. The number of the at least one target sub-equalizer enabled can be adjusted through the first intensity control signal or the second intensity control signal, thereby achieving flexible adjustment of the amplitude of the first pulse or the second pulse output by the equalization circuit.

[0017] In any possible implementation of the first aspect, each of the plurality of sub-equalizers includes: a first charge unit and a second charge unit; the first charge unit is used to: load the first pulse onto the signal channel; the second charge unit is used to: load the second pulse onto the signal channel. In the above possible implementation, the first charge unit can be used to load the first pulse to increase the speed of the rising edge change, and the second charge unit can be used to load the second pulse to increase the speed of the falling edge change.

[0018] In any possible implementation of the first aspect, each of the plurality of sub-equalizers is a multiplexed charge unit; the multiplexed charge unit is used to load the first pulse or the second pulse onto the signal channel. In the above possible implementations, each multiplexed charge unit can load the first pulse to increase the speed of the rising edge change, or load the second pulse to increase the speed of the falling edge change. When the sub-equalizer includes the multiplexed charge unit, since each multiplexed charge unit has the same structure, it is possible to avoid increasing the structural complexity of the equalizer, thereby avoiding increasing the power consumption of the equalizer.

[0019] In any possible implementation of the first aspect, the amplitude of the pulse output by each of the plurality of sub-equalizers is controllable. In the above possible implementation, when adjusting the amplitude of the output pulses of m (m is an integer greater than 1) enabled target sub-equalizers, the amplitude of the pulses loaded onto the signal channel by the m target sub-equalizers can be greater than m times the amplitude of the pulse loaded by a single target sub-equalizer, less than m times the amplitude of the pulse loaded by a single target sub-equalizer, or equal to m times the amplitude of the pulse loaded by a single target sub-equalizer, thereby achieving a further goal of flexibly adjusting the charge injection intensity or charge extraction intensity according to the code pattern.

[0020] In a second aspect, a serializer / deserializer is provided, comprising: a driving circuit, and an equalizer as provided in the first aspect or any possible implementation thereof; the driving circuit is configured to: drive a transmission signal; the output of the equalizer is connected to the output of the driving circuit, and the equalizer is configured to load the first pulse and the second pulse onto the output of the driving circuit.

[0021] Thirdly, a data transmission chip is provided, the data transmission chip comprising: a data processing circuit, and a serializer / deserializer as provided in the second aspect; the serializer / deserializer is used to: transmit the transmit signal output by the data processing circuit.

[0022] Fourthly, an electronic device is provided, comprising: a plurality of data transmission chips as provided in the third aspect, wherein the plurality of data transmission chips communicate with each other via a serializer / deserializer.

[0023] Understandably, the beneficial effects that can be achieved by the second to fourth aspects mentioned above can be compared with the beneficial effects of the equalizer provided by the first aspect or any possible implementation of the first aspect, which will not be repeated here. Attached Figure Description

[0024] Figure 1 A schematic diagram illustrating an application scenario of an equalizer provided in an embodiment of this application;

[0025] Figure 2 A schematic diagram illustrating another application scenario of the equalizer provided in this application embodiment;

[0026] Figure 3 A schematic diagram illustrating another application scenario of an equalizer provided in this application embodiment;

[0027] Figure 4 A schematic diagram illustrating another application scenario of the equalizer provided in the embodiments of this application;

[0028] Figures 5(a)-5(d) A schematic diagram of a feedforward equalizer provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram of the structure of an equalizer based on code pattern selection is provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the structure of an equalizer provided in an embodiment of this application;

[0031] Figure 8 A waveform diagram of an equalizer processing raw data signal provided in an embodiment of this application;

[0032] Figure 9(a) is a signal eye diagram of a transmission signal before the loading pulse provided in an embodiment of this application;

[0033] Figure 9(b) is a signal eye diagram of a transmitted signal after a loading pulse, provided in an embodiment of this application;

[0034] Figure 10 A schematic diagram of another equalizer provided in an embodiment of this application;

[0035] Figure 11 A truth table diagram of a thermometer code decoder provided in this application embodiment;

[0036] Figure 12 This is a schematic diagram of the structure of another equalizer provided in an embodiment of this application;

[0037] Figure 13This is a schematic diagram of another equalizer provided in an embodiment of this application;

[0038] Figure 14 This is a schematic diagram of the structure of a data transmission chip provided in an embodiment of this application;

[0039] Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0040] Figure 16 This is a flowchart illustrating a signal equalization method provided in an embodiment of this application. Detailed Implementation

[0041] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this application and technology, and do not limit the scope of this application.

[0042] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0043] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0044] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0045] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0046] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0047] Before introducing the embodiments of this application, the application scenarios involved in this application will be described first.

[0048] With the development of data communication services, especially the rapid development of cloud computing, big data, and the Internet of Things, higher demands are being placed on the speed and quality of data transmission. SerDes technology has become a key technology in the field of high-speed communication and is widely used in data centers, communications, and consumer electronics.

[0049] The following combination Figures 1 to 4 This section introduces several application scenarios of SerDes.

[0050] In the first possible application scenario, such as Figure 1 As shown, this SerDes can be applied to a chip, which can interconnect with an optical module via chip-to-module (C2M) technology and be housed on a single board. This chip can be a chip in a switch, such as an application-specific integrated circuit (ASIC) chip. Alternatively, the chip can be a computing chip, a memory chip, a digital signal processor (DSP) chip related to data center interconnects, or a coherent optical interconnect chip for metropolitan areas, etc.

[0051] In the second possible application scenario, such as Figure 2 As shown, this SerDes can also be applied to optical modules and can be interconnected with chips via C2M technology. Figure 2As shown, the optical module may include an optical digital signal processor (ODSP), which may include a SerDes. Optionally, the ODSP in the optical module can communicate with a chip (such as an ASIC chip or a computing chip) through the SerDes. Further, the optical module may also include a signal conversion circuit, which includes a driver, a laser, a trans-impedance amplifier (TIA), and a photodetector (PD). Electrical signals are converted to optical signals by sequentially passing through the ODSP, driver, and laser in the aforementioned devices, and optical signals are converted back to electrical signals by sequentially passing through the photodetector, trans-impedance amplifier, and ODSP in the aforementioned devices.

[0052] In the third possible application scenario, such as Figure 3 As shown, this SerDes can be applied to the interconnection of various interfaces such as the processor, memory, and peripheral component interconnect express (PCIe) within a computing board. Both the processor and memory have SerDes installed and can communicate through them. The processor is exemplified by a central processing unit (CPU) 1 and CPU 2. The memory can include double data rate (DDR) static random-access memory (SRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), and solid state disks (SSDs), etc. For example,... Figure 3 As shown, the PCIe interface may include an optical copper link (OCuLink) interface and an M.2 interface. Figure 3The card electromechanical (CEM) slot shown can be used to insert memory such as DDR and SSD. Different lengths of the CEM slot correspond to different specifications (e.g., the longest slot indicates a x16 specification, a slightly shorter slot indicates a x8 specification, and an even shorter slot indicates a x4 specification), used to insert different types of memory or expansion cards. For example, a x16 CEM slot can be used to insert graphics cards, GPUs, or other types of expansion cards. In this third possible application scenario, refer to... Figure 3 Independent SerDes can also be set up as repeaters (RTs) between CPU1 and CPU2 and the memory (or PCIe interface) to extend the signal transmission distance and enhance the signal propagation capability.

[0053] In the fourth possible application scenario, such as Figure 4 As shown, this SerDes can be applied to the interconnection between various small chips within a large chip package. For example, Figure 4 The large chip shown may include multiple graphics processing unit (GPU) modules and multiple stacked memory chips, which may be dynamic random access memory (DRAM). Both the GPU module and the DRAM may include SerDes, and the GPU modules can communicate with each other, with the GPU module and the input / output system (system + I / O), and with the GPU module and the DRAM via SerDes.

[0054] Based on the above scenario descriptions, SerDes can be used for short-range interconnects between chips or between chips and optical modules. For example, it can be applied to interconnects between computing chips and memory chips, or between GPUs and data processing units (DPUs). The package types of the optical modules can include quad small form-factor pluggable-double-density (QSFP-DD) optical modules, eight-channel octal small form-factor pluggable (OSFP) optical modules, consortium for on-board optics (COBO) optical modules, CFP2, and CFP8, etc. In CFP, "C" refers to a 100G optical module, and "FP" indicates form factor pluggable. Alternatively, this optical module can also be used in co-packaged optics (CPO) and on-board optics (OBO) scenarios.

[0055] Currently, with the continuous improvement of link transmission rates, next-generation data center optoelectronic interconnect modules will move towards 800GE / 1.6TE, where GE stands for Gigabit Ethernet and TE stands for Terabit Ethernet. During high-speed data signal transmission, SerDes needs to process and adjust data signals in real time to ensure correct transmission, thus leading to higher power consumption. In the energy consumption structure of a typical data center, information technology equipment accounts for more than 50% of the energy consumption, with network equipment accounting for approximately 10% of the energy consumption of information technology equipment, and optoelectronic modules accounting for nearly 40% of the energy consumption of network equipment. Therefore, the surge in energy consumption of optical communication equipment has put enormous pressure on the energy consumption and cost of the entire data center, making energy and cost reduction an urgent priority.

[0056] The higher the data signal transmission rate, the greater the challenge to the link, and the limited bandwidth channels between links become the bottleneck restricting the data transmission rate. As the core module in SerDes, the equalizer's ability to equalize data signals determines the overall performance of SerDes, but existing equalizers have limited capabilities in equalizing data signals.

[0057] As a first example, the feed forward equalizer (FFE) can effectively compensate for the linearity impairments that the signal suffers during transmission, including pre-cursor inter-symbol interference and post-cursor inter-symbol interference, and is therefore widely used in communication systems. Figures 5(a)-5(d) A circuit structure for a feedforward equalizer (FFE) is illustrated. The overall structure of the FFE is shown in Figure 5(a). The FFE includes an analog multiplier, an adder, delay units, tap coefficient adjustment units, and load matching. The FFE's data input receives the original data signal to be equalized. This original data signal passes through n delay units, delayed by 1, 2, ..., n unit intervals (UI), respectively. The original data signal and the n delayed data signals from these n delay units then pass through corresponding analog multipliers (represented by T1-T4 in Figure 5(a)) and are then fed into the adder with different weights. The adder sums all the data signals to obtain the pre-emphasized signal. The number of delay units and analog multipliers can be configured according to actual conditions; Figure 5(a) uses 3 delay units and 4 analog multipliers as an example. Figure 5(b) shows the circuit structure of the four analog multipliers mentioned above. Each analog multiplier includes two transistors, two adjustable current sources, and resistors. The specific connections are shown in Figure 5(b). Each analog multiplier changes the current magnitude by adjusting the adjustable current sources, thereby achieving different tap coefficients. Figure 5(c) shows the circuit structure of the adjustable current source, which includes a digital-to-analog converter (DAC), an operational amplifier, and multiple P-type transistors. The specific connections are shown in Figure 5(c). Figure 5(d) shows a schematic diagram of the delay unit, which also includes multiple transistors. The connections of these transistors are shown in Figure 5(d). As can be seen from the above, the circuit structure of this FFE is relatively complex. Increasing the number of taps (the number of analog multipliers) in the FFE, while improving its equalization capability to some extent, also increases the number of circuit branches, further exacerbating the circuit complexity and power consumption of the FFE. Furthermore, this FFE eliminates all inter-symbol interference in the original data at the same ratio, resulting in a generally poor effect on inter-symbol interference elimination and limited equalization capability.

[0058] As a second example Figure 6An example of a pattern selection-based equalizer is presented. This equalizer includes a 4-Level Pulse Amplitude Modulation (PMA4) driver, a pattern detection logic unit, and an equalizer module. The pattern detection logic unit detects the data stream from the transmitting end. When it detects a specific pattern (i.e., the pattern determined based on the MSB and LSB of the transmitting end's data stream), it generates a corresponding pull-down control signal PDN / PDP. The equalizer module generates a single-ended pull-down current under the action of this pull-down control signal PDN / PDP, thereby increasing the equalization strength for the specific pattern. Here, MSB refers to the most significant bit, and LSB refers to the least significant bit. Figure 6 It can be seen that this equalizer can only equalize the PMA4 signal, and only increases the equalization strength for a specific code pattern. For non-specific code patterns or non-PMA4 signals in the PMA4 signal, the equalizer's equalization capability is not strong.

[0059] Based on this, embodiments of this application provide an equalizer that can be applied to SerDes. The circuit structure of this equalizer is simpler than the first and second examples described above. It can not only accelerate the rising edge change of the transmitted signal but also accelerate the falling edge change, thereby achieving the purpose of eliminating inter-symbol interference. Furthermore, compared to the equalizer in the first example, the equalizer provided in this application has lower power consumption and better equalization performance; compared to the equalizer in the second example, the equalization method provided in this application is more flexible and has better equalization performance. Therefore, when SerDes uses the equalizer provided in this application, its performance can be improved without significantly increasing circuit complexity and power consumption.

[0060] Figure 7 This is a schematic diagram of an equalizer provided in an embodiment of this application. The equalizer 10 is applied in a SerDes transmitter. The equalizer 10 includes a detection and control circuit 11 and an equalization circuit 12. The detection and control circuit 11 is used to detect the rising edge and falling edge changes of the transmitted signal of the SerDes at the transmitting end, and outputs a first control signal to the equalization circuit 12 based on the rising edge change, and outputs a second control signal to the equalization circuit 12 based on the falling edge change. The equalization circuit 12 is used to: based on the first control signal, load a first pulse onto the signal channel carrying the transmitted signal during the rising edge change; and based on the second control signal, load a second pulse onto the signal channel carrying the transmitted signal during the falling edge change.

[0061] The rising edge transition process represents the period from the start time of the rising edge transition to the end time of the rising edge transition, and the falling edge transition process represents the period from the start time of the falling edge transition to the end time of the falling edge transition. The first control signal can be used to instruct the equalization circuit 12 to apply the first pulse to the signal channel carrying the transmitted signal during the rising edge transition process. The second control signal can be used to instruct the equalization circuit 12 to apply the second pulse to the signal channel carrying the transmitted signal during the falling edge transition process. The first pulse is used to accelerate the rising edge transition rate, and the second pulse is used to accelerate the falling edge transition rate.

[0062] Furthermore, the signal channel carrying this transmitted signal can also be called the load channel of the SerDes transmitter, which can be equivalent to... Figure 7 The resistor-capacitor (RC) circuit shown, or the load channel, can also be equivalent to a resistor-inductor-capacitor (RLC) circuit. The SerDes transmitter also includes a drive circuit 20 for driving the transmit signal to the load channel. For example, the drive circuit 20 can also be referred to as the transmitter's main data path, and the equalizer 10 can be referred to as the transmitter's auxiliary path.

[0063] Optionally, the first pulse and the second pulse can be current pulses. The equalization circuit 12 can load the first pulse by injecting charge into the load channel and load the second pulse by extracting charge from the load channel.

[0064] In one possible embodiment, the first control signal includes a first direction control signal for indicating that the first pulse is an upward additional current; the second control signal includes a second direction control signal for indicating that the second pulse is a downward additional current.

[0065] For example, during the rising edge transition of the transmitted signal, as the signal level gradually increases, the equalization circuit 12, under the instruction of the first direction control signal, applies an additional pull-up current to the signal channel carrying the transmitted signal to inject charge at the rising edge of the transmitted signal. Similarly, during the falling edge transition of the transmitted signal, as the signal level gradually decreases, the equalization circuit 12, under the instruction of the second direction control signal, applies an additional pull-down current to the signal channel carrying the transmitted signal to extract charge at the falling edge of the transmitted signal.

[0066] Furthermore, the first control signal further includes a first time control signal and a first duration control signal; the second control signal further includes a second time control signal and a second duration control signal. Specifically, the first time control signal indicates that the start time of the first pulse is delayed by a first duration compared to the start time of the rising edge change, and the first duration control signal indicates that the duration of the first pulse is a second duration; the second time control signal indicates that the start time of the second pulse is delayed by a third duration compared to the start time of the falling edge change, and the second duration control signal indicates that the duration of the second pulse is a fourth duration. The equalization circuit 12 is further configured to: based on the first time control signal and the first duration control signal, load the first pulse of the second duration onto the signal channel after the first duration following the change of the rising edge of the transmitted signal, and based on the second time control signal and the second duration control signal, load the second pulse of the fourth duration onto the signal channel after the third duration following the change of the falling edge of the transmitted signal.

[0067] Wherein, the first duration represents the time interval between the start time of the rising edge change and the first pulse loading time, the second duration represents the time interval between the first pulse loading time and the first pulse loading end time, the third duration represents the time interval between the start time of the falling edge change and the second pulse loading time, and the fourth duration represents the time interval between the second pulse loading time and the second pulse loading end time.

[0068] Furthermore, at the rising edge of the transmitted signal, the equalization circuit 12 may begin loading the first pulse onto the signal channel after the rising edge of the transmitted signal has lasted for a first duration. The duration of the first pulse is the second duration. After the first pulse has been loaded for the second duration, the equalization circuit 12 stops loading the first pulse. At the falling edge of the transmitted signal, the equalization circuit 12 may begin loading the second pulse onto the signal channel after the falling edge of the transmitted signal has lasted for a third duration. The duration of the second pulse is the fourth duration. After the second pulse has been loaded for the fourth duration, the equalization circuit 12 stops loading the second pulse.

[0069] Optionally, if the start time and end time of the rising edge change are considered as a unit interval (UI), the sum of the first duration and the second duration can be equal to the UI, so that the first pulse can end loading at the end time of the rising edge change; similarly, if the start time and end time of the falling edge change are considered as one UI, the sum of the third duration and the fourth duration can be equal to the UI, so that the second pulse can end loading at the end time of the falling edge change.

[0070] For ease of description, the first duration control signal and the second duration control signal will be referred to as duration control signals, and the first time control signal and the second time control signal will be referred to as time control signals. The durations indicated by the duration control signal and the time control signal can be manually configured, or can be obtained by the detection and control circuit 11 based on an adaptive algorithm. For example, the detection control circuit 11 can be configured with multiple sets of first alternative durations and multiple sets of second alternative durations according to the rising edge change and the falling edge change, respectively. Each set of first alternative durations includes a first alternative duration and a second alternative duration, and each set of second alternative durations includes a third alternative duration and a fourth alternative duration. The detection control circuit 11 can traverse the multiple sets of first alternative durations when the rising edge changes, and output the first moment control signal and the first duration control signal to the equalization circuit 12 based on the set of first alternative durations with the best equalization effect. The detection control circuit 11 can also traverse the multiple sets of second alternative durations when the falling edge changes, and output the second moment control signal and the second duration control signal to the equalization circuit 12 based on the set of second alternative durations with the best equalization effect.

[0071] Furthermore, the first control signal also includes a first intensity control signal, which is used to indicate the amplitude (i.e., pulse intensity) of the first pulse, and the amplitude of the first pulse is positively correlated with the amplitude of the rising edge change; the second control signal also includes a second intensity control signal, which is used to indicate the amplitude of the second pulse, and the amplitude of the second pulse is positively correlated with the amplitude of the falling edge change.

[0072] The amplitude of the rising edge change represents the difference between the level at the start of the rising edge and the level at the end of the change. The larger the amplitude of the rising edge change, the larger the difference between the level at the start of the rising edge and the level at the end of the change, and the larger the slope of the rising edge change, thus the larger the amplitude of the first pulse. Similarly, the amplitude of the falling edge change represents the difference between the level at the start of the falling edge and the level at the end of the change. The larger the amplitude of the falling edge change, the larger the difference between the level at the start of the falling edge and the level at the end of the change, and the larger the slope of the falling edge change, thus the larger the amplitude of the second pulse.

[0073] The following are Figure 7 Taking the equalizer structure in the example, combined with Figure 8 This application provides a detailed description of the equalization process of the transmitted signal by the equalizer 10 provided in the embodiments of this application.

[0074] For example, refer to Figure 8The transmitted signal is represented by a solid black line, the first pulse by a dotted dashed line, and the second pulse by a straight dashed line. Assuming the transmitted signal level is 3 at time t0 and begins to decrease, and is 2 at time t1 and stops decreasing, then within a UI between times t0 and t1, the edge change of the transmitted signal is a falling edge change. Based on this falling edge change, the detection and control circuit 11 outputs the second control signal to the equalization circuit 12. The second control signal includes the second direction control signal, the second duration control signal, the second time control signal, and the second intensity control signal. Specifically, the second direction control signal indicates that the second pulse is a pull-down additional current, used to perform charge extraction processing on the transmitted signal within a UI between time t0 and time t1, thereby changing the falling speed of the transmitted signal; the second duration control signal indicates that the time interval between the second pulse and time t0 is a third duration Td1 (i.e., delayed by a third duration Td1 compared to time t0); the second time control signal indicates that the duration of the second pulse (i.e., the loading duration) is a fourth duration T1; at the same time, the level of the transmitted signal drops from 3 to 2, with a level change amplitude of 1, and the second intensity control signal indicates that the amplitude of the second pulse is related to the level change of 1 on the falling edge.

[0075] Similarly, assuming the level of the transmitted signal is 2 at time t2 and begins to rise, and the level is 3 at time t3 and stops rising, then within a period UI between time t2 and time t3, the edge change of the transmitted signal is a rising edge change. Based on this rising edge change, the detection and control circuit 11 outputs the first control signal to the equalization circuit 12. The first control signal includes the first direction control signal, the first duration control signal, the first time control signal, and the first intensity control signal. Specifically, the first direction control signal indicates that the first pulse is a pull-up additional current, used to perform charge injection processing on the transmitted signal within a UI between time t2 and time t3, thereby changing the rise rate of the transmitted signal; the first duration control signal indicates that the time interval between the first pulse and time t2 is a first duration Td4 (i.e., delayed by a first duration Td4 compared to time t2); the first time control signal indicates that the duration of the first pulse is a second duration T4; simultaneously, the level of the transmitted signal rises from 2 to 3, with a level change amplitude of 1, and the first intensity control signal indicates that the amplitude of the first pulse is related to the level change of 1 at the rising edge.

[0076] For example, within a UI between times t4 and t5, the level of the transmitted signal drops from 3 to 1, with a level change of 2. The second strength control signal can indicate that the amplitude of the second pulse is related to the level change of 2 on the falling edge, and the edge change of the transmitted signal is a falling edge change. Accordingly, the time interval between the second pulse and time t4 is a third duration Td2 (i.e., delayed by a third duration Td2 compared to time t4), and the duration of the second pulse is a fourth duration T2. ​​Within a UI between times t6 and t7, the level of the transmitted signal rises from 1 to 3, with a level change of 2. The first strength control signal can indicate that the amplitude of the first pulse is related to the level change of 2 on the rising edge, and the edge change of the transmitted signal is a rising edge change. Accordingly, the time interval between the first pulse and time t6 is a first duration Td5 (i.e., delayed by a first duration Td5 compared to time t6), and the duration of the first pulse is a second duration T5.

[0077] For example, within a UI between times t8 and t9, the level of the transmitted signal drops from 3 to 0, with a level change amplitude of 3. The second strength control signal can indicate that the amplitude of the second pulse is related to the falling edge change of level 3, and the edge change of the transmitted signal is a falling edge change. Accordingly, the time interval between the second pulse and time t8 is a third duration Td3 (i.e., delayed by a third duration Td3 compared to time t8), and the duration of the second pulse is a fourth duration T3. Within a UI between times t10 and t11, the level of the transmitted signal rises from 0 to 3, with a level change amplitude of 3. The first strength control signal can indicate that the amplitude of the first pulse is related to the rising edge change of level 3, and the edge change of the transmitted signal is a rising edge change. Accordingly, the time interval between the first pulse and time t10 is a first duration Td6 (i.e., delayed by a first duration Td6 compared to time t10), and the duration of the first pulse is a second duration T6.

[0078] Figures 9(a)-9(b)This application provides an embodiment of a signal eye diagram for a transmitted signal before and after a loading pulse, using a PAM4-modulated signal as an example. In the signal eye diagram, the size of the "eye" (represented by the elliptical dashed line in Figures 9(a) and 9(b)) indicates the strength of crosstalk between signals. The larger the eye opening, the more positive the eye diagram, and the weaker the crosstalk. Figure 9(a) shows the signal eye diagram of the transmitted signal before the loading pulse, and Figure 9(b) shows the signal eye diagram of the transmitted signal after equalization processing using the equalizer 10 provided in this application embodiment. Clearly, compared to Figure 9(a), the eye opening in Figure 9(b) is larger. Therefore, when the transmitted signal is equalized using the equalizer 10 provided in this application embodiment, crosstalk between signals can be effectively reduced.

[0079] Based on the structure and operation of the equalizer 10 described above, the detection and control circuit 11 can output a corresponding first control signal or a second control signal to the equalization circuit 12 based on the rising and falling edge changes of the transmitted signal. The equalization circuit 12 can, based on the first or second control signal, apply a first pulse to the signal channel carrying the transmitted signal during the rising edge change and a second pulse to the signal channel carrying the transmitted signal during the falling edge change. Since the first pulse applied by the equalization circuit 12 can accelerate the rising edge change rate, and the second pulse can accelerate the falling edge change rate, the transmitted signal can reach the required level as quickly as possible, reducing the rising or falling edge change time of the transmitted signal. This effectively avoids inter-symbol interference to signals at other times, thereby achieving a better equalization effect. Furthermore, the equalization circuit 12 achieves signal equalization by loading pulses. Compared with other equalizers provided above, it does not require multiple multipliers, multiple delay units, and adders. Therefore, the circuit structure of the equalizer 10 provided in this application embodiment is relatively simple, and it can improve equalization performance while reducing power consumption.

[0080] Furthermore, within a unit time interval, the loading time and duration of the first pulse or the second pulse by the equalizer 10 can be flexibly adjusted. Therefore, the equalizer 10 provided in this application embodiment has a wider range of applications and higher application flexibility.

[0081] Furthermore, combined with Figure 7 , Figure 10A schematic diagram of another equalizer 10 provided in an embodiment of this application is illustrated. Optionally, the detection and control circuit 11 may include an edge detection circuit 111 and a timing control circuit 112. The edge detection circuit 111 is used to detect the rising edge change and falling edge change of the transmitted signal, and output the first direction control signal and the first intensity control signal to the equalization circuit 12 based on the rising edge change, and output the second direction control signal and the second intensity control signal to the equalization circuit 12 based on the falling edge change. The timing control circuit 112 is used to output the first moment control signal, the first duration control signal, the second moment control signal, and the second duration control signal to the equalization circuit 12.

[0082] Specifically, the edge detection circuit 111 can detect the rising edge change of the transmitted signal and control the direction and intensity of the first pulse based on the rising edge change. The edge detection circuit 111 can also detect the falling edge change of the transmitted signal and control the direction and intensity of the second pulse based on the falling edge change. The timing control circuit 112 can control the loading time and duration of the first pulse, i.e., control the first duration and the second duration of the first pulse. The timing control circuit 112 can also control the loading time and duration of the second pulse, i.e., control the third duration and the fourth duration of the second pulse. Here, T represents the second duration of the first pulse or the fourth duration of the second pulse, and Td represents the first duration of the first pulse or the third duration of the second pulse.

[0083] Optionally, the edge detection circuit 111 and the timing control circuit 112 can be implemented by one circuit or by two separate circuits, and the two circuits can be coupled.

[0084] In addition, the edge detection circuit 111 can output only the direction control signal without outputting the intensity control signal, and the equalization circuit 12 can output the first pulse and the second pulse with fixed intensity.

[0085] Optional, such as Figure 10 As shown, the edge detection circuit 111 includes a subtractor 1111 and a converter 1112. The subtractor 1111 compares the first level of the transmitted signal at a first moment and the second level at a second moment during the rising edge change or the falling edge change, outputs the level difference between the second level and the first level to the converter 1112, and outputs a borrow signal to the equalization circuit 12. The borrow signal is either the first direction control signal or the second direction control signal. The converter 1112 converts the level difference into the first intensity control signal or the second intensity control signal, and outputs the first intensity control signal or the second intensity control signal to the equalization circuit 12.

[0086] Here, the first time and the second time can represent two adjacent sampling times, the first time can represent the previous sampling time, and the second time can represent the current sampling time.

[0087] Specifically, during the rising edge change process, the subtractor 1111 can compare the second level of the transmitted signal at the current sampling moment with the first level at the previous sampling moment, and subtract the first level and the second level to obtain the level difference between the second level and the first level, as well as the borrow signal; the subtractor 1111 can output the level difference to the converter 1112 and output the borrow signal to the equalization circuit 12, the borrow signal being the first direction control signal; the converter 1112 can convert the level difference into the first intensity control signal that can be recognized by the equalization circuit 12, and output the first intensity control signal to the equalization circuit 12, thereby controlling the amplitude of the first pulse. Similarly, during the falling edge transition, the subtractor 1111 can compare the second level of the transmitted signal at the current sampling moment with the first level at the previous sampling moment, and subtract the first level and the second level to obtain the level difference between the second level and the first level, as well as a borrow signal; the subtractor 1111 can output the level difference to the converter 1112 and output the borrow signal to the equalization circuit 12, the borrow signal being the second direction control signal; the converter 1112 can convert the level difference into the second intensity control signal that can be recognized by the equalization circuit 12, and output the second intensity control signal to the equalization circuit 12, thereby controlling the amplitude of the second pulse.

[0088] For example, such as Figure 10 As shown, the input terminal INA of the subtractor 1111 can be used to receive the second level D0 at the current sampling time, and the input terminal INB is used to receive the first level D1 at the previous sampling time. The output of the subtractor 1111 is O. A-B The level difference between the unsigned bits of input terminals INA and INB, i.e., D0-D1 of the unsigned bits. This level difference of the unsigned bits can characterize the magnitude of the level change of the transmitted signal at two adjacent sampling times. The converter 1112 converts this level difference to obtain a strength control signal for controlling the equalization circuit 12. This strength control signal includes either the first strength control signal or the second strength control signal mentioned above.

[0089] like Figure 10As shown, the subtractor 1111 also has a borrow output terminal, which can output the borrow signal. Based on the working principle of the subtractor 1111, it is known that the borrow signal can characterize the magnitude of the second level D0 and the first level D1, that is, characterize the direction of the level change of the transmitted signal. Therefore, the borrow signal can be used as a direction control signal, which includes the aforementioned first direction control signal or second direction control signal. For example, the borrow signal can be 1 bit of data, and when the borrow signal is 0, it can indicate no borrow, that is, the second level is greater than the first level, and the level change of the transmitted signal is a rising edge change. When the borrow signal is 1, it can indicate a borrow, that is, the second level is less than the first level, and the level change of the transmitted signal is a falling edge change. Furthermore, when the first level D1 of the transmitted signal at the first moment and the second level D0 at the second moment are equal, the level of the transmitted signal does not change, and the borrow signal is also 0, indicating no borrow. At the same time, the level difference of the output of the subtractor 1111 is also 0. Therefore, the intensity control signal output by the converter 1112 after converting the level difference to 0 can instruct the equalization circuit 12 not to output the first pulse. For example, the first intensity control signal instructs the equalization circuit 12 to remain in the disabled state.

[0090] Furthermore, the converter 1112 can be a decoder used to decode the level difference to obtain the first strength control signal or the second strength control signal.

[0091] Specifically, the decoder can decode the level difference into a first intensity control signal that controls the amplitude of the first pulse output by the equalization circuit 12, or decode the level difference into a second intensity control signal that controls the amplitude of the second pulse output by the equalization circuit 12.

[0092] Optional, such as Figure 10As shown, the equalization circuit 12 may include multiple sub-equalizers, each capable of loading a pulse onto the signal channel. The decoder can decode the level difference into a first intensity control signal capable of controlling the multiple sub-equalizers. The first intensity control signal, used to indicate the amplitude of the first pulse, includes: the first intensity signal indicating the number of at least one target sub-equalizer enabled among the multiple sub-equalizers, and the number of the at least one target sub-equalizer being positively correlated with the amplitude of the rising edge variation of the transmitted signal. The decoder can also decode the level difference into a second intensity control signal capable of controlling the multiple sub-equalizers. The second intensity control signal, used to indicate the amplitude of the second pulse, includes: the second intensity signal indicating the number of at least one target sub-equalizer enabled among the multiple sub-equalizers, and the number of the at least one target sub-equalizer being positively correlated with the amplitude of the falling edge variation of the transmitted signal. Accordingly, the equalization circuit 12 can load the first pulse onto the signal channel through the at least one target sub-equalizer based on the first intensity control signal; or, the equalization circuit 12 can load the second pulse onto the signal channel through the at least one target sub-equalizer based on the second intensity control signal.

[0093] The circuit structures of the aforementioned multiple sub-equalizers can be identical. When n (n is an integer greater than 1) target sub-equalizers are enabled, the amplitude of the pulses loaded onto the signal channel by these n target sub-equalizers can be n times the amplitude of the pulse loaded by a single target sub-equalizer. The more target sub-equalizers enabled, the larger the amplitude of the first pulse or the second pulse loaded onto the signal channel. Therefore, the amplitude of the first pulse or the second pulse can be flexibly adjusted by adjusting the number of enabled target sub-equalizers among the multiple sub-equalizers.

[0094] Optionally, the amplitude of the pulse output by each of the multiple sub-equalizers can be controlled. That is, the amplitude of the pulse loaded by each sub-equalizer onto the signal channel can be adjusted. The signal used to adjust the amplitude of the pulse loaded by each sub-equalizer onto the signal channel will be referred to as the charge intensity control signal.

[0095] In the first example, the first control signal and the second control signal may further include the charge intensity control signal, in which case the charge intensity control signal can be output by the detection control circuit 11 to the at least one target sub-equalizer.

[0096] In the second example, the first intensity control signal and the second intensity control signal include the charge intensity control signal, which can be output by the edge detection circuit 111 to the at least one target sub-equalizer.

[0097] In the third example, the duration control signal includes the charge intensity control signal, or the time control signal includes the charge intensity control signal, in which case the charge intensity control signal can be output by the time control circuit 112 to the at least one target sub-equalizer.

[0098] In the fourth example, the charge intensity control signal can be output to the at least one target sub-equalizer by other control circuitry.

[0099] Based on the four examples above, the charge intensity control signal can adjust the amplitude of the output pulse of one or more target sub-equalizers in the at least one target sub-equalizer, thereby allowing for more precise adjustment of the amplitude of the first pulse or the second pulse, to achieve further flexible adjustment of the charge injection intensity or charge extraction intensity according to the code pattern. For example, when using this charge intensity control signal to adjust the amplitude of the output pulses of m (m is an integer greater than 1) enabled target sub-equalizers, the amplitude of the pulses loaded into the signal channel by the m target sub-equalizers can be greater than m times the amplitude of the pulse loaded by a single target sub-equalizer, less than m times the amplitude of the pulse loaded by a single target sub-equalizer, or equal to m times the amplitude of the pulse loaded by a single target sub-equalizer.

[0100] Optionally, the level difference output by the subtractor 1111 is a binary code; the decoder is a thermometer code decoder, and the first intensity control signal or the second intensity control signal is the thermometer code output by the thermometer code decoder after decoding the binary code.

[0101] Based on the working principle of the thermometer code decoder, the larger the level difference output by the subtractor 1111, the more 1s are contained in the thermometer code output by the thermometer code decoder. The equalization circuit 12 can control the amplitude of the first pulse or the amplitude of the second pulse it outputs based on the number of 1s contained in the thermometer code.

[0102] In this embodiment, the transmitted signal can be modulated using N-order PAM, where N can be an integer greater than 1. For example, when N is 2, it indicates that the transmitted signal uses non-return-to-zero (NRZ) modulation; when N is 3, it indicates that the transmitted signal uses PAM3 modulation; when N is 5, it indicates that the transmitted signal uses PAM5 modulation; and when N is 8, it indicates that the transmitted signal uses PAM8 modulation. The subtractor 1111 can be a log2(N)-bit subtractor 1111, meaning that both the input and output of the subtractor 1111 are log2(N)-bit binary numbers. The input of the thermometer code decoder can be a log2(N)-bit binary number, and the output can be an N-1-bit thermometer code. When N is 3, the subtractor 1111 has the same number of bits as the subtractor 1111 when N is 4, both being log2(4) bits. The input and output bits of the thermometer code decoder can also be the same as when N is 4. When N is 5, the subtractor 1111 has the same number of bits as the subtractor 1111 when N is 8, both being log2(8) bits. The input and output bits of the thermometer code decoder can also be the same as when N is 8. Therefore, the input and output bits of the subtractor 1111 and the thermometer code decoder can all be related to positive integer powers of 2.

[0103] Figure 11 This is a truth table for a thermometer code decoder provided in an embodiment of this application, showing the input and output of the thermometer code decoder when N=2, N=4, and N=8, respectively. Figure 11 As shown, when N=2, i.e., the transmitted signal is an NRZ signal, the input of the thermometer code decoder is a binary number 0 or 1. Furthermore, when the input is 0, the output is also 0; when the input is 1, the output is also 1. When N=4, i.e., the transmitted signal is a PAM4 signal, the input of the thermometer code decoder is a binary number 00, 01, 10, or 11. Furthermore, when the input is 00, the output is 000; when the input is 01, the output is 001; when the input is 10, the output is 011; and when the input is 11, the output is 111. Figure 11 As can be seen, the number of 1s in the N-1 bits of thermometer code output by this thermometer code decoder is the same as the value of the input binary number. For example, when the input of the thermometer code decoder is the binary number 111, since 111 represents 7, the output thermometer code includes 7 1s. When the input of the thermometer code decoder is the binary number 100, since 100 represents 4, the output thermometer code includes 4 1s.

[0104] For example, such as Figure 10 As shown, the equalization circuit 12 may include N-1 sub-equalizers, and the N-1 bits of thermometer code output by the thermometer code decoder can correspond one-to-one with the N-1 sub-equalizers. Each bit of the N-1 thermometer code can serve as an enable signal for the corresponding sub-equalizer. When any bit of the N-1 thermometer code is 1, it indicates that the sub-equalizer corresponding to that bit is enabled; when any bit of the N-1 thermometer code is 0, it indicates that the sub-equalizer corresponding to that bit is not enabled. The enabled sub-equalizer (i.e., the target sub-equalizer) can apply pulses to the signal channel, while the disabled sub-equalizer will not apply pulses to the signal channel.

[0105] The above-described edge detection circuit 111 based on subtractor 1111 and converter 1112 is merely an illustration. In this embodiment, the edge detection circuit 111 can also be implemented in other ways, as long as it is ensured that the edge detection circuit 111 can output a first direction control signal (or output a first direction control signal and a first intensity control signal) based on the rising edge change of the transmitted signal, and can output a second direction control signal (or output a second direction control signal and a second intensity control signal) based on the falling edge change of the transmitted signal.

[0106] In one example, for each sub-equalizer in the equalization circuit 12, each sub-equalizer in the equalization circuit 12 can be a multiplexed charge unit; the multiplexed charge unit is used to load the first pulse or the second pulse onto the signal channel.

[0107] Specifically, such as Figure 10 As shown, each sub-equalizer can receive the first control signal and, under the control of the first control signal, can load the first pulse onto the signal channel to accelerate the change speed of the rising edge. Each sub-equalizer can also receive the second control signal and, under the control of the second control signal, can load the second pulse onto the signal channel to accelerate the change speed of the falling edge.

[0108] In another example, each of the plurality of sub-equalizers includes a first charge unit 121 and a second charge unit 122. The first charge unit 121 is used to load the first pulse into the signal channel. The second charge unit 122 is used to load the second pulse into the signal channel.

[0109] Specifically, such as Figure 12As shown, the first charge unit 121 can receive the first control signal and, during the change of the rising edge, load the first pulse onto the signal channel based on the first control signal to accelerate the change speed of the rising edge; the second charge unit 122 can receive the second control signal and, during the change of the falling edge, load the second pulse onto the signal channel based on the second control signal to accelerate the change speed of the falling edge.

[0110] In the two examples above, the first control signal may include a first intensity control signal, a first direction control signal, a first time control signal, a first duration control signal, and a charge intensity control signal, and the second control signal may include a second intensity control signal, a second direction control signal, a second time control signal, a second duration control signal, and a charge intensity control signal.

[0111] Optionally, each charge unit in the equalization circuit 12 (e.g., first charge unit 121, second charge unit 122, or multiplexed charge unit) may include at least one transistor, and an RC circuit (such as a first-order RC circuit) or an RLC circuit. In this embodiment, the structure of the at least one transistor, RC circuit, and / or RLC circuit can be flexibly selected based on the needs of the application scenario to flexibly adjust the shape of the pulse applied to the signal channel, thereby flexibly adjusting the equalization effect of the equalizer 10.

[0112] Furthermore, the structures of the first charge unit 121 and the second charge unit 122 can be the same or different, as long as it is ensured that the first charge unit 121 and the second charge unit 122 can recognize and process the control signals provided by the detection control circuit 11.

[0113] It is also understandable that, as mentioned above, the edge detection circuit 111 may not require an output intensity control signal. Correspondingly, the equalization circuit 12 may have only one sub-equalizer, or the equalization circuit 12 may have multiple sub-equalizers, all of which may be enabled.

[0114] The following text is in the format of Figure 12 Taking the equalizer 10 structure shown as an example, combined with Figure 8 The working principle of the equalizer 10 is introduced below. Assume... Figure 8 The transmitted signal shown is a PAM4 signal. Accordingly, the input and output of the subtractor 1111 are both 2-bit binary numbers. The input of the converter 1112 is a 2-bit binary number, and the output is a 3-bit thermometer code. The equalization circuit 12 includes sub-equalizer 1, sub-equalizer 2, and sub-equalizer 3.

[0115] like Figure 8As shown, from time t0 to time t1, the level of the transmitted signal jumps from the first level D1 = 3 to the second level D0 = 2. The level difference output by the subtractor 1111 is D0 - D1 = 01, and the output borrow signal is 1, indicating that the level change of the transmitted signal is a falling edge change. This borrow signal serves as the second control signal. Combined with... Figure 11 It can be seen that the output of converter 1112 is 001. At this time, only sub-equalizer 1 is enabled, and the second direction control signal indicates that the second pulse is a pull-down additional current. Accordingly, the second charge unit 122 in the sub-equalizer 1 can be delayed by a third time period Td1 compared to time t0 to load a pull-down additional current onto the signal channel, and the duration of the pull-down additional current is a fourth time period T1.

[0116] Between time t2 and t3, the level of the transmitted signal jumps from the first level D1 = 2 to the second level D0 = 3. The level difference output by the subtractor 1111 is D0 - D1 = 01, and the borrow signal output is 0, indicating that the level change of the transmitted signal is a rising edge change. This borrow signal serves as the first control signal. Combined with... Figure 11 It can be seen that the output of converter 1112 is 001. At this time, only sub-equalizer 1 is enabled, and the first direction control signal indicates that the first pulse is a pull-up additional current. Accordingly, the first charge unit 121 in the sub-equalizer 1 can be delayed by a first duration Td4 compared to time t2 to load a pull-up additional current onto the signal channel, and the duration of the pull-up additional current is a second duration T4.

[0117] Similarly, from time t4 to t5, the level of the transmitted signal jumps from the first level D1 = 3 to the second level D0 = 1. The level difference output by the subtractor 1111 is D0 - D1 = 10, and the output borrow signal is 1, indicating that the level change of the transmitted signal is a falling edge change. This borrow signal serves as the second control signal. Combined with... Figure 11 It is known that the output of converter 1112 is 011. At this time, sub-equalizers 1 and 2 are enabled, and the second direction control signal indicates that the second pulse is a pull-down additional current. Accordingly, the second charge unit 122 in sub-equalizers 1 and 2 can be delayed by a third time interval Td2 compared to time t4 to apply a pull-down additional current to the signal channel, the duration of which is a fourth time interval T2. The pulse amplitudes of sub-equalizer 1 and sub-equalizer 2 can be the same or different.

[0118] Similarly, from time t6 to t7, the level of the transmitted signal jumps from the first level D1 = 1 to the second level D0 = 3. The level difference output by the subtractor 1111 is D0 - D1 = 10, and the borrow signal output is 0, indicating that the level change of the transmitted signal is a rising edge change. This borrow signal serves as the first control signal. Combined with...Figure 11 It is known that the output of converter 1112 is 011. At this time, sub-equalizers 1 and 2 are enabled, and the first direction control signal indicates that the first pulse is a pull-up additional current. Accordingly, the first charge unit 121 in sub-equalizers 1 and 2 can be delayed by a first duration Td5 compared to time t6 to apply a pull-up additional current to the signal channel, the duration of which is a second duration T5. The pulse amplitude of sub-equalizer 1 and the pulse amplitude of sub-equalizer 2 can be the same or different.

[0119] Comparing the falling edge amplitudes from time t0 to t1 and from time t4 to t5, we can see that the larger the falling edge amplitude, the more sub-equalizers are enabled, and the larger the amplitude of the second pulse. Similarly, comparing the rising edge amplitudes from time t2 to t3 and from time t6 to t7, we can see that the larger the rising edge amplitude, the more sub-equalizers are enabled, and the larger the amplitude of the first pulse.

[0120] Optionally, for multiple rising edges with the same amplitude, the first duration corresponding to each rising edge can be the same or different, and the second duration corresponding to each rising edge can be the same or different. Similarly, for multiple falling edges with the same amplitude, the third duration corresponding to each falling edge can be the same or different, and the fourth duration corresponding to each falling edge can be the same or different. Furthermore, for multiple rising edges with different amplitudes, the pulse intensity of each enabled target sub-equalizer can be the same or different. For multiple falling edges with different amplitudes, the pulse intensity of each enabled target sub-equalizer can be the same or different.

[0121] Furthermore, the equalizer 10 provided in this application embodiment can equalize transmitted signals using different modulation methods. For example, it can equalize not only transmitted signals using NRZ modulation, but also transmitted signals using higher-order modulation methods such as PAM3, PAM4, PAM5 or PAM8. The equalizer 10 has a wider range of applications and higher application flexibility.

[0122] Optional, such as Figure 13As shown, the edge detection circuit 111 includes a first edge detection sub-circuit and a second edge detection sub-circuit. The first edge detection sub-circuit is used to detect the rising edge change of the transmitted signal and output the first direction control signal and the first intensity control signal to the equalization circuit 12 based on the rising edge change. The second edge detection sub-circuit is used to detect the falling edge change of the transmitted signal and output the second direction control signal and the second intensity control signal to the equalization circuit 12 based on the falling edge change.

[0123] For example, such as Figure 13 As shown, the first edge detection sub-circuit is used to output the first control signal to the charge unit (including the first charge unit 121 or the multiplexed charge unit) in the equalization circuit 12 during the rising edge change of the transmitted signal; the second edge detection sub-circuit is used to output the second control signal to the charge unit (including the second charge unit 122 or the multiplexed charge unit) in the equalization circuit 12 during the falling edge change of the transmitted signal. The first edge detection sub-circuit can be a rising edge detection circuit, and the second edge detection sub-circuit can be a falling edge detection circuit. The rising edge detection circuit and the falling edge detection circuit can adopt the same circuit structure (e.g., the subtractor 1111 and converter 1112 in the aforementioned embodiment or other circuit structures), or adopt different circuit structures, as long as it is ensured that the rising edge detection circuit can detect and identify the rising edge change of the transmitted signal and output the first control signal based on the rising edge change, and the falling edge detection circuit can detect and identify the falling edge change of the transmitted signal and output the second control signal based on the falling edge change.

[0124] This application also provides a SerDes, which can be a circuit module in a chip or a separate integrated circuit (i.e., a separate chip). Figure 7 As shown, the SerDes may include an equalizer 10 as provided in the above embodiment, and a driving circuit 20. The driving circuit 20 is used to drive the transmission signal of the SerDes. For example, the driving circuit 20 may include a charge pump circuit.

[0125] from Figure 7 It can be seen that the output terminal of the equalizer 10 is connected to the output terminal of the drive circuit 20, and is used to load the first pulse or the second pulse onto the output terminal of the drive circuit 20. It can be understood that the channel where the drive circuit 20 is located is the signal channel for transmitting the signal as described above, and the output terminal of the drive circuit 20 is the loading point for loading the first pulse or the second pulse.

[0126] It is also understood that the SerDes can include a transmitter and a receiver. The equalizer 10 and the drive circuit 20 mentioned above can both be set in the transmitter to process the transmitted signal. That is, the SerDes including the equalizer 10 can be applied at the transmitting end. Since the equalization performance of the SerDes at the transmitting end is good, the number of equalization units included in the equalizer 10 used in the SerDes at the receiving end can be reduced, thereby effectively simplifying the circuit structure of the equalizer 10 at the receiving end and reducing the power consumption of the SerDes at the receiving end.

[0127] This application also provides a data transmission chip, such as... Figure 14 As shown, the data transmission chip includes a data processing circuit 100 and a SerDes 200 as provided in the above embodiment. The SerDes 200 is used to transmit the transmit signal output by the data processing circuit 100.

[0128] Optionally, the data transmission chip can be a chip within a switch, such as an ASIC chip. Alternatively, the chip can be a computing chip, a memory chip, a DSP chip related to data center interconnects, or a coherent optical interconnect chip for metropolitan areas. The computing chip can include CPUs, GPUs, and DPUs. The memory chip can include DDR, SSDs, and DRAM.

[0129] This application also provides an optical module, such as... Figure 2 As shown, the optical module may include an ODSP and a signal conversion circuit. The ODSP may include a SerDes as provided in the above embodiment. The signal conversion circuit is used to convert optical signals into electrical signals. For example, the signal conversion circuit may include a driver, a laser, a TIA, and a PD, etc.

[0130] This application also provides an electronic device, such as... Figure 15 As shown, the electronic device may include: a plurality of data transmission chips as provided in the above embodiments, which communicate with each other via SerDes. For example, Figure 15 The electronic device shown includes a data transmission chip A and a data transmission chip B, which can communicate with each other via SerDes.

[0131] Alternatively, the electronic device may include at least one data transmission chip as provided in the above embodiments, and at least one optical module as provided in the above embodiments, wherein the data transmission chip and the optical module can communicate via SerDes.

[0132] Optionally, the electronic device can be a terminal device, a server, or a network device such as a switch or router. The terminal device can include, but is not limited to: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), cameras, wearable devices (such as smartwatches, smart bracelets, pedometers, etc.), audio equipment, audio / video players, set-top boxes, game consoles, printers, mice, keyboards, in-vehicle equipment (e.g., equipment on vehicles such as cars, bicycles, electric vehicles, airplanes, ships, trains, and high-speed trains), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (e.g., refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or smart homes. Wireless terminals and flying equipment (e.g., intelligent robots, hot air balloons, drones, airplanes) in the home.

[0133] In another aspect of this application, embodiments of this application also provide a signal equalization method, which can be applied to an equalizer including a detection control circuit and an equalization circuit, the structure of which can be referred to the description above. Figure 16 As shown, the method includes:

[0134] S301: The detection and control circuit detects the rising edge and falling edge changes of the transmit signal of the serializer / deserializer at the transmitting end, and outputs a first control signal to the equalization circuit based on the rising edge change, and outputs a second control signal to the equalization circuit based on the falling edge change.

[0135] S302: Based on the first control signal, the equalization circuit loads a first pulse onto the signal channel carrying the transmitted signal during the rising edge change, and based on the second control signal, loads a second pulse onto the signal channel carrying the transmitted signal during the falling edge change.

[0136] It is understood that all relevant content involved in the above-described equalizer embodiments can be referenced in the above-described method embodiments, the SerDes embodiments, the data transmission chip embodiments, the optical module embodiments, and the electronic device embodiments, and the embodiments of this application will not be repeated here.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0138] The unit described as a separate component may or may not be physically separate. The component shown as a unit can be one physical unit or multiple physical units, that is, it can be located in one place or distributed in multiple different places. Some or all of the units can be selected to achieve the purpose of the solution in this embodiment according to actual needs.

[0139] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium can include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0140] In another embodiment of this application, a readable storage medium is also provided, which stores computer execution instructions. When the computer program or instructions are run, a device (which may be a microcontroller, chip, etc.) or a processor executes the steps in the above method embodiments.

[0141] In another embodiment of this application, a computer program product is also provided, the computer program product including computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and the at least one processor executes the computer instructions to cause the device to perform the steps in the above method embodiments.

[0142] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An equalizer, characterized in that, The equalizer includes: a detection and control circuit and an equalization circuit, wherein: The detection and control circuit is used to detect the rising edge and falling edge changes of the transmission signal of the serializer / deserializer at the transmitting end, and output a first control signal to the equalization circuit based on the rising edge change, and output a second control signal to the equalization circuit based on the falling edge change. The equalization circuit is configured to apply a first pulse to the signal channel carrying the transmitted signal based on the first control signal during the rising edge change, and to apply a second pulse to the signal channel carrying the transmitted signal based on the second control signal during the falling edge change.

2. The equalizer according to claim 1, characterized in that, The first control signal includes a first direction control signal, which indicates that the first pulse is an upward additional current; the second control signal includes a second direction control signal, which indicates that the second pulse is a downward additional current.

3. The equalizer according to claim 2, characterized in that, The first control signal further includes: a first time control signal and a first duration control signal; the second control signal further includes: a second time control signal and a second duration control signal; Wherein, the first time control signal is used to indicate that the start time of the first pulse is delayed by a first duration compared to the start time of the rising edge change, and the first duration control signal is used to indicate that the duration of the first pulse is a second duration; the second time control signal is used to indicate that the start time of the second pulse is delayed by a third duration compared to the start time of the falling edge change, and the second duration control signal is used to indicate that the duration of the second pulse is a fourth duration; The equalization circuit is configured to, based on the first time control signal and the first duration control signal, load the first pulse of the second duration onto the signal channel after the first duration following the change of the rising edge of the transmitted signal, and based on the second time control signal and the second duration control signal, load the second pulse of the fourth duration onto the signal channel after the third duration following the change of the falling edge of the transmitted signal.

4. The equalizer according to claim 3, characterized in that, The first control signal further includes a first intensity control signal, which indicates the amplitude of the first pulse, and the amplitude of the first pulse is positively correlated with the amplitude of the rising edge change; the second control signal further includes a second intensity control signal, which indicates the amplitude of the second pulse, and the amplitude of the second pulse is positively correlated with the amplitude of the falling edge change.

5. The equalizer according to claim 4, characterized in that, The detection control circuit includes: an edge detection circuit and a time control circuit; The edge detection circuit is used to detect the rising edge change and falling edge change of the transmitted signal, and output the first direction control signal and the first intensity control signal to the equalization circuit based on the rising edge change, and output the second direction control signal and the second intensity control signal to the equalization circuit based on the falling edge change. The time control circuit is used to output the first moment control signal, the first duration control signal, the second moment control signal, and the second duration control signal to the equalization circuit.

6. The equalizer according to claim 5, characterized in that, The edge detection circuit includes: a subtractor and a converter; The subtractor is used to compare the first level of the transmitted signal at a first moment and the second level at a second moment during the rising edge change or the falling edge change, output the level difference between the second level and the first level to the converter, and output a borrow signal to the equalization circuit, wherein the borrow signal is the first direction control signal or the second direction control signal. The converter is used to convert the level difference into the first intensity control signal or the second intensity control signal, and output the first intensity control signal or the second intensity control signal to the equalization circuit.

7. The equalizer according to claim 6, characterized in that, The converter is a decoder, which is used to decode the level difference to obtain the first intensity control signal or the second intensity control signal.

8. The equalizer according to claim 7, characterized in that, The level difference output by the subtractor is a binary code; The decoder is a thermometer code decoder, and the first intensity control signal or the second intensity control signal is the thermometer code output by the thermometer code decoder after decoding the binary code.

9. The equalizer according to claim 5, characterized in that, The edge detection circuit includes: a first edge detection sub-circuit and a second edge detection sub-circuit; The first edge detection sub-circuit is used to detect the rising edge change of the transmitted signal, and output the first direction control signal and the first intensity control signal to the equalization circuit based on the rising edge change. The second edge detection sub-circuit is used to detect the falling edge change of the transmitted signal, and output the second direction control signal and the second intensity control signal to the equalization circuit based on the falling edge change.

10. The equalizer according to any one of claims 4 to 9, characterized in that, The equalization circuit includes: multiple sub-equalizers; The intensity control signal, either the first intensity control signal or the second intensity control signal, is used to indicate the amplitude of the corresponding pulse, including: indicating at least one target sub-equalizer that is enabled among the plurality of sub-equalizers, and the number of the at least one target sub-equalizer is positively correlated with the amplitude of the rising edge change or the falling edge change; The equalization circuit is used to load the first pulse or the second pulse onto the signal channel through the at least one target sub-equalizer based on the first intensity control signal or the second intensity control signal.

11. The equalizer according to claim 10, characterized in that, Each of the plurality of sub-equalizers includes: a first charge unit and a second charge unit; The first charge unit is used to load the first pulse into the signal channel; The second charge unit is used to load the second pulse into the signal channel.

12. The equalizer according to claim 10, characterized in that, Each of the plurality of sub-equalizers is a multiplexed charge unit; The multiplexed charge unit is used to load the first pulse or the second pulse into the signal channel.

13. The equalizer according to any one of claims 10-12, characterized in that, The amplitude of the pulse output by each of the multiple sub-equalizers can be controlled.

14. A serializer / deserializer, characterized in that, The serializer / deserializer includes: a driver circuit, and an equalizer as described in any one of claims 1 to 13; The driving circuit is used to drive the transmission signal; The output terminal of the equalizer is connected to the output terminal of the driving circuit, and is used to load a first pulse and a second pulse onto the output terminal of the driving circuit.

15. A data transmission chip, characterized in that, The data transmission chip includes: a data processing circuit, and a serializer / deserializer as described in claim 14; The serializer / deserializer is used to transmit the transmit signal output by the data processing circuit.

16. An electronic device, characterized in that, The electronic device includes: a plurality of data transmission chips as described in claim 15, wherein the plurality of data transmission chips communicate with each other via a serializer / deserializer.

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