Semiconductor device

Abstract

A semiconductor device includes: a first active pattern and a second active pattern on a bit line structure; a cell gate structure between the first active pattern and the second active pattern; and a separation structure between the bit line structure and the cell gate structure. The cell gate structure includes: first and second gate electrodes adjacent to the first and second active patterns, respectively; an insulating layer between the first gate electrode and the second gate electrode; and a gate dielectric layer on the first and second gate electrodes and the insulating layer. The gate dielectric layer includes: a first vertical portion between the first active pattern and the first gate electrode; a second vertical portion between the second active pattern and the second gate electrode; and an intermediate portion connected to the first vertical portion and the second vertical portion. The separation structure includes: a pad between the middle portion and the bit line structure; and a cap layer between the pads.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices. Background Technology

[0002] With the increasing demand for high performance, high speed, and / or multifunctionality in semiconductor devices, the integration level of semiconductor devices has increased. In responding to this trend towards higher integration, the fabrication of finely patterned semiconductor devices requires patterns with fine widths or fine separation distances. Summary of the Invention

[0003] One aspect of this disclosure is to provide a semiconductor device including a separation structure between a bit line and a gate structure.

[0004] As a means to address the above-mentioned issues, an exemplary embodiment of this disclosure provides a semiconductor device comprising: a bit line structure; a first active pattern and a second active pattern, spaced apart from each other on the bit line structure; a cell gate structure between the first active pattern and the second active pattern; and a first separation structure between the bit line structure and the cell gate structure, wherein the cell gate structure comprises: a first gate electrode adjacent to the first active pattern; a second gate electrode adjacent to the second active pattern; an insulating layer between the first gate electrode and the second gate electrode; and a gate dielectric layer on at least a portion of the first gate electrode, the second gate electrode, and the insulating layer, the gate dielectric layer comprising: a first vertical portion including a vertical portion between the first active pattern and the first gate electrode and a vertical portion between the second active pattern and the second gate electrode; and a first intermediate portion connected to the first vertical portion and inserted between the first gate electrode, the second gate electrode, and the first separation structure, the first separation structure comprising: a first pad spaced apart from each other between the first intermediate portion of the gate dielectric layer and the bit line structure; and a first capping layer between the first pads.

[0005] Furthermore, a semiconductor device is provided, comprising: a first vertical active pattern and a second vertical active pattern spaced apart from each other; a gate structure between the first vertical active pattern and the second vertical active pattern; and an insulating structure on the gate structure, wherein the gate structure includes: at least one gate electrode; an insulating layer on the at least one gate electrode; and a gate dielectric layer on at least a portion of the insulating layer and the at least one gate electrode, wherein the gate dielectric layer includes: a first portion between the first vertical active pattern and the at least one gate electrode; a second portion between the second vertical active pattern and the at least one gate electrode; and a third portion connected to the first portion and the second portion and interposed between the at least one gate electrode and the insulating structure, wherein the insulating structure includes: pads spaced apart from each other on the third portion of the gate dielectric layer; and a capping layer between the pads.

[0006] Furthermore, a semiconductor device is provided, comprising: a storage region and a peripheral region, wherein the storage region includes: a first vertical active pattern and a second vertical active pattern spaced apart from each other; a cell gate structure between the first vertical active pattern and the second vertical active pattern; and a separation structure on the cell gate structure, wherein the cell gate structure includes: a first gate electrode adjacent to the first vertical active pattern; a second gate electrode adjacent to the second vertical active pattern; an insulating layer between the first gate electrode and the second gate electrode; and a gate dielectric layer on the insulating layer and at least a portion of the first gate electrode and the second gate electrode, wherein the separation structure includes: pads spaced apart from each other on a lower surface of the gate dielectric layer; and a capping layer between the pads, wherein the peripheral region includes an insulating structure including a lower portion and an upper portion on the lower portion, wherein the lower portion of the insulating structure includes: pad patterns spaced apart from each other on the lower surface of the upper portion; and a capping pattern between the pad patterns.

[0007] According to an example embodiment of the technical concept of this disclosure, a semiconductor device is provided, which includes a separation structure between a bit line and a gate structure.

[0008] Specifically, a semiconductor device is provided, comprising a first discrete structure and a second discrete structure, wherein the first discrete structure is located between a bit line and a cell gate structure and includes an insulating pattern, and the second discrete structure is located between a bit line and a back gate structure and includes an insulating pattern.

[0009] More specifically, according to this disclosure, a first separation structure is formed before the unit gate electrode of the unit gate structure is formed, and a second separation structure is formed before the back gate electrode of the back gate structure is formed, thereby providing a semiconductor device with reduced vertical active pattern loss.

[0010] The advantages and effects of this application are not limited to the foregoing, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein the same reference numerals (when used) consistently indicate corresponding elements in several views, and wherein:

[0012] Figure 1 This is a schematic top view of a semiconductor device according to an example embodiment;

[0013] Figure 2 It is along Figure 1 A schematic vertical cross-sectional view of the semiconductor device shown, taken along line I-I'.

[0014] Figures 3A to 3Cyes Figure 2 A partially enlarged schematic cross-sectional view of the semiconductor device shown;

[0015] Figure 4A and Figure 4B This is a partially enlarged schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0016] Figure 5A and Figure 5B This is a partially enlarged schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Figure 6A and Figure 6B This is a partially enlarged schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0018] Figure 7A and Figure 7B This is a partially enlarged schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0019] Figures 8 to 23 This is a schematic vertical cross-sectional view illustrating an intermediate process in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0020] Figures 24 to 30 This is a schematic vertical cross-sectional view illustrating intermediate processes in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; and

[0021] Figures 31 to 36 This is a schematic vertical cross-sectional view illustrating an intermediate process in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0022] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic top view of a semiconductor device according to an example embodiment. Figure 2 It is along Figure 1 The schematic vertical cross-sectional view of the semiconductor device shown is taken along line I-I'. Figure 3A yes Figure 2 A partially enlarged schematic cross-sectional view of region "A" of the semiconductor device shown. Figure 3B yes Figure 2 A partially enlarged schematic cross-sectional view of region "B" of the semiconductor device shown. Figure 3C yes Figure 2 A partially enlarged schematic cross-sectional view of region "C" of the semiconductor device shown.

[0024] refer to Figures 1 to 3CThe semiconductor device 100 may include a storage region CR and a peripheral region PR.

[0025] The memory region CR may include an insulating layer 101, a bit line 120 extending on the insulating layer 101 in a first horizontal direction (e.g., the X direction), vertical (i.e., Z direction) active patterns 140 spaced apart from each other on the bit line 120, a cell upper source / drain pattern 170 disposed on the upper part of the vertical active pattern 140, a cell lower source / drain pattern 110 disposed on the lower part of the vertical active pattern 140, and a back gate structure 130 and a cell gate structure 160 disposed between the vertical active patterns adjacent to each other in the first horizontal direction in the vertical active pattern 140.

[0026] The semiconductor device 100 may also include a first discrete structure 103 on the unit gate structure 160 and a second discrete structure 105 on the back gate structure 130.

[0027] Semiconductor device 100 may include a vertical channel transistor, the vertical channel transistor including a vertical active pattern 140, a bit line 120 electrically connected to the vertical active pattern 140, and gate structures 130 and 160 disposed on at least one side of the vertical active pattern 140.

[0028] Semiconductor device 100 can be applied to cell arrays such as dynamic random access memory (DRAM), but this disclosure is not limited thereto.

[0029] The insulating layer 101 may include an insulating material such as silicon oxide, silicon nitride, silicon nitride (SiON), or silicon carbon nitride (SiCN).

[0030] Bit line 120 may extend on insulating layer 101 in a first horizontal direction (X direction). In an example embodiment, bit line 120 may be embedded in insulating layer 101. For example, insulating layer 101 may cover the side surface of bit line 120. The term "cover" (or "covers" or similar terms) as may be used herein is intended to broadly refer to an element, structure, or layer being located directly on or over another element, structure, or layer, or having one or more other intermediate elements, structures, or layers therebetween.

[0031] Bit line 120 can be electrically connected to vertical active pattern 140 through cell lower source / drain pattern 110.

[0032] Bit line 120 may include doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, bit line 120 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x The electrode line 120 may be formed from graphene, carbon nanotubes, or combinations thereof, although the implementation is not limited thereto. In an example embodiment, the electrode line 120 may include a first conductive layer 120a and a second conductive layer 120b sequentially stacked on the insulating layer 101 in a vertical direction (i.e., the Z direction).

[0033] The first conductive layer 120a may include, for example, a metal nitride (such as titanium nitride (TiN)) or a silicide material (such as titanium silicide (TiSi)). The second conductive layer 120b may include a metallic material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). However, according to the example embodiments, the materials included in the bit line 120, the number of layers, and the cross-sectional thickness of the layers can be varied.

[0034] Vertical active patterns 140 may be spaced apart from each other on bit line 120 along a first horizontal direction (X direction). Vertical active patterns 140 may include first to third vertical active patterns 141, 142, and 143 spaced apart from each other on bit line 120. Each of the vertical active patterns 140 may include a first source / drain region and a second source / drain region, and a vertical channel region between the first and second source / drain regions. For example, each of the first to third vertical active patterns 141, 142, and 143 may include a first source / drain region SD1 contacting the lower source / drain pattern 110 of the cell, a second source / drain region SD2 contacting the upper source / drain pattern 170 of the cell, and a vertical channel region VC between the first source / drain region SD1 and the second source / drain region SD2. As may be used herein, the term “contact” (or “contacting” or similar terms such as “connect” or “connecting”) is intended to refer to a physical and / or electrical connection between two or more elements and may include other intermediate elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0035] In the example implementation, the first source / drain region SD1 and the second source / drain region SD2 may have a first conductivity type, and the vertical channel region VC may have a second conductivity type different from the first conductivity type, or it may be an undoped intrinsic region. For example, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

[0036] In an example embodiment, the vertical active pattern 140 may include a single-crystal semiconductor material. The single-crystal semiconductor material may include group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors, and may include, for example, a single-crystal semiconductor (which includes at least one of silicon, silicon carbide, germanium, and silicon germanium). However, according to an example embodiment, the vertical active pattern 140 may include at least one of polycrystalline semiconductor materials, oxide semiconductor materials (such as indium gallium zinc oxide (IGZO)), and two-dimensional materials (such as MoS2).

[0037] refer to Figure 3A The first vertical active pattern 141 can be defined as being disposed on one side of the cell gate structure 160, and the second vertical active pattern 142 can be defined as being disposed on the opposite side of the cell gate structure 160. (See reference...) Figure 3B The second vertical active pattern 142 can be defined as being disposed on one side of the back gate structure 130, and the third vertical active pattern 143 can be defined as being disposed on the opposite side of the back gate structure 130. In other words, the second vertical active pattern 142 can be defined as a vertical active pattern between adjacent gate structures 130 and 160.

[0038] Each of the cell source / drain patterns 170 may include a first cell source / drain pattern 170a and a second cell source / drain pattern 170b that are stacked sequentially. The side surfaces of the first cell source / drain pattern 170a and the second cell source / drain pattern 170b may be aligned. The first cell source / drain pattern 170a and the second cell source / drain pattern 170b may vertically overlap with and contact the vertical active pattern 140. The term “overlap” (or “overlapping” or similar terms, as may be used herein) is intended to broadly refer to the first element intersecting at least a portion of the second element in the vertical direction (i.e., the Z direction), but does not require the first element and the second element to be perfectly aligned with each other in the horizontal plane (i.e., the X direction and / or the Y direction). The first cell source / drain pattern 170a and the second cell source / drain pattern 170b may be of a first conductivity type. In other words, the source / drain pattern 170a on the first unit, the source / drain pattern 170b on the second unit, and the second source / drain region SD2 can be of the same conductivity type, and the second source / drain region SD2 can be the region defined by the source / drain pattern 170a on the first unit and the source / drain pattern 170b on the second unit.

[0039] The lower source / drain pattern 110 of the cell vertically overlaps with the vertical active pattern 140 on the bit line 120 and can contact the vertical active pattern 140. The lower source / drain pattern 110 of the cell may have a first conductivity type. In other words, the lower source / drain pattern 110 of the cell and the first source / drain region SD1 may be of the same conductivity type, and the first source / drain region SD1 may be the region defined by the lower source / drain pattern 110 of the cell. Therefore, the bit line 120 can be electrically connected to the first source / drain region SD1 of the vertical active pattern 140 through the lower source / drain pattern 110 of the cell. According to the example embodiment, the lower source / drain pattern 110 of the cell and the bit line 120 may be collectively referred to as the bit line structure.

[0040] The cell gate structure 160 may be spaced apart from each other in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction) on both sides of the back gate structure 130. As described above, the vertical active patterns on both sides of the cell gate structure 160 may be referred to as the first vertical active pattern 141 and the second vertical active pattern 142, respectively.

[0041] Each of the unit gate structures 160 may include a gate dielectric layer 162, a gate electrode 165, and gate capping layers 167 and 169.

[0042] The gate electrode 165 may include a first unit gate electrode 165_1 adjacent to the first vertical active pattern 141 and a second unit gate electrode 165_2 adjacent to the second vertical active pattern 142. The first unit gate electrode 165_1 and the second unit gate electrode 165_2 may be spaced apart from each other in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction). The first unit gate electrode 165_1 and the second unit gate electrode 165_2 may be spaced apart from the first vertical active pattern 141 and the second vertical active pattern 142 respectively through the gate dielectric layer 162. The first unit gate electrode 165_1 may overlap with the vertical channel region VC of the first vertical active pattern 141, and the second unit gate electrode 165_2 may overlap with the vertical channel region VC of the second vertical active pattern 142.

[0043] The gate electrode 165 may comprise doped polycrystalline silicon, a metal, a conductive metal nitride, a metal semiconductor compound, a conductive metal oxide, conductive graphene, carbon nanotubes, or a combination thereof. For example, the gate electrode 165 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x It is formed from graphene, carbon nanotubes or combinations thereof, but this disclosure is not limited thereto.

[0044] The lower surface of the gate electrode 165 may be spaced apart from the upper surface of the lower source / drain pattern 110 of the cell by a first distance L1 in the vertical direction (Z direction). According to an example embodiment, the first distance L1 may be in the range of about 10 nm to about 100 nm. According to an example embodiment, the first distance L1 may be in the range of about 10 nm to about 90 nm. According to an example embodiment, the first distance L1 may be in the range of about 10 nm to about 80 nm.

[0045] The gate dielectric layer 162 may include a first vertical portion 162_v and a first intermediate portion 162_m connected to the first vertical portion 162_v.

[0046] The first vertical portion 162_v may include a vertical portion 162_va between the first vertical active pattern 141 and the first cell gate electrode 165_1, and a vertical portion 162_vb between the second vertical active pattern 142 and the second cell gate electrode 165_2. Each of the vertical portions 162_va and 162_vb may extend in the vertical direction (Z direction) over the first vertical active pattern 141 and the second vertical active pattern 142 and may contact the lower surface of the cell source / drain pattern 170.

[0047] The first intermediate portion 162_m can connect the lower portions of the vertical portions 162_va and 162_vb, and can be disposed between the gate electrode 165 and the first separation structure 103. The first intermediate portion 162_m can extend horizontally between the gate electrode 165 and the first separation structure 103, but this disclosure is not limited thereto. According to an exemplary embodiment, the first intermediate portion 162_m can have an upper surface and a lower surface protruding toward the first separation structure 103 (see...). Figure 4A ).

[0048] The gate dielectric layer 162 can have a uniform thickness. For example, the first vertical portion 162_v and the first intermediate portion 162_m can have the same first width w1.

[0049] The gate dielectric layer 162 may include at least one of an oxide (e.g., silicon oxide) and a high-k dielectric. The high-k dielectric may include a metal oxide or a metal nitride. For example, the high-k dielectric may be formed from HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof, but this disclosure is not limited thereto. The gate dielectric layer 162 may be formed from multiple layers or a single layer of the above materials.

[0050] Gate capping layers 167 and 169 may include a first gate capping layer 167 between the first unit gate electrode 165_1 and the second unit gate electrode 165_2, and a second gate capping layer 169 covering the first unit gate electrode 165_1, the second unit gate electrode 165_2, and the first gate capping layer 167. The upper region of the first gate capping layer 167 may be disposed at a vertical level higher than the vertical level of the upper surfaces of the first unit gate electrode 165_1 and the second unit gate electrode 165_2 relative to the upper surface of the bit line 120, and may be disposed at a vertical level lower than the vertical level of the upper surface of the first vertical portion 162_v of the gate dielectric layer 162 relative to the upper surface of the bit line 120. Therefore, the second gate capping layer 169 may cover the upper surfaces of the first unit gate electrode 165_1 and the second unit gate electrode 165_2, and may cover the upper surface and side surface of the upper region of the first gate capping layer 167. The first gate cap layer 167 may be formed of an insulating oxide (e.g., silicon oxide), and the second gate cap layer 169 may be formed of an insulating nitride (e.g., silicon nitride).

[0051] The first separation structure 103 can be disposed between the bit line 120 (or "cell lower source / drain pattern 110") and the cell gate structure 160, and can separate the cell gate structure 160 from the bit line 120 in the vertical direction (Z direction). The side surface of the first separation structure 103 can be aligned with the side surface of the cell gate structure 160.

[0052] The first separation structure 103 may include first pads 103a spaced apart from each other in a first horizontal direction (X direction) between a first intermediate portion 162_m of the gate dielectric layer 162 and the bit line 120, and a first capping layer 103b between the first pads 103a. The first pads 103a may be formed of an insulating oxide (e.g., silicon oxide), and the first capping layer 103b may be formed of an insulating nitride (e.g., silicon nitride), but this disclosure is not limited thereto. For example, the first capping layer 103b may be formed of an insulating oxide (e.g., silicon oxide) (see [link to documentation]). Figure 5A Each of the first pads 103a may have a third width w3 in the horizontal direction.

[0053] The first separation structure 103 may have a first thickness d1 in the vertical direction (Z direction). The first thickness d1 may be smaller than the first distance L1. For example, the first thickness d1 may be at most about 10 nm smaller than the first distance L1. According to an example embodiment, the first thickness d1 may be in the range of about 10 nm to about 90 nm. According to an example embodiment, the first thickness d1 may be in the range of about 10 nm to about 80 nm. According to an example embodiment, the first thickness d1 may be in the range of about 10 nm to about 70 nm.

[0054] The back gate structures 130 may be spaced apart from each other in a first horizontal direction (X direction) and may extend in a second horizontal direction (Y direction) on both sides of the cell gate structure 160. As described above, the vertical active patterns on both sides of the back gate structure 130 may be referred to as the second vertical active pattern 142 and the third vertical active pattern 143, respectively.

[0055] Each of the back gate structures 130 may include a back gate dielectric layer 132, a back gate electrode 135, and a back gate capping layer 137.

[0056] The back gate electrode 135 may overlap with the vertical channel region VC of the second vertical active pattern 142 and the third vertical active pattern 143.

[0057] The lower surface of the back gate electrode 135 may be spaced apart from the upper surface of the lower source / drain pattern 110 of the cell by a second distance L2 in the vertical direction (Z direction). The second distance L2 may have substantially the same dimensions as the first distance L1. According to an example embodiment, the second distance L2 may be in the range of about 10 nm to about 100 nm. According to an example embodiment, the second distance L2 may be in the range of about 10 nm to about 90 nm. According to an example embodiment, the second distance L2 may be in the range of about 10 nm to about 80 nm.

[0058] The back gate electrode 135 may comprise doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, the back gate electrode 135 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x It is formed from graphene, carbon nanotubes or combinations thereof, but this disclosure is not limited thereto.

[0059] The back gate dielectric layer 132 may include a second vertical portion 132_v and a second intermediate portion 132_m connected to the second vertical portion 132_v.

[0060] The second vertical portion 132_v may include a vertical portion 132_va between the second vertical active pattern 142 and the back gate electrode 135, and a vertical portion 132_vb between the third vertical active pattern 143 and the back gate electrode 135. The vertical portions 132_va and 132_vb may extend in the vertical direction (Z direction) on the second vertical active pattern 142 and the third vertical active pattern 143, respectively, and may contact the lower surface of the source / drain pattern 170 on the cell.

[0061] The second intermediate portion 132_m connects the lower portions of the vertical portions 132_va and 132_vb, and can be disposed between the back gate electrode 135 and the second separation structure 105. The second intermediate portion 132_m can extend horizontally between the back gate electrode 135 and the second separation structure 105, but this disclosure is not limited thereto. According to an exemplary embodiment, the second intermediate portion 132_m can have an upper surface and a lower surface protruding toward the second separation structure 105 (see...). Figure 4B ).

[0062] The second vertical portion 132_v and the second intermediate portion 132_m can have the same second width w2. Here, the second width w2 can be greater than the first width w1.

[0063] The back gate dielectric layer 132 may include at least one of an oxide (e.g., silicon oxide) and a high-k dielectric. The high-k dielectric may include a metal oxide or a metal nitride. For example, the high-k dielectric may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof, but this disclosure is not limited thereto. The back gate dielectric layer 132 may be formed from multiple layers or a single layer of the above materials.

[0064] A back gate cap layer 137 may cover the upper surface of the back gate electrode 135 between the second vertical portions 132_v of the back gate dielectric layer 132. The upper surface of the back gate cap layer 137 may be at substantially the same level as the upper surface of the second vertical portion 132_v of the back gate dielectric layer 132; that is, the upper surface of the back gate cap layer 137 may be coplanar with respect to the upper surface of the bit line 120 serving as the reference layer and the upper surface of the second vertical portion 132_v of the back gate dielectric layer 132. The back gate cap layer 137 may be formed of an insulating oxide (e.g., silicon oxide).

[0065] The second separation structure 105 is disposed between the bit line 120 (or "cell lower source / drain pattern 110") and the back gate structure 130, and can separate the back gate structure 130 from the bit line 120 in the vertical direction (Z direction). The side surface of the second separation structure 105 can be aligned with the side surface of the back gate structure 130.

[0066] The second separation structure 105 may include second pads 105a spaced apart from each other in a first horizontal direction (X direction) between the second intermediate portion 132_m of the back gate dielectric layer 132 and the bit line 120, and a second capping layer 105b between the second pads 105a. The second pads 105a may include the same material as the first pads 103a, and the second capping layer 105b may include the same material as the first capping layer 103b. Therefore, the second pads 105a may be formed of an insulating oxide (e.g., silicon oxide), and the second capping layer 105b may be formed of an insulating nitride (e.g., silicon nitride). According to an example embodiment, the second capping layer 105b may be formed of an insulating oxide (e.g., silicon oxide) (see [link to example embodiment]). Figure 5B ).

[0067] Each of the second pads 105a may have a width equal to the horizontal width of each of the first pads 103a. For example, each of the second pads 105a may have a third width w3 in the horizontal direction (X direction).

[0068] The third width w3 may be different from the first width w1, and the third width w3 may be different from the second width w2. In some embodiments, the third width w3 may be substantially equal to or greater than the first width w1, and the third width w3 may be substantially equal to or less than the second width w2.

[0069] The second separation structure 105 may have a second thickness d2 in the vertical direction (Z direction). The second thickness d2 may be smaller than the second distance L2. For example, the second thickness d2 may be at most about 10 nm smaller than the second distance L2. According to an example embodiment, the second thickness d2 may be in the range of about 10 nm to about 90 nm. According to an example embodiment, the second thickness d2 may be in the range of about 10 nm to about 80 nm. According to an example embodiment, the second thickness d2 may be in the range of about 10 nm to about 70 nm.

[0070] The storage region CR may also include contact plugs 175. Contact plugs 175 may be disposed on the cell-on-source / drain pattern 170. Each of the contact plugs 175 may include a metal-semiconductor compound layer 175a in contact with the upper surface of the second cell-on-source / drain pattern 170b, and a plug pattern 175b on the metal-semiconductor compound layer 175a. Cell-on-source / drain patterns 170 and contact plugs 175 sequentially stacked in the vertical direction (Z direction) may have side surfaces aligned with each other. Contact plugs 175 may be aligned with and in contact with the cell-on-source / drain pattern 170.

[0071] The storage region CR may also include a separation pattern 107. The separation pattern 107 may define the side surfaces of the source / drain patterns 170 and contact plugs 175 on the sequentially stacked cells. The separation pattern 107 may surround the side surfaces of the source / drain patterns 170 and contact plugs 175 on the sequentially stacked cells. As may be used herein, the term "surround" (or "surrounding" or similar terms) is intended to broadly refer to an element, structure, or layer extending around, encapsulating, surrounding, or enclosing another element, structure, or layer on all sides, although breaks or gaps may also be present. Thus, for example, a material layer having voids or gaps may still "surround" the other layer it surrounds. Each of the separation patterns 107 may be positioned at the same vertical level as each other and may include the same insulating material as each other. For example, each of the separation patterns 107 may include an insulating nitride.

[0072] The storage area CR may also include an information storage structure 180 and an insulating layer 190.

[0073] The information storage structure 180 may include a first electrode 181 connected to a contact plug 175 in the storage region CR and extending in the vertical direction (Z direction), a second electrode 183 on the side and top surfaces of each of the first electrodes 181, and a dielectric layer 182 between the first electrode 181 and the second electrode 183. The information storage structure 180 may be a cell capacitor of a memory such as DRAM.

[0074] The insulating layer 190 may cover the information storage structure 180 within the storage region CR. The insulating layer 190 may include at least one of silicon oxide and low-k dielectric.

[0075] The peripheral region PR may include an insulating structure 150. The insulating structure 150 may include a lower insulating pattern 150L and an upper insulating pattern 150U on the lower insulating pattern 150L.

[0076] The lower insulating pattern 150L may include pad patterns 150La spaced apart from each other in a first horizontal direction (X direction) on the lower surface of the upper insulating pattern 150U, and cover patterns 150Lb between the pad patterns 150La. Each of the pad patterns 150La may have a width substantially equal to the width of each of the first pads 103a of the first separation structure 103 and the width of each of the second pads 105a of the second separation structure 105. That is, each of the pad patterns 150La may have a third width w3 in the first horizontal direction (X direction). The pad patterns 150La may include the same material as the first pads 103a and the second pads 105a. That is, the pad patterns 150La may be formed of an insulating oxide (e.g., silicon oxide). The cover patterns 150Lb may include the same material as the first cover layer 103b and the second cover layer 105b. That is, the cover patterns 150Lb may be formed of an insulating nitride (e.g., silicon nitride).

[0077] The lower insulating pattern 150L may have a thickness substantially the same as the first separation structure 103 in the vertical direction (Z direction). That is, the lower insulating pattern 150L may have a first thickness d1. In other words, the upper surface of the pad pattern 150La may be at substantially the same level as the upper surface of the first pad 103a, and the upper surface of the cover pattern 150Lb may be at substantially the same level as the upper surface of the first cover layer 103b (i.e., coplanar with the upper surface of the first cover layer 103b).

[0078] The upper insulating pattern 150U may include multiple insulating patterns 152, 157 and 159 and a conductive pattern 155.

[0079] The insulating pattern 152 may include a vertical portion 152v extending in the vertical direction (Z direction) on the vertical active pattern 140, and a horizontal portion 152m extending in the first horizontal direction (X direction) from the end of the lower region of the vertical portion 152v. The vertical portion 152v of the insulating pattern 152 may have an upper surface that contacts the lower surface of the source / drain pattern 170a of the first cell, and may overlap with the pad pattern 150La. The horizontal portion 152m of the insulating pattern 152 may be connected to the vertical portion 152v and may extend in the first horizontal direction (X direction) on at least a portion of the lower insulating pattern 150L. The end of the horizontal portion 152m of the insulating pattern 152 may be disposed on the cover pattern 150Lb.

[0080] The upper surface of the vertical portion 152v may be at substantially the same level as the upper surface of each of the first vertical portions 162_v of the gate dielectric layer 162 (i.e., coplanar with the upper surface of each of the first vertical portions 162_v of the gate dielectric layer 162). The lower surface of the horizontal portion 152m may be at substantially the same level as the lower surface of the first intermediate portion 162_m of the gate dielectric layer 162 (i.e., coplanar with the lower surface of the first intermediate portion 162_m of the gate dielectric layer 162). The vertical portion 152v and the horizontal portion 152m may have the same width as the first width w1 of the gate dielectric layer 162. The insulating pattern 152 and the gate dielectric layer 162 may include the same insulating material.

[0081] The conductive pattern 155 can be on the side surface of the vertical portion 152v on the horizontal portion 152m. The upper surface of the conductive pattern 155 can be at the same level as the upper surfaces of the first unit gate electrode 165_1 and the second unit gate electrode 165_2, and the lower surface of the conductive pattern 155 can be at the same level as the lower surfaces of the first unit gate electrode 165_1 and the second unit gate electrode 165_2.

[0082] The insulating pattern 157 may include a first portion 157a on the lower insulating pattern 150L and a second portion 157b having a lower surface formed to bulge downward in the vertical direction by at least a portion of the lower region of the first portion 157a. Therefore, in the vertical direction (Z direction), the level of the lowermost surface of the second portion 157b may be lower than the level of the lower surface of the horizontal portion 152m. The upper surface of the insulating pattern 157 may be at a lower level than the upper surface of the vertical portion 152m. The insulating pattern 157 may include the same material as the first gate cap layer 167 of the cell gate structure 160.

[0083] The insulating pattern 159 may include a portion that covers the upper surface of the conductive pattern 155 and extends in the vertical direction (Z direction) between the vertical portion 152v of the insulating pattern 152 and the first portion 157a of the insulating pattern 157, and a portion that extends in the first horizontal direction (X direction) on the upper surface of the first portion 157a of the insulating pattern 157.

[0084] The lower insulation pattern 150L and the upper insulation pattern 150U can be aligned.

[0085] The peripheral region PR may also include an insulating structure 177 on the upper part of the insulating structure 150. The insulating structure 177 may also include an insulating pattern 177b and an insulating pad 177a covering the side and lower surfaces of the insulating pattern 177b. The insulating pattern 177b may include an oxide, and the insulating pad 177a may include a nitride.

[0086] The insulating layer 190 of the storage region CR can extend horizontally (e.g., in the X direction) into the peripheral region PR. Therefore, the insulating layer 190 can cover the upper surface of the insulating structure 177 in the peripheral region PR.

[0087] The insulating layer 101 of the storage region CR can extend horizontally into the peripheral region PR. The insulating layer 101 can cover the side surface of the bit line 120 and the lower surface of the insulating structure 150 in the peripheral region PR.

[0088] The peripheral area PR may also include an insulating pattern 102. The side and top surfaces of the insulating pattern 102 may be covered with an insulating layer 101.

[0089] The storage area CR and the peripheral area PR may also include an insulating layer 195 disposed on the lower part of the insulating layer 101 and the insulating pattern 102.

[0090] In the following text, see references Figures 4A to 7B Various modification examples of the components of the above embodiments will be described below. The focus will be on the modified or replaced components in describing the various modifications of the components of the above embodiments described below. Furthermore, the components that can be modified or replaced as described below will be described with reference to the accompanying drawings; however, the modified or replaced components can be combined with each other or with the above components to configure a semiconductor device according to an exemplary embodiment of this disclosure.

[0091] Figure 4A and Figure 4B This is a partial magnified view of a semiconductor device according to an example embodiment. Figure 4A It shows the corresponding Figure 2 A magnified view of area "A" in the image. Figure 4B It shows the corresponding Figure 2 A magnified view of area "B" in the image.

[0092] refer to Figure 4A and Figure 4B Semiconductor device 100a can be used with reference Figures 1 to 3C The semiconductor devices described are identical or similar, except that each of the discrete structures 103 and 105 has a downwardly convex upper surface, and each of the gate electrodes 135 and 165 has a downwardly convex upper surface.

[0093] refer to Figure 4A The upper surface 103US of the first separation structure 103 may have a shape that protrudes toward the lower source / drain pattern 110 of the cell. Therefore, the first intermediate portion 162_m of the gate dielectric layer 162 may have a shape that protrudes toward the first separation structure 103. Similarly, each of the cell gate electrodes 165_1 and 165_2 and the first gate cap layer 167 may have downwardly curved lower surfaces 165LS and 167LS.

[0094] Meanwhile, in the example embodiment, each of the unit gate electrodes 165_1 and 165_2 may have a protruding upper surface 165US facing the first separation structure 103. Therefore, on the unit gate electrodes 165_1 and 165_2, the second gate capping layer 169 may have a lower surface 169LS formed to protrude towards the unit gate electrodes 165_1 and 165_2.

[0095] refer to Figure 4B The upper surface 105US of the second separation structure 105 may have a shape that protrudes toward the lower source / drain pattern 110 of the cell. Therefore, the second intermediate portion 132_m of the back gate dielectric layer 132 may have a shape that protrudes toward the second separation structure 105. Similarly, the back gate electrode 135 may have a lower surface 135LS formed to protrude downwards.

[0096] Meanwhile, in the example embodiment, the back gate electrode 135 may have an upper surface 135US formed to protrude toward the second separation structure 105. Therefore, the back gate cap layer 137 may have a lower surface 137LS formed on the back gate electrode 135 to protrude toward the back gate electrode 135.

[0097] Figure 5A and Figure 5B This is a partial magnified view of a semiconductor device according to an example embodiment. Figure 5A It shows the corresponding Figure 2 A magnified view of area "A" in the image. Figure 5B It shows the corresponding Figure 2 A magnified view of area "B" in the image.

[0098] refer to Figure 5A and Figure 5B Semiconductor device 100b can be used with reference Figures 1 to 4B The semiconductor devices described are the same or similar, except that the first capping layer 103b of the first separation structure 103 and the second capping layer 105b of the second separation structure 105 include insulating oxide.

[0099] refer to Figure 5A The first capping layer 103b may include an insulating oxide, such as silicon oxide. Therefore, the first liner 103a and the first capping layer 103b may include the same insulating material, but may be distinguishable from each other.

[0100] refer to Figure 5B The second cover layer 105b may include an insulating oxide, such as silicon oxide. Similarly, the second liner 105a and the second cover layer 105b may include the same insulating material, but may be distinguishable from each other.

[0101] Figure 6A and Figure 6B This is a partial magnified view of a semiconductor device according to an example embodiment. Figure 6A It shows the corresponding Figure 2 A magnified view of area "A" in the image. Figure 6B It shows the corresponding Figure 2 A magnified view of area "B" in the image.

[0102] refer to Figure 6A and Figure 6B Semiconductor device 100c can be compared with reference Figures 1 to 5B The semiconductor devices described are the same or similar, except that the width of each of the first pads 103a of the first separation structure 103 and the width of each of the second pads 105a of the second separation structure 105 can vary in the vertical direction (Z direction).

[0103] refer to Figure 6A The width w3' of each of the first pads 103a of the first separation structure 103 can decrease in the vertical direction (Z direction) as the distance from the lower surface of the first intermediate portion 162_m of the gate dielectric layer 162 increases. Complementarily, the horizontal width (e.g., in the X direction) of the first capping layer 103b of the first separation structure 103 can increase in the vertical direction (Z direction) as the distance from the lower surface of the first intermediate portion 162_m of the gate dielectric layer 162 increases.

[0104] refer to Figure 6BThe width w3' of each of the second pads 105a of the second separation structure 105 can decrease in the vertical direction (Z direction) as the distance from the lower surface of the second intermediate portion 132_m of the back gate dielectric layer 132 increases. Complementarily, the horizontal width of the second capping layer 105b of the second separation structure 105 can increase in the vertical direction (Z direction) as the distance from the lower surface of the second intermediate portion 132_m of the back gate dielectric layer 132 increases.

[0105] In an example implementation, the lower surface of each of the first pad 103a and the second pad 105a may contact the upper surface of the cell lower source / drain pattern 110.

[0106] Figure 7A and Figure 7B This is a partial magnified view of a semiconductor device according to an example embodiment. Figure 7A It shows the corresponding Figure 2 A magnified view of area "A" in the image. Figure 7B It shows the corresponding Figure 2 A magnified view of area "B" in the image.

[0107] refer to Figure 7A and Figure 7B Semiconductor device 100d can be compared with reference Figures 1 to 6B The semiconductor devices described are the same or similar, except that the lower surface of the first pad 103a of the first separation structure 103 and the lower surface of the second pad 105a of the second separation structure 105 do not contact the upper surface of the cell lower source / drain pattern 110.

[0108] refer to Figure 7A and Figure 7B Especially similar Figure 6A and Figure 6B The width w3' of each of the first pads 103a of the first separation structure 103 and the width w3' of each of the second pads 105a of the second separation structure 105 can decrease as the vertical distance from the upper surface of the lower source / drain pattern 110 of the cell decreases.

[0109] Compare Figure 7A and Figure 7B and Figure 6A and Figure 6B ,exist Figure 7A and Figure 7B In one embodiment, the lower surface of the first pad 103a of the first separation structure 103 and the lower surface of the second pad 105a of the second separation structure 105 may not contact the upper surface of the lower source / drain pattern 110 of the cell.

[0110] Figures 8 to 23This is a vertical cross-sectional view showing an intermediate process in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0111] refer to Figure 8 It can provide a semiconductor substrate 10 and multiple masks M1 and M2 sequentially stacked on the semiconductor substrate 10.

[0112] The semiconductor substrate 10 may be a silicon-on-insulator (SOI) substrate. The semiconductor substrate 10 may include a lower semiconductor layer 11, an insulating layer 12, and an upper semiconductor layer 13. For example, the upper semiconductor layer 13 and the lower semiconductor layer 11 may include monocrystalline silicon.

[0113] Masks M2 and M1 can be configured for use in a subsequent etching process to form the back gate trench (BGT).

[0114] Next, a back gate trench (BGT) can be formed in the semiconductor substrate 10, and an initial insulating layer 105a' can be formed in the back gate trench (BGT).

[0115] An etching process using mask M2 can be performed to form a back gate trench (BGT) that penetrates the upper semiconductor layer 13 and the insulating layer 12 (i.e., extends within the upper semiconductor layer 13 and the insulating layer 12) and exposes at least the bottom of the lower semiconductor layer 11. The term "exposing" (or "exposed" or similar terms) may be used herein to describe relationships between elements and / or to refer to intermediate processes in the fabrication of semiconductor devices, but may not require the exposure of a specific element in the completed device. Similarly, the term "not exposed" may be used to describe relationships between elements and / or to refer to intermediate processes in the fabrication of semiconductor devices, but may not require a specific element to be unexposed in the completed device. The back gate trench (BGT) may be formed as a line shape extending in a second horizontal direction (Y direction).

[0116] An initial insulating layer 105a' may be formed on the sidewalls of the back gate trench (BGT). The initial insulating layer 105a' may be deposited to substantially conformally cover the upper and side surfaces of mask M2, the side surface of mask M1, the side surface of the upper semiconductor layer 13, the side surface of the insulating layer 12, and the upper surface of the lower semiconductor layer 11. The term "conformally" (or "conformal" or similar term) as used herein in the context of material layers or coatings is intended to broadly refer to a material layer or coating having a substantially uniform profile thickness relative to the contour of the surface to which the material layer or coating is applied. The initial insulating layer 105a' may be formed by depositing an insulating material such as silicon oxide, silicon nitride, silicon oxide nitride (SiON), or silicon carbon nitride (SiCN). In this example embodiment, the initial insulating layer 105a' may be formed of silicon oxide.

[0117] refer to Figure 9 A growth-prevention film GBF1 can be formed on the surface of the upper region of the initial insulating layer 105a', and a replacement structure SS1 can be grown on the surface of the lower region of the initial insulating layer 105a'.

[0118] The growth prevention film GBF1 can be formed on the sidewall of the portion of the DLU (which may be referred to as the "upper portion") located at a distance from the lower surface of the back gate trench BGT equal to or greater than the desired level within the sidewall of the initial insulating layer 105a'. This can be achieved using a large aspect ratio of the back gate trench BGT. At least one cycle can be performed such that the growth prevention film GBF1 can be formed on the sidewall of the portion of the DLU equal to or greater than the desired level. The growth prevention film GBF1 can be formed by chemical vapor deposition (CVD) using gaseous hydrogen (H2).

[0119] Here, the growth prevention film GBF1 can be configured to selectively form a substitution structure SS1 on the surface of a portion of the DLL (which may be referred to as the “lower portion”) at a distance equal to or less than the desired level from the lower surface of the back gate trench BGT in the surface of the initial insulating layer 105a'.

[0120] Subsequently, the substituted structure SS1 can grow from the lower surface and sidewalls of the lower DLL of the initial insulating layer 105a'. Highly reactive and desired substituent materials (or predetermined substituent materials) (e.g., free radicals) can form islands on the lower surface and sidewalls of the lower DLL, which can then gradually grow to form the substituted structure SS1. The substituted structure SS1 can grow to the level required to form the growth-preventing film GBF1. The substituent material may include carbon, and the substituted structure SS1 may be referred to as an amorphous carbon layer.

[0121] refer to Figure 10It can remove the upper DLU of the initial insulating layer 105a' and the growth prevention film GBF1.

[0122] Let's refer to each other. Figure 9 and Figure 10 The upper DLU of the initial insulating layer 105a' and the growth prevention film GBF1 can be removed during the etching process. Therefore, an initial second separation structure 105p, including the initial insulating layer 105a' and the replacement structure SS1, can be formed in the lower region of the back gate trench (BGT). Simultaneously, through etching, the initial second separation structure 105p can have a downwardly convex upper surface (see...). Figure 4B ).

[0123] refer to Figure 11 It can be done in the back gate trench (BGT) (see Figure 10 The initial back gate structure 130' is formed in the middle.

[0124] An initial back gate insulating layer 132' can be formed on the sidewalls and lower surface of the back gate trench BGT. Next, conductive material can be filled into the back gate trench BGT, and then an etch-back process can be performed to form the back gate electrode 135. The term "filled" (or "filling" or similar terms) is intended to refer to either completely filling the defined space (e.g., the back gate trench BGT) or partially filling the defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or always have gaps or other spaces. Next, insulating material can be filled to cover the upper surface of the back gate electrode 135, thus forming an initial back gate capping layer 137'. Then, a planarization process can be performed to give the initial back gate structure 130' and the mask M1 a flat upper surface.

[0125] Meanwhile, in the etch-back process, the upper surface of the back gate electrode 135 can have a downwardly convex shape (see...). Figure 4B ).

[0126] refer to Figure 12 The cell gate trench CGT can be formed in the memory region CR, and the peripheral region trench PRT can be formed in the peripheral region PR.

[0127] The mask M1 on the semiconductor substrate 10 can be removed (see...) Figure 11 And, a mask M3 used in the etching process for forming the unit gate trench CGT and the peripheral region trench PRT can be formed on the semiconductor substrate 10.

[0128] Then, by using mask M3, the cell gate trench CGT between the initial back gate structures 130' can be formed in the memory region CR, and the peripheral region trench PRT can be formed in the peripheral region PR.

[0129] Then, an initial insulating layer 103a' can be formed in the cell gate trench CGT and the peripheral region trench PRT. The initial insulating layer 103a' can be formed to substantially conformally cover the upper surface of the initial back gate structure 130', the upper and side surfaces of the mask M3, the side surface of the upper semiconductor layer 13, the side surface of the insulating layer 12, and the upper surface of the lower semiconductor layer 11. The initial insulating layer 103a' can be formed by depositing an insulating material such as silicon oxide, silicon nitride, silicon oxide nitride (SiON), or silicon carbon nitride (SiCN). In this example embodiment, the initial insulating layer 103a' can be formed of silicon oxide.

[0130] refer to Figure 13 For reference Figure 9 In the same manner described, a growth-preventing film GBF2 can be formed on the surface of the upper region of the initial insulating layer 103a', and a replacement structure SS2 can be grown on the surface of the lower region of the initial insulating layer 103a'.

[0131] As described above, the growth-preventing film GBF2 can be formed on the surface of the upper region of the initial insulating layer 103a' by chemical vapor deposition (CVD), and the replacement structure SS2 can be grown on the surface of the lower region of the initial insulating layer 103a' to the level of forming the growth-preventing film GBF2.

[0132] refer to Figure 14 For reference Figure 10 The same method described can be used to remove the top of the initial insulating layer 103a' and the growth prevention film GBF2 (see [link to original text]). Figure 13 ).

[0133] Let's refer to each other. Figure 13 and Figure 14 The upper part of the initial insulating layer 103a' and the growth prevention film GBF2 can be removed during the etching process. Therefore, an initial first separation structure 103p, including the initial insulating layer 103a' and the replacement structure SS2, can be formed in the lower region of the cell gate trench CGT. Simultaneously, through the etching process, the initial first separation structure 103p can have a downwardly convex upper surface (see...). Figure 4A ).

[0134] refer to Figure 15An initial cell gate dielectric layer 162' can be formed on the sidewalls and lower surface of each of the cell gate trench CGT and the peripheral region trench PRT, and a conductive material can be deposited on the surface of the initial cell gate dielectric layer 162' to form an initial cell gate electrode layer 165'. Meanwhile, the conductive material deposited in the peripheral region PR can be referred to as a dummy gate electrode layer 165d'.

[0135] Then, an etching process (e.g., an anisotropic etching process) can be performed such that the initial cell gate electrode layers 165' can be spaced apart from each other on the lowest surface of the initial cell gate dielectric layer 162' in the first horizontal direction (X direction), so that the portion of the initial cell gate electrode layers 165' on the lowest surface of the initial cell gate dielectric layer 162' can be removed.

[0136] refer to Figure 16 It can form a resist film PRF covering a portion of the peripheral region trench PRT and the cell gate trench CGT, and can remove the portion of the initial cell gate dielectric layer 162' in the peripheral region PR that is not covered by the resist film PRF and the dummy gate electrode layer 165d'.

[0137] Since this portion of the initial cell gate dielectric layer 162' is removed, a groove H can be formed in the upper region of the replacement structure SS2 in the peripheral region trench PRT. Simultaneously, the resist film PRF can be a photoresist layer comprising a photoresist material. The resist film (PRF) can then be removed during an ashing process.

[0138] refer to Figure 17 An initial gate cap 167' can be formed by filling the cell gate trench CGT with insulating material.

[0139] The initial gate capping layer 167' can be formed by filling the cell gate trench CGT with an insulating material such as silicon oxide, silicon nitride, silicon oxide nitride (SiON), or silicon carbon nitride (SiCN). In an example embodiment, the initial gate capping layer 167' can be formed of silicon nitride. Meanwhile, the insulating material layer filling the peripheral region trench PRT can be referred to as the initial insulating pattern 157'.

[0140] refer to Figure 18 Mask M3 can be removed by performing a planarization process (see...) Figure 17 ).

[0141] In the planarization process, the mask M3 in the memory region CR and the peripheral region PR can be removed. Therefore, the back gate structure 130 and the vertical active pattern 140 can be defined in the memory region CR.

[0142] Then, it can be removed by performing an etch-back process. Figure 17 It is a part of the initial unit gate electrode layer 165'. Therefore, the gate electrode 165 can be defined in the storage region CR, and the conductive pattern 155 can be defined in the peripheral region PR.

[0143] In the etch-back process, it is possible to remove Figure 17 A portion of the upper region of the initial gate cap layer 167' and the initial insulating pattern 157' is positioned such that, relative to the upper surface of the lower semiconductor layer 11 serving as a reference layer, its upper surface is at a level lower than the level of the upper surface of the back gate cap layer 137. Therefore, multiple openings OP can be formed in the memory region CR and the peripheral region PR. Through the multiple openings OP, the first gate cap layer 167 can be defined in the memory region CR, and the insulating pattern 157 can be defined in the peripheral region PR.

[0144] Meanwhile, in the etch-back process, the gate electrode 165 can have a downwardly convex upper surface (see...). Figure 4A ).

[0145] refer to Figure 19 A second gate capping layer 169 can be formed in the storage region CR, and an insulating pattern 159 can be formed in the peripheral region PR.

[0146] Let's refer to each other. Figure 18 and Figure 19 Multiple openings (OPs) can be filled with insulating material and a planarization process can be performed, thus forming a second gate cap layer 169 in the storage region CR and an insulating pattern 159 in the peripheral region PR. Therefore, a cell gate structure 160 can be defined in the storage region CR. Furthermore, an upper insulating pattern 150U including multiple insulating patterns 152, 157, and 159 and a conductive pattern 155 can be defined in the peripheral region PR.

[0147] The second gate cap layer 169 and the insulating pattern 159 can be formed by filling multiple openings OP with an insulating material such as silicon oxide, silicon nitride, silicon oxide nitride (SiON), or silicon carbon nitride (SiCN). In an example embodiment, the second gate cap layer 169 and the insulating pattern 159 may be formed of silicon nitride.

[0148] refer to Figure 20 The substitution structures SS1 and SS2 of the initial first separation structure 103p and the initial second separation structure 105p can be removed (see...) Figure 19 ).

[0149] Let's refer to each other. Figure 19 and Figure 20 , Figure 19The initial semiconductor structure can be flipped up and down so that the lower surface of the lower semiconductor layer 11 can face upwards.

[0150] Then, portions of the lower semiconductor layer 11 and the initial insulating layers 103a' and 105a' can be removed by performing a planarization process, thereby exposing the surfaces of the replacement structures SS1 and SS2. Thus, the initial pad pattern 150La' can be defined in the peripheral region PR.

[0151] Then, the replacement structures SS1 and SS2 exposed by the planarization process can be selectively removed. Therefore, multiple openings OR can be defined on the cell gate structure 160 and back gate structure 130 of the memory region CR and on the upper insulating pattern 150U of the peripheral region PR.

[0152] refer to Figure 21 Multiple openings can be filled with insulating material OR (see Figure 20 This forms the first initial capping layer 103b', the second initial capping layer 105b', and the initial capping pattern 150Lb'.

[0153] Let's refer to each other. Figure 20 and Figure 21 Multiple openings OR can be filled with insulating material to form a first initial capping layer 103b', a second initial capping layer 105b', and an initial capping pattern 150Lb'.

[0154] Therefore, an initial first separation structure 103p' including an initial insulating layer 103a' and a first initial capping layer 103b' and an initial second separation structure 105p' including an initial insulating layer 105a' and a second initial capping layer 105b' can be defined in the storage region CR. Furthermore, an initial lower insulating pattern 150L' including an initial pad pattern 150La' and an initial capping pattern 150Lb' can be defined in the peripheral region PR.

[0155] The first initial capping layer 103b', the second initial capping layer 105b', and the initial capping pattern 150Lb' can be formed by filling multiple openings OR with an insulating material such as silicon oxide, silicon nitride, silicon oxide nitride (SiON), or silicon carbon nitride (SiCN). In an example embodiment, the first initial capping layer 103b', the second initial capping layer 105b', and the initial capping pattern 150Lb' can be formed of silicon nitride.

[0156] refer to Figure 22 It can form a source / drain pattern 170, a contact plug 175, an insulating structure 177, an information storage structure 180, and an insulating layer 190 on the unit.

[0157] Let's refer to each other. Figure 21 and Figure 22 , Figure 21 The initial semiconductor structure can be flipped upside down so that the lower surface of the vertical active pattern 140 and the lower surfaces of the gate cap layers 137 and 169 can face upwards.

[0158] Subsequently, a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an insulating layer (not shown) on the second semiconductor layer can be sequentially formed covering the upper surface of the vertical active pattern 140 and the upper surfaces of the gate cap layers 137 and 169.

[0159] Then, a separation pattern 107 defining the side surfaces of the first semiconductor layer, the second semiconductor layer, and the insulating layer can be formed. Thus, the first semiconductor layer can be defined as a source / drain pattern 170a on the first cell, and the second semiconductor layer can be defined as a source / drain pattern 170b on the second cell.

[0160] Subsequently, an insulating structure 177 can be formed. The insulating structure 177 can penetrate the first semiconductor layer and the second semiconductor layer (i.e., extend within the first semiconductor layer and the second semiconductor layer). The insulating structure 177 may include an insulating pattern 177b and an insulating pad 177a covering the side and bottom surfaces of the insulating pattern 177b. The insulating pattern 177b may include an oxide, and the insulating pad 177a may include a nitride.

[0161] Subsequently, the insulating layer can be removed to expose the upper surface of the source / drain pattern 170b on the second cell and the side surface of the upper region of the insulating pad 177a, and the metal semiconductor compound layer 175a on the source / drain pattern 170b on the second cell and the plug pattern 175b on the metal semiconductor compound layer 175a can be formed sequentially.

[0162] Subsequently, an information storage structure 180 can be formed. The information storage structure 180 may include a first electrode 181 connected to the plug pattern 175b and extending in the vertical direction (Z direction), a second electrode 183 on the side surface and top surface of each first electrode 181, and a dielectric layer 182 between the first electrode 181 and the second electrode 183.

[0163] Then, an insulating layer 190 can be formed that covers the information storage structure 180 in the storage area CR and the insulating structure 177 in the peripheral area PR.

[0164] refer to Figure 23 This can remove the insulating layer 12 of the semiconductor substrate 10.

[0165] Let's refer to each other. Figure 22 and Figure 23 , Figure 22The initial semiconductor structure can be flipped upside down so that the lower surface of the insulating layer 12 can face upwards.

[0166] The insulating layer 12 can be removed by performing a planarization process. Therefore, a first separation structure 103 on the cell gate structure 160 and a second separation structure 105 on the back gate structure 130 can be defined in the storage region CR. Furthermore, a lower insulating pattern 150L can be defined in the peripheral region PR, thus defining an insulating structure 150 comprising an upper insulating pattern 150U and a lower insulating pattern 150L, ​​respectively.

[0167] Although not explicitly shown, reference Figure 2 The source / drain pattern 110, the first conductive layer 120a and the second conductive layer 120b of the cell can be sequentially formed on the first separation structure 103 and the second separation structure 105 in the storage region CR and the insulating structure 150 in the peripheral region PR.

[0168] Then, an insulating layer 101 and an insulating pattern 102 can be formed. The insulating layer 101 can cover the lower and side surfaces of the bit line 120, and can cover the side and upper surfaces of the insulating pattern 102. The insulating layer 101 may include a nitride, and the insulating pattern 102 may include an oxide. Then, an insulating layer 195 can be formed on the insulating layer 101 and the insulating pattern 102, thereby forming a semiconductor device 100.

[0169] Figures 24 to 30 This is a vertical cross-sectional view showing an intermediate process in a method for manufacturing a semiconductor device 100b according to an example embodiment. Figure 24 It can be a successor Figure 8 The subsequent process diagrams.

[0170] refer to Figure 24 The upper surface of the lower semiconductor layer 11 can be exposed through the back gate trench (BGT).

[0171] The initial insulating layer 105a' on the lower surface of the back gate trench (BGT) can be removed using an etching process, thereby exposing the upper surface of the lower semiconductor layer 11. Therefore, the initial insulating layer 105a' on the mask M2 can also be removed.

[0172] refer to Figure 25 A first semiconductor pattern EGS1 can be formed from the upper surface of the lower semiconductor layer 11.

[0173] The first semiconductor pattern EGS1 can be derived from, according to... Figure 24 The epitaxial silicon grown on the upper surface of the lower semiconductor layer 11 is exposed by the etching process.

[0174] refer to Figure 26This can form the first oxide pattern EGO1.

[0175] The first semiconductor pattern EGS1 can be reduced to the desired height using an etch-back process.

[0176] The first oxide pattern EGO1 can be formed by oxidizing the first semiconductor pattern EGS1. The first oxide pattern EGO1 can be formed from silicon oxide.

[0177] Subsequently, similar to reference Figure 10 The described content allows for the removal of the upper portion of the initial insulating layer 105a', thereby enabling the formation of an initial second separation structure 105p comprising the initial insulating layer 105a' and the first oxide pattern EGO1 in the lower region of the back gate trench BGT.

[0178] refer to Figure 27 Similar to a reference Figure 11 The described content can form an initial back gate structure 130' in the back gate trench (BGT).

[0179] An initial back gate insulating layer 132' can be formed on the sidewalls and lower surface of the back gate trench BGT. Next, the back gate trench BGT can be filled with a conductive material, and then an etch-back process can be performed to form the back gate electrode 135. Next, the back gate trench BGT can be filled with an insulating material to cover the upper surface of the back gate electrode 135, thereby forming an initial back gate capping layer 137'. Then, a planarization process can be performed to give the initial back gate structure 130' and the mask M1 a flat upper surface.

[0180] refer to Figure 28 Similar to a reference Figure 12 The described content can form the cell gate trench CGT in the memory region CR and the peripheral region trench PRT in the peripheral region PR.

[0181] The mask M1 on the semiconductor substrate 10 can be removed, and the mask M3 used in the etching process for forming the cell gate trench CGT and the peripheral region trench PRT can be formed on the semiconductor substrate 10.

[0182] Then, the cell gate trench CGT between the initial back gate structure 130' in the memory region CR and the peripheral region trench PRT in the peripheral region PR can be formed using the mask M3.

[0183] Then, an initial insulating layer 103a' can be formed in the cell gate trench CGT and the peripheral region trench PRT. The initial insulating layer 103a' can be formed to substantially conformally cover the upper surface of the initial back gate structure 130', the upper and side surfaces of the mask M3, the side surface of the upper semiconductor layer 13, the side surface of the insulating layer 12, and the upper surface of the lower semiconductor layer 11.

[0184] refer to Figure 29 The upper surface of the lower semiconductor layer 11 can be exposed, and a second semiconductor pattern EGS2 can be formed from the upper surface of the lower semiconductor layer 11.

[0185] Similar to a reference Figure 24 The described process allows for the removal of the initial insulating layer 103a' on the lower surface of the cell gate trench CGT and the lower surface of the peripheral region trench PRT using an etching process, thereby exposing the upper surface of the lower semiconductor layer 11. Therefore, the initial insulating layer 103a' on the mask M3 can also be removed.

[0186] Similar to a reference Figure 25 The described content allows for the formation of a second semiconductor pattern EGS2 from the upper surface of the lower semiconductor layer 11. The second semiconductor pattern EGS2 can be formed from epitaxial silicon.

[0187] refer to Figure 30 This can form a second oxide pattern, EGO2.

[0188] Similar to a reference Figure 26 As described, the second semiconductor pattern EGS2 can be reduced to the desired height through an etch-back process.

[0189] The second oxide pattern EGO2 can be formed by oxidizing the second semiconductor pattern EGS2. The second oxide pattern EGO2 can be formed from silicon oxide.

[0190] Next, similar to a reference Figure 14 The described content allows for the removal of the initial insulating layer 103a' in the upper region of the cell gate trench CGT and the peripheral region trench PRT, thereby forming an initial first separation structure 103p including the second oxide pattern EGO2 and the initial insulating layer 103a', and an initial second separation structure 105p including the first oxide pattern EGO1 and the initial insulating layer 105a'.

[0191] Then, through reference Figures 15 to 19 The described process sequence can form gate structures 130 and 160 and upper insulating pattern 150U.

[0192] Subsequently, with reference Figure 20 and Figure 21The described process differs; in this example embodiment, the first oxide pattern EGO1 and the second oxide pattern EGO2 may not need to be removed. In other words, the process has already undergone the reference... Figure 19 The initial semiconductor structure of the described process can be flipped upside down so that the lower surface of the lower semiconductor layer 11 can face upwards, and the surfaces of the first oxide pattern EGO1 and the second oxide pattern EGO2 can be exposed using a planarization process.

[0193] Next, you can refer to Figure 22 The described process and subsequent processes form semiconductor device 100b.

[0194] Figures 31 to 36 This is a vertical cross-sectional view showing an intermediate process in a method of manufacturing a semiconductor device 100c according to an exemplary embodiment of the present disclosure. Figure 31 It can be a successor Figure 25 The process diagram following the process shown.

[0195] refer to Figure 31 A first semiconductor pattern EGS1 can be formed from the upper surface of the lower semiconductor layer 11.

[0196] Similar to a reference Figure 25 The described content indicates that the first semiconductor pattern EGS1 can be derived from a reference. Figure 24 The described etching process exposes the epitaxial silicon grown on the upper surface of the lower semiconductor layer 11.

[0197] Next, the first semiconductor pattern EGS1 can be reduced to the desired height using an etch-back process. Therefore, the initial second discrete structure 105p in the back gate trench BGT can be defined.

[0198] refer to Figure 32 Similar to a reference Figure 27 The described content can form an initial back gate structure 130' in the back gate trench (BGT).

[0199] refer to Figure 33 Similar to a reference Figure 28 The described content allows for the formation of a cell gate trench CGT in the memory region CR and a peripheral region trench PRT in the peripheral region PR. An initial insulating layer 103a' can then be formed in the cell gate trench CGT and the peripheral region trench PRT.

[0200] refer to Figure 34 Similar to a reference Figure 29The described method allows for the removal of the initial insulating layer 103a' on the lower surface of the cell gate trench CGT to expose the upper surface of the lower semiconductor layer 11, and the formation of a second semiconductor pattern EGS2 from the upper surface of the lower semiconductor layer 11. Therefore, an initial first separation structure 103p can be defined in the cell gate trench CGT.

[0201] refer to Figure 35 Similar to a reference Figures 14 to 19 The described contents can form gate structures 130 and 160 and an upper insulating pattern 150U.

[0202] refer to Figure 36 Similar to a reference Figure 20 The described content can remove the first semiconductor pattern EGS1 and the second semiconductor pattern EGS2 from the initial first separation structure 103p and the initial second separation structure 105p, respectively.

[0203] Let's refer to each other. Figure 35 and Figure 36 , Figure 35 The initial semiconductor structure can be flipped upside down so that the lower surface of the lower semiconductor layer 11 can face upwards.

[0204] Then, portions of the lower semiconductor layer 11 and the initial insulating layers 103a' and 105a' can be removed by performing a planarization process, thereby exposing the surfaces of the first semiconductor pattern EGS1 and the second semiconductor pattern EGS2. Therefore, the initial pad pattern 150La' can be defined in the peripheral region PR.

[0205] Then, the first semiconductor pattern EGS1 and the second semiconductor pattern EGS2 exposed by the planarization process can be removed. The first semiconductor pattern EGS1 and the second semiconductor pattern EGS2 can be selectively removed by using an etching process with different etching selectivity for the insulating layers 103a', 105a', and 12 (see [link to etching process]). Figure 35 The etching process can be, for example, a wet etching process. Therefore, the initial insulating layers 103a' and 105a' can have a shape in which the width increases as the initial insulating layers 103a' and 105a' approach the gate structures 130 and 160 (see also...). Figure 7A and Figure 7B ).

[0206] Then, you can refer to Figures 21 to 23 The described process and subsequent processes form semiconductor devices 100c or 100d.

[0207] This disclosure is not limited to the embodiments and drawings described above, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, or alterations without departing from the scope of this disclosure as defined by the appended claims, and such substitutions, modifications, or alterations should be construed as being included within the scope of this disclosure.

[0208] This application claims priority to Korean Patent Application No. 10-2024-0066329, filed on May 22, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Bitline structure; The first active pattern and the second active pattern are spaced apart from each other on the bit line structure and in a first direction parallel to the upper surface of the bit line structure. A cell gate structure is located between the first active pattern and the second active pattern; as well as A first separation structure is located between the bit line structure and the cell gate structure. The unit gate structure includes: The first gate electrode is adjacent to the first active pattern; The second gate electrode is adjacent to the second active pattern; An insulating layer is located between the first gate electrode and the second gate electrode; and A gate dielectric layer is disposed on at least a portion of the insulating layer and on the first gate electrode and the second gate electrode; The gate dielectric layer includes: A first vertical portion and a second vertical portion, the first vertical portion being between the first active pattern and the first gate electrode, and the second vertical portion being between the second active pattern and the second gate electrode; and A first intermediate portion, connected to the first vertical portion and the second vertical portion, and between the first gate electrode and the second gate electrode and the first separated structure, and The first separation structure includes: A first pad is spaced apart from each other in the first direction between the first intermediate portion of the gate dielectric layer and the bit line structure; and The first cover layer is located between the first liner layers.

2. The semiconductor device of claim 1, wherein each of the first active pattern and the second active pattern comprises: The first source / drain region is electrically connected to the bit line structure; The second source / drain region is at a higher level than the first source / drain region relative to the upper surface of the bit line structure. as well as The vertical channel region is located between the first source / drain region and the second source / drain region.

3. The semiconductor device of claim 2, wherein at least a portion of the vertical channel region faces the first gate electrode and the second gate electrode.

4. The semiconductor device of claim 1, wherein the gate dielectric layer and the first pad of the first discrete structure comprise an oxide, and The first capping layer of the first separation structure comprises a nitride.

5. The semiconductor device of claim 1, wherein the thickness of the gate dielectric layer in a second direction perpendicular to the upper surface of the bit line structure is different from the thickness of each of the first pads in the first separation structure in the first direction.

6. The semiconductor device of claim 1, wherein the upper surface of the first discrete structure protrudes toward the upper surface of the bit line structure, and The first middle portion of the gate dielectric layer protrudes toward the upper surface of the bit line structure.

7. The semiconductor device of claim 6, wherein the lower regions of the first gate electrode and the second gate electrode and the lower region of the insulating layer have a shape that protrudes toward the upper surface of the bit line structure.

8. The semiconductor device of claim 1, wherein the upper surfaces of the first gate electrode and the second gate electrode protrude toward the first discrete structure.

9. The semiconductor device of claim 1, wherein the gate dielectric layer, the first pad, and the first capping layer comprise oxides.

10. The semiconductor device of claim 1, wherein the width of each of the first pads in the first separation structure decreases in the first direction as the distance from the first intermediate portion of the gate dielectric layer increases in a second direction perpendicular to the upper surface of the bit line structure.

11. The semiconductor device of claim 10, wherein the lower surface of each of the first pads is in contact with the upper surface of the bit line structure.

12. The semiconductor device of claim 1, wherein the vertical distance from the upper surface of the bit line structure to the lower surfaces of the first gate electrode and the second gate electrode is in the range of 10 nm to 100 nm.

13. The semiconductor device according to claim 1, wherein, The vertical height of the first separation structure is in the range of 10 nm to 90 nm relative to the upper surface of the bit line structure used as a reference.

14. The semiconductor device according to claim 1, further comprising: A third active pattern is spaced apart from the second active pattern on the bit line structure and in the first direction; A back gate structure is located between the second active pattern and the third active pattern; as well as The second separation structure is located between the bit line structure and the back gate structure. The back gate structure includes: Back gate electrode; and A back gate dielectric layer, on at least a portion of the back gate electrode. The back gate dielectric layer includes: A third vertical portion and a fourth vertical portion, the third vertical portion being between the second active pattern and the back gate electrode, and the fourth vertical portion being between the third active pattern and the back gate electrode; and The second intermediate portion connects to the third vertical portion and the fourth vertical portion and lies between the back gate electrode and the second separation structure. The second separation structure includes: A second pad is spaced apart from each other in the first direction between the second intermediate portion of the back gate dielectric layer and the bit line structure; and The second cover layer is located between the second liner.

15. The semiconductor device of claim 14, wherein the thickness of the back gate dielectric layer in a second direction perpendicular to the upper surface of the bit line structure is different from the thickness of each of the second pads in the second separation structure in the first direction.

16. A semiconductor device, comprising: The first vertical active pattern and the second vertical active pattern are spaced apart from each other; A gate structure is located between the first vertical active pattern and the second vertical active pattern; as well as Insulating structure on the gate structure, The gate structure includes: At least one gate electrode; Insulating layer on the at least one gate electrode; and A gate dielectric layer, on at least a portion of the insulating layer and on the at least one gate electrode. The gate dielectric layer includes: The first portion is located between the first vertical active pattern and the at least one gate electrode; The second portion is located between the second vertical active pattern and the at least one gate electrode; and The third part is connected to the first part and the second part and is located between the at least one gate electrode and the insulating structure. The insulating structure includes: The pads are spaced apart from each other on the third portion of the gate dielectric layer; and Cover layer, between the pads.

17. The semiconductor device of claim 16, wherein the at least one gate electrode of the gate structure comprises a plurality of unit gate electrodes. The plurality of unit gate electrodes include: The first unit gate electrode is adjacent to the first vertical active pattern; as well as The second unit gate electrode is adjacent to the second vertical active pattern, and The insulating layer of the gate structure is located between the first unit gate electrode and the second unit gate electrode. The first portion of the gate dielectric layer is located between the first vertical active pattern and the first unit gate electrode. The second portion is located between the second vertical active pattern and the second cell gate electrode, and At least a portion of the third part is in contact with the lower surfaces of the first unit gate electrode and the second unit gate electrode, as well as the lower surface of the insulating layer.

18. The semiconductor device of claim 16, wherein the insulating layer of the gate structure is on the upper portion of the at least one gate electrode, and At least a portion of the third portion of the gate dielectric layer is in contact with the lower surface of the at least one gate electrode.

19. A semiconductor device, comprising: Storage area and peripheral area The storage area includes: The first vertical active pattern and the second vertical active pattern are spaced apart from each other; A cell gate structure is located between the first vertical active pattern and the second vertical active pattern; and A separate structure is provided on the unit gate structure. The unit gate structure includes: The first gate electrode is adjacent to the first vertical active pattern; The second gate electrode is adjacent to the second vertical active pattern; An insulating layer is located between the first gate electrode and the second gate electrode; and A gate dielectric layer, on at least a portion of the insulating layer and on the first gate electrode and the second gate electrode. The separation structure includes: Pads are spaced apart from each other on the lower surface of the gate dielectric layer; and Cover layer, between the pads, The peripheral region includes an insulating structure comprising a lower portion and an upper portion above the lower portion. The lower portion of the insulating structure includes: The padding patterns are spaced apart from each other on the lower surface of the upper part; and Cover pattern, between the pad pattern.

20. The semiconductor device of claim 19, wherein the upper surface of the lower portion of the insulating structure and the upper surface of the separating structure are substantially coplanar.

Images