Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors.The semiconductor structure comprises a substrate and an epitaxial structure on one side of the substrate, the epitaxial structure has a grid-shaped groove, and the epitaxial structure comprises a drift region, a first shielding doped region and a plurality of second shielding doped regions; when the semiconductor structure is reversely cut off, PN junctions are formed between the first shielding doped region and the drift region and between the second shielding doped regions and the drift region, so that the electric field is adjusted and dispersed, and the electric field is prevented from being concentrated near the gate structure; since the first shielding doped region and the second shielding doped region are arranged, the breakdown problem of the bottom and the sidewall of the gate structure is avoided, and the reliability of the semiconductor structure is improved; and since the first shielding doped region is connected with the second shielding doped region, the first shielding doped region and the second shielding doped region can be grounded together, and the preparation process is saved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a semiconductor device that controls current through an electric field effect. Compared to planar silicon carbide MOSFETs, trench MOSFETs have smaller feature sizes, and their on-resistance can be further reduced because the channel of the trench device is located on the <11-20> crystal plane with higher mobility.

[0003] To further increase channel density, the trenches of trench MOSFET devices can be configured as a mesh-like trench structure, resulting in better on-resistance. However, existing mesh-like trench MOSFET devices are prone to gate breakdown, compromising the reliability of the MOSFET device. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of low reliability of MOSFET devices.

[0005] To achieve the above objectives, in one aspect, the present invention provides a semiconductor structure comprising:

[0006] Substrate;

[0007] An epitaxial structure is located on one side of the substrate. The epitaxial structure has a grid-like trench and includes a drift region, a first shielding doped region, and multiple second shielding doped regions. The drift region is located on the side of the first shielding doped region, the second shielding doped regions, and the grid-like trenches closest to the substrate. The drift region has a first conductivity type, and the first and second shielding doped regions have a second conductivity type, which are different from each other. The grid-like trenches include multiple first directional trenches and multiple second directional trenches arranged in a cross pattern. The first shielding doped region is located on the side of the grid-like trenches closest to the substrate, and the orthographic projection of the grid-like trenches onto the substrate lies within the orthographic projection of the first shielding doped region onto the substrate. Multiple second shielding doped regions surround a first intersection area of ​​the first and second directional trenches, forming the sidewall of the first intersection area of ​​the grid-like trenches. In a direction perpendicular to the substrate, the doping depth of the second shielding doped regions is greater than or equal to the trench depth of the grid-like trenches. The first and second shielding doped regions are connected.

[0008] The gate structure is located within the mesh-like trench.

[0009] In one embodiment, the doping concentration of the first shielding doped region is less than the doping concentration of the second shielding doped region.

[0010] In one embodiment, the bottom surface of the mesh-like groove is connected to the sidewall of the mesh-like groove via a first arcuate surface;

[0011] The top of the sidewall of the mesh trench is connected to the side of the epitaxial structure away from the substrate via a second arcuate surface.

[0012] In one embodiment, the epitaxial structure further includes;

[0013] The source region is located on the side of the drift region away from the substrate and within the area enclosed by the mesh trench;

[0014] In a direction perpendicular to the substrate, the doping depth of the source region is less than the doping depth of the second shielding doping region.

[0015] On the other hand, this application also provides a method for fabricating a semiconductor structure, comprising:

[0016] Provide substrate;

[0017] An epitaxial structure is formed on one side of the substrate. The epitaxial structure has a grid-like trench and includes a drift region, a first shielding doped region, and a plurality of second shielding doped regions. The drift region is located on the side of the first shielding doped region, the second shielding doped region, and the grid-like trench closer to the substrate. The drift region has a first conductivity type, and the first and second shielding doped regions have a second conductivity type, which are different from each other. The grid-like trench includes a plurality of first directional trenches and a plurality of second directional trenches arranged in a cross pattern. The first shielding doped region is located on the side of the grid-like trench closer to the substrate, and the orthographic projection of the grid-like trench on the substrate is within the orthographic projection of the first shielding doped region on the substrate. The plurality of second shielding doped regions surround a first intersection area of ​​the first directional trenches and the second directional trenches, and form the sidewall of the first intersection area of ​​the grid-like trench. In a direction perpendicular to the substrate, the doping depth of the second shielding doped region is greater than or equal to the doping depth of the grid-like trench. The first shielding doped region is connected to the second shielding doped region.

[0018] A gate structure is formed within the mesh-like trench.

[0019] In one embodiment, forming an epitaxial structure on one side of the substrate includes:

[0020] An epitaxial initial layer is formed on one side of the substrate;

[0021] Multiple source initial regions are formed in an array within the epitaxial initial layer. The region between the multiple source initial regions includes multiple first-direction extension regions and multiple second-direction extension regions arranged in a cross pattern. There is a second cross region between the first-direction extension regions and the second-direction extension regions.

[0022] A shielding doped initial region is formed, the orthographic projection of the shielding doped initial region on the substrate covers the orthographic projection of the second cross region on the substrate, and covers the orthographic projection of a portion of the source initial region surrounding the second cross region on the substrate, the remaining source initial region forming the source region;

[0023] The epitaxial structure is etched to form the first-direction extension regions and the second-direction extension regions located between the multiple source regions to form the mesh-like trenches, and the remaining shielding doped regions form the second shielding doped regions;

[0024] The first shielding doped region is formed on the side of the mesh-like trench near the substrate.

[0025] In one embodiment, the etching of the epitaxial structure of a plurality of first-direction extension regions and a plurality of second-direction extension regions located between a plurality of source regions to form the mesh-like trenches, after the remaining shielding doped initial regions form the second shielding doped regions, includes:

[0026] The area between the bottom surface of the mesh-like groove and the sidewall of the mesh-like groove is rounded to form a first arc-shaped surface;

[0027] The area between the top of the sidewall of the mesh trench and the surface of the epitaxial structure on the side away from the substrate is rounded to form a second arcuate surface.

[0028] In one embodiment, etching the epitaxial structure of a plurality of first-direction extension regions and a plurality of second-direction extension regions located between a plurality of source regions to form the mesh-like trench includes:

[0029] A first mask is used to form a patterned first mask layer on the side of the epitaxial structure away from the substrate;

[0030] Based on the patterned first mask layer, a plurality of first-direction extension regions and a plurality of second-direction extension regions of the epitaxial structure located between a plurality of source regions are etched;

[0031] Remove the first patterned mask layer;

[0032] The formation of the first shielding doped region on the side of the mesh-like trench near the substrate includes:

[0033] Using the first mask, a patterned second mask layer is formed on the side of the epitaxial structure away from the substrate;

[0034] Based on the patterned second mask layer, ion implantation is performed on the side of the mesh trench near the substrate to form a first shielding doped region.

[0035] In one embodiment, after forming the gate structure within the mesh-like trench, the process includes:

[0036] A dielectric layer is formed on the side of the gate structure away from the substrate, the dielectric layer exposing at least a portion of the source region and a portion of the second shielding doped region;

[0037] Metal silicides are formed on the exposed source region and the second shielding doped region;

[0038] A first electrode is formed on the side of the dielectric layer and the metal silicide away from the substrate;

[0039] A second electrode is formed on the side of the substrate away from the epitaxial structure.

[0040] In one embodiment, after forming the first electrode on the side of the dielectric layer and the metal silicide away from the substrate, the process includes:

[0041] A passivation layer is formed on the side of the first electrode away from the epitaxial structure.

[0042] Compared with existing technologies, the above technical solution has the following advantages:

[0043] The semiconductor structure includes a substrate and an epitaxial structure located on one side of the substrate. The epitaxial structure has a grid-like trench and includes a drift region, a first shielding doped region, and multiple second shielding doped regions. The drift region is located on the side of the first shielding doped region, the second shielding doped region, and the grid-like trench closer to the substrate. The drift region has a first conductivity type, while the first and second shielding doped regions have a second conductivity type. The first and second conductivity types are different. When the semiconductor structure is reverse-biased, PN junctions are formed between the first shielding doped region and the drift region, and between the second shielding doped region and the drift region, thereby regulating and dispersing the electric field and preventing the electric field from concentrating near the gate structure. The presence of the first and second shielding doped regions avoids breakdown problems at the bottom and sidewalls of the gate structure, improving the reliability of the semiconductor structure.

[0044] Furthermore, the mesh-like trench includes multiple first-directional trenches and multiple second-directional trenches arranged in a cross pattern. The first shielding doped region is located on the side of the mesh-like trench closer to the substrate. The orthographic projection of the mesh-like trench on the substrate is within the orthographic projection of the first shielding doped region on the substrate. At the same time, multiple second shielding doped regions surround the first intersection area of ​​the first and second-directional trenches, forming the sidewall of the first intersection area of ​​the mesh-like trench. In the direction perpendicular to the substrate, the doping depth of the second shielding doped region is greater than or equal to the doping depth of the mesh-like trench, so that the first and second shielding doped regions are connected. At this time, the first and second shielding doped regions can be grounded together, saving fabrication steps. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a top view of an existing mesh-like trench device.

[0047] Figure 2 A top view of a semiconductor structure provided in an embodiment of this application;

[0048] Figure 3 A top view of an epitaxial layer provided in an embodiment of this application;

[0049] Figures 4-12 for Figure 2 A schematic diagram of a partial cross-sectional structure along the AA' or CC' cutting line;

[0050] Figure 13 for Figure 2 A schematic diagram of a partial cross-sectional structure along the BB' cutting line;

[0051] Figure 14 This is a schematic diagram of a semiconductor structure fabrication method provided in an embodiment of this application.

[0052] Explanation of reference numerals in the attached figures: 01-First shielding injection region; 02-Source region; 03-Grid trench; 11-Substrate; 12-Epipolar structure; 121-Drift region; 13-Grid trench; 131-First directional trench; 132-Second directional trench; 133-First cross region; 14-First shielding doped region; 15-Second shielding doped region; 151-Initial shielding doped region; 16-Gate structure; 161-Gate oxide layer; 162-Polysilicon; 17-Source region; 170-Initial source region; 171-Trap region; 172-First doped region; 173-First directional extension region; 174-Second directional extension region; 175-Second cross region; 18-Dielectric layer; 19-Metal silicide; 20-First electrode; 21-Second electrode; 22-Passivation layer; 221-First passivation layer; 222-Second passivation layer. Detailed Implementation

[0053] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0055] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0057] Based on the content in the background art, refer to Figure 1 , Figure 1 This is a top view of an existing mesh trench device; wherein, the first shielding injection region 01 is located at the center of the source region 02 and is distributed in a separate block shape. When the semiconductor structure is reverse cut off, it cannot effectively protect the bottom of the mesh trench 03. The reverse voltage is as high as several hundred volts or more, which can easily cause the gate structure located in the mesh trench 03 to break down.

[0058] Based on this, this application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate and an epitaxial structure located on one side of the substrate. The epitaxial structure has a grid-like trench and includes a drift region, a first shielding doped region, and multiple second shielding doped regions. The drift region is located on the side of the first shielding doped region, the second shielding doped region, and the grid-like trench closer to the substrate. The drift region has a first conductivity type, and the first and second shielding doped regions have a second conductivity type. The first and second conductivity types are different. When the semiconductor structure is reverse-biased, a PN junction is formed between the first shielding doped region and the drift region, and between the second shielding doped region and the drift region, thereby adjusting and dispersing the electric field and preventing the electric field from concentrating near the gate structure. The presence of the first and second shielding doped regions avoids the problem of breakdown at the bottom and sidewalls of the gate structure, improving the reliability of the semiconductor structure.

[0059] Furthermore, the mesh-like trench includes multiple first-directional trenches and multiple second-directional trenches arranged in a cross pattern. The first shielding doped region is located on the side of the mesh-like trench closer to the substrate. The orthographic projection of the mesh-like trench on the substrate is within the orthographic projection of the first shielding doped region on the substrate. At the same time, multiple second shielding doped regions surround the first intersection area of ​​the first and second-directional trenches, forming the sidewall of the first intersection area of ​​the mesh-like trench. In the direction perpendicular to the substrate, the doping depth of the second shielding doped region is greater than or equal to the doping depth of the mesh-like trench, so that the first and second shielding doped regions are connected. At this time, the first and second shielding doped regions can be grounded together, saving fabrication steps.

[0060] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] refer to Figure 2 , Figure 2 This application provides a top view schematic diagram of a semiconductor structure as an embodiment; see reference. Figure 3 , Figure 3 A top view of an epitaxial layer provided in an embodiment of this application; Reference Figures 4-12 , Figures 4-12 for Figure 2 A schematic diagram of a partial cross-sectional structure along the AA' or CC' cutting line; Reference Figure 13 , Figure 13 for Figure 2 A schematic diagram of a partial cross-sectional structure along the BB' cutting line; the semiconductor structure includes:

[0062] Substrate 11;

[0063] The epitaxial structure 12 is located on one side of the substrate 11. The epitaxial structure 12 has a grid-like trench 13 and includes a drift region 121, a first shielding doped region 14, and a plurality of second shielding doped regions 15. The drift region 121 is located on the side of the first shielding doped region 14, the second shielding doped region 15, and the grid-like trench 13 that is close to the substrate 11. The drift region 121 has a first conductivity type, and the first shielding doped region 14 and the second shielding doped region 15 have a second conductivity type. The first conductivity type and the second conductivity type are different.

[0064] The mesh-like trench 13 includes a plurality of first-directional trenches 131 and a plurality of second-directional trenches 132 arranged in a cross pattern. The first shielding doped region 14 is located on the side of the mesh-like trench 13 closest to the substrate 11 (e.g., Figure 8 As shown), the orthographic projection of the mesh trench 13 on the substrate 11 lies within the orthographic projection of the first shielding doped region 14 on the substrate 11; a plurality of second shielding doped regions 15 surround the first intersection region 133 of the first directional trench 131 and the second directional trench 132 (as shown). Figure 2 As shown), and the sidewalls of the first intersection region 133 that forms the mesh trench 13, in the direction perpendicular to the substrate 11, the doping depth of the second shielding doped region 15 is greater than or equal to the doping depth of the mesh trench 13 (as shown). Figure 7 As shown), the first shielding doped region 14 and the second shielding doped region 15 are connected (as shown). Figure 8 (as shown)

[0065] The gate structure 16 is located within the mesh trench 13.

[0066] Specifically, the substrate 11 may include, but is not limited to, a silicon substrate, and the epitaxial structure 12 may be a silicon carbide epitaxial structure.

[0067] The extensional structure 12 includes a grid-like groove 13, which comprises a plurality of first-direction grooves 131 and a plurality of second-direction grooves 132 arranged in a cross pattern. The plurality of first-direction grooves 131 and the plurality of second-direction grooves 132 may have a plurality of first intersection regions 133, for example... Figure 2 There are 4 first intersection areas 133.

[0068] The epitaxial structure 12 includes a drift region 121, a first shielding doped region 14, and multiple second shielding doped regions 15. The first shielding doped region 14 is disposed on the side of the mesh trench 13 near the substrate 11, i.e., at the bottom of the mesh trench 13 (e.g., at the bottom of the substrate 11). Figure 8 As shown), multiple second shielding doped regions 15 surround the first intersection region 133 of the first directional slot 131 and the second directional slot 132 (as shown). Figure 2 As shown), and the sidewalls of the first intersecting region 133 surrounding the grid-like trench 13, that is, a second shielding doped region 15 can be provided at the corner of each partition area within the area surrounded by the grid-like trench 13, forming as shown. Figure 2 The layout structure shown.

[0069] Drift region 121 is located below the mesh trench 13, the first shielded doped region 14, and a plurality of second shielded doped regions 15, i.e., on the side close to the substrate 11. Drift region 121 has a first conductivity type; for example, in some embodiments, drift region 121 is N-type. The first shielded doped region 14 and the second shielded doped region 15 have a second conductivity type; for example, in some embodiments, the first shielded doped region 14 and the second shielded doped region 15 are P-type. The first conductivity type and the second conductivity type are different. When the semiconductor structure is reverse-biased, since a gate structure 16 (e.g., ...) is provided in the mesh trench 13... Figure 9 As shown, the electric field at the bottom of the gate structure 16 is dispersed by the PN junction formed between the first shielded doped region 14 and the drift region 121, thus dispersing the electric field concentrated at the bottom of the mesh trench 13 and preventing breakdown at the bottom of the gate structure 16. The PN junction formed between the second shielded doped region 15 and the drift region 121 disperses the electric field concentrated on the sidewalls of the gate structure 16, preventing breakdown on the sidewalls of the gate structure 16 and improving the reliability of the semiconductor structure.

[0070] In the direction perpendicular to the substrate 11, the doping depth of the second shielding doped region 15 is greater than or equal to the doping depth of the mesh trench 13, and the orthogonal projection of the mesh trench 13 on the substrate 11 is located within the orthogonal projection of the first shielding doped region 14 on the substrate 11. That is to say, the first shielding doped region 14 and the second shielding doped region 15 are connected at this time, so that the first shielding doped region 14 and the second shielding doped region 15 can be grounded together, avoiding the need to design an additional grounding structure for the first shielding doped region 14.

[0071] In this embodiment, the presence of a first shielding doped region 14 and a second shielding doped region 15 prevents breakdown at the bottom and sidewalls of the gate structure 16, thus improving the reliability of the semiconductor structure. Furthermore, since the doping depth of the second shielding doped region 15 is greater than or equal to the doping depth of the mesh trench 13 in the direction perpendicular to the substrate 11, and the first shielding doped region 14 is located on the side of the mesh trench 13 closest to the substrate 11, the first shielding doped region 14 and the second shielding doped region 15 are connected. In this case, the first shielding doped region 14 and the second shielding doped region 15 can be grounded together, saving the process of fabricating an additional ground, reducing the manufacturing difficulty, and saving costs.

[0072] In another embodiment of this application, the doping concentration of the first shielding doped region 14 is less than the doping concentration of the second shielding doped region 15.

[0073] Specifically, the first shielding doped region 14 and the second shielding doped region 15 have the same doping type. For example, when the drift region 121 is N-type, the first shielding doped region 14 and the second shielding doped region 15 can both be P-type doped.

[0074] The doping concentration of the first shielding doped region 14 is less than that of the second shielding doped region 15; that is, the first shielding doped region 14 can be p-doped, and the second shielding doped region 15 can be p+doped. When the semiconductor structure is reverse-biased, the p+ doping of the second shielding doped region 15 can form a PN junction with the N-type epitaxial structure 12, reducing the electric field concentration at the trench corner. The p-doping of the first shielding doped region 14 can form a PN junction with the N-type epitaxial structure 12, reducing the electric field concentration at the bottom of the trench.

[0075] It should be noted that setting the doping concentration of the first shielding doped region 14 to be less than the doping concentration of the second shielding doped region 15 can reduce the on-resistance and further improve the performance of the semiconductor structure.

[0076] In another embodiment of this application, such as Figure 7 As shown, the bottom surface of the mesh-like groove 13 is connected to the side wall of the mesh-like groove 13 through a first arc-shaped surface;

[0077] The top of the sidewall of the mesh trench 13 is connected to the side of the epitaxial structure 12 away from the substrate 11 via a second arcuate surface.

[0078] Specifically, to avoid the tip effect, the bottom surface of the mesh trench 13 can be connected to the sidewall of the mesh trench 13 through a first arc surface, that is, the corner of the bottom of the mesh trench 13 is rounded. Similarly, the top of the sidewall of the mesh trench 13 is connected to the side of the epitaxial structure 12 away from the substrate 11 through a second arc surface, that is, the top of the mesh trench 13 is rounded.

[0079] It should be noted that when the width of the trench is W, the radius of the first arc-shaped surface can be set to R1, and the range of R1 can be 0.3W-0.4W, including the endpoint values. For example, the radius R1 of the first arc-shaped surface can be set to 0.3W, or 0.32W, or 0.37W, etc. The radius of the second arc-shaped surface can be set to R2, and the range of R2 can be 0.6W-0.7W, including the endpoint values. For example, the radius R2 of the second arc-shaped surface can be set to 0.61W, or 0.64W, or 0.7W, etc. There is no specific limitation, and it can be set according to specific needs.

[0080] In another embodiment of this application, the epitaxial structure 12 further includes;

[0081] The source region 17 is located on the side of the drift region 121 away from the substrate 11 and within the area enclosed by the mesh trench 13;

[0082] In the direction perpendicular to the substrate 11, the doping depth of the source region 17 is less than the doping depth of the second shielding doping region 15.

[0083] Specifically, the epitaxial structure 12 also includes a source region 17 located between the mesh trench 13 and the second shielded doped region 15. This source region 17 may include a well region 171 disposed in a direction perpendicular to the substrate 11 and a first doped region 172 located on the side of the well region 171 away from the substrate 11. The source region 17 can serve as either a source or a drain region of the semiconductor structure. The doping concentration of the second shielded doped region 15 can be greater than the doping concentration of the well region 171.

[0084] In the direction perpendicular to the substrate 11, the doping depth of the source region 17 is less than the doping depth of the second shielding doped region 15. When the semiconductor structure is reverse-cut off, the depletion region of the second shielding doped region 15 can penetrate deep into the lower side of the epitaxial structure 12, guiding the depletion region of the entire epitaxial structure 12 to expand uniformly, and avoiding the electric field from being concentrated near the mesh trench 13.

[0085] In another embodiment of this application, reference is made to Figure 14 , Figure 14This application provides a schematic flowchart of a semiconductor structure fabrication method according to an embodiment of the present application; it also provides a semiconductor structure fabrication method, the fabrication steps of which include:

[0086] S10: Provides substrate 11.

[0087] In this step, the substrate 11 provided can be a silicon substrate.

[0088] S20: An epitaxial structure 12 is formed on one side of the substrate 11 (e.g., Figure 8 (As shown).

[0089] The epitaxial structure 12 has a grid-like trench 13 and includes a drift region 121, a first shielding doped region 14, and a plurality of second shielding doped regions 15. The drift region 121 is located on the side of the first shielding doped region 14, the second shielding doped region 15, and the grid-like trench 13 that is close to the substrate 11. The drift region 121 has a first conductivity type, and the first shielding doped region 14 and the second shielding doped region 15 have a second conductivity type. The first conductivity type and the second conductivity type are different.

[0090] The mesh-like trench 13 includes a plurality of first-directional trenches 131 and a plurality of second-directional trenches 132 arranged in a cross pattern. The first shielding doped region 14 is located on the side of the mesh-like trench 13 closest to the substrate 11 (e.g., Figure 8 As shown), the orthographic projection of the mesh trench 13 on the substrate 11 lies within the orthographic projection of the first shielding doped region 14 on the substrate 11; a plurality of second shielding doped regions 15 surround the first intersection region 133 of the first directional trench 131 and the second directional trench 132 (as shown). Figure 2 As shown), and the sidewalls of the first intersection region 133 that forms the mesh trench 13, in the direction perpendicular to the substrate 11, the doping depth of the second shielding doped region 15 is greater than or equal to the doping depth of the mesh trench 13 (as shown). Figure 7 As shown), the first shielding doped region 14 and the second shielding doped region 15 are connected (as shown). Figure 8 (As shown).

[0091] In this step, the epitaxial structure 12 formed on one side of the substrate 11 includes a grid-like trench 13. It should be noted that the grid-like trench 13 is formed by etching. The grid-like trench 13 includes a plurality of first-direction trenches 131 and a plurality of second-direction trenches 132 arranged in a cross pattern. The plurality of first-direction trenches 131 and the plurality of second-direction trenches 132 may have a plurality of first intersection regions 133, for example... Figure 2 There are 4 first intersection areas 133.

[0092] The epitaxial structure 12 includes a drift region 121, a first shielding doped region 14, and multiple second shielding doped regions 15. The first shielding doped region 14 is disposed on the side of the mesh trench 13 near the substrate 11, i.e., at the bottom of the mesh trench 13 (e.g., at the bottom of the substrate 11). Figure 8 As shown), multiple second shielding doped regions 15 surround the first intersection region 133 of the first directional slot 131 and the second directional slot 132 (as shown). Figure 2 As shown), and the sidewalls of the first intersecting region 133 that forms a grid-like trench 13, that is, a second shielding doped region 15 can be provided at the corner of each partition area of ​​the first intersecting region 133, forming a grid-like trench 13. Figure 2 The layout structure shown.

[0093] Drift region 121 is located below the mesh trench 13, the first shielded doped region 14, and a plurality of second shielded doped regions 15, i.e., on the side close to the substrate 11. Drift region 121 has a first conductivity type; for example, in some embodiments, drift region 121 is N-type. The first shielded doped region 14 and the second shielded doped region 15 have a second conductivity type; for example, in some embodiments, the first shielded doped region 14 and the second shielded doped region 15 are P-type. The first conductivity type and the second conductivity type are different. When the semiconductor structure is reverse-biased, since a gate structure 16 (e.g., ...) is provided in the mesh trench 13... Figure 9 As shown, the electric field at the bottom of the gate structure 16 is dispersed by the PN junction formed between the first shielded doped region 14 and the drift region 121, thus dispersing the electric field concentrated at the bottom of the mesh trench 13 and preventing breakdown at the bottom of the gate structure 16. The PN junction formed between the second shielded doped region 15 and the drift region 121 disperses the electric field concentrated on the sidewalls of the gate structure 16, preventing breakdown on the sidewalls of the gate structure 16 and improving the reliability of the semiconductor structure.

[0094] In the direction perpendicular to the substrate 11, the doping depth of the second shielding doped region 15 is greater than or equal to the doping depth of the mesh trench 13, and the orthogonal projection of the mesh trench 13 on the substrate 11 is located within the orthogonal projection of the first shielding doped region 14 on the substrate 11. That is to say, the first shielding doped region 14 and the second shielding doped region 15 are connected at this time, so that the first shielding doped region 14 and the second shielding doped region 15 can be grounded together, avoiding the need to design an additional grounding structure for the first shielding doped region 14.

[0095] It should be noted that the first shielding doped region 14 and the second shielding doped region 15 can be formed by ion implantation.

[0096] S30: A gate structure 16 is formed within the mesh trench 13 (e.g., ...). Figure 9 (As shown).

[0097] In this step, a gate structure 16 is formed in the mesh trench 13. First, a gate oxide layer 161 is formed on the bottom surface and sidewalls of the mesh trench 13 and on the side of the epitaxial structure 12 away from the substrate 11. Then, polysilicon 162 is filled on one side of the gate oxide layer 161 in the mesh trench 13 to form the gate structure 16.

[0098] In this embodiment, the presence of a first shielding doped region 14 and a second shielding doped region 15 prevents breakdown at the bottom and sidewalls of the gate structure 16, thus improving the reliability of the semiconductor structure. Furthermore, since the doping depth of the second shielding doped region 15 is greater than or equal to the doping depth of the mesh trench 13 in the direction perpendicular to the substrate 11, and the first shielding doped region 14 is located on the side of the mesh trench 13 closest to the substrate 11, the first shielding doped region 14 and the second shielding doped region 15 are connected. In this case, the first shielding doped region 14 and the second shielding doped region 15 can share a common ground, saving on fabrication steps.

[0099] In another embodiment of this application, an epitaxial structure 12 is formed on one side of the substrate 11, including:

[0100] S201: An epitaxial initial layer is formed on one side of the substrate 11.

[0101] In this step, the epitaxial initial layer can be an N-type silicon carbide epitaxial initial layer.

[0102] S202: Multiple source initial regions 170 are formed in an array within the epitaxial initial layer. The region between the multiple source initial regions 170 includes multiple first-direction extension regions 173 and multiple second-direction extension regions 174 arranged in a cross pattern. A second cross region 175 exists between the first-direction extension regions 173 and the second-direction extension regions 174 (e.g., ...). Figure 3 and Figure 4 (As shown).

[0103] In this step, a third mask material layer is first formed on the side of the epitaxial initial layer away from the substrate 11. Then, photolithography, dry etching, etc. are performed to form a patterned third mask layer. The patterned third mask layer is used to perform an implantation process on the epitaxial initial layer to form multiple source initial regions 170. It should be noted that the region between the multiple source initial regions 170 includes multiple first direction extension regions 173 and multiple second direction extension regions 174 arranged in a cross pattern. There is a second cross region 175 between the first direction extension regions 173 and the second direction extension regions 174, which forms the basis for subsequent etching and doping.

[0104] It should also be noted that forming the source initial region 170 includes using a patterned third mask layer to perform ion implantation on the epitaxial initial layer to form multiple well regions 171. The well region 171 can be a p-well, and the implantation depth of the well region 171 can be in the range of 0.5um-0.8um, including the endpoint value. For example, the implantation depth of the well region 171 can be 0.5um, or the implantation depth of the well region 171 can be 0.6um, or the implantation depth of the well region 171 can be 0.8um, etc.

[0105] Ion implantation is then performed on the initial epitaxial layer using a patterned third mask layer to form a first doped region 172 within the well region 171. This first doped region 172 can be N+ doped, and its implantation depth can range from 0.1µm to 0.4µm, including endpoint values. For example, the implantation depth of the first doped region 172 can be 0.1µm, 0.3µm, or 0.35µm, etc., so that the first doped region 172 is located on the side of the well region 171 furthest from the substrate 11.

[0106] It should be noted that the injection depth of the initial source region 170 can be designed according to the channel length.

[0107] S203: A shielding doped initial region 151 is formed. The orthogonal projection of the shielding doped initial region 151 onto the substrate 11 covers the orthogonal projection of the second cross region 175 onto the substrate 11, and also covers the orthogonal projection of a portion of the source initial region 170 surrounding the second cross region 175 onto the substrate 11. The remaining source initial region 170 forms the source region 17 (e.g., ...). Figure 5 (As shown).

[0108] In this step, the patterned third mask layer is first removed. Then, a fourth mask material layer is formed on the side of the epitaxial initial layer away from the substrate 11. Photolithography and dry etching are then performed to form the patterned fourth mask layer. The patterned fourth mask layer is used to implant the epitaxial initial layer to form a shielded doped initial region 151. The orthogonal projection of this shielded doped initial region 151 onto the substrate 11 covers the orthogonal projection of the second cross region 175 onto the substrate 11, and also covers the orthogonal projection of a portion of the source initial region 170 surrounding the second cross region 175 onto the substrate 11. The remaining source initial region 170 forms the source region 17. It should be noted that, at this point, in the direction perpendicular to the substrate 11, the doping depth of the shielded doped initial region 151 is greater than the doping depth of the source region 17. The shielded doped initial region 151 can be P+ doped, and the doping concentration of the shielded doped initial region 151 can be much greater than the doping concentration of the P-well region 171.

[0109] S204: Etch the epitaxial structure 12 to form a plurality of first-direction extension regions 173 and a plurality of second-direction extension regions 174 located between a plurality of source regions 17 to form a mesh-like trench 13, and the remaining shielding doped initial region 151 forms a second shielding doped region 15 (e.g., Figure 6 (As shown).

[0110] In this step, the etching depth of the mesh trench 13 can range from 0.8μm to 1μm, including the endpoint values. For example, the etching depth of the mesh trench 13 can be 0.8μm, or the etching depth of the mesh trench 13 can be 0.85μm, or the etching depth of the mesh trench 13 can be 0.9μm, etc.

[0111] S205: A first shielding doped region 14 is formed on the side of the mesh trench 13 near the substrate 11 (e.g., Figure 8 (As shown).

[0112] In this step, an implantation process can be used to form a first shielding doped region 14 at the bottom of the grid-like trench 13. The first shielding doped region 14 can be P-doped.

[0113] In another embodiment of this application, the epitaxial structure 12 is etched with a plurality of first-direction extension regions 173 and a plurality of second-direction extension regions 174 located between a plurality of source regions 17 to form a mesh-like trench 13. After the remaining shielding doped initial region 151 forms the second shielding doped region 15, it includes:

[0114] The area between the bottom surface of the grid-like groove 13 and the sidewall of the grid-like groove 13 is rounded to form a first arc-shaped surface;

[0115] The area between the top of the sidewalls of the mesh trench 13 and the surface of the epitaxial structure 12 on the side away from the substrate 11 is rounded to form a second arcuate surface (e.g., Figure 7 (As shown).

[0116] Specifically, when the area between the bottom surface of the mesh groove 13 and the sidewall of the mesh groove 13 is rounded to form the first arc-shaped surface, the first arc-shaped surface can be defined according to the width of the mesh groove 13. For example, when the width of the mesh groove 13 is W, the radius of the first arc-shaped surface can be set to R1. The range of R1 can be 0.3W-0.4W, including the endpoint values. For example, the radius R1 of the first arc-shaped surface can be set to 0.3W, or the radius R1 of the first arc-shaped surface can be set to 0.32W, or the radius R1 of the first arc-shaped surface can be set to 0.37W, etc.

[0117] When the area between the top of the sidewall of the mesh trench 13 and the surface of the epitaxial structure 12 away from the substrate 11 is rounded to form a second arc-shaped surface, the second arc-shaped surface can be defined according to the width of the mesh trench 13. For example, when the width of the mesh trench 13 is W, the radius of the second arc-shaped surface can be set to R2. The range of R2 can be 0.6W-0.7W, including the endpoint values. For example, the radius R2 of the second arc-shaped surface can be set to 0.61W, or 0.64W, or 0.7W, etc. There is no specific limitation; it can be set according to specific needs.

[0118] It should be noted that the first and second arc-shaped surfaces reduce the tip effect and avoid electric field concentration, further preventing the breakdown of the gate structure 16.

[0119] In another embodiment of this application, etching a plurality of first-direction extension regions 173 and a plurality of second-direction extension regions 174 located between a plurality of source regions 17 of the epitaxial structure 12 to form a mesh-like trench 13, including:

[0120] A patterned first mask layer is formed on the side of the epitaxial structure 12 away from the substrate 11 using a first mask.

[0121] Based on the patterned first mask layer, the epitaxial structure 12 is etched with a plurality of first-direction extension regions 173 and a plurality of second-direction extension regions 174 located between a plurality of source regions 17.

[0122] Remove the first mask layer of the graphical representation;

[0123] A first shielding doped region 14 is formed on the side of the mesh trench 13 near the substrate 11, including:

[0124] Using a first mask, a patterned second mask layer is formed on the side of the epitaxial structure 12 away from the substrate 11;

[0125] Based on the patterned second mask layer, ion implantation is performed on the side of the mesh trench 13 near the substrate 11 to form a first shielding doped region 14.

[0126] Specifically, when etching the multiple first-direction extension regions 173 and multiple second-direction extension regions 174 located between the multiple source regions 17 of the epitaxial structure 12, a first mask material layer can be formed first on the side of the epitaxial structure 12 away from the substrate 11. Then, based on the first mask, photolithography, dry etching, etc., are performed to form a patterned first mask layer. Then, based on the patterned first mask layer, the multiple first-direction extension regions 173 and multiple second-direction extension regions 174 between the source regions 17 are etched. Then, the patterned first mask layer is removed.

[0127] When forming the first shielding doped region 14 at the bottom of the mesh trench 13, a second mask material layer can be formed on the side of the epitaxial structure 12 away from the substrate 11 based on the first mask. Then, a patterned second mask layer is formed based on the first mask by photolithography, dry etching, etc. Then, the first shielding doped region 14 is formed at the bottom of the mesh trench 13 by ion implantation based on the patterned second mask layer.

[0128] It should be noted that the same first mask is used to form the mesh-like trench 13 and the first shielding doped region 14, which can reduce the fabrication of the mask and lower the process cost.

[0129] In another embodiment of this application, after forming the gate structure 16 within the mesh trench 13, the following is included:

[0130] S40: A dielectric layer 18 is formed on the side of the gate structure 16 away from the substrate 11, the dielectric layer 18 exposing at least a portion of the source region 17 and a portion of the second shielding doped region 15 (e.g., Figure 10 (As shown).

[0131] In this step, a dielectric material layer is first deposited on one side of the gate structure 16 and the epitaxial structure 12. This dielectric material layer can be made of materials such as undoped silicate glass, borophosphate glass, or silicon nitride. Then, a dielectric layer 18 is formed by dry etching. This dielectric layer 18 exposes at least a portion of the source region 17 and a portion of the second shielding doped region 15 to facilitate the formation of contact openings.

[0132] S50: Metal silicide 19 is formed on the exposed source region 17 and the second shielding doped region 15 (e.g., Figure 11 (As shown).

[0133] In this step, nickel is sputtered on the exposed portion of the source region 17 and the portion of the second shielded doped region 15, followed by two annealing processes to form metal silicide 19 within the contact opening.

[0134] S60: A first electrode 20 is formed on the side of the dielectric layer 18 and the metal silicide 19 away from the substrate 11 (e.g., Figure 11 (As shown).

[0135] In this step, a dielectric layer 18 and a metal silicide 19 are used to cover the first electrode 20, which can be the source electrode.

[0136] It should be noted that the first shielding doped region 14 is connected to the second shielding doped region 15, and then connected to the first electrode 20 through the metal silicide 19, so that the first shielding doped region 14 and the second shielding doped region 15 are grounded together.

[0137] S70: A second electrode 21 is formed on the side of the substrate 11 away from the epitaxial structure 12 (e.g., Figure 12 (As shown).

[0138] In this step, the side of the substrate 11 away from the epitaxial structure 12 can be thinned first, and then nickel can be sputtered to form an ohmic contact. Then, metals such as titanium, nickel, and silver can be used to deposit the second electrode 21, which can be a drain electrode.

[0139] In another embodiment of this application, after forming the first electrode 20 on the side of the dielectric layer 18 and the metal silicide 19 away from the substrate 11, the process includes:

[0140] A passivation layer 22 is formed on the side of the first electrode 20 away from the epitaxial structure 12.

[0141] Specifically, after the first electrode 20 is formed, a passivation layer 22 can be deposited on the side of the first electrode 20 away from the epitaxial structure 12 to protect the chip. It should be noted that the passivation layer 22 may include a first passivation layer 221 and a second passivation layer 222 stacked together. The material of the first passivation layer 221 may be silicon nitride, and the material of the second passivation layer 222 may be a polyimide layer, etc.

[0142] In addition, the passivation layer 22 can be removed where metal contact is required, and the specific removal location can be designed according to specific needs.

[0143] After the passivation layer 22 is formed, the following can be obtained: Figure 12 and Figure 13 In the structure shown, the first shielding doped region 14 at the bottom of the mesh-like trench 13 is grounded together with the second shielding doped region 15, thus avoiding the need for an additional grounding step for the first shielding doped region 14.

[0144] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An epitaxial structure is located on one side of the substrate. The epitaxial structure has a grid-like trench and includes a drift region, a first shielding doped region, and a plurality of second shielding doped regions. The drift region is located on the side of the first shielding doped region, the second shielding doped region, and the grid-like trench closer to the substrate. The drift region has a first conductivity type, and the first and second shielding doped regions have a second conductivity type, wherein the first conductivity type and the second conductivity type are different. The grid-like trench includes a plurality of first directional trenches and a plurality of second directional trenches arranged in a cross pattern. The first shielding doped region is located on the side of the grid-like trench closer to the substrate, and the orthographic projection of the grid-like trench on the substrate lies within the orthographic projection of the first shielding doped region on the substrate. Multiple second shielding doped regions surround the first intersection area of ​​the first directional groove and the second directional groove, and form the sidewall of the first intersection area of ​​the grid-like trench. In the direction perpendicular to the substrate, the doping depth of the second shielding doped region is greater than or equal to the trench depth of the grid-like trench. The first shielding doped region and the second shielding doped region are connected. The gate structure is located within the mesh-like trench.

2. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the first shielding doped region is less than that of the second shielding doped region.

3. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the grid-like groove is connected to the sidewall of the grid-like groove through a first arc-shaped surface; The top of the sidewall of the mesh trench is connected to the side of the epitaxial structure away from the substrate via a second arcuate surface.

4. The semiconductor structure according to claim 1, characterized in that, The epitaxial structure also includes; The source region is located on the side of the drift region away from the substrate and within the area enclosed by the mesh trench; In a direction perpendicular to the substrate, the doping depth of the source region is less than the doping depth of the second shielding doping region.

5. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; An epitaxial structure is formed on one side of the substrate. The epitaxial structure has a grid-like trench and includes a drift region, a first shielding doped region, and a plurality of second shielding doped regions. The drift region is located on the side of the first shielding doped region, the second shielding doped region, and the grid-like trench closer to the substrate. The drift region has a first conductivity type, and the first and second shielding doped regions have a second conductivity type, wherein the first conductivity type and the second conductivity type are different. The grid-like trench includes a plurality of first directional trenches and a plurality of second directional trenches arranged in a cross pattern. The first shielding doped region is located on the side of the grid-like trench closer to the substrate, and the orthographic projection of the grid-like trench on the substrate is located within the orthographic projection of the first shielding doped region on the substrate. Multiple second shielding doped regions surround the first intersection area of ​​the first directional groove and the second directional groove, and form the sidewall of the first intersection area of ​​the grid-like trench. In the direction perpendicular to the substrate, the doping depth of the second shielding doped region is greater than or equal to the doping depth of the grid-like trench. The first shielding doped region and the second shielding doped region are connected. A gate structure is formed within the mesh-like trench.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The formation of an epitaxial structure on one side of the substrate includes: An epitaxial initial layer is formed on one side of the substrate; Multiple source initial regions are formed in an array within the epitaxial initial layer. The region between the multiple source initial regions includes multiple first-direction extension regions and multiple second-direction extension regions arranged in a cross pattern. There is a second cross region between the first-direction extension regions and the second-direction extension regions. A shielding doped initial region is formed, the orthographic projection of the shielding doped initial region on the substrate covers the orthographic projection of the second cross region on the substrate, and covers the orthographic projection of a portion of the source initial region surrounding the second cross region on the substrate, the remaining source initial region forming the source region; The epitaxial structure is etched to form the first-direction extension region and the second-direction extension region located between the multiple source regions to form the mesh-like trench, and the remaining shielding doped initial region forms the second shielding doped region; The first shielding doped region is formed on the side of the mesh-like trench near the substrate.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The etching of the epitaxial structure, comprising a plurality of first-direction extension regions and a plurality of second-direction extension regions located between the plurality of source regions, to form the mesh-like trenches, and the remaining shielding doped initial regions forming the second shielding doped regions, includes: The area between the bottom surface of the mesh-like groove and the sidewall of the mesh-like groove is rounded to form a first arc-shaped surface; The area between the top of the sidewall of the mesh trench and the surface of the epitaxial structure on the side away from the substrate is rounded to form a second arcuate surface.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, The etching of the epitaxial structure, comprising a plurality of first-direction extension regions and a plurality of second-direction extension regions located between a plurality of source regions, to form the mesh-like trenches, includes: A first mask is used to form a patterned first mask layer on the side of the epitaxial structure away from the substrate; Based on the patterned first mask layer, a plurality of first-direction extension regions and a plurality of second-direction extension regions of the epitaxial structure located between a plurality of source regions are etched; Remove the first patterned mask layer; The formation of the first shielding doped region on the side of the mesh-like trench near the substrate includes: Using the first mask, a patterned second mask layer is formed on the side of the epitaxial structure away from the substrate; Based on the patterned second mask layer, ion implantation is performed on the side of the mesh trench near the substrate to form a first shielding doped region.

9. The method for preparing a semiconductor structure according to claim 6, characterized in that, After forming the gate structure within the mesh-like trench, the process includes: A dielectric layer is formed on the side of the gate structure away from the substrate, the dielectric layer exposing at least a portion of the source region and a portion of the second shielding doped region; Metal silicides are formed on the exposed source region and the second shielding doped region; A first electrode is formed on the side of the dielectric layer and the metal silicide away from the substrate; A second electrode is formed on the side of the substrate away from the epitaxial structure.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, After forming the first electrode on the side of the dielectric layer and the metal silicide away from the substrate, the process includes: A passivation layer is formed on the side of the first electrode away from the epitaxial structure.

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