IBC battery and preparation method thereof, photovoltaic module and power generation device

Abstract

The invention provides an IBC battery and a preparation method thereof, a photovoltaic module and a power generation device. The IBC battery comprises a silicon substrate, a first doping layer, a second doping layer and a leakage conduction structure. Wherein the first doping layer and the second doping layer are arranged on the back face of the silicon substrate in a spaced mode, the doping types of the first doping layer and the second doping layer are different, and the first doping layer and the second doping layer are separated through an isolation area; the electric leakage conduction structure is arranged between the first doping layer and the second doping layer, the electric leakage conduction structure comprises a first conduction block, a second conduction block and an electric leakage tunneling layer, the first conduction block is connected with the first doping layer, the second conduction block is connected with the second doping layer, the first conduction block and the second conduction block are at least partially overlapped, and the electric leakage tunneling layer is arranged between the first conduction block and the second conduction block. The electric leakage tunneling layer is arranged between the first conduction block and the second conduction block. According to the IBC battery, the risk that hot spots appear is small, and the technological process is easy to implement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to an IBC cell, a preparation method thereof, a photovoltaic module and a power generation device. BACKGROUND

[0002] The IBC (Interdigitated Back Contact) photovoltaic module is suitable to be used as a household photovoltaic module due to its beautiful appearance and high power density, but it is easily blocked by trees or bird droppings near the household, or when the IBC photovoltaic module is installed in a non-household scene, the hot spot effect of the IBC photovoltaic module is easily caused when external factors causing the blocking exist. How to reduce the influence of the hot spot effect of the IBC photovoltaic module on the output power of the module is a technical problem to be solved by the person skilled in the art. SUMMARY

[0003] Based on this, the present application provides an IBC cell for reducing the hot spot effect of an IBC photovoltaic module, and correspondingly provides a preparation method of the IBC cell, and a photovoltaic module and a power generation device using the IBC cell.

[0004] The technical solution provided in the present application is as follows:

[0005] According to the first aspect of the present application, an IBC cell is provided, comprising a silicon substrate, a first doped layer, a second doped layer and a leakage conduction structure;

[0006] The first doped layer and the second doped layer are arranged at the back surface of the silicon substrate, the doping types of the first doped layer and the second doped layer are different, and an isolation region is arranged between the first doped layer and the second doped layer;

[0007] The leakage conduction structure is arranged between the first doped layer and the second doped layer, the leakage conduction structure comprises a first conduction block, a second conduction block and a leakage tunneling layer, the first conduction block is connected with the first doped layer, the second conduction block is connected with the second doped layer, the first conduction block and the second conduction block at least partially overlap each other, and the leakage tunneling layer is arranged between the first conduction block and the second conduction block.

[0008] In any embodiment, the material of the first conduction block and the first doped layer is the same or different.

[0009] In any embodiment, the material of the second conduction block and the second doped layer is the same or different.

[0010] In any embodiment, the first conduction block is doped silicon with the same doping type as the first doped layer.

[0011] In any of the embodiments, the second conductive block is doped silicon of the same doping type as the second doped layer.

[0012] In any of the embodiments, the first conductive block is integrally formed with the first doped layer.

[0013] In any of the embodiments, the second conductive block is integrally formed with the second doped layer.

[0014] In any of the embodiments, the drain tunneling layer is a silicon oxide layer or a hydrogenated amorphous silicon layer.

[0015] In any of the embodiments, the drain tunneling layer has a thickness of 1 nm to 5 nm.

[0016] In any of the embodiments, the first conductive block has a width of 5 μm to 500 μm.

[0017] In any of the embodiments, the second conductive block has a width of 5 μm to 500 μm.

[0018] In any of the embodiments, the overlapping portion between the first conductive block and the second conductive block has a width of 1 μm to 300 μm.

[0019] In any of the embodiments, along the thickness direction of the silicon substrate, the orthographic projection of the first conductive block is located within the orthographic projection of the second conductive block, or the orthographic projection of the first conductive block partially overlaps the orthographic projection of the second conductive block.

[0020] In any of the embodiments, the edge of the first doped layer is inwardly recessed to form a recessed portion, and the first conductive block is located within the recessed portion.

[0021] In any of the embodiments, the first conductive block is convex to the second doped layer from the edge of the first doped layer.

[0022] In any of the embodiments, the drain conductive structure further comprises an insulating layer, which is arranged between the overlapping portion of the first conductive block and the second conductive block.

[0023] In any of the embodiments, the insulating layer comprises one or more of a phosphor-silicon glass layer, a boron-silicon glass layer, a silicon nitride layer, and a silicon oxide layer.

[0024] In any of the embodiments, the insulating layer has a thickness of 1 nm to 90 nm.

[0025] In any of the embodiments, part of the drain tunneling layer is arranged between the insulating layer and the second conductive block.

[0026] In any embodiment, the first doped layer includes a first main gate region and a plurality of first sub-gate regions connected to the first main gate region, and the second doped layer includes a second main gate region and a plurality of second sub-gate regions connected to the second main gate region, wherein the first sub-gate regions and the second sub-gate regions located between adjacent first main gate regions and second main gate regions are alternately spaced.

[0027] In any embodiment, the number of leakage conduction structures is multiple, and at least some of the leakage conduction structures are connected to adjacent first sub-gate regions and second sub-gate regions.

[0028] In any embodiment, the number of leakage current conduction structures is multiple, and at least some of the leakage current conduction structures are connected to the first sub-gate region and the second main gate region.

[0029] In any embodiment, there are multiple leakage current conduction structures, and at least some of the leakage current conduction structures are connected to the second sub-gate region and the first main gate region.

[0030] In any embodiment, there are multiple leakage current conduction structures, the first main gate region is provided with a first solder joint region, and at least a portion of the leakage current conduction structures are connected to the second sub-gate region and the first solder joint region.

[0031] In any embodiment, there are multiple leakage current conduction structures, and a second solder joint area is provided on the second main gate area. At least a portion of the leakage current conduction structures are connected to the first sub-gate area and the second solder joint area.

[0032] In any embodiment, the IBC cell further includes a first passivation tunneling layer and a second passivation tunneling layer, wherein the first passivation tunneling layer is disposed between the first doped layer and the silicon substrate and between the first conductive block and the silicon substrate, and the second passivation tunneling layer is disposed between the second doped layer and the silicon substrate.

[0033] In any embodiment, the second passivation tunneling layer and the leakage tunneling layer are integrally formed structures.

[0034] In any embodiment, the first passivation tunneling layer abuts against the leakage tunneling layer.

[0035] In any embodiment, a passivation layer and a protective layer are sequentially stacked on the side of the first doped layer, the second doped layer, the isolation region, and the leakage conduction structure away from the silicon substrate.

[0036] According to a second aspect of this application, a method for preparing an IBC battery according to the first aspect of this application is provided, comprising the following steps:

[0037] Provide silicon substrates;

[0038] A first doped layer, a first conductive block, a second doped layer, a second conductive block, and a leakage tunneling layer are formed on the back side of the silicon substrate, respectively.

[0039] The first doped layer and the second doped layer are spaced apart to form an isolation region. The first conductive block is located in the isolation region and connected to the first doped layer. The second conductive block is located in the isolation region and connected to the second doped layer. The first conductive block and the second conductive block overlap at least partially. The leakage tunneling layer is disposed between the first conductive block and the second conductive block. The first conductive block, the second conductive block and the leakage tunneling layer constitute a leakage conduction structure.

[0040] In any embodiment, forming the first doped layer and the first conductive block on the back side of the silicon substrate includes the following steps:

[0041] A first tunneling oxide layer, a first doped silicon layer, and a mask layer are sequentially deposited on the back side of the silicon substrate; and

[0042] The mask layer, the first doped silicon layer, and the first tunneling oxide layer are removed from the area on the back side of the silicon substrate, excluding the area where the first doped layer and the first conductive block are located, to obtain a battery cell intermediate.

[0043] In any embodiment, forming the second doped layer, the second conductive block, and the leakage tunneling layer on the back side of the silicon substrate includes the following steps:

[0044] A second tunneling oxide layer and a second doped silicon layer are sequentially deposited on the back side of the silicon substrate after the formation of the first doped layer and the first conductive block; and

[0045] Remove the second doped silicon layer and the second tunneling oxide layer from the area on the back side of the silicon substrate where the second doped layer and the second conductive block are located.

[0046] In any embodiment, removing the mask layer, the first doped silicon layer, and the first tunneling oxide layer outside the region where the first doped layer and the first conductive block are located on the back side of the silicon substrate includes the following steps:

[0047] The mask layer, excluding the area containing the first doped layer and the first conductive block on the back side of the silicon substrate, is etched using a laser; and

[0048] The first doped silicon layer and the first tunneling oxide layer outside the area where the first doped layer and the first conductive block are located on the back side of the silicon substrate are removed by etching with an alkaline solution.

[0049] In any embodiment, removing the second doped silicon layer and the second tunneling oxide layer outside the region where the second doped layer and the second conductive block are located on the back side of the silicon substrate includes the following steps:

[0050] The second doped silicon layer and the second tunneling oxide layer outside the area where the second doped layer and the second conductive block are located on the back side of the silicon substrate are removed by etching with an alkaline solution.

[0051] In any embodiment, the step of removing the second doped silicon layer and the second tunneling oxide layer outside the region where the second doped layer and the second conductive block are located on the back side of the silicon substrate further includes the step of removing the mask layer located outside the region where the second doped layer and the second conductive block are located on the back side of the silicon substrate, so that the remaining mask layer serves as an insulating layer.

[0052] In any embodiment, after removing the second doped silicon layer and the second tunneling oxide layer outside the region where the second doped layer and the second conductive block are located on the back side of the silicon substrate, the step of sequentially forming a passivation layer and a protective layer on the back side of the silicon substrate is further included.

[0053] According to a third aspect of this application, an IBC photovoltaic module is provided, comprising a plurality of IBC cells according to the first aspect of this application, wherein the plurality of IBC cells are interconnected to form an IBC cell string.

[0054] According to a fourth aspect of this application, a power generation device is provided, including an IBC battery according to the first aspect of this application, or an IBC photovoltaic module according to the third aspect of this application.

[0055] Compared with traditional technologies, this application has at least the following beneficial effects:

[0056] A leakage current conduction structure is provided within the isolation region. This structure includes a first conducting block, a second conducting block, and a leakage tunneling layer. The first conducting block is connected to a first doped layer, and the second conducting block is connected to a second doped layer, with at least partial overlap between them. The leakage tunneling layer is disposed between the first and second conducting blocks. Under normal operating conditions of the solar cell, the leakage current conduction structure separates the first and second conducting blocks through the leakage tunneling layer. When the cell has a certain reverse bias voltage, charge carriers can pass through the leakage tunneling layer to achieve conduction between the first and second conducting blocks. The leakage current conduction structure forms a leakage path, which can alleviate or prevent leakage current from accumulating in individual areas of the solar cell under high reverse bias conditions, thereby reducing the impact of hot spot effects.

[0057] Furthermore, by making the first conducting block and the second conducting block at least partially overlap, that is, the first conducting block is at least partially stacked on the second conducting block, or the second conducting block is at least partially stacked on the first conducting block, the leakage current conduction structure has low requirements for the precision of the manufacturing process, is less affected by manufacturing precision and process fluctuations, and is easy to implement and manufacture in the process. Attached Figure Description

[0058] To better describe and illustrate the embodiments or examples provided in this application, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the currently described embodiments or examples, or the best mode of conduct of these applications as currently understood. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0059] Figure 1 This is a schematic diagram of the structure of a traditional IBC battery;

[0060] Figure 2 Photograph of a localized defect in an IBC battery;

[0061] Figure 3 Photograph of hot spot phenomenon caused by local defects in IBC battery;

[0062] Figure 4 This is a schematic diagram of the structure of an IBC battery according to one embodiment of this application;

[0063] Figure 5 This is a schematic diagram of the back of an IBC battery according to one embodiment of this application;

[0064] Figure 6 This is a schematic diagram of the leakage conduction structure in an IBC battery according to an embodiment of this application.

[0065] Figure 7 This is a schematic diagram of the leakage conduction structure in an IBC battery according to another embodiment of this application.

[0066] Figure 8 This is a schematic diagram of the structure of the first doped layer in an IBC battery according to an embodiment of this application;

[0067] Figure 9 This is a schematic diagram of the connection structure between the first doped layer and the first conductive block in an IBC battery according to an embodiment of this application.

[0068] Figure 10 This is a schematic diagram of the connection structure between the first doped layer and the first conductive block in an IBC battery according to another embodiment of this application.

[0069] Figure 11This is a schematic diagram of the leakage conduction structure in an IBC battery according to one embodiment of this application;

[0070] Figure 12 This is a schematic diagram of the structure of the back doped layer of an IBC battery according to one embodiment of this application;

[0071] Figure 13 This is a schematic diagram of the structure of the back doped layer of an IBC battery according to another embodiment of this application;

[0072] Figure 14 This is a schematic diagram of the structure of the back doped layer of an IBC battery according to another embodiment of this application;

[0073] Figure 15 This is a schematic diagram of the structure of the back doped layer of an IBC battery according to another embodiment of this application;

[0074] Figure 16 This is a schematic diagram of the leakage conduction structure in an IBC battery according to another embodiment of this application;

[0075] Figure 17 This is a schematic diagram of the leakage conduction structure in an IBC battery according to another embodiment of this application;

[0076] Figure 18 This is a schematic diagram of the leakage conduction structure in an IBC battery according to another embodiment of this application;

[0077] Figure 19 This is a schematic diagram of the leakage conduction structure in an IBC battery according to another embodiment of this application;

[0078] Figure 20 This is a schematic diagram of the back electrode grid lines and leakage conduction structure of an IBC battery according to an embodiment of this application.

[0079] Figure 21 This is a schematic diagram of the back electrode grid lines and leakage conduction structure of a gridless IBC battery according to an embodiment of this application.

[0080] Figure 22 This is a schematic diagram of the structure after depositing a first tunneling oxide layer, a first doped silicon layer, and a mask layer on the back side of a silicon substrate according to an embodiment of this application.

[0081] Figure 23 A schematic diagram of the structure of a battery cell intermediate prepared by the preparation method of one embodiment of this application;

[0082] Figure 24 This is a schematic diagram of the structure after depositing a second tunneling oxide layer, a second doped silicon layer, and a second mask layer on the intermediate layer of the solar cell.

[0083] Figure 25This is a schematic diagram of the structure after removing the second mask layer, the second doped silicon layer, the second tunneling oxide layer and the first mask layer outside the area where the second doped layer and the second conductive block are located on the back side of the silicon substrate, and removing the remaining second mask layer, according to a preparation method of an embodiment of this application.

[0084] Figure 26 This is a schematic diagram of the structure of an IBC battery prepared by the preparation method according to one embodiment of this application.

[0085] Explanation of reference numerals in the attached figures:

[0086] 1. IBC cell; 1-1. Silicon substrate; 1-2. First doped layer; 1-3. Second doped layer; 1-4. Isolation region; 1-5. First passivation tunneling layer; 1-6. Second passivation tunneling layer; 1-7. Passivation layer; 1-8. Protective layer; 1-9. First electrode; 1-10. Second electrode;

[0087] 10. IBC cell; 11. Silicon substrate; 12. First doped layer; 13. Second doped layer; 14. Leakage conduction structure; 15. Isolation region; 16. First passivation tunneling layer; 17. Second passivation tunneling layer; 18. Passivation layer; 19. Protective layer; 20. First electrode; 21. Second electrode; 22. First tunneling oxide layer; 23. First doped silicon layer; 24. First mask layer; 25. Cell intermediate; 26. Second tunneling oxide layer ; 27. Second doped silicon layer; 28. Second mask layer; 121. First main gate region; 122. First sub-gate region; 123. First solder joint region; 131. Second main gate region; 132. Second sub-gate region; 133. Second solder joint region; 141. First conductive block; 142. Second conductive block; 143. Leakage tunneling layer; 144. Insulating layer; 201. First main gate; 202. First sub-gate; 211. Second main gate; 212. Second sub-gate. Detailed Implementation

[0088] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0090] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0092] Please see Figure 1 In a conventional IBC cell 1, a first doped layer 1-2 and a second doped layer 1-3 with different doping types are provided on the back side of the silicon substrate 1-1, and the first doped layer 1-2 and the second doped layer 1-3 are separated by an isolation region 1-4; a first passivation tunneling layer 1-5 is provided between the first doped layer 1-2 and the silicon substrate 1-1, and a second passivation tunneling layer 1-6 is provided between the second doped layer 1-3 and the silicon substrate 1-1; a passivation layer 1-7 and a protective layer 1-8 are also stacked sequentially on the front and back sides of the silicon substrate 1-1; a first electrode 1-9 passes through the passivation layer 1-7 and the protective layer 1-8 on the back side and is connected to the first doped layer 1-2, and a second electrode 1-10 passes through the passivation layer 1-7 and the protective layer 1-8 on the back side and is connected to the second doped layer 1-3.

[0093] IBC cell 1 is easily shaded by trees or bird droppings near residents, making the IBC photovoltaic module prone to hot spot effect, which in turn leads to a decrease in the output power of the photovoltaic module. Therefore, how to reduce the impact of the hot spot effect of the IBC photovoltaic module on the module output power is a technical problem that urgently needs to be solved by those skilled in the art. This application improves the structure of IBC cell 1, effectively reducing the probability of hot spot phenomenon in IBC cell 1 and its photovoltaic module.

[0094] Please see Figure 4 , Figure 5 and Figure 6 According to one embodiment of this application, an IBC battery 10 is provided. The IBC battery 10 includes a silicon substrate 11, a first doped layer 12, a second doped layer 13, and a leakage conduction structure 14. The first doped layer 12 and the second doped layer 13 are disposed at intervals on the back side of the silicon substrate 11. The first doped layer 12 and the second doped layer 13 have different doping types. An isolation region 15 is provided between the first doped layer 11 and the second doped layer 12. The leakage conduction structure 14 is disposed between the first doped layer 12 and the second doped layer 13. The leakage conduction structure 14 includes a first conducting block 141, a second conducting block 142, and a leakage tunneling layer 143. The first conducting block 141 is connected to the first doped layer 12, and the second conducting block 142 is connected to the second doped layer 13. The first conducting block 141 and the second conducting block 142 overlap at least partially. The leakage tunneling layer 143 is disposed between the first conducting block 141 and the second conducting block 142.

[0095] In traditional IBC cells, the first doped layer 1-2 and the second doped layer 1-3 are separated by an isolation region 1-4. However, in the actual manufacturing process, the cells sometimes have problems or defects such as scratches, over-etching, cracks, pinholes, leakage, PN region overlap, and edge leakage. At this time, when the IBC photovoltaic module has local shading that causes hot spot effect, under a high reverse bias voltage, the leakage current passes through these defect points, causing a large current path to be formed locally in the cell, generating high temperature and causing hot spot phenomenon in the cell.

[0096] The IBC battery 10 described above in this application includes a leakage current conduction structure 14 provided in the isolation region 15. The leakage current conduction structure 14 includes a first conducting block 141, a second conducting block 142, and a leakage current tunneling layer 143. The first conducting block 141 is connected to the first doped layer 12, the second conducting block 142 is connected to the second doped layer 13, and the first conducting block 141 and the second conducting block 142 overlap at least partially. The leakage current tunneling layer 143 is disposed between the first conducting block 141 and the second conducting block 142. Under normal operating conditions of the solar cells, i.e., when the IBC photovoltaic module is not shaded by a hot spot effect, the leakage current conduction structure 14 separates the first conducting block 141 and the second conducting block 142 through the leakage current tunneling layer 143. When the IBC photovoltaic module experiences a hot spot effect, and the IBC cell has a certain reverse bias voltage, photogenerated carriers can pass through the leakage current tunneling layer 143 to achieve conduction between the first conducting block 141 and the second conducting block 142. At this time, the leakage current conduction structure 14 forms a leakage current path, which can alleviate or prevent leakage current from concentrating in individual areas of the solar cell, thereby reducing the impact of the hot spot effect.

[0097] In addition, by making the first conductive block 141 and the second conductive block 142 at least partially overlap, that is, the first conductive block 141 is at least partially superimposed on the second conductive block 142, or the second conductive block 142 is at least partially superimposed on the first conductive block 141, the leakage current conduction structure 14 has low requirements for the precision of the manufacturing process, is less affected by manufacturing precision and process fluctuation factors, and is easy to realize and manufacture in the process.

[0098] In some embodiments, the first conducting block 141 is doped silicon with the same doping type as the first doped layer 12; the second conducting block 142 is doped silicon with the same doping type as the second doped layer 13. Thus, under reverse bias, charge carriers can pass through the leakage tunneling layer 143 to conduct the first doped layer 12 and the second doped layer 13, forming a leakage path. It can be understood that when the first doped layer 12 is an N-type doped layer, the first conducting block 141 is also an N-type doped conducting block; when the first doped layer 12 is a P-type doped layer, the first conducting block 141 is also a P-type doped conducting block; when the second doped layer 13 is an N-type doped layer, the second conducting block 142 is also an N-type doped conducting block; and when the second doped layer 13 is a P-type doped layer, the second conducting block 142 is also a P-type doped conducting block.

[0099] In some specific examples, the first doped layer 12 and the first conductive block 141 are both N-type doped silicon layers, and the second doped layer 13 and the second conductive block 142 are both P-type doped silicon layers. In other specific examples, the first doped layer 12 and the first conductive block 141 are both P-type doped silicon layers, and the second doped layer 13 and the second conductive block 142 are both N-type doped silicon layers.

[0100] It should be noted that the materials of the first conducting block 141 and the first doped layer 12 can be the same or different, as long as the first conducting block 141 can effectively transport charge carriers when the battery is under reverse bias. Similarly, the materials of the second conducting block 142 and the second doped layer 13 can be the same or different, as long as the second conducting block 142 can effectively transport charge carriers when the battery is under reverse bias.

[0101] In some specific examples, the materials of the first conducting block 141 and the second conducting block 142 are each independently one or more of a doped silicon layer and a conductive oxide. The doped silicon layer includes one or more of boron-doped silicon, phosphorus-doped silicon, gallium-doped silicon, arsenic-doped silicon, antimony-doped silicon, and aluminum-doped silicon; the conductive oxide includes one or more of indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium oxide, and ruthenium oxide.

[0102] Please see Figure 7In some embodiments, the first conductive block 141 and the first doped layer 12 are integrally formed, and the second conductive block 142 and the second doped layer 13 are integrally formed. That is, the first conductive block 141 and the first doped layer 12 can be formed as an integral structure simultaneously during fabrication; the second conductive block 142 and the second doped layer 13 can also be formed as an integral structure simultaneously during fabrication. This simplifies the fabrication process of the leakage conduction structure 14.

[0103] Please see Figure 4 and Figure 6 In some embodiments, the first conductive block 141 and the first doped layer 12 may not be integrally formed, and the second conductive block 142 and the second doped layer 13 may not be integrally formed. When using this structure, the first conductive block 141 and the first doped layer 12 need to be fabricated separately, and the second conductive block 142 and the second doped layer 13 need to be fabricated separately.

[0104] In some embodiments, the leakage tunneling layer 143 is a silicon oxide layer or a hydrogenated amorphous silicon layer, and the thickness of the leakage tunneling layer 143 is 1 nm to 5 nm, optionally 1 nm to 3 nm. By providing the aforementioned extremely thin leakage tunneling layer 143 between the first conducting block 141 and the second conducting block 142 for separation, charge carriers can tunnel through the leakage tunneling layer 143 between the first conducting block 141 and the second conducting block 142 in the event of a hot spot effect. In addition, using a silicon oxide layer or a hydrogenated amorphous silicon layer as the leakage tunneling layer 143 can also passivate the dangling bonds on the surface of the silicon substrate 11, achieving a better passivation effect.

[0105] In some embodiments, the width of the first conducting block 141 (see [reference]) Figure 11 The width of L1 and the second conduction block 142 (see [reference]). Figure 11The widths of the first conducting block 141 and the second conducting block 142 are each independently 5μm to 500μm. Controlling the widths of the first conducting block 141 and the second conducting block 142 within the above range is more conducive to mitigating or avoiding leakage current accumulation in individual areas of the battery cell, and is more conducive to reducing the impact of hot spot effect. It is understood that the widths of the first conducting block 141 and the second conducting block 142 can each independently be 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, 220μm, 250μm, 280μm, 300μm, 320μm, 350μm, 380μm, 400μm, 420μm, 450μm, 480μm, 500μm, or any value within the range formed by any two of the above values.

[0106] It should be noted that the width of the first conducting block 141 refers to the maximum length between any two endpoints of the first conducting block 141 along a direction parallel to the length direction of the first doped layer 12; similarly, the width of the second conducting block 142 refers to the maximum length between any two endpoints of the second conducting block 142 along a direction parallel to the length direction of the second doped layer 13.

[0107] In some embodiments, the width of the overlapping portion between the first conducting block 141 and the second conducting block 142 (see [reference]). Figure 6 L3) is 1μm to 300μm. It can be understood that the width of the overlapping portion between the first conductive block 141 and the second conductive block 142 can be 1μm, 5μm, 10μm, 20μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, 220μm, 250μm, 280μm, 300μm, or any value within the range formed by any two of the above values.

[0108] It should be noted that the width of the overlapping portion between the first conductive block 141 and the second conductive block 142 refers to the maximum length between any two endpoints of the overlapping portion of the first conductive block 141 and the second conductive block 142 along a direction parallel to the width direction of the first doped layer 12 or the second doped layer 13.

[0109] In some embodiments, along the thickness direction of the silicon substrate 11, the orthographic projection of the first conductive block 141 lies within the orthographic projection range of the second conductive block 142; that is, the first conductive block 141 is completely overlapped and covered by the second conductive block 142. In other embodiments, along the thickness direction of the silicon substrate 11, the orthographic projection of the first conductive block 141 and the orthographic projection of the second conductive block 142 partially overlap; that is, the second conductive block 142 only overlaps and covers a portion of the first conductive block 141.

[0110] Please see Figure 8 and Figure 9 In some embodiments, the edge of the first doped layer 12 is recessed inward to form a recess, and the first conductive block 141 is located within this recess. That is, the first conductive block 141 is embedded in the recess formed by the first doped layer 12. It can be understood that in this structure, the outer wall of the first conductive block 141 and the outer wall of the area of ​​the first doped layer 12 other than the recess may be coplanar or non-coplanar.

[0111] Please see Figure 10 In some embodiments, the first conductive block 141 protrudes from the edge of the first doped layer 12 toward the second doped layer 142. That is, the aforementioned recess is not provided at the edge of the first doped layer 12, the first conductive block 141 is connected to the outer wall of the first doped layer 12, and protrudes from the outer wall of the first doped layer 12 toward the second doped layer 142.

[0112] Please see Figure 6 In some embodiments, the leakage conduction structure 14 further includes an insulating layer 144 disposed between the overlapping portions of the first conducting block 141 and the second conducting block 142. Specifically, the insulating layer 144 may be one or more of a phosphosilicate glass layer, a borosilicate glass layer, silicon nitride, and silicon oxide layer. In some specific examples, the thickness of the insulating layer 144 may be 1 nm to 90 nm.

[0113] By providing the aforementioned insulating layer 144 between the overlapping portions of the first conductive block 141 and the second conductive block 142, when the first conductive block 141 and the second conductive block 142 are doped silicon layers of different doping types, it is beneficial to reduce or avoid the doping elements in the second conductive block 142 from entering the first conductive block 141 and affecting the carrier transport capability of the first conductive block 141 during the fabrication of the second conductive block 142.

[0114] In some embodiments, a portion of the leakage tunneling layer 143 is disposed between the insulating layer 144 and the second conductive block 142. That is, a structure is formed within the leakage conductive structure 14 by sequentially stacking the first conductive block 141, the insulating layer 144, the leakage tunneling layer 143, and the second conductive block 142. It is understood that the aforementioned leakage tunneling layer 143 may or may not be disposed between the insulating layer 144 and the second conductive block 142.

[0115] In some embodiments, the first doped layer 12 includes a first main gate region 121 and a plurality of first sub-gate regions 122 connected to the first main gate region 121; the second doped layer 13 includes a second main gate region 131 and a plurality of second sub-gate regions 132 connected to the second main gate region 131; and the first sub-gate regions 122 and the second sub-gate regions 132 located between adjacent first main gate regions 121 and second main gate regions 131 are alternately arranged to form an interdigitated distribution structure.

[0116] Please see Figure 11 to Figure 16 In some embodiments, there are multiple leakage conduction structures 14, with at least some of the leakage conduction structures 14 connected between adjacent first sub-gate regions 122 and second sub-gate regions 132. Thus, the aforementioned leakage conduction structures 14 can provide leakage conduction to the area near the first sub-gate region 122 and second sub-gate region 132, mitigating or avoiding the adverse effects of hot spot effects on the IBC photovoltaic module when hot spot effects occur.

[0117] It should be noted that the number of leakage current conduction structures 14 between a first sub-gate region 122 and its adjacent second sub-gate region 132 can be one or more. The multiple leakage current conduction structures 14 can be evenly spaced along the length direction of the first sub-gate region 122 and the second sub-gate region 132, or they can be unevenly spaced along the length direction of the first sub-gate region 122 and the second sub-gate region 132. The leakage current conduction structures 14 on different first sub-gate regions 122 or different second sub-gate regions 132 can be in corresponding or non-corresponding positions.

[0118] Please see Figure 17 In some embodiments, there are multiple leakage current conduction structures 14, with at least a portion of the leakage current conduction structures 14 connected between the first sub-gate region 122 and the second main gate region 131. That is, the end of the first sub-gate region 122 is connected to the second main gate region 131 through the leakage current conduction structure 14. In this way, leakage current conduction can be achieved in the area near the end of the first sub-gate region 122 and the second main gate region 131, mitigating or avoiding the adverse effects of hot spot effect on the IBC photovoltaic module when hot spot effect occurs.

[0119] Please see Figure 18Similarly, in some embodiments, there are multiple leakage conduction structures 14, with at least a portion of the leakage conduction structures 14 connected between the second sub-gate region 132 and the first main gate region 121. That is, the end of the second sub-gate region 132 is connected to the first main gate region 121 through the leakage conduction structures 14. In this way, leakage conduction can be achieved between the end of the second sub-gate region 132 and the area near the first main gate region 121, mitigating or avoiding the adverse effects of hot spot effect on the IBC photovoltaic module when hot spot effect occurs.

[0120] Please see Figure 19 In some embodiments, there are multiple leakage current conduction structures 14. A portion of the leakage current conduction structures 14 are connected between the first sub-gate region 122 and the second main gate region 131; another portion of the leakage current conduction structures 14 are connected between the second sub-gate region 132 and the first main gate region 121. That is, the end of the first sub-gate region 122 is connected to the second main gate region 131 through a portion of the leakage current conduction structures 14, and simultaneously the end of the second sub-gate region 132 is connected to the first main gate region 121 through a portion of the leakage current conduction structures 14.

[0121] In some embodiments, there are multiple leakage conduction structures 14. A first solder joint area 123 is provided on the first main grid region 121, and at least a portion of the leakage conduction structures 14 are connected between the second sub-grid region 132 and the first solder joint area 123. That is, the end of the second sub-grid region 132 is connected to the first solder joint area 123 through the leakage conduction structures 14. In this way, leakage conduction can be achieved in the area near the end of the second sub-grid region 132 and the first solder joint area 123, mitigating or avoiding the adverse effects of hot spot effect on the IBC photovoltaic module when hot spot effect occurs.

[0122] In some embodiments, there are multiple leakage conduction structures 14, and a second solder joint area 133 is provided on the second main grid region 131. At least a portion of the leakage conduction structures 14 are connected between the first sub-grid region 122 and the second solder joint area 133. That is, the end of the first sub-grid region 122 is connected to the second solder joint area 133 through the leakage conduction structures 14. In this way, leakage conduction can be achieved in the area near the end of the first sub-grid region 122 and the second solder joint area 133, mitigating or avoiding the adverse effects of hot spot effect on the IBC photovoltaic module when hot spot effect occurs.

[0123] Please see Figure 4 In some embodiments, a first passivation tunneling layer 16 is provided between the first doped layer 12 and the back side of the silicon substrate 11; a second passivation tunneling layer 17 is also provided between the second doped layer 13 and the back side of the silicon substrate 11. Thus, the first doped layer 12 and its corresponding first passivation tunneling layer 16 together form a passivation contact structure, and the second doped layer 13 and its corresponding second passivation tunneling layer 17 together form a passivation contact structure.

[0124] In some embodiments, the second passivation tunneling layer 17 and the leakage tunneling layer 143 are integrally formed. The first passivation tunneling layer 16 abuts against the leakage tunneling layer 143.

[0125] Please see Figure 4 In some embodiments, a passivation layer 18 and a protective layer 19 are sequentially stacked on the side of the first doped layer 12, the second doped layer 13, the isolation region 15, and the leakage conduction structure 14 facing away from the silicon substrate 11. By providing the passivation layer 18 on the back side of the silicon substrate 11, the passivation effect is further improved; by providing the protective layer 19, the silicon substrate 11 and the doped layers can be protected from external damage, and it can also passivate and / or adjust the light reflectivity. The passivation layer 18 can be made of conventional passivation materials, such as alumina; the protective layer 19 can be made of conventional materials with certain passivation effects, such as silicon nitride or silicon oxynitride. It is understood that the above-mentioned passivation layer 18 and protective layer 19 can also be provided on the front side of the silicon substrate 11, but the protective layer 19 on the front side needs to have an anti-reflection effect.

[0126] Please see Figure 4 In some embodiments, a first electrode 20 is disposed on a first doped layer 12, and a second electrode 21 is disposed on a second doped layer 13, for the collection and extraction of charge carriers. The first electrode 20 passes through the protective layer 19 and passivation layer 18 on the first doped layer 12 and is connected to the first doped layer 12; the second electrode 21 passes through the protective layer 19 and passivation layer 18 on the second doped layer 13 and is connected to the second doped layer 13.

[0127] Please see Figure 20 Specifically, the first electrode 20 includes a first main gate 201 and a first sub-gate 202, with the first main gate 201 connected to the first main gate region 121 and the first sub-gate 202 connected to the first sub-gate region 122; the second electrode 21 includes a second main gate 211 and a second sub-gate 212, with the second main gate 211 connected to the second main gate region 131 and the second sub-gate 212 connected to the second sub-gate region 132. The first sub-gate 202 and the second sub-gate 212 are used to collect carriers from the silicon substrate 11 and transport them to the first main gate 201 and the second main gate 211, respectively; the first main gate 201 and the second main gate 211 are then used to extract the carriers.

[0128] In some embodiments, the IBC battery 10 has a gridless structure, and the leakage conduction structure 14 is located at any position between the first sub-gate region 122 and the second sub-gate region 132. See also... Figure 21The first electrode includes a first sub-gate 202, which is connected to a first sub-gate region 122; the second electrode includes a second sub-gate 212, which is connected to a second sub-gate region 132. The first sub-gate 202 and the second sub-gate 212 are used to collect carriers from the silicon substrate 11.

[0129] According to one embodiment of this application, a method for preparing the above-described IBC battery 10 is provided, the method comprising the following steps:

[0130] Provide silicon substrate 11;

[0131] A first doped layer 12, a first conductive block 141, a second doped layer 13, a second conductive block 142, and a leakage tunneling layer 143 are formed on the back side of the silicon substrate 11, respectively.

[0132] In this configuration, a first doped layer 12 and a second doped layer 13 are spaced apart to form an isolation region 15. A first conductive block 141 is located within the isolation region 15 and connected to the first doped layer 12. A second conductive block 142 is located within the isolation region 15 and connected to the second doped layer 13. The first conductive block 141 and the second conductive block 142 overlap at least partially. A leakage tunneling layer 143 is disposed between the first conductive block 141 and the second conductive block 142. The first conductive block 141, the second conductive block 142, and the leakage tunneling layer 143 constitute a leakage conduction structure 14.

[0133] Please see Figure 22 to Figure 26 In some embodiments, a first doped layer 12 and a first conductive block 141 are first formed on the back side of the silicon substrate 11; then a second doped layer 13, a second conductive block 142 and a leakage tunneling layer 143 are formed on the back side of the silicon substrate 11, and the second doped layer 13 is spaced apart from the first doped layer 12 to form an isolation region 15.

[0134] Thus, by first forming a first doped layer 12 and a first conductive block 141 on the back side of the silicon substrate 11, and then forming a second doped layer 13, a second conductive block 142, and a leakage tunneling layer 143 on the back side of the silicon substrate 11, the second doped layer 13 and the first doped layer 12 are spaced apart to form an isolation region 15; wherein the first conductive block 141, the leakage tunneling layer 143, and the second conductive block 142 form a leakage conductive structure 14 within the isolation region 15, and the first conductive block 141 and the second conductive block 142 at least partially overlap. This fabrication method has low requirements for the precision of the fabrication process when forming the leakage conductive structure, is less affected by manufacturing precision and process fluctuations, and is easy to implement and manufacture in terms of process technology.

[0135] In some embodiments, a first tunneling oxide layer 22, a first doped silicon layer 23, and a first mask layer 24 are first sequentially deposited on the back side of the silicon substrate 11. Then, the first mask layer 24, the first doped silicon layer 23, and the first tunneling oxide layer 22 are removed from the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11, thereby forming the first doped layer 12 and the first conductive block 141 on the back side of the silicon substrate 11, resulting in a battery cell intermediate 25. This configuration allows for the simultaneous formation of the first doped layer 12 and the first conductive block 141, resulting in an integrally formed structure of the first doped layer 12 and the first conductive block 141, which helps to further simplify the battery fabrication process.

[0136] It is understood that in the above preparation method, the first doped silicon layer 23 retained in the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11 serves as the first doped layer 12 and the first conductive block 141 in the subsequently prepared IBC cell 10; the retained first tunneling oxide layer 22 serves as the first passivation tunneling layer 16 in the subsequently prepared IBC cell 10.

[0137] In some embodiments, a second tunneling oxide layer 26, a second doped silicon layer 27, and a second mask layer 28 are first sequentially deposited on the back side of the silicon substrate 11 of the intermediate cell 25. Then, the second mask layer 28, the second doped silicon layer 27, the second tunneling oxide layer 26, and the first mask layer 24 are removed from the area containing the second doped layer 13 and the second conductive block 142 on the back side of the silicon substrate 11. The remaining second mask layer 28 is then removed, thereby forming the second doped layer 13, the second conductive block 142, and the leakage tunneling layer 143 on the back side of the silicon substrate 11, and forming an isolation region 15 between the second doped layer 13 and the first doped layer 12. The retained first mask layer 24 serves as the insulating layer 144 in the subsequently fabricated IBC cell 10. This configuration allows for the simultaneous formation of the second doped layer 13 and the second conductive block 142, resulting in an integrally formed structure of the second doped layer 13 and the second conductive block 142, which further simplifies the cell fabrication process.

[0138] It is understood that in the above-described fabrication method, the second doped silicon layer 27 retained within the region where the second doped layer 13 and the second conductive block 142 are located on the back side of the silicon substrate 11 serves as the second doped layer 13 and the second conductive block 142 in the IBC cell 10; the retained second tunneling oxide layer 26 serves as the integrally formed leakage tunneling layer 143 and the second passivation tunneling layer 17 in the IBC cell 10.

[0139] In some embodiments, the first doped silicon layer 23 is a boron-doped silicon layer, and the first mask layer 24 is a borosilicate glass layer; the second doped silicon layer 27 is a phosphorus-doped silicon layer, and the second mask layer 28 is a phosphorus-silicon glass layer. In other embodiments, the first doped silicon layer 23 is a phosphorus-doped silicon layer, the first mask layer 24 is a phosphorus-silicon glass layer; the second doped silicon layer 27 is a boron-doped silicon layer, and the second mask layer 28 is a borosilicate glass layer. Both the first tunneling oxide layer 22 and the second tunneling oxide layer 26 can be ultrathin silicon oxide layers with a thickness of less than 5 nm; further, they can be 1 nm to 3 nm.

[0140] In some embodiments, the first mask layer 24, the first doped silicon layer 23, and the first tunneling oxide layer 22 outside the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11 are removed by the following method: firstly, the first mask layer 24 outside the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11 is etched by laser; then, the first doped silicon layer 23 and the first tunneling oxide layer 22 outside the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11 are removed by alkaline solution etching.

[0141] Specifically, a light spot size of 10μm~300μm, a wavelength of 200nm~1300nm, and an energy density of 100mJ / cm² can be used. 2 ~600mJ / cm 2 Nanosecond, picosecond, or femtosecond lasers are used to etch the first mask layer 24 outside the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11; then, a sodium hydroxide solution with a concentration of 0.5wt%~30wt% is used to etch at 50℃~90℃ for 1min~30min to remove the first doped silicon layer 23 and the first tunneling oxide layer 22 outside the area where the first doped layer 12 and the first conductive block 141 are located on the back side of the silicon substrate 11.

[0142] In some embodiments, the second doped silicon layer 27 and the second tunneling oxide layer 26, outside the area where the second doped layer 13 and the second conductive block 142 are located on the back side of the silicon substrate 11, are removed by etching with an alkaline solution. Similarly, the alkaline solution can be a sodium hydroxide solution with a concentration of 0.5wt% to 30wt%, the etching temperature can be 50°C to 90°C, and the etching time can be 1 min to 30 min.

[0143] In some embodiments, after removing the second doped silicon layer 27 and the second tunneling oxide layer 26 outside the area where the second doped layer 13 and the second conductive block 142 are located on the back side of the silicon substrate 11, a passivation layer 18 and a protective layer 19 are sequentially formed on both the front and back sides of the silicon substrate 11. The pastes for the first electrode 20 and the second electrode 21 are then printed on the first doped layer 12 and the second doped layer 13 on the back side of the silicon substrate 11, respectively. After sintering, the first electrode 20 and the second electrode 21 are formed. Furthermore, the prepared IBC cell 10 can be subjected to light injection treatment.

[0144] One embodiment of this application provides an IBC photovoltaic module (not shown), which includes a plurality of IBC cells 10 as described above, and the plurality of IBC cells 10 are interconnected to form an IBC cell string. By employing the IBC cells 10 of this application, the IBC photovoltaic module of this application can effectively alleviate or avoid leakage current accumulation in individual areas of the cells, effectively reducing the risk of hot spots in the IBC photovoltaic module.

[0145] One embodiment of this application also provides a power generation device (not shown), which includes the IBC battery 10 described above, or the IBC photovoltaic module described above. It is understood that the power generation device includes various devices having the IBC battery 10 or the IBC photovoltaic module described above. Examples include solar power plants, solar water heaters, solar streetlights, solar-powered drones, etc.

[0146] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0147] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. An IBC battery, characterized in that, It includes a silicon substrate, a first doped layer, a second doped layer, and a leakage conduction structure; The first doped layer and the second doped layer are disposed on the back side of the silicon substrate at a distance, the first doped layer and the second doped layer have different doping types, and an isolation region is provided between the first doped layer and the second doped layer; The leakage conduction structure is disposed between the first doped layer and the second doped layer. The leakage conduction structure includes a first conducting block, a second conducting block and a leakage tunneling layer. The first conducting block is connected to the first doped layer, and the second conducting block is connected to the second doped layer. The first conducting block and the second conducting block overlap at least partially. The leakage tunneling layer is disposed between the first conducting block and the second conducting block.

2. The IBC battery according to claim 1, characterized in that, The materials of the first conductive block and the first doped layer may be the same or different; And / or, the material of the second conducting block is the same as or different from that of the second doped layer.

3. The IBC battery according to claim 1, characterized in that, The first conducting block is doped silicon with the same doping type as the first doped layer; And / or, the second conducting block is doped silicon of the same doping type as the second doped layer.

4. The IBC battery according to any one of claims 1 to 3, characterized in that, The first conductive block and the first doped layer are integrally formed. And / or, the second conductive block and the second doped layer are integrally formed.

5. The IBC battery according to any one of claims 1 to 3, characterized in that, The leakage tunneling layer is a silicon oxide layer or a hydrogenated amorphous silicon layer; And / or, the thickness of the leakage tunneling layer is 1nm~5nm.

6. The IBC battery according to any one of claims 1 to 3, characterized in that, The width of the first conductive block is 5μm~500μm; And / or, the width of the second conductive block is 5μm~500μm.

7. The IBC battery according to any one of claims 1 to 3, characterized in that, The width of the overlapping portion between the first conductive block and the second conductive block is 1μm~300μm.

8. The IBC battery according to any one of claims 1 to 3, characterized in that, Along the thickness direction of the silicon substrate, the orthographic projection of the first conductive block is located within the orthographic projection range of the second conductive block, or the orthographic projection of the first conductive block partially overlaps with the orthographic projection of the second conductive block.

9. The IBC battery according to any one of claims 1 to 3, characterized in that, The leakage current conduction structure also includes an insulating layer, which is disposed between the overlapping portions of the first conduction block and the second conduction block.

10. The IBC battery according to claim 9, characterized in that, The insulating layer includes one or more of the following: a phosphosilicate glass layer, a borosilicate glass layer, a silicon nitride layer, and a silicon oxide layer; And / or, the thickness of the insulating layer is 1 nm to 90 nm.

11. The IBC battery according to claim 9, characterized in that, A portion of the leakage tunneling layer is disposed between the insulating layer and the second conductive block.

12. The IBC battery according to any one of claims 1-3 and 10-11, characterized in that, The first doped layer includes a first main gate region and a plurality of first sub-gate regions connected to the first main gate region. The second doped layer includes a second main gate region and a plurality of second sub-gate regions connected to the second main gate region. The first sub-gate regions and the second sub-gate regions located between adjacent first main gate regions and second main gate regions are alternately spaced.

13. The IBC battery according to claim 12, characterized in that, The number of leakage current conduction structures is multiple, and at least some of the leakage current conduction structures are connected to adjacent first sub-gate regions and second sub-gate regions.

14. The IBC battery according to claim 12, characterized in that, The number of leakage current conduction structures is multiple, and at least some of the leakage current conduction structures are connected to the first sub-gate region and the second main gate region.

15. The IBC battery according to claim 12, characterized in that, The number of leakage current conduction structures is multiple, and at least some of the leakage current conduction structures are connected to the second sub-gate region and the first main gate region.

16. The IBC battery according to claim 12, characterized in that, The number of leakage current conduction structures is multiple, and a first solder joint area is provided on the first main gate area. At least a portion of the leakage current conduction structures are connected to the second sub-gate area and the first solder joint area.

17. The IBC battery according to claim 12, characterized in that, The number of leakage current conduction structures is multiple, and a second solder joint area is provided on the second main gate area. At least a portion of the leakage current conduction structures are connected between the first sub-gate area and the second solder joint area.

18. The IBC battery according to any one of claims 1-3, 10-11, and 13-17, characterized in that, The IBC cell further includes a first passivation tunneling layer and a second passivation tunneling layer. The first passivation tunneling layer is disposed between the first doped layer and the silicon substrate, and between the first conductive block and the silicon substrate. The second passivation tunneling layer is disposed between the second doped layer and the silicon substrate.

19. The IBC battery according to claim 18, characterized in that, The second passivation tunneling layer and the leakage tunneling layer are integrally formed structures.

20. The IBC battery according to claim 18, characterized in that, The first passivation tunneling layer abuts against the leakage tunneling layer.

21. The IBC battery according to any one of claims 1-3, 10-11, 13-17, and 19-20, characterized in that, A passivation layer and a protective layer are sequentially stacked on the side of the first doped layer, the second doped layer, the isolation region, and the leakage conduction structure away from the silicon substrate.

22. A method for preparing an IBC battery, characterized in that, Includes the following steps: Provide silicon substrates; A first doped layer, a first conductive block, a second doped layer, a second conductive block, and a leakage tunneling layer are formed on the back side of the silicon substrate, respectively. The first doped layer and the second doped layer are spaced apart to form an isolation region. The first conductive block is located in the isolation region and connected to the first doped layer. The second conductive block is located in the isolation region and connected to the second doped layer. The first conductive block and the second conductive block overlap at least partially. The leakage tunneling layer is disposed between the first conductive block and the second conductive block. The first conductive block, the second conductive block and the leakage tunneling layer constitute a leakage conduction structure.

23. The method for preparing an IBC battery according to claim 22, characterized in that, Forming the first doped layer and the first conductive block on the back side of the silicon substrate includes the following steps: A first tunneling oxide layer, a first doped silicon layer, and a mask layer are sequentially deposited on the back side of the silicon substrate; and Remove the mask layer, the first doped silicon layer, and the first tunneling oxide layer from the area on the back side of the silicon substrate where the first doped layer and the first conductive block are located.

24. The method for preparing an IBC battery according to claim 23, characterized in that, Forming the second doped layer, the second conductive block, and the leakage tunneling layer on the back side of the silicon substrate includes the following steps: A second tunneling oxide layer and a second doped silicon layer are sequentially deposited on the back side of the silicon substrate after the formation of the first doped layer and the first conductive block; and Remove the second doped silicon layer and the second tunneling oxide layer from the area on the back side of the silicon substrate where the second doped layer and the second conductive block are located.

25. The method for preparing an IBC battery according to claim 24, characterized in that, The step of removing the second doped silicon layer and the second tunneling oxide layer outside the region where the second doped layer and the second conductive block are located on the back side of the silicon substrate further includes: removing the mask layer located outside the region where the second doped layer and the second conductive block are located on the back side of the silicon substrate, so that the remaining mask layer serves as an insulating layer.

26. An IBC photovoltaic module, characterized in that, The invention includes multiple IBC batteries as described in any one of claims 1 to 21, wherein the multiple IBC batteries are interconnected to form an IBC battery string.

27. A power generation device, characterized in that, It includes the IBC battery as described in any one of claims 1 to 21, or the IBC photovoltaic module as described in claim 26.

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