Light emitting device

Abstract

A light emitting device is provided. A light emitting device according to the present invention includes a substrate structure, a first upper surface electrode, a second upper surface electrode, a light emitting element, a first lower surface electrode, a second lower surface electrode, and a light transmitting member. A first upper surface electrode is formed on the first via group in one region. A second upper surface electrode is formed on the second via group in one region. The light emitting element is disposed on one region across the first upper surface electrode and the second upper surface electrode. A first lower surface electrode is formed on the first via group on a lower surface of the first substrate. A second lower surface electrode is formed on the second via group on the lower surface of the first substrate. The light transmitting member is formed on an upper surface of the second substrate and seals a space including the opening. The light transmissive member is light transmissive. A corresponding lt of the silicon crystals of the first substrate and the second substrate; 110gt, 110gt; the orientations are offset from each other in a plan view of the substrate structure viewed from above.

Description

Technical Field

[0001] This invention relates to light-emitting devices. Background Technology

[0002] As a light-emitting device that emits ultraviolet light, light-emitting devices in which semiconductor light-emitting devices such as light-emitting diodes (LEDs) are used as light sources have been disclosed. For example, JP-A-2022-040769 discloses a light-emitting device in which a light-emitting element made of aluminum gallium nitride (AlGaN) is placed on a mounting substrate and the light-emitting element is hermetically sealed on the mounting substrate by a light-transmitting member. Summary of the Invention

[0003] In the light-emitting device disclosed in JP-A-2022-040769, for example, during the temperature rise and fall process when the light-emitting element is mounted on the mounting substrate, cracks may appear on the mounting substrate due to the difference in the coefficient of thermal expansion between the mounting substrate and the electrodes disposed on the mounting substrate.

[0004] For example, if a crack appears on the mounting substrate, the existing crack will propagate on both the surface exposed to the hermetically sealed space with the light-transmitting member and the surface exposed to the external space. Therefore, gas leakage from the hermetically sealed light-emitting element can cause gas from the external space (i.e., outside air) to enter the hermetically sealed space. As a result, problems such as premature degradation of the light-emitting element due to contact with moisture-containing outside air may occur.

[0005] The present invention was made in consideration of the above points and aims to provide a light-emitting device capable of suppressing the destruction of the hermetic seal of the light-emitting element.

[0006] The light-emitting device according to the present invention includes a substrate structure, a first upper surface electrode, a second upper surface electrode, a light-emitting element, a first lower surface electrode, a second lower surface electrode, and a light-transmitting member. The substrate structure includes a first substrate made of monocrystalline silicon and a second substrate made of monocrystalline silicon. The first substrate includes thermally oxidized films formed on its upper and lower surfaces. The second substrate is bonded to the upper surface of the first substrate and has an opening that exposes a region on the upper surface of the first substrate. The first substrate has a first via group and a second via group. The first via group includes one or more vias penetrating from a first portion region of a region to the lower surface of the first substrate. The second via group includes one or more vias penetrating from a second portion region to the lower surface of the first substrate. The second portion region is arranged in a region to form a gap extending in one direction relative to the first portion region. The first upper surface electrode is formed in a region on the first via group. The second upper surface electrode is formed in a region on the second via group to face the first upper surface electrode. The light-emitting element is disposed across the first and second upper surface electrodes in a region. The first lower surface electrode is formed on the lower surface of the first substrate on the first via group. A second lower surface electrode is formed on the lower surface of the first substrate on the second via group to face the first lower surface electrode. A light-transmitting member is formed on the upper surface of the second substrate and seals the space including the opening. The light-transmitting member is light-transmitting. The silicon crystals of the first and second substrates are respectively... <110> The orientations are staggered in a plan view of the substrate structure viewed from above. Attached Figure Description

[0007] Figure 1 This is a top view of the light-emitting device according to Embodiment 1 of the present invention;

[0008] Figure 2 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention;

[0009] Figure 3 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during a step of its manufacturing process.

[0010] Figure 4 This is a top view of the light-emitting device according to Embodiment 1 of the present invention during a step of manufacturing;

[0011] Figure 5 This is a top view of the light-emitting device according to Embodiment 1 of the present invention during a step of manufacturing;

[0012] Figure 6 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0013] Figure 7This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0014] Figure 8 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0015] Figure 9 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0016] Figure 10 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0017] Figure 11 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0018] Figure 12 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during one step of its manufacturing process;

[0019] Figure 13 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during a step of its manufacturing process; and

[0020] Figure 14 This is a cross-sectional view of the light-emitting device according to Embodiment 1 of the present invention during a step of its manufacturing process.

[0021] Description of reference numerals in the attached figures

[0022] 100 Light-emitting devices

[0023] 11. Substrate Structure

[0024] 13 Light-emitting elements

[0025] 15. Light-transmitting components

[0026] 21 First substrate

[0027] 22 Second substrate

[0028] 24 First insulating film

[0029] 25 Second insulating film

[0030] 26 Through-electrode

[0031] 28 First lower surface electrode

[0032] 29 Second lower surface electrode

[0033] 31 First upper surface electrode

[0034] 32 Second upper surface electrode

[0035] 34 Thermal Oxidation Film

[0036] 41 Semiconductor structural layer

[0037] 42 Transparent substrate

[0038] 43 n electrode

[0039] 44 p electrode

[0040] 46 Bonding Layer

[0041] 48 Glass bonding layer Detailed Implementation

[0042] Embodiments of the present invention are described in detail below. In the following description and drawings, the same reference numerals are assigned to substantially the same or equivalent parts.

[0043] [Implementation Method 1]

[0044] [Overview of the light-emitting device 100]

[0045] Reference Figure 1 and Figure 2 The configuration of the light-emitting device 100 according to Embodiment 1 is described. Figure 1 This is a top view of the light-emitting device 100 according to Embodiment 1. Figure 2 It is along Figure 1 The cross-sectional view of the light-emitting device 100 shown is taken from line 2-2.

[0046] The light-emitting device 100 is configured to include a substrate structure 11, a light-emitting element 13 disposed on the substrate structure 11, and a light-transmitting member 15 that hermetically seals the light-emitting element 13 onto the substrate structure 11. Figure 1 In order to clearly show the structural and positional relationships of each component, the light-transmitting component 15 has been omitted. Additionally, in... Figure 2 For illustrative purposes, the vertical direction in the figure represents the height of the light-emitting device 100, and the horizontal direction represents the width of the light-emitting device 100.

[0047] [Substrate Structure 11]

[0048] First, the configuration of the substrate structure 11 will be described. The substrate structure 11 has a flat first substrate 21 with a rectangular upper surface and a frame-shaped second substrate 22 formed along the outer edge of the upper surface of the first substrate 21. The second substrate 22 has an opening 22O that exposes a region CA (hereinafter also referred to as the central region CA) at the center of the upper surface of the first substrate 21. In other words, the substrate structure 11 is a recessed structure configured to expose the central region CA of the first substrate 21 through the second substrate 22.

[0049] In substrate structure 11, both the first substrate 21 and the second substrate 22 are silicon substrates made of single-crystal silicon (Si) with the (100) side as the main surface. Substrate structure 11 is a so-called silicon-on-insulator (SOI) substrate in which the first substrate 21 and the second substrate 22 are bonded together via a first insulating film 24 as a buried oxide (BOX) film.

[0050] In the SOI substrate, the first insulating film 24 is a thermally oxidized film made of silicon oxide (SiO2) formed on the upper surface of the first substrate 21 by performing a thermal oxidation process on the first substrate 21.

[0051] The first substrate 21 has a plurality of through holes 21H, each through hole penetrating the first substrate 21 from the central region CA on the upper surface of the first substrate 21 exposed by the second substrate 22 to the lower surface of the first substrate 21.

[0052] like Figure 1 As shown, multiple vias 21H are formed into a first via group TG1 and a second via group TG2. The first via group TG1 is arranged in the region to the left of the central region CA of the first substrate 21. The second via group TG2 is arranged in the region to the right of the central region CA to be separated from the first via group TG1. In other words, the first via group TG1 and the second via group TG2 are formed in a first portion region and a second portion region of the central region CA, respectively. The second portion region is arranged to be formed relative to the first portion region along... Figure 1 The gap G extends vertically within the middle.

[0053] In each of the first via group TG1 and the second via group TG2, the corresponding plurality of vias 21H are arranged in a regular triangular lattice pattern. In the light-emitting device 100, the spacing between the vias 21H in the first via group TG1 is the same as the spacing between the vias in the second via group TG2, and the area where the first via group TG1 is formed is larger than the area where the second via group TG2 is formed. As a result, the number of vias 21H in the first via group TG1 is greater than the number of vias 21H in the second via group TG2.

[0054] As described above, on the first substrate 21, a first insulating film 24 is formed on the upper surface of the first substrate 21 in a region opposite to the lower surface of the second substrate 22, that is, in the region overlapping with the second substrate 22 in the top view. In addition, on the first substrate 21, a second insulating film 25 is formed on the inner surface of each of the through holes 21H and on the lower surface of the first substrate 21, starting from the central region CA.

[0055] That is, on the upper surface of the first substrate 21, the second insulating film 25 is formed in the central region CA, which is a region, and the first insulating film 24 is formed in another region surrounding the central region CA. Similar to the first insulating film 24, the second insulating film 25 is an insulating film made of SiO2 formed by performing a thermal oxidation process on the first substrate 21.

[0056] The first substrate 21 has a columnar through electrode 26 made of Cu filled inside a corresponding through hole 21H via a second insulating film 25, so as to penetrate the first substrate 21. That is, the corresponding through electrode 26 is exposed from the central region CA of the upper surface of the first substrate 21 and the lower surface of the first substrate 21, while being insulated from each other by the second insulating film 25 formed on the corresponding inner surface of the through hole 21H.

[0057] The first substrate 21 has a first lower surface electrode 28 and a second lower surface electrode 29, each having a rectangular upper surface shape. The first lower surface electrode 28 and the second lower surface electrode 29 are formed to be separated from each other on the lower surface of the first substrate 21. The first lower surface electrode 28 is electrically connected to each of the through electrodes 26 arranged in the through holes 21H belonging to the first through hole group TG1, so as to cover each of the through holes 21H when viewed from a direction perpendicular to the lower surface of the first substrate 21.

[0058] Furthermore, the second lower surface electrode 29 is electrically connected to each of the through electrodes 26 arranged in the through holes 21H belonging to the second through hole group TG2, so as to cover each of the through holes 21H when viewed from a direction perpendicular to the lower surface of the first substrate 21. That is, the first lower surface electrode 28 and the second lower surface electrode 29 are connected via a direction along the lower surface of the first substrate 21. Figure 1 The gap G extends vertically within the arrangement.

[0059] The first lower surface electrode 28 and the second lower surface electrode 29 are made of titanium (Ti), copper (Cu), nickel (Ni), and gold (Au) sequentially stacked from the lower surface side of the first substrate 21. When the light-emitting device 100 is mounted on a mounting substrate (not shown), the first lower surface electrode 28 and the second lower surface electrode 29 serve as mounting electrodes.

[0060] The first substrate 21 has a first upper surface electrode 31 and a second upper surface electrode 32, each having a rectangular upper surface shape. The first upper surface electrode 31 and the second upper surface electrode 32 are formed on the upper surface of the first substrate 21 and are separated from each other in a central region CA. The first upper surface electrode 31 is electrically connected to each of the through electrodes 26 arranged in the through holes 21H belonging to the first through hole group TG1, so as to cover each of the through holes 21H when viewed from a direction perpendicular to the upper surface of the first substrate 21.

[0061] Furthermore, the second upper surface electrode 32 is electrically connected to each of the through electrodes 26 arranged in the through holes 21H belonging to the second through hole group TG2, so as to cover each of the through holes 21H when viewed from a direction perpendicular to the upper surface of the first substrate 21. That is, the first upper surface electrode 31 and the second upper surface electrode 32 are connected via a direction along the through holes 21H. Figure 1 The gap G extends vertically within the arrangement.

[0062] Therefore, the first upper surface electrode 31 is electrically connected to the first lower surface electrode 28 via each of the through electrodes 26 in the first via group TG1. Additionally, the second upper surface electrode 32 is electrically connected to the second lower surface electrode 29 via each of the through electrodes 26 in the second via group TG2. The first upper surface electrode 31 and the second upper surface electrode 32 are made of Ti, Cu, and Ni sequentially stacked from the upper surface side of the first substrate 21.

[0063] The Cu film included in each of the first lower surface electrode 28, the second lower surface electrode 29, the first upper surface electrode 31, and the second upper surface electrode 32 described above has a sufficient thickness to dissipate the heat generated when the light-emitting element 13, described later, is driven to the outside. For example, the Cu film included in each electrode has a thickness of about 20 μm to 30 μm.

[0064] In the plan view of the substrate structure 11 viewed from above, the Si crystal of the first substrate 21... <110> Orientation relative to the extension direction of the aforementioned gap G ( Figure 1 The vertical direction (in the middle) has an angle different from 0° and 90°. Additionally, the Si crystal of the first substrate 21... <110> The orientation has an angle different from 45° relative to the extension direction of the gap G.

[0065] In the (100) plane of Si crystal, <110> Orientation and <100> The orientations are at a 45° angle to each other. Therefore, in the substrate structure 11 of the light-emitting device 100, the Si crystal of the first substrate 21... <110> The orientation also has an angle different from 0° and 90° relative to the extension direction of the gap G.

[0066] The second substrate 22 has an opening 22O that exposes the central region CA on the upper surface of the first substrate 21. The inner surface of the second substrate 22 forming the opening 22O is inclined so as to extend from the lower surface of the second substrate 22 toward the upper surface. That is, the recess of the substrate structure 11 has a shape in which the truncated form of a square pyramid is reversed.

[0067] In the light-emitting device 100, the inner surface of the second substrate 22 is inclined at an angle of approximately 54.7° relative to the upper surface of the first substrate 21. On the inner surface inclined at this angle, the (111) plane of the Si crystal appears.

[0068] In the plan view of the substrate structure 11 viewed from above, the Si crystal of the second substrate 22... <110> The orientation has an angle of 0° or 90° relative to the extending direction of the aforementioned gap G. Therefore, due to the Si crystal of the first substrate 21 as described above... <110> The orientation has an angle different from 0° and 90° relative to the extension direction of the gap G, therefore the Si crystals of the first substrate 21 and the second substrate 22 each <110> The orientations are staggered in a plan view of the substrate structure 11 viewed from above.

[0069] The second substrate 22 has a thermal oxide film 34 formed on its upper and inner surfaces. Similar to the first insulating film 24, the thermal oxide film 34 is an insulating film made of SiO2 formed by performing a thermal oxidation process on the second substrate 22.

[0070] [Light-emitting element 13]

[0071] Next, the configuration of the light-emitting element 13 will be described. The light-emitting element 13 is a light-emitting diode with a rectangular upper surface shape disposed on the central region CA of the upper surface of the first substrate 21. In other words, the light-emitting element 13 is disposed on the bottom surface of the recess of the substrate structure 11. The light-emitting element 13 is configured to include a semiconductor structure layer 41, a transparent substrate 42, an n-electrode 43, and a p-electrode 44.

[0072] Semiconductor structure layer 41 is a semiconductor stack consisting of an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer (not shown), each containing AlGaN as the main material. When the light-emitting device 100 is driven, the light-emitting layer of semiconductor structure layer 41 emits light with wavelengths in the deep ultraviolet region, such as light with wavelengths from 100 nm to 280 nm.

[0073] The transparent substrate 42 is a flat substrate disposed on the semiconductor structure layer 41. The transparent substrate 42 is made of a material such as aluminum nitride (AlN) that is semi-transparent to ultraviolet light emitted from the light-emitting layer of the semiconductor structure layer 41. In addition, the transparent substrate 42 is also a growth substrate for growing the semiconductor crystal that forms the semiconductor structure layer 41.

[0074] The n-electrode 43 and p-electrode 44 are electrodes with Au plated on Cu, and they are respectively connected to the n-type semiconductor layer and p-type semiconductor layer of the semiconductor structure layer 41. The n-electrode 43 and p-electrode 44 are bonded to the first upper surface electrode 31 and the second upper surface electrode 32 via a gold-tin (AuSn) bonding layer 46. That is, in the light-emitting device 100, the light-emitting element 13 is mounted on the first substrate 21 of the substrate structure 11 in a flip-chip manner.

[0075] The bonding layer 46 is heated, melted, and cured, thereby bonding the light-emitting element 13 to the first upper surface electrode 31 and the second upper surface electrode 32. When the bonding layer 46 is heated and melted, the Ni layer constituting the first upper surface electrode 31 and the second upper surface electrode 32 acts as a barrier layer to inhibit the diffusion mixing of the Cu layer below the Ni layer with the AuSn constituting the bonding layer 46.

[0076] [Light-transmitting component 15]

[0077] Next, the structure of the light-transmitting member 15 will be described. The light-transmitting member 15 is a plate-shaped body with a rectangular upper surface, which is bonded to the upper surface of the second substrate 22 via a glass bonding layer 48 made of a paste containing powdered glass frit. The light-transmitting member 15 is made of glass containing SiO2 as the main raw material and transmits deep ultraviolet light emitted from the light-emitting element 13.

[0078] In the light-emitting device 100, ultraviolet light emitted from the light-emitting element 13 is incident on the lower surface of the light-transmitting member 15 and emitted from the upper surface of the light-transmitting member 15. That is, the upper surface of the light-transmitting member 15 serves as the light extraction surface of the light-emitting device 100.

[0079] The light-transmitting member 15 is bonded to the upper surface of the second substrate 22 via a glass bonding layer 48, thereby hermetically sealing the light-emitting element 13 arranged in the opening 22O. Specifically, the light-transmitting member 15 and the substrate structure 11 define a space SP as a receiving space (see Figure 2 For example, gases such as nitrogen (N2) that are not altered by ultraviolet light are enclosed in space SP and sealed, thereby suppressing the light-emitting element 13 from being exposed to the outside air.

[0080] Instead of using a glass bonding layer 48, a bonding layer made of AuSn, for example, can be used to bond the light-transmitting member 15 to the second substrate 22. In this case, corresponding metallization layers in which Ni and Au are sequentially stacked are formed on the lower surface of the light-transmitting member 15 and the upper surface of the second substrate 22, and layers made of AuSn are arranged between the formed corresponding metallization layers, thereby bonding the light-transmitting member 15 to the second substrate 22.

[0081] [Suppression of sealed gas leakage]

[0082] Here, using Figure 1 and Figure 2 The paper describes how the light-emitting device 100 of this embodiment suppresses the leakage of the sealing gas of the sealed light-emitting element 13.

[0083] As described above, in the light-emitting device 100, the silicon crystal of the first substrate 21... <110> The orientation has an angle different from 0°, 45° and 90° relative to the extension direction of the gap G. Therefore, in the light-emitting device 100 of this embodiment, even if brittle fracture occurs in the central region CA formed on the upper surface of the first substrate 21 or in the second insulating film 25 formed on the lower surface of the first substrate 21, the propagation of cracks from the second insulating film 25 into the first substrate 21 can be suppressed.

[0084] When the light-emitting element 13 is mounted on the first substrate 21, for example, the light-emitting element 13 is placed on a bonding layer 46 made of AuSn, and the bonding layer 46 is melted and solidified by raising the temperature from room temperature to about 260°C to 320°C, thereby bonding the light-emitting element 13 to the first upper surface electrode 31 and the second upper surface electrode 32.

[0085] Here, Cu, contained in each of the first lower surface electrode 28, the second lower surface electrode 29, the first upper surface electrode 31, and the second upper surface electrode 32, has a relatively large coefficient of thermal expansion, and especially in the temperature region close to the melting point of the aforementioned bonding layer 46, it expands significantly with increasing temperature. On the other hand, since Si constituting the first substrate 21 has a smaller coefficient of thermal expansion than Cu, Si expands less than Cu at the same temperature.

[0086] Since this occurs when the light-emitting element 13 is installed, each of the first lower surface electrode 28, the second lower surface electrode 29, the first upper surface electrode 31, and the second upper surface electrode 32 expands and contracts, thereby generating thermal stress on the first substrate 21.

[0087] Specifically, for example, on the lower surface side of the first substrate 21, when the thermally expanded first lower surface electrode 28 and second lower surface electrode 29 contract during a temperature decrease, tensile stress is generated, which attempts to pull the first substrate 21 in opposite directions. On the upper surface side of the first substrate 21, when the thermally expanded first upper surface electrode 31 and second upper surface electrode 32 contract during a temperature decrease, tensile stress is generated, which attempts to pull the first substrate 21 in opposite directions.

[0088] When such tensile stress is generated on the first substrate 21, it may cause stress to be exerted on, for example, by... Figure 2 The two-dot dashed lines enclose and indicate the region AR (i.e., the region between the first lower surface electrode 28 and the second lower surface electrode 29, and the region between the first upper surface electrode 31 and the second upper surface electrode 32) which exert a large force.

[0089] For example, when the first substrate 21 is subjected to the aforementioned tensile stress, the fracture toughness of SiO2 is 0.3 MPa·m. 1 / 2 The lower limit is relatively small. Therefore, brittle fracture occurs on the second insulating film 25 in region AR, resulting in cracks on the second insulating film 25. Cracks that have already appeared, for example, are found in... Figure 1 The gap G between the first through-hole group TG1 and the second through-hole group TG2 extends along the vertical direction shown in the attached figure.

[0090] Cracks can easily propagate from the second insulating film 25, which is a thermally oxidized film formed by thermal oxidation of Si, to the first substrate 21 made of Si. Furthermore, in a Si crystal having a (100) facet as its main surface, and... <100> Orientation and <110> Orientations parallel or perpendicular to the grain are known as directions where cleavage is likely to occur. In these directions, once a crack enters the Si crystal, it will... Figure 2 It expands rapidly in the vertical direction.

[0091] Therefore, in the (100) plane of the Si crystal, for example, when the Si crystal of the first substrate 21... <100> Orientation and <110> When the orientation has an angle of 0° or 90° relative to the extension direction of the gap G, that is, when the extension direction of the gap G is parallel or perpendicular to the easy cleavage crystal orientation of the Si crystal, once the crack propagates from the second insulating film 25 to the first substrate 21 as described above, the crack may directly propagate and penetrate the first substrate 21. In other words, there is a risk that the first substrate 21 will break.

[0092] Furthermore, even if the crack only appears Figure 2 In one region of region AR, as an existing crack extends from one side to the other, the crack may eventually penetrate the first substrate 21.

[0093] For example, when a crack penetrates the first substrate 21, the gas that hermetically seals the light-emitting element 13 may leak to the outside. If this happens, there is a risk that the light-emitting element 13 will deteriorate prematurely due to external air containing external moisture or the like entering the space SP of the substrate structure 11.

[0094] In the light-emitting device 100 of this embodiment, the Si crystal of the first substrate 21... <110> The orientation has an angle different from 0°, 45°, and 90° relative to the extension direction of the gap G. That is, in the top view, the extension direction of the gap G has an angle that is neither parallel nor perpendicular to the crystal orientation in which cleavage of the Si crystal of the first substrate 21 may occur. This makes it unlikely that cleavage will occur on the first substrate 21 even if the crack propagates from the second insulating film 25.

[0095] Therefore, by using the light-emitting device 100 of this embodiment, even if cracks appear on the second insulating film 25 due to thermal stress generated on the first substrate 21, the propagation of cracks into the first substrate 21 can be suppressed by using a first substrate 21 on which electrodes with gap G are formed (which has an angle that is neither parallel nor perpendicular to the crystal orientation in the Si crystal where cleavage may occur).

[0096] Therefore, the light-emitting device 100 of this embodiment can suppress leakage of sealing gas caused by the destruction of the hermetic seal of the light-emitting element 13 and exposure of the light-emitting element 13 to external air containing moisture.

[0097] Furthermore, as described above, in the light-emitting device 100 of this embodiment, the Si crystal of the second substrate 22... <110> The orientation has an angle of 0° or 90° relative to the extending direction of the gap G. That is, in the substrate structure 11, only the Si crystal of the second substrate 22... <110> The orientation is parallel or perpendicular to the extension direction of gap G.

[0098] When manufacturing the light-emitting device 100, an opening 22O exposing the (111) surface is formed by performing anisotropic etching of the crystal on the second substrate 22. For example, as in the case of the first substrate 21, if the Si crystal of the second substrate 22... <110> If the orientation has an angle different from 0°, 45° and 90° relative to the extension direction of the gap G, the crystal anisotropic etching cannot be performed well and the flat and smooth (111) surface cannot be exposed on the inner surface.

[0099] In the light-emitting device 100 of this embodiment, since only the Si crystal of the second substrate 22... <110> The orientation is parallel or perpendicular to the extension direction of the gap G, so the flat and smooth (111) surface can be exposed on the inner surface forming the opening 22O by anisotropic crystal etching. Therefore, for the light-emitting device 100 of this embodiment, while suppressing the crack from propagating into the first substrate 21, a recessed portion can be formed on the second substrate 22 by anisotropic crystal etching.

[0100] Because the (111) plane of the Si crystal is a very flat and smooth surface, for example, light emitted from the light-emitting element 13 and... Figure 2The ultraviolet light traveling in the left and right directions is not scattered but mirror-reflected on the inner surface of the second substrate 22, thereby improving the efficiency of ultraviolet light incident on the light-transmitting member 15. In other words, the amount of light incident on the light-transmitting member 15 can be increased.

[0101] Therefore, the light-emitting device 100 of this embodiment can improve the light extraction efficiency by making the inner surface of the second substrate 22 a (111) surface to increase the amount of light incident on the light-transmitting member 15.

[0102] Furthermore, in the light-emitting device 100 of this embodiment, the corresponding plurality of through holes 21H belonging to the first through hole group TG1 and the second through hole group TG2 are each formed as a regular triangular lattice pattern. That is, each of the plurality of through electrodes 26 is arranged on a regular triangular lattice point in the central region CA. For example, each of the plurality of through electrodes 26 is formed by a pillar with a diameter of 30 μm, and the distance between the center points of adjacent through electrodes 26 is 60 μm.

[0103] Compared to arranging the through electrodes 26 in, for example, a square lattice pattern, a greater number of through electrodes 26 can be formed in the light-emitting device 100 of this embodiment. Therefore, compared to arranging the through electrodes 26 in a square lattice pattern such as a square lattice, more heat generated when the light-emitting element 13 is driven can be released to the outside.

[0104] In the light-emitting device 100 of this embodiment, only the Si crystal of the first substrate 21 in the substrate structure 11... <110> The orientation has an angle different from 0°, 45°, and 90° relative to the extension direction of the gap G, but this should not be interpreted as restrictive. For example, the Si crystal of the second substrate 22 <110> The orientation can also have an angle different from 0° or 90° relative to the extension direction of the gap G. In this case, the opening 22O of the second substrate 22 is formed by, for example, a dry etching method.

[0105] Furthermore, in the light-emitting device 100 of this embodiment, the Si crystal of the first substrate 21 in the substrate structure 11... <110> The orientation has an angle different from 0°, 45°, and 90° relative to the extension direction of the interstitial G. However, only Si crystal is required. <110> The orientation only needs to have at least one angle different from 0° and 90° relative to the extension direction of the interstitial G, and for example, Si crystals. <110> The orientation can be at a 45° angle relative to the extending direction of the gap G. That is, for example, in the first substrate 21, the Si crystal... <110> The orientation and the extension direction of the gap G can have angles of 0° and 90°.

[0106] Here, the surface free energy (J / m²) of each crystal plane of Si2 For example, the surface free energy of the (111) plane is 1.15, the (110) plane is 1.41, and the (100) plane is 1.99. The smaller the surface free energy of the crystal plane, the easier it is for cleavage to occur in Si crystal. Therefore, cleavage is easier to occur with respect to surface free energy. <111> orientation, <110> Orientation and <100> The order of orientation occurs. Therefore, by at least making the ratio <100> Orientation makes cleavage more likely <110> The orientation is offset from the extension direction of the gap G, which can suppress the occurrence of cleavage due to crack propagation.

[0107] In Si crystal planes with (100) orientation, only <100> Orientation and <110> These two orientations lie within the plane. Because... <111> The orientation is at 54.7° diagonally when viewed from the (100) plane, so it is considered to be not closely related to the crack phenomenon on the surface.

[0108] Furthermore, in the light-emitting device 100 of this embodiment, the case where the upper surface of the first substrate 21 is the (100) plane of a Si crystal has been described, but this should not be interpreted as limiting. For example, the upper surface of the first substrate 21 may be the (111) plane of a Si crystal.

[0109] In the light-emitting device 100 of this embodiment, a plurality of through holes 21H are formed in each of the first through hole group TG1 and the second through hole group TG2 in the first substrate 21, but this should not be construed as limiting. The number of through holes 21H in each through hole group can be one. In this case, a larger diameter can be set for a single through hole 21H.

[0110] [verify]

[0111] Here, the verification performed on the light-emitting device 100 of this embodiment and the results of the verification are described. In this verification, a square silicon substrate with a side length of 2.6 mm was prepared to simulate the first substrate 21. An insulating film made of SiO2 with a thickness of 0.3 μm was formed on the upper and lower surfaces of the prepared silicon substrate. Two Cu electrodes (each with a thickness of 25 μm) were formed only on the lower surface side of the silicon substrate to be separated from each other, that is, to form the gap G in the light-emitting device 100. The product prepared as described above was used as a sample.

[0112] In this verification, the Si crystal included <110> A sample of a silicon substrate with an orientation at a 10° angle relative to the extension direction of the gap G was used as the first sample. This included a silicon substrate containing Si crystals. <110> A sample of a silicon substrate oriented parallel to the extension direction of gap G was used as a second sample.

[0113] In addition, including the Si crystal <110> The orientation has a 45° angle relative to the extension direction of the interstitial G (i.e., its Si crystal has a 45° angle relative to the extension direction of the interstitial G). <100> A sample of a silicon substrate (oriented parallel to the extension direction of gap G) was used as the third sample. That is, among the first, second, and third samples, only the Si crystal... <110> Different orientations.

[0114] In this verification, 27 samples were prepared for each of the first, second, and third samples described above. Each sample was placed on a hot plate heated to 260°C for 2 minutes. The samples were then placed on a heat sink and rapidly cooled, and then examined using an optical microscope to check for the presence or absence of cracks in the silicon substrate.

[0115] Table 1 shows the number of samples with cracks in the first, second, and third samples during this verification. According to the results shown in Table 1, no cracks were confirmed in all 27 samples of the first sample. On the other hand, in the second sample (Comparative Example 1), cracks were confirmed in 15 out of 27 samples, and in the third sample (Comparative Example 2), cracks were confirmed in two out of 27 samples.

[0116] [Table 1]

[0117]

[0118] The above results indicate that by using a configuration that makes the Si crystal... <110> Silicon substrates with orientations at angles different from 0°, 45°, and 90° relative to the extension direction of gap G do not exhibit cracks.

[0119] Additionally, it shows the relationship with Si crystal. <110> Compared to the case where the orientation is parallel or perpendicular to the extension direction of the interstitial space G, even the Si crystal... <110> The orientation having a 45° angle relative to the extension direction of the gap G can also suppress the occurrence of cracks.

[0120] Therefore, for example, in the light-emitting device 100, by using a method configured to cause the Si crystal to... <110> The first substrate 21, which has an orientation angle different from 0°, 45° and 90° relative to the extension direction of the gap G, can suppress the occurrence of cracks in the first substrate 21 when the light-emitting element 13 is mounted.

[0121] [Manufacturing method of light-emitting device]

[0122] Next, use Figures 2 to 14 This paper describes a method for manufacturing a light-emitting device 100 according to Embodiment 1 of this application. Figure 3 and Figures 6 to 14 Each of these is a cross-sectional view of the light-emitting device 100 at one step during manufacturing. Figure 3 and Figures 6 to 14 Each of the middle, similar to Figure 2 along Figure 1 The cross-sectional view shown by line 2-2 is for illustration.

[0123] In this embodiment, the light-emitting device 100 is manufactured in the form of a wafer-level package (WLP), in which multiple light-emitting devices 100 are integrally manufactured on a wafer-like substrate structure 11 and then individually diced after manufacturing. Figures 3 to 14 In each of them, a dividing line CL is shown as a dividing line used to individualize the light-emitting device 100 by cutting.

[0124] First, such as Figure 3 As shown, a substrate structure 11 is fabricated in which a first substrate 21 made of single-crystal Si and a second substrate 22 made of single-crystal Si are bonded together. A first insulating film 24, which is a buried oxide film made of SiO2, is formed on the upper surface of the first substrate 21 (step S1: substrate structure fabrication step). Although a SiO2 film, which is a natural oxide film, is formed on the lower surface of the first substrate 21 and the upper surface of the second substrate 22, the natural oxide film is not illustrated in this description.

[0125] Here, refer to Figure 4 and Figure 5 , described Figure 3 The substrate structure 11 shown. Figure 4 This is a top view of the silicon wafer 21Wa, which serves as the substrate of the first substrate 21, as viewed from above. Figure 5 This is a top view of the silicon wafer 22Wa, which serves as the substrate for the second substrate 22.

[0126] The substrate structure 11 in the light-emitting device 100 of this embodiment is manufactured by bonding silicon wafers 21Wa and 22Wa together and then cutting them in a final step. Figure 4 As shown, silicon wafer 21Wa is configured such that the Si crystal... <110> The orientation has an angle θ relative to the orientation plane OF1 set on the silicon wafer 21Wa, and the angle θ is different from 0°, 45° and 90°.

[0127] Therefore, when electrodes are formed along the dividing line CL on the upper or lower surface of the silicon wafer 21Wa in the steps described later, the Si crystal... <110> The angle between the orientation and the extension direction of the aforementioned gap G is at an angle θ.

[0128] like Figure 5As shown, silicon wafer 22Wa is configured such that the Si crystal... <110> The orientation is parallel to the orientation plane OF2 disposed on the silicon wafer 22Wa. Therefore, when electrodes are formed along the dividing line CL on the upper or lower surface of the silicon wafer 21Wa in the steps described later, the Si crystal… <110> The orientation is parallel to the extension direction of the aforementioned gap G.

[0129] Considering the precision tolerance when forming the alignment plane OF1 on the silicon wafer 21Wa, the alignment plane OF1 in the aforementioned silicon wafer 21Wa and <110> The angle θ formed between the orientations is preferably 2.5° to 42.5° or 47.5° to 87.5°.

[0130] Next, as Figure 6 As shown, etching is performed from the lower surface side of the first substrate 21 to form a plurality of columnar holes 21HA, which become a plurality of through holes 21H in the steps described later (step S2: hole formation step). Each of the plurality of holes 21HA is formed, for example, using deep reactive ion etching (DRIE) via a Bosch process. In the formation of the plurality of holes 21HA, the first insulating film 24 acts as an etch stop layer.

[0131] Although not illustrated, the step includes applying a photoresist to the lower surface of the first substrate 21 and removing the photoresist after etching to form a plurality of holes 21HA.

[0132] Next, as Figure 7 As shown, a thermal oxide film 34A made of SiO2 is formed from the lower surface of the first substrate 21 to the inner surface of each of the holes 21HA and above the upper surface of the second substrate 22 by performing a wet thermal oxidation process at 1100°C in a water vapor atmosphere for 7 hours or longer (step S3: thermal oxide film formation step). When etching is performed in the next step, the thermal oxide film 34A formed in this step forms an etch stop layer on the inner surface of the holes 21HA.

[0133] Next, as Figure 8 As shown, a wet etching process using an aqueous tetramethylammonium hydroxide (TMAH) solution is performed until the first insulating film 24 formed on the upper surface of the first substrate 21 is exposed from the upper surface of the second substrate 22 to form an opening 22O (step S4: opening formation process). That is, a recess is formed in the substrate structure 11. In the formation of the opening 22O, the first insulating film 24 acts as an etch stop layer.

[0134] In this step, as described above, so-called anisotropic etching is performed using the difference in etching rate depending on the crystal plane of Si. Therefore, as etching proceeds, the (111) plane appears on the inner surface of the second substrate 22. The (111) plane is less likely to be etched than the (100) plane, that is, it has a slower etching rate.

[0135] Next, as Figure 9 As shown, the thermal oxide film 34A and the first insulating film 24 exposed in the central region CA on the upper surface of the first substrate 21 are removed using buffered hydrofluoric acid (BHF) (step S5: oxide film removal step). Therefore, removing the first insulating film 24 from the central region CA exposed on the upper surface of the first substrate 21 allows each of the plurality of holes 21HA formed in step S2 to communicate with the central region CA and form a plurality of through holes 21H. Furthermore, through this step, the first insulating film 24 remains only in the peripheral region surrounding the central region CA on the upper surface of the first substrate 21.

[0136] Next, as Figure 10 As shown, the second insulating film 25 is formed in the central region CA on the upper surface of the first substrate 21, on the inner surface of each of the through holes 21H, and on the lower surface of the first substrate 21. A thermal oxide film 34 is formed on the upper surface and inner surface of the second substrate 22 (step S6: thermal oxide film formation step). For example, the second insulating film 25 and the thermal oxide film 34 are formed by wet heat oxidation at 1100°C for 7 hours or longer in a water vapor atmosphere while masking the central region CA on the upper surface of the first substrate 21 and the lower surface of the first substrate 21.

[0137] Next, as Figure 11 As shown, each of the plurality of through-holes 21H is formed inside each of the plurality of through-holes 21H, and each of the plurality of through-holes 26 is formed of Cu (step S7: through-hole electrode formation step). For example, the lower surface of the first substrate 21 is masked by forming a seed layer (not shown) on the lower surface of the first substrate 21 and a portion of the inner surface of the through-hole 21H in which Ti and Cu are sequentially stacked, and then Cu is filled into the seed layer from the lower surface to the upper surface of the first substrate 21 by electrolytic plating to form the through-hole 26.

[0138] Next, as Figure 12 As shown, a first upper surface electrode 31 and a second upper surface electrode 32 are formed in the central region CA on the upper surface of the first substrate 21. A first lower surface electrode 28 and a second lower surface electrode 29 are formed on the lower surface of the first substrate 21. An AuSn layer 46A, which serves as the substrate material for the bonding layer 46, is formed on the first upper surface electrode 31 and the second upper surface electrode 32 (step S8: electrode formation step).

[0139] In step S8, a seed layer (not shown) having sequentially stacked Ti and Cu layers is formed over the central region CA on the upper surface of the first substrate 21 by sputtering deposition. After masking the portion excluding the corresponding upper surface electrode with a photoresist, Cu / Ni layers and AuSn layers 46A are respectively stacked by electroplating. Then, by removing the photoresist used for masking and etching the remaining seed layer, the first upper surface electrode 31, the second upper surface electrode 32, and the AuSn layer 46A are formed.

[0140] Furthermore, in step S8, the first lower surface electrode 28 and the second lower surface electrode 29 are formed by masking the portion of the lower surface of the first substrate 21 except for the corresponding lower surface electrode with a photoresist and then electroplating Ni and Au sequentially.

[0141] Next, as Figure 13 As shown, a light-emitting element 13 is mounted in the central region CA on the upper surface of the first substrate 21 (step S9: element mounting step). For example, the light-emitting element 13 is mounted by heating the substrate structure 11 on which the light-emitting element 13 is placed for 30 seconds at 340°C under a nitrogen (N2) atmosphere and performing eutectic bonding on the Au layer formed on the surfaces of the n electrode 43, the p electrode 44, and the AuSn layer 46A.

[0142] Next, as Figure 14 As shown, the light-transmitting member 15 is bonded to the upper surface of the second substrate 22 (step S10: light-transmitting member bonding step). In this step, a glass bonding layer 48 is pre-formed on the light-transmitting member 15, and the light-transmitting member 15 on which the glass bonding layer 48 is formed is arranged to cover the opening 22O.

[0143] In this step, the glass bonding layer 48 is applied above the lower surface of the light-transmitting member 15 at a position corresponding to the upper surface of the second substrate 22, so as to surround the opening 22O and have a size that does not overlap with the dividing line CL of the substrate structure 11.

[0144] Subsequently, the glass bonding layer 48 is irradiated by a near-infrared laser beam passing through the light-transmitting member 15 placed on the upper surface of the second substrate 22 under an N2 atmosphere, thereby locally heating and melting the glass bonding layer 48, thus bonding the light-transmitting member 15 to the upper surface of the second substrate 22. At this time, the molten glass bonding layer 48 and the thermal oxide film 34 formed on the upper surface of the second substrate 22 interdiffusion to form an interdiffusion layer (not shown). Therefore, the opening 22O is filled with N2 as an inert gas, and an airtight space SP is formed.

[0145] A laser beam is emitted along the shape of the upper surface of the second substrate 22 and is emitted onto the glass bonding layer 48. The laser scanning time is approximately 2 to 3 seconds for each light-emitting device 100. Therefore, in each light-emitting device 100, the glass bonding layer 48 is locally heated by the laser for a short period of time. This prevents the bonding layer made of AuSn used to bond the light-emitting element 13 from remelting due to overheating.

[0146] In conventional light-emitting devices, a hermetic seal is achieved through a double bonding process using eutectic bonding with AuSn. This double bonding involves bonding the light-emitting device itself and bonding the light-transmitting component to the AlN substrate. In this case, during the second AuSn eutectic bonding process of bonding the light-transmitting component, there is a possibility that the bonding layer 46 bonding the light-emitting element may remelt, leading to manufacturing defects such as misalignment of the light-emitting element placement.

[0147] In the manufacturing method of the light-emitting device 100 in this embodiment, as described above, a hermetically sealed seal is achieved by locally heating the glass bonding layer 48 with a laser for a short period of time. Therefore, remelting of the bonding layer 46 that bonds the light-emitting element 13 can be avoided, thereby suppressing manufacturing defects such as misalignment of the light-emitting element placement position.

[0148] Finally, the substrate structure 11, which is joined with the light-transmitting member 15, is placed in a dicing machine, and the light-transmitting member 15 and the substrate structure 11 are cut along the dividing line CL to individualize the light-emitting device 100 (step S11: individualization step). Through the above steps, a light-emitting device 100 can be obtained as shown above. Figure 2 The light-emitting device 100 shown.

[0149] As described above, the light-emitting device 100 of this embodiment can be manufactured as a wafer-level package in which the light-emitting device 100 is formed in a lattice pattern on a silicon wafer. Conventionally, there are disadvantages in cycle time and cost during manufacturing because a single substrate made of AlN needs to be used and the substrates are hermetically sealed one by one.

[0150] In the manufacturing method of the light-emitting device 100 of this embodiment, multiple light-emitting devices 100 can be manufactured at once by placing the substrate structure 11 with the light-transmitting member 15 attached in a cutting machine and cutting it. Therefore, cycle time and cost can be reduced during manufacturing.

[0151] It should be understood that the foregoing description and drawings currently illustrate preferred embodiments of the invention. Of course, various modifications, additions, and alternative designs will become apparent to those skilled in the art based on the foregoing teachings without departing from the spirit and scope of the disclosed invention. Therefore, it should be understood that the invention is not limited to the disclosed examples but can be practiced within the full scope of the appended claims. This application is based on and claims priority to Japanese Patent Application No. 2024-83302, filed May 22, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A light-emitting device, the light-emitting device comprising: A substrate structure comprising a first substrate made of monocrystalline silicon and a second substrate made of monocrystalline silicon, the first substrate comprising a thermal oxide film formed on an upper surface and a lower surface of the first substrate, the second substrate being bonded to the upper surface of the first substrate and having an opening exposing a region on the upper surface of the first substrate, the first substrate having a first via group and a second via group, the first via group comprising one or more vias penetrating from a first portion region of the first region to a lower surface of the first substrate, the second via group comprising one or more vias penetrating from a second portion region to a lower surface of the first substrate, the second portion region being arranged in the first region to form a gap extending in one direction relative to the first portion region. A first upper surface electrode is formed on the first via group in the region; A second upper surface electrode is formed on the second via group in the region to be opposite to the first upper surface electrode; A light-emitting element, the light-emitting element being disposed on the one region across the first upper surface electrode and the second upper surface electrode; The first lower surface electrode is formed on the lower surface of the first substrate on the first via group; The second lower surface electrode is formed on the lower surface of the first substrate on the second via group to be opposite to the first lower surface electrode; as well as A light-transmitting member is formed on the upper surface of the second substrate and seals the space including the opening. The light-transmitting member is light-transmitting. In a plan view of the substrate structure viewed from above, the corresponding silicon crystals of the first substrate and the second substrate are shown. <110> Their orientations are different.

2. The light-emitting device according to claim 1, wherein, In the plan view, the silicon crystal of the first substrate <110> The orientation has an angle different from 0° and 90° relative to the said direction, and In the plan view, the silicon crystal of the second substrate <110> The orientation has an angle of 0° or 90° relative to the said direction.

3. The light-emitting device according to claim 2, wherein, In the plan view, the silicon crystal of the first substrate <110> The orientation has an angle different from 45° relative to the stated direction.

4. The light-emitting device according to claim 1, wherein, The upper surface of the first substrate is the (100) surface or (111) surface of the silicon crystal.

5. The light-emitting device according to claim 1, wherein, The second substrate has the thermally oxidized film formed on the upper surface of the second substrate, and The light-transmitting member is bonded to the upper surface of the second substrate via the thermal oxide film and a glass bonding layer made of glass material disposed on the thermal oxide film.

6. The light-emitting device according to claim 1, wherein, The inner surface of the second substrate forming the opening is the (111) face of the silicon crystal.

7. The light-emitting device according to claim 1, wherein, The one or corresponding plurality of through holes belonging to the first through hole group and the second through hole group are formed in a triangular lattice pattern.

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