Array substrate, display device, method for operating pixel driving circuit and pixel driving circuit

Abstract

An array substrate is provided. The array substrate comprises a pixel driving circuit. The pixel driving circuit includes: a third node connection line; and an auxiliary third node connection line. And the orthographic projection of the auxiliary third node connecting line on the substrate is at least partially overlapped with the orthographic projection of the corresponding first light-emitting control signal line on the substrate. The orthographic projection of the third node connecting line on the substrate is not overlapped with the orthographic projection of the corresponding first light-emitting control signal line on the substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate, a display device, a method for operating a pixel driving circuit, and a pixel driving circuit. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate including a plurality of pixel driving circuits arranged in an array, the array including a plurality of rows and a plurality of columns; wherein, the pixel driving circuit includes: a third node connection line; an auxiliary third node connection line; a driving transistor; an auxiliary driving transistor; a compensation transistor; an auxiliary compensation transistor; a second light-emitting control transistor; an auxiliary second light-emitting control transistor; a second reset transistor; and an auxiliary second reset transistor; wherein, the third node connection line is connected to the second electrode of the second reset transistor and the first electrode of the compensation transistor, and is also connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor; the auxiliary third node connection line is connected to the second electrode of the auxiliary second reset transistor and the second light-emitting control transistor; and the auxiliary third node connection line is connected to the second electrode of the auxiliary second reset transistor and the second light-emitting control transistor. The auxiliary compensation transistor has a first electrode and is connected to the second electrode of the auxiliary driving transistor and the first electrode of the auxiliary second light-emitting control transistor; the orthographic projection of the auxiliary third node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate; and the orthographic projection of the third node connection line on the substrate does not overlap with the orthographic projection of the corresponding first light-emitting control signal line on the substrate; wherein the corresponding first light-emitting control signal line extends along a first direction; the third node connection line and the auxiliary third node connection line extend along a second direction; the first direction is the row direction of the array; the second direction is the column direction of the array; and the first direction and the second direction intersect each other.

[0004] Optionally, the pixel driving circuit further includes a first light-emitting control transistor; wherein the gates of the first light-emitting control transistor and the second light-emitting control transistor are connected to the corresponding first light-emitting control signal line; and the gate of the auxiliary second light-emitting control transistor is connected to the corresponding second light-emitting control signal line.

[0005] Optionally, the orthographic projection of the auxiliary third node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding third light emission control signal line on the substrate.

[0006] Optionally, the pixel driving circuit further includes a first light-emitting control transistor; wherein the gate of the second light-emitting control transistor is connected to the corresponding first light-emitting control signal line; the gate of the first light-emitting control transistor is connected to the corresponding third light-emitting control signal line; and the gate of the auxiliary second light-emitting control transistor is connected to the corresponding second light-emitting control signal line.

[0007] Optionally, the pixel driving circuit further includes: a first light-emitting control transistor; a first node connection line; an auxiliary first node connection line; a voltage connection pad; a storage capacitor including a first capacitor electrode and a second capacitor electrode; and an auxiliary storage capacitor including an auxiliary first capacitor electrode and an auxiliary second capacitor electrode; wherein the first node connection line is connected to the first capacitor electrode and to the second electrode of the compensation transistor; the auxiliary first node connection line is connected to the auxiliary first capacitor electrode and to the second electrode of the auxiliary compensation transistor; the voltage connection pad is connected to the first electrode of the first light-emitting control transistor; a corresponding first voltage supply line is connected to the voltage connection pad; and a corresponding second voltage supply line is connected to the voltage connection pad; the corresponding first voltage supply line and the corresponding second voltage supply line extend along the second direction.

[0008] Optionally, the combination of the first node connection line, the auxiliary first node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, and the auxiliary second capacitor electrode has substantially mirror symmetry with respect to a mirror surface that intersects the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

[0009] Optionally, the array substrate further includes corresponding data lines configured to provide data signals to the pixel driving circuit; wherein the pixel driving circuit further includes: a data writing transistor; and a data connection pad that connects the corresponding data line to the data writing transistor; wherein the combination of the first node connection line, the auxiliary first node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, the auxiliary second capacitor electrode, the data connection pad, the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding data line has substantially mirror symmetry with respect to a mirror surface that intersects the corresponding data line and the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

[0010] Optionally, the pixel driving circuit further includes a second node connection line, which is connected to the first electrode of the driving transistor and the auxiliary driving transistor, and to the second electrode of the first light-emitting control transistor.

[0011] Optionally, the orthographic projection of the second node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate, and at least partially overlaps with the orthographic projection of the corresponding third light-emitting control signal line on the substrate.

[0012] Optionally, the combination of the first node connection line, the auxiliary first node connection line, the second node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, and the auxiliary second capacitor electrode has substantially mirror symmetry with respect to a mirror surface that intersects the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

[0013] Optionally, the array substrate further includes corresponding data lines configured to provide data signals to the pixel driving circuit; wherein the pixel driving circuit further includes: a data writing transistor; and a data connection pad that connects the corresponding data line to the data writing transistor; wherein the combination of the first node connection line, the auxiliary first node connection line, the second node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, the auxiliary second capacitor electrode, the data connection pad, the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding data line has substantially mirror symmetry with respect to a mirror surface that intersects the corresponding data line, the second node connection line, and the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

[0014] Optionally, the pixel driving circuit further includes: a first reset transistor; and a fourth node connection line connected to the second electrode of the second light-emitting control transistor, connected to the second electrode of the first reset transistor, and connected to the second electrode of the auxiliary second light-emitting control transistor.

[0015] Optionally, the fourth node connection line is asymmetrical about a mirror surface that intersects the corresponding data line and the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

[0016] In another aspect, this disclosure provides a display device including the array substrate described herein and one or more integrated circuits connected to the array substrate.

[0017] In another aspect, this disclosure provides a method for operating a pixel driving circuit, wherein the pixel driving circuit includes: a driving transistor; an auxiliary driving transistor; a first light-emitting control transistor; a second light-emitting control transistor; and an auxiliary second light-emitting control transistor; wherein a first electrode of the driving transistor and the auxiliary driving transistor is connected to a second electrode of the first light-emitting control transistor; a second electrode of the driving transistor is connected to a first electrode of the second light-emitting control transistor; a second electrode of the auxiliary driving transistor is connected to a first electrode of the auxiliary second light-emitting control transistor; a gate of the second light-emitting control transistor is connected to a corresponding first light-emitting control signal line; a gate of the auxiliary second light-emitting control transistor is connected to a corresponding second light-emitting control signal line; and the second electrodes of the second light-emitting control transistor and the auxiliary second light-emitting control transistor are connected to each other; wherein the method includes providing different light-emitting control signals to the gate of the second light-emitting control transistor and the gate of the auxiliary second light-emitting control transistor respectively in at least one operating mode.

[0018] Optionally, the method includes, in a first mode: providing an on control signal to the gates of the first light-emitting control transistor and the second light-emitting control transistor during a light-emitting sub-phase of a frame image; and providing an off control signal to the gate of the auxiliary second light-emitting control transistor during the light-emitting sub-phase.

[0019] Optionally, the method includes, in a second mode: providing a turn-on control signal to the gates of the first light-emitting control transistor and the second light-emitting control transistor during a light-emitting sub-phase of a frame image; and providing a turn-on control signal to the gate of the auxiliary second light-emitting control transistor during the light-emitting sub-phase.

[0020] Optionally, the method includes, in a third mode: providing an on control signal to the gate of the second light-emitting control transistor during a light-emitting sub-phase of a frame image; providing an off control signal to the gate of the auxiliary second light-emitting control transistor during the light-emitting sub-phase; and providing an on control signal to the gate of the first light-emitting control transistor during the light-emitting sub-phase.

[0021] Optionally, the method includes, in a fourth mode: providing a cutoff control signal to the gate of the second light-emitting control transistor during a light-emitting sub-phase of a frame image; providing an on-control signal to the gate of the auxiliary second light-emitting control transistor during the light-emitting sub-phase; and providing an on-control signal to the gate of the first light-emitting control transistor during the light-emitting sub-phase.

[0022] In another aspect, this disclosure provides a pixel driving circuit, comprising: a driving transistor; an auxiliary driving transistor; a first light-emitting control transistor; a second light-emitting control transistor; and an auxiliary second light-emitting control transistor; wherein the first electrodes of the driving transistor and the auxiliary driving transistor are connected to the second electrode of the first light-emitting control transistor; the second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor; the second electrode of the auxiliary driving transistor is connected to the first electrode of the auxiliary second light-emitting control transistor; the gate of the second light-emitting control transistor is connected to a corresponding first light-emitting control signal line; the gate of the auxiliary second light-emitting control transistor is connected to a corresponding second light-emitting control signal line; and the second electrodes of the second light-emitting control transistor and the auxiliary second light-emitting control transistor are connected to each other. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit in a first mode according to some embodiments of the present disclosure.

[0027] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit in a second mode according to some embodiments of the present disclosure.

[0028] Figure 3AThis is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0029] Figure 3B yes Figure 3A The diagram shows the arrangement of pixel driving circuits in the array substrate.

[0030] Figure 3C It is shown Figure 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0031] Figure 3D It is shown Figure 3A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate.

[0032] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate shown.

[0033] Figure 3F It is shown Figure 3A A schematic diagram of a via extending through an interlayer dielectric layer in an array substrate shown.

[0034] Figure 3G It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0035] Figure 3H It is shown Figure 3A A schematic diagram of a via extending through a passivation layer in an array substrate shown.

[0036] Figure 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0037] Figure 3J It is shown Figure 3A A schematic diagram of a via extending through a planarization layer in an array substrate shown.

[0038] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0039] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0040] Figure 4C It is along Figure 3A A cross-sectional view of the C-C' line in the diagram.

[0041] Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram.

[0042] Figure 5A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0043] Figure 5B This is a timing diagram illustrating the operation of a pixel driving circuit in a third mode according to some embodiments of the present disclosure.

[0044] Figure 5C This is a timing diagram illustrating the operation of a pixel driving circuit in a fourth mode according to some embodiments of the present disclosure.

[0045] Figure 6A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0046] Figure 6B yes Figure 6A The diagram shows the arrangement of pixel driving circuits in the array substrate.

[0047] Figure 6C It is shown Figure 6A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0048] Figure 6D It is shown Figure 6A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate.

[0049] Figure 6E It is shown Figure 6A A schematic diagram of the structure of the second gate metal layer in the array substrate shown.

[0050] Figure 6F It is shown Figure 6A A schematic diagram of a via extending through an interlayer dielectric layer in an array substrate shown.

[0051] Figure 6G It is shown Figure 6A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0052] Figure 6H It is shown Figure 6A A schematic diagram of a via extending through a passivation layer in an array substrate shown.

[0053] Figure 6I It is shown Figure 6A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0054] Figure 6J It is shown Figure 6A A schematic diagram of a via extending through a planarization layer in an array substrate shown.

[0055] Figure 7A It is along Figure 6A A cross-sectional view of the E-E' line in the diagram.

[0056] Figure 7B It is along Figure 6A A cross-sectional view of line F-F' in the diagram.

[0057] Figure 7C It is along Figure 6A A cross-sectional view of the G-G' line in the diagram.

[0058] Figure 7D It is along Figure 6A A cross-sectional view of the H-H' line in the diagram. Detailed Implementation

[0059] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0060] In the field of display technology, conventional pixel circuits present critical problems, particularly when operating under high brightness conditions. These circuits are typically based on a single DTFT (dual thin-film transistor) design, where the brightness of each sub-pixel is proportional to the current flowing through the DTFT within the pixel circuit. To increase the DTFT current and thus improve brightness, techniques such as increasing the Vdata (data voltage) range or adjusting the aspect ratio (W / L) of the DTFT are employed. However, these methods significantly increase power consumption and heat generation in the display assembly. Furthermore, the reliance on a single DTFT makes the system more susceptible to damage, leading to potential display anomalies.

[0061] Therefore, this disclosure particularly provides an array substrate, a display device, a method for operating pixel driving circuits, and pixel driving circuits that substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in an array, the array comprising a plurality of rows and a plurality of columns. Optionally, the pixel driving circuit includes a third node connection line; an auxiliary third node connection line; a driving transistor; an auxiliary driving transistor; a compensation transistor; an auxiliary compensation transistor; a second light-emitting control transistor; an auxiliary second light-emitting control transistor; a second reset transistor; and an auxiliary second reset transistor. Optionally, the third node connection line is connected to the second electrode of the second reset transistor and the first electrode of the compensation transistor, and is also connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor. Optionally, the auxiliary third node connection line is connected to the second electrode of the auxiliary second reset transistor and the first electrode of the auxiliary compensation transistor, and is also connected to the second electrode of the auxiliary driving transistor and the first electrode of the auxiliary second light-emitting control transistor. Optionally, the orthographic projection of the auxiliary third node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate. Optionally, the orthographic projection of the third node connection line on the substrate does not overlap with the orthographic projection of the corresponding first light-emitting control signal line on the substrate. Optionally, the corresponding first light-emitting control signal line extends along a first direction; the third node connection line and the auxiliary third node connection line extend along a second direction; the first direction is the row direction of the array; the second direction is the column direction of the array; and the first direction and the second direction intersect each other.

[0062] Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T1C, 8T2C, 9T1C, 9T2C, 10T1C, 10T2C, 11T1C, 11T2C, 12T1C, 12T2C, 13T1C, 13T2C, 14T1C, 14T2C, 15T1C, 15T2C, 16T1C, and 16T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is an 11T2C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0063] Figure 1This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple first gate lines GL1, multiple second gate lines GL2, multiple data lines DL, and multiple voltage supply lines (e.g., a high-voltage supply line Vdd and a low-voltage supply line Vss). Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via the corresponding high-voltage supply line among the multiple voltage supply lines Vdd; a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via the low-voltage supply line. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0064] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes a first sub-circuit SC1 and a second sub-circuit SC2. In some embodiments, the first sub-circuit SC1 and the second sub-circuit SC2 are electrically connected to the light-emitting element LE and are configured to provide driving current to the light-emitting element LE individually or in combination. In some embodiments, the first sub-circuit SC1 includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding first gate line GL1 of a plurality of first gate lines, a first electrode connected to a corresponding data line DL of a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second gate line GL2 of a plurality of second gate lines, a first electrode connected to the second electrode of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding first light-emitting control signal line em1 of a plurality of first light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1. The second electrode; the fourth transistor T4, having a gate connected to a corresponding first light-emitting control signal line em1 among a plurality of first light-emitting control signal lines, a first electrode connected to a second electrode of the driving transistor Td and a first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; the first reset transistor Tr1, having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; and the second reset transistor Tr2, having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to the first electrode of the second transistor T2 and the second electrode of the driving transistor Td. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0065] In some embodiments, the second sub-circuit SC2 includes an auxiliary driving transistor Td' having a first electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; an auxiliary storage capacitor Cst' having an auxiliary first capacitor electrode Ce1' and an auxiliary second capacitor electrode Ce2'; an auxiliary second transistor T2' having a gate connected to a corresponding second gate line GL2 of a plurality of second gate lines, a first electrode connected to the second electrode of the auxiliary driving transistor Td', and a second electrode connected to the auxiliary first capacitor electrode Ce1' of the auxiliary storage capacitor Cst' and the gate of the auxiliary driving transistor Td'; and an auxiliary fourth transistor T 4' has a gate connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, a first electrode connected to a second electrode of an auxiliary driving transistor Td' and a first electrode of an auxiliary second transistor T2', and a second electrode connected to the anode of the light-emitting element LE; and an auxiliary second reset transistor Tr2' has a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a first electrode of an auxiliary second transistor T2' and a second electrode of an auxiliary driving transistor Td'. An auxiliary second capacitor electrode Ce2' is connected to a corresponding voltage supply line and the first electrode of a third transistor T3.

[0066] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0067] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the auxiliary fourth transistor T4', the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0068] The pixel driving circuit also includes an auxiliary first node N1' and an auxiliary third node N3'. The auxiliary first node N1' is connected to the gate of the auxiliary driving transistor Td', the auxiliary first capacitor electrode Ce1', and the second electrode of the auxiliary second transistor T2'. The auxiliary third node N3' is connected to the second electrode of the auxiliary driving transistor Td', the first electrode of the auxiliary second transistor T2', the first electrode of the auxiliary fourth transistor T4', and the second electrode of the auxiliary second reset transistor Tr2'.

[0069] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, S3 represents a corresponding third sub-pixel, and S4 represents a corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, C3 represents a corresponding third sub-pixel of a third color, and C4 represents a corresponding fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, the corresponding third sub-pixel is a blue sub-pixel, and the corresponding fourth sub-pixel is a green sub-pixel.

[0070] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, an auxiliary second transistor T2', an auxiliary fourth transistor T4', an auxiliary second reset transistor Tr2', and an auxiliary driving transistor Td'.

[0071] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Reference Figure 2AThe transistor is a p-type transistor, such as a polysilicon transistor. For a p-type transistor, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For an n-type transistor, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0072] In some embodiments, the pixel driving circuit includes one or more driving transistors (e.g., driving transistor Td and auxiliary driving transistor Td'), a data writing transistor (e.g., first transistor T1), one or more compensation transistors (e.g., second transistor T2 and auxiliary second transistor T2'), a plurality of light-emitting control transistors (e.g., third transistor T3, fourth transistor T4 and auxiliary fourth transistor T4'), and a plurality of reset transistors (e.g., first reset transistor Tr1, second reset transistor Tr2 and auxiliary second reset transistor Tr2').

[0073] In some embodiments, multiple light-emitting control transistors (e.g., a fourth transistor T4 and an auxiliary fourth transistor T4') are controlled by different light-emitting control signal lines. In some embodiments, the gates of the multiple light-emitting control transistors (e.g., the fourth transistor T4 and the auxiliary fourth transistor T4') are respectively connected to different light-emitting control signal lines. In some embodiments, the gate of the fourth transistor T4 is connected to a corresponding first light-emitting control signal line em1 among a plurality of first light-emitting control signal lines, and the gate of the auxiliary fourth transistor T4' is connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines.

[0074] In some embodiments, the second electrodes of a plurality of light-emitting control transistors (e.g., a fourth transistor T4 and an auxiliary fourth transistor T4') are connected to the anode of the light-emitting element LE.

[0075] In some embodiments, the first electrodes of a plurality of light-emitting control transistors (e.g., a fourth transistor T4 and an auxiliary fourth transistor T4') are connected to different driving transistors. In some embodiments, the first electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor Td, and the first electrode of the auxiliary fourth transistor T4' is connected to the second electrode of the auxiliary driving transistor Td'.

[0076] The pixel driving circuit according to this disclosure can be operated in various alternative implementations.

[0077] In some embodiments, the pixel driving circuit operates in a first mode. In some embodiments, in the first mode, only one of a plurality of light-emitting control transistors connected to the anode of the light-emitting element LE is configured to be turned on to allow drive current to flow, while the other light-emitting control transistors connected to the anode of the light-emitting element LE are configured to be turned off. Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit in a first mode according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit in the first mode includes a first sub-stage t1, a second sub-stage t2, a third sub-stage t3, a fourth sub-stage t4, and a fifth sub-stage t5.

[0078] In the first mode, a cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' via a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, thereby cutting off the auxiliary fourth transistor T4'. In the first mode, the second sub-circuit SC2 is configured not to provide drive current to the light-emitting element LE.

[0079] In the first sub-stage t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to turn on the first reset transistor Tr1; allowing the initialization voltage signal from the corresponding first reset signal line Vint1 among a plurality of first reset signal lines to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to the fourth node N4. The anode of the light-emitting element LE is initialized. In the first sub-stage t1, a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via a second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2 and the auxiliary second transistor T2'.

[0080] In the second sub-stage t2, a turn-on reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, to turn on the second reset transistor Tr2 and the auxiliary second reset transistor Tr2'; a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via the corresponding second gate line GL2 among the plurality of second gate lines, to turn on the second transistor T2 and the auxiliary second transistor T2'; thereby allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the second reset transistor Tr2 and the second transistor T2, and sequentially to the first node N1; and allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the auxiliary second reset transistor Tr2' and the auxiliary second transistor T2', and sequentially to the auxiliary first node N1'. The gate of the driving transistor Td is initialized. The gate of the auxiliary driving transistor Td' is initialized. The third node N3 is initialized. The auxiliary third node N3' is initialized.

[0081] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2; and a turn-off control signal is provided to the gate of the second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the second reset transistor Tr2. The second electrode of the driving transistor Td is connected to the first electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the third sub-stage t3, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thereby putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, in the third sub-stage t3, the voltage level at the first node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. In the third sub-stage t3, a high voltage signal is provided on the corresponding first light-emitting control signal line em1 to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the fourth transistor T4 via the corresponding first light-emitting control signal line em1 among the multiple first light-emitting control signal lines to turn off the fourth transistor T4.

[0082] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the auxiliary second transistor T2' through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the auxiliary second transistor T2'; and a cut-off control signal is provided to the gate of the auxiliary second reset transistor Tr2' through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the auxiliary second reset transistor Tr2'. The second electrode of the auxiliary driving transistor Td' is connected to the first electrode of the auxiliary second transistor T2'. The gate of the auxiliary driving transistor Td' is electrically connected to the second electrode of the auxiliary second transistor T2'. Since the auxiliary second transistor T2' is turned on in the third sub-stage t3, the gate of the auxiliary driving transistor Td' is connected to the second electrode and short-circuited, so only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is effective, thereby putting the auxiliary driving transistor Td' in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the auxiliary driving transistor Td', which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the auxiliary driving transistor Td' has the voltage level of the data voltage signal. Since only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is active, in the third sub-stage t3, the voltage level at the auxiliary first node N1' gradually increases to (Vdata + Vth'), where Vdata is the voltage level of the data voltage signal and Vth' is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the auxiliary first capacitor electrode Ce1' and the auxiliary second capacitor electrode Ce2' decreases to a relatively small value, the auxiliary storage capacitor Cst' discharges. In the third sub-stage t3, the corresponding first light-emitting control signal line em1 provides a high voltage signal to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light emission control signal line em2 among the multiple second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0083] In the fourth sub-stage t4, a cutoff control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to cut off the second transistor T2, and to the gate of the auxiliary second transistor T2' to cut off the auxiliary second transistor T2'. A cutoff control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to cut off the first transistor T1. A cutoff reset control signal is provided to the gate of the first reset transistor Tr1 through a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to cut off the first reset transistor Tr1. A cutoff reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines. A cutoff control signal is provided to the gates of the third transistor T3 and the fourth transistor T4 through a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines to cut off the third transistor T3 and the fourth transistor T4. A cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' through a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0084] In the fifth sub-stage t5, the corresponding first light-emitting control signal line em1 among the plurality of first light-emitting control signal lines provides a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the fifth sub-stage t5, the voltage level at the first node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, and the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the third node N3, connected to the second electrode of the driving transistor Td, is equal to the light-emitting voltage of the light-emitting element LE.

[0085] In the fifth sub-stage t5, the cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light-emitting control signal line em2 among the multiple second light-emitting control signal lines, thereby turning off the auxiliary fourth transistor T4'. No drive current is provided from the auxiliary drive transistor Td' to the light-emitting element LE.

[0086] In some embodiments, the pixel driving circuit operates in a second mode. In some embodiments, in the second mode, a plurality of light-emitting control transistors connected to the anode of the light-emitting element LE are configured to be turned on simultaneously to allow drive current to flow. Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit in a second mode according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2CDuring one frame of an image, the operation of the pixel driving circuit in the second mode includes a first sub-stage t1, a second sub-stage t2, a third sub-stage t3, a fourth sub-stage t4, and a fifth sub-stage t5.

[0087] In the second mode, a corresponding second light-emitting control signal line em2 among the plurality of second light-emitting control signal lines is configured to transmit a light-emitting control signal that is substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) synchronized with the light-emitting control signal provided by a corresponding first light-emitting control signal line em1 among the plurality of first light-emitting control signal lines. In the second mode, both the first sub-circuit SC1 and the second sub-circuit SC2 are configured to provide drive current to the light-emitting element LE during the light-emitting sub-phase of a frame of image.

[0088] In the first sub-stage t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to turn on the first reset transistor Tr1; allowing the initialization voltage signal from the corresponding first reset signal line Vint1 among a plurality of first reset signal lines to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to the fourth node N4. The anode of the light-emitting element LE is initialized. In the first sub-stage t1, a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via a corresponding second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2 and the auxiliary second transistor T2'.

[0089] In the second sub-stage t2, a turn-on reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, to turn on the second reset transistor Tr2 and the auxiliary second reset transistor Tr2'; a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via the corresponding second gate line GL2 among the plurality of second gate lines, to turn on the second transistor T2 and the auxiliary second transistor T2'; thereby allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the second reset transistor Tr2 and the second transistor T2, and sequentially to the first node N1; and allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the auxiliary second reset transistor Tr2' and the auxiliary second transistor T2', and sequentially to the auxiliary first node N1'. The gate of the driving transistor Td is initialized. The gate of the auxiliary driving transistor Td' is initialized. The third node N3 is initialized. The auxiliary third node N3' is initialized.

[0090] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2; and a turn-off control signal is provided to the gate of the second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the second reset transistor Tr2. The second electrode of the driving transistor Td is connected to the first electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the third sub-stage t3, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thereby putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The second node N2, connected to the first electrode of the driving transistor Td, has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the third sub-stage t3, the voltage level at the first node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. In the third sub-stage t3, a high voltage signal is provided on the corresponding first light-emitting control signal line em1 to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the fourth transistor T4 via the corresponding first light-emitting control signal line em1 among the multiple first light-emitting control signal lines to turn off the fourth transistor T4.

[0091] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the auxiliary second transistor T2' through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the auxiliary second transistor T2'; and a cut-off control signal is provided to the gate of the auxiliary second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the auxiliary second reset transistor Tr2. The second electrode of the auxiliary driving transistor Td' is connected to the first electrode of the auxiliary second transistor T2'. The gate of the auxiliary driving transistor Td' is electrically connected to the second electrode of the auxiliary second transistor T2'. Since the auxiliary second transistor T2' is turned on in the third sub-stage t3, the gate of the auxiliary driving transistor Td' is connected to the second electrode and short-circuited, so only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is effective, thereby putting the auxiliary driving transistor Td' in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the auxiliary driving transistor Td', which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the auxiliary driving transistor Td' has the voltage level of the data voltage signal. Since only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is active, in the third sub-stage t3, the voltage level at the auxiliary first node N1' gradually increases to (Vdata + Vth'), where Vdata is the voltage level of the data voltage signal and Vth' is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the auxiliary first capacitor electrode Ce1' and the auxiliary second capacitor electrode Ce2' decreases to a relatively small value, the auxiliary storage capacitor Cst' discharges. In the third sub-stage t3, the corresponding first light-emitting control signal line em1 provides a high voltage signal to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light emission control signal line em2 among the multiple second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0092] In the fourth sub-stage t4, a cutoff control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to cut off the second transistor T2, and to the gate of the auxiliary second transistor T2' to cut off the auxiliary second transistor T2'. A cutoff control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to cut off the first transistor T1. A cutoff reset control signal is provided to the gate of the first reset transistor Tr1 through a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to cut off the first reset transistor Tr1. A cutoff reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines. A cutoff control signal is provided to the gates of the third transistor T3 and the fourth transistor T4 through a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines to cut off the third transistor T3 and the fourth transistor T4. A cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' through a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0093] In the fifth sub-stage t5, the corresponding first light-emitting control signal line em1 among the plurality of first light-emitting control signal lines is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the fifth sub-stage t5, the voltage level at the first node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light.

[0094] In the fifth sub-stage t5, a low voltage signal is provided to the corresponding first light-emitting control signal line em1 among the plurality of first light-emitting control signal lines to turn on the third transistor T3. A turn-on control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light-emitting control signal line em2 among the plurality of second light-emitting control signal lines to turn on the auxiliary fourth transistor T4'. In the fifth sub-stage t5, the voltage level at the auxiliary first node N1' is maintained at (Vdata+Vth'), and the auxiliary driving transistor Td' is turned on by this voltage level, operating in the saturation region. A path is formed from the third transistor T3, the auxiliary driving transistor Td', the auxiliary fourth transistor T4' to the light-emitting element LE. The auxiliary driving transistor Td' generates an auxiliary driving current to drive the light-emitting element LE to emit light.

[0095] The inventors of this disclosure have discovered that by connecting the driving transistor Td and the auxiliary driving transistor Td' in parallel to provide driving current to the light-emitting element LE in combination, the voltage drop across each of the driving transistor Td and the auxiliary driving transistor Td' can be reduced, thereby reducing power consumption and heat generation of the display device.

[0096] The inventors of this disclosure have also discovered that the pixel driving circuit according to this disclosure can reduce the voltage difference between VSS and VDD by at least 0.5V (e.g., at least 6%) and reduce the data range. Compared to a related pixel driving circuit having a first sub-circuit but no second sub-circuit, the data range of the red sub-pixel can be reduced by 16.0%, the data range of the green sub-pixel by 16.7%, and the data range of the blue sub-pixel by 16.5%. The pixel driving circuit according to this disclosure can also reduce power consumption and improve series bright spots. Tables 1 and 2 summarize the comparison between the pixel driving circuit according to this disclosure and a related pixel driving circuit without a second sub-circuit.

[0097] Table 1 is a comparison between the pixel driving circuit according to this disclosure and related pixel driving circuits without a second sub-circuit.

[0098]

[0099] Table 2 compares the pixel driving circuit according to this disclosure with a related pixel driving circuit that does not have a second sub-circuit.

[0100]

[0101]

[0102] In an alternative embodiment, the pixel driving circuit according to this disclosure can reduce the voltage difference between VSS and VDD by at least 0.7V (e.g., at least 8%) and reduce the data range. Compared to a related pixel driving circuit having a first sub-circuit but not a second sub-circuit, the data range of the red sub-pixel can be reduced by 18.4%, the data range of the green sub-pixel by 19.5%, and the data range of the blue sub-pixel by 20.8%. Tables 3 and 4 summarize the comparison between the pixel driving circuit according to this disclosure and a related pixel driving circuit without a second sub-circuit.

[0103] Table 3 is a comparison between the pixel driving circuit according to this disclosure and a related pixel driving circuit without a second sub-circuit.

[0104]

[0105]

[0106] Table 4 compares the pixel driving circuit according to this disclosure with a related pixel driving circuit that does not have a second sub-circuit.

[0107]

[0108] The inventors of this disclosure have also discovered that, by having a first sub-circuit and a second sub-circuit, the array substrate can emit light even if one of the sub-circuits is defective.

[0109] In some embodiments, the driving transistor Td has a first ratio of the channel width to the channel length of the channel portion of the driving transistor Td; the auxiliary driving transistor Td' has a second ratio of the channel width to the channel length of the auxiliary driving transistor Td'. In some embodiments, the first ratio is less than or equal to the second ratio.

[0110] In some embodiments, the first ratio is less than the second ratio. A larger channel width to channel length ratio results in a larger leakage current in the transistor. In some embodiments, the auxiliary driving transistor Td' has a larger leakage current than the driving transistor Td. In some embodiments, when the pixel driving circuit operates in the first mode, a cutoff signal is provided to the gate of the auxiliary fourth transistor T4' to turn off the auxiliary fourth transistor T4', preventing drive current from being supplied from the auxiliary driving transistor Td' to the light-emitting element LE. Through this operation, low-grayscale bright spot defects can be avoided because the auxiliary driving transistor Td' has a larger leakage current.

[0111] Figure 3A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B yes Figure 3A The diagram shows the arrangement of pixel driving circuits in the array substrate. Figure 3C It is shown Figure 3A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0112] Figure 3D It is shown Figure 3A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate shown. Figure 3F It is shown Figure 3A A schematic diagram of a via extending through an interlayer dielectric layer in an array substrate shown. Figure 3G It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 3H It is shown Figure 3A A schematic diagram of a via extending through a passivation layer in an array substrate shown. Figure 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 3J It is shown Figure 3A A schematic diagram of a via extending through a planarization layer in an array substrate shown. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram. Figure 4C It is along Figure 3A A cross-sectional view of the C-C' line in the diagram. Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram. Figures 3A to 3J A portion of an array substrate with two pixel driving circuits (including PDC1 and PDC2) is shown. In some embodiments, the array substrate includes a plurality of pixel driving circuits arranged in an array, the array including a plurality of rows and a plurality of columns. The row direction of the array is denoted as a first direction DR1. The column direction of the array is denoted as a second direction DR2. The first direction DR1 and the second direction DR2 intersect each other.

[0113] Reference Figures 3A to 3J ,as well as Figures 4A to 4D In some embodiments, the array substrate includes a substrate BS; a buffer layer BUF located on the substrate BS; a semiconductor material layer SML located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; and a second gate metal layer Gate2 located on the side of the buffer layer BUF away from the substrate BS. Layer IN is located on the side away from the first gate metal layer Gate1; interlayer dielectric layer ILD is located on the side of the second gate metal layer Gate2 away from the insulating layer IN; first signal line layer SD1 is located on the side of the interlayer dielectric layer away from the second gate metal layer Gate2; passivation layer PVX is located on the side of the first signal line layer SD1 away from the interlayer dielectric layer ILD; second signal line layer SD2 is located on the side of the passivation layer PVX away from the first signal line layer SD1; and planarization layer PLN1 is located on the side of the second signal line layer SD2 away from the passivation layer PVX.

[0114] Reference Figure 2A , Figure 3A , Figure 3C as well as Figures 4A to 4DIn some embodiments, the semiconductor material layer SML includes at least an active layer of a plurality of transistors of the pixel driving circuit (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a driving transistor Td, an auxiliary second transistor T2', an auxiliary fourth transistor T4', an auxiliary second reset transistor Tr2', and an auxiliary driving transistor Td'). Optionally, the semiconductor material layer SML also includes at least a corresponding portion of the first electrode of the plurality of transistors of the pixel driving circuit (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a driving transistor Td, an auxiliary second transistor T2', an auxiliary fourth transistor T4', an auxiliary second reset transistor Tr2', and an auxiliary driving transistor Td'). Optionally, the semiconductor material layer SML further includes at least a corresponding portion of the second electrode of the plurality of transistors of the pixel driving circuit (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, driving transistor Td, auxiliary second transistor T2', auxiliary fourth transistor T4', auxiliary second reset transistor Tr2', and auxiliary driving transistor Td'). Optionally, the semiconductor material layer SML includes an active layer, a first electrode, and a second electrode of the plurality of transistors of the pixel driving circuit (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, driving transistor Td, auxiliary second transistor T2', auxiliary fourth transistor T4', auxiliary second reset transistor Tr2', and auxiliary driving transistor Td'). Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SML. Examples of semiconductor materials used to fabricate the semiconductor material layer SML include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0115] exist Figure 3C In, corresponding to Figure 3BThe pixel driving circuit of PDC2 is labeled with a tag indicating the components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Td, T2', T4', Tr2', and Td') in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd. The auxiliary second transistor T2' includes an active layer ACT2', a first electrode S2', and a second electrode D2'. The auxiliary fourth transistor T4' includes an active layer ACT4', a first electrode S4', and a second electrode D4'. The auxiliary second reset transistor Tr2' includes an active layer ACTr2', a first electrode Sr2', and a second electrode Dr2'. The auxiliary drive transistor Td includes an active layer ACTd', a first electrode Sd', and a second electrode Dd'.

[0116] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, Td, T2', T4', Tr2' and Td') of each transistor (T1, T2, T3, T4, Tr1, Tr2, Td, T2', T4', Tr2' and Td'), the first electrode (S1, S2, S3, S4, Sr1, Sr2, Sd, S2', S4', Sr2' and Sd'), and the second electrode (D1, D2, D3, D4, Dr1, Dr2, Dd, D2', D4', Dr2' and Dd') are located on the same layer.

[0117] Reference Figure 2A , Figure 3A , Figure 3D as well as Figures 4A to 4DIn some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of second gate lines (e.g., corresponding second gate line GL2), a plurality of first light emission control signal lines (e.g., corresponding first light emission control signal line em1), a plurality of second light emission control signal lines (e.g., corresponding second light emission control signal line em2), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a first capacitor electrode Ce1 of the storage capacitor Cst, and an auxiliary first capacitor electrode Ce1' of the auxiliary storage capacitor Cst'. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first gate lines, a plurality of second gate lines, a plurality of first light emission control signal lines, a plurality of second light emission control signal lines, a plurality of first reset control signal lines, a plurality of second reset control signal lines, a first capacitor electrode Ce1, and an auxiliary first capacitor electrode Ce1' are located on the same layer. Optionally, the corresponding first light emission control signal line em1 extends along the first direction DR1.

[0118] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple first gate lines and first capacitor electrodes Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed on the same material layer. In another example, multiple first gate lines and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple first gate lines and the step of forming the first capacitor electrodes Ce1. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0119] Reference Figure 2A , Figure 3A , Figure 3E as well as Figures 4A to 4DIn some embodiments, the second gate metal layer Gate2 includes a second capacitor electrode Ce2 of the storage capacitor Cst and an auxiliary second capacitor electrode Ce2' of the auxiliary storage capacitor Cst'. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer Gate2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0120] In some embodiments, a portion of the second capacitor electrode Ce2 is absent in the hole region H. Optionally, except for the portion of the hole region H where the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is greater than the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, a portion of the auxiliary second capacitor electrode Ce2' is absent in the auxiliary hole region H'. Optionally, except for the portion of the auxiliary second capacitor electrode Ce2' being absent in the auxiliary hole region H', the orthographic projection of the auxiliary second capacitor electrode Ce2' on the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is greater than the orthographic projection of the auxiliary first capacitor electrode Ce1' on the substrate BS.

[0121] Figure 3F The image shows a via extending through the interlayer dielectric layer (ILD).

[0122] refer to Figure 2A , Figure 3A , Figure 3G and Figures 4A to 4DIn some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines (e.g., a corresponding first reset signal line Vint1), a plurality of second reset signal lines (e.g., a corresponding second reset signal line Vint2), a first node connection line Cln1, a voltage connection pad VCP, a third node connection line Cln3, a fourth node connection line Cln4, an auxiliary first node connection line Cln1', an auxiliary third node connection line Cln3', and a data connection pad DCP. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer SD1. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple first reset signal lines, multiple second reset signal lines, a first node connection line Cln1, a voltage connection pad VCP, a third node connection line Cln3, a fourth node connection line Cln4, an auxiliary first node connection line Cln1', an auxiliary third node connection line Cln3', and a data connection pad DCP are located on the same layer. Optionally, the third node connection line Cln3 and the auxiliary third node connection line Cln3' extend along the second direction DR2.

[0123] Figure 3H The image shows a via extending through the passivation layer PVX.

[0124] refer to Figure 2A , Figure 3A , Figure 3I and Figures 4A to 4DIn some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vdd1), a plurality of data lines (e.g., corresponding data lines DL), a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vdd2), and an anode contact pad ACP. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vdd1), the plurality of data lines (e.g., corresponding data lines DL), the plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vdd2), and the anode contact pad ACP are located in the same layer. Optionally, the corresponding first voltage supply line Vdd1 and the corresponding second voltage supply line Vdd2 extend along the second direction DR2.

[0125] Figure 3J The image shows a via extending through the planarization layer PLN.

[0126] In some embodiments, reference Figures 3A to 3J ,as well as Figures 4A to 4D A first node connection line Cln1 is connected to a first capacitor electrode Ce1 and to a second electrode D2 of a second transistor T2. In some embodiments, the first node connection line Cln1 is connected to the second electrode D2 of the second transistor T2 through a first via v1 and to the first capacitor electrode Ce1 through a second via v2. In one example, the first via v1 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In another example, the second via v2 extends through at least one of the interlayer dielectric layer ILD and the insulating layer IN.

[0127] In some embodiments, the auxiliary first node connection line Cln1' is connected to the auxiliary first capacitor electrode Ce1' and to the second electrode D2' of the auxiliary second transistor T2'. In some embodiments, the first node connection line Cln1 is connected to the second electrode D2' of the auxiliary second transistor T2' through a via extending through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI, and is connected to the auxiliary first capacitor electrode Ce1' through a via extending through at least one of the interlayer dielectric layer ILD and the insulating layer IN.

[0128] In some embodiments, the corresponding first voltage supply line Vdd1 is connected to the voltage connection pad VCP, and the voltage connection pad VCP is connected to the first electrode S3 of the third transistor T3. In some embodiments, the corresponding first voltage supply line Vdd1 is connected to the voltage connection pad VCP through a third via v3, and the voltage connection pad VCP is connected to the first electrode S3 of the third transistor T3 through a fourth via v4. In one example, the third via v3 extends at least through the passivation layer PVX. In another example, the fourth via v4 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0129] In some embodiments, the corresponding second voltage supply line Vdd2 is connected to the voltage connection pad VCP, for example, via a via extending through at least the passivation layer PVX.

[0130] In some embodiments, the third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 and the first electrode S2 of the second transistor T2, and also to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4. In some embodiments, the third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 and the first electrode S2 of the second transistor T2 through a fifth via v5, and to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 through a sixth via v6. In one example, the fifth via v5 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In another example, the sixth via v6 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0131] In some embodiments, the auxiliary third node connection line Cln3' is connected to the second electrode Dr2' of the auxiliary second reset transistor Tr2' and the first electrode S2' of the auxiliary second transistor T2', and is also connected to the second electrode Dd' of the auxiliary driving transistor Td' and the first electrode S4' of the auxiliary fourth transistor T4'. In some embodiments, the auxiliary third node connection line Cln3' is connected to the second electrode Dr2' of the auxiliary second reset transistor Tr2' and the first electrode S2' of the auxiliary second transistor T2' through a via extending through at least one of the interlayer dielectric layer ILD, insulating layer IN, and gate insulating layer GI, and is also connected to the second electrode Dd' of the auxiliary driving transistor Td' and the first electrode S4' of the auxiliary fourth transistor T4' through a via extending through at least one of the interlayer dielectric layer ILD, insulating layer IN, and gate insulating layer GI.

[0132] In some embodiments, the fourth node connection line Cln4 is connected to the second electrode D4 of the fourth transistor T4, to the second electrode Dr1 of the first reset transistor Tr1, and to the second electrode D4' of the auxiliary fourth transistor T4'. In some embodiments, the fourth node connection line Cln4 is connected to the second electrode D4 of the fourth transistor T4 through a seventh via v7, to the second electrode Dr1 of the first reset transistor Tr1 through an eighth via v8, and to the second electrode D4' of the auxiliary fourth transistor T4' through a ninth via v9. In one example, the seventh via v7 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In one example, the eighth via v8 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In one example, the ninth via v9 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0133] In some embodiments, the anode connection pad ACP is connected to the fourth node connection line Cln4. In some embodiments, the anode connection pad ACP is connected to the fourth node connection line Cln4 via a tenth via v10. In one example, the tenth via v10 extends at least through the passivation layer PVX. In some embodiments, the anode is connected to the anode connection pad ACP, for example, via a via extending at least through the planarization layer PLN.

[0134] In some embodiments, the combination of the first node connection line Cln1, the auxiliary first node connection line Cln1', the voltage connection pad VCP, the first capacitor electrode Ce1, the auxiliary first capacitor electrode Ce1', the second capacitor electrode Ce2, the auxiliary second capacitor electrode Ce2', the data connection pad DCP, the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, and the corresponding data line DL has substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) mirror symmetry about a surface that intersects with the corresponding data line DL and the voltage connection pad VCP, is parallel to the second direction DR2, and is perpendicular to the substrate BS.

[0135] In some embodiments, the third node connection line Cln3 and the auxiliary third node connection line Cln3' are mirror-asymmetrical about the surface of the substrate BS, which intersects the corresponding data line DL and voltage connection pad VCP, is parallel to the second direction DR2, and is perpendicular to the substrate BS. In some embodiments, the auxiliary third node connection line Cln3' intersects the corresponding first light emission control signal line em1, while the third node connection line Cln3 does not intersect the corresponding first light emission control signal line em1. In some embodiments, the orthographic projection of the auxiliary third node connection line Cln3' on the substrate BS at least partially overlaps with the orthographic projection of the corresponding first light emission control signal line em1 on the substrate BS, while the orthographic projection of the third node connection line Cln3 on the substrate does not overlap with the orthographic projection of the corresponding first light emission control signal line em1 on the substrate BS. In some embodiments, the orthographic projection of the auxiliary third node connection line Cln3' on the substrate BS at least partially overlaps with the orthographic projection of the corresponding first gate line GL1 on the substrate BS, and at least partially overlaps with the orthographic projection of the corresponding second gate line GL2 on the substrate BS. In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the corresponding first gate line GL1 on the substrate BS, and at least partially overlaps with the orthographic projection of the corresponding second gate line GL2 on the substrate BS.

[0136] In some embodiments, the fourth node connection line Cln4 is mirror-asymmetric about the surface of the substrate BS that intersects with the corresponding data line DL and voltage connection pad VCP, is parallel to the second direction DR2, and is perpendicular to the substrate BS.

[0137] Figure 5A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 5AIn some embodiments, the pixel driving circuit includes a first sub-circuit SC1 and a second sub-circuit SC2. In some embodiments, the first sub-circuit SC1 and the second sub-circuit SC2 are electrically connected to the light-emitting element LE and are configured to provide driving current to the light-emitting element LE individually or in combination. In some embodiments, the first sub-circuit SC1 includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding first gate line GL1 of a plurality of first gate lines, a first electrode connected to a corresponding data line DL of a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second gate line GL2 of a plurality of second gate lines, a first electrode connected to the second electrode of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding third light-emitting control signal line em3 of a plurality of third light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1. The second electrode; the fourth transistor T4, having a gate connected to a corresponding first light-emitting control signal line em1 among a plurality of first light-emitting control signal lines, a first electrode connected to a second electrode of the driving transistor Td and a first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; the first reset transistor Tr1, having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; and the second reset transistor Tr2, having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to the first electrode of the second transistor T2 and the second electrode of the driving transistor Td. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0138] In some embodiments, the second sub-circuit SC2 includes an auxiliary driving transistor Td' having a first electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; an auxiliary storage capacitor Cst' having an auxiliary first capacitor electrode Ce1' and an auxiliary second capacitor electrode Ce2'; an auxiliary second transistor T2' having a gate connected to a corresponding second gate line GL2 of a plurality of second gate lines, a first electrode connected to the second electrode of the auxiliary driving transistor Td', and a second electrode connected to the auxiliary first capacitor electrode Ce1' of the auxiliary storage capacitor Cst' and the gate of the auxiliary driving transistor Td'; and an auxiliary fourth transistor T 4, which has a gate connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, a first electrode connected to a second electrode of an auxiliary driving transistor Td' and a first electrode of an auxiliary second transistor T2', and a second electrode connected to the anode of a light-emitting element LE; and an auxiliary second reset transistor Tr2', which has a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a first electrode of an auxiliary second transistor T2' and a second electrode of an auxiliary driving transistor Td'. An auxiliary second capacitor electrode Ce2' is connected to a corresponding voltage supply line and the first electrode of a third transistor T3.

[0139] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the auxiliary fourth transistor T4', the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0140] The pixel driving circuit also includes an auxiliary first node N1' and an auxiliary third node N3'. The auxiliary first node N1' is connected to the gate of the auxiliary driving transistor Td', the auxiliary first capacitor electrode Ce1', and the second electrode of the auxiliary second transistor T2'. The auxiliary third node N3' is connected to the second electrode of the auxiliary driving transistor Td', the first electrode of the auxiliary second transistor T2', the first electrode of the auxiliary fourth transistor T4', and the second electrode of the auxiliary second reset transistor Tr2'.

[0141] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, S3 represents a corresponding third sub-pixel, and S4 represents a corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, C3 represents a corresponding third sub-pixel of a third color, and C4 represents a corresponding fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, the corresponding third sub-pixel is a blue sub-pixel, and the corresponding fourth sub-pixel is a green sub-pixel.

[0142] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, an auxiliary second transistor T2', an auxiliary fourth transistor T4', an auxiliary second reset transistor Tr2', and an auxiliary driving transistor Td'.

[0143] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Reference Figure 2AThe transistor is a p-type transistor, such as a polysilicon transistor. For a p-type transistor, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For an n-type transistor, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0144] In some embodiments, the pixel driving circuit includes one or more driving transistors (e.g., driving transistor Td and auxiliary driving transistor Td'), a data writing transistor (e.g., first transistor T1), one or more compensation transistors (e.g., second transistor T2 and auxiliary second transistor T2'), a plurality of light-emitting control transistors (e.g., third transistor T3, fourth transistor T4 and auxiliary fourth transistor T4'), and a plurality of reset transistors (e.g., first reset transistor Tr1, second reset transistor Tr2 and auxiliary second reset transistor Tr2').

[0145] In some embodiments, multiple light-emitting control transistors (e.g., third transistor T3, fourth transistor T4, and auxiliary fourth transistor T4') are controlled by different light-emitting control signal lines. In some embodiments, the gates of the multiple light-emitting control transistors (e.g., third transistor T3, fourth transistor T4, and auxiliary fourth transistor T4') are respectively connected to different light-emitting control signal lines. In some embodiments, the gate of the fourth transistor T4 is connected to a corresponding first light-emitting control signal line em1 among multiple first light-emitting control signal lines, the gate of the auxiliary fourth transistor T4' is connected to a corresponding second light-emitting control signal line em2 among multiple second light-emitting control signal lines, and the gate of the third transistor T3 is connected to a corresponding third light-emitting control signal line em3 among multiple third light-emitting control signal lines.

[0146] In some embodiments, the second electrodes of a plurality of light-emitting control transistors (e.g., a fourth transistor T4 and an auxiliary fourth transistor T4') are connected to the anode of the light-emitting element LE.

[0147] In some embodiments, the first electrodes of a plurality of light-emitting control transistors (e.g., a fourth transistor T4 and an auxiliary fourth transistor T4') are connected to different driving transistors. In some embodiments, the first electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor Td, and the first electrode of the auxiliary fourth transistor T4' is connected to the second electrode of the auxiliary driving transistor Td'.

[0148] The pixel driving circuit according to this disclosure can be operated in various alternative implementations.

[0149] In some embodiments, the pixel driving circuit operates in a third mode. In some embodiments, in the third mode, only one of the plurality of light-emitting control transistors connected to the anode of the light-emitting element LE is configured to be turned on to allow drive current to flow, while the other light-emitting control transistors connected to the anode of the light-emitting element LE are configured to be turned off. Figure 5B This is a timing diagram illustrating the operation of a pixel driving circuit in a third mode according to some embodiments of the present disclosure. (Refer to...) Figure 5A and Figure 5B During one frame of an image, the operation of the pixel driving circuit in the third mode includes a first sub-stage t1, a second sub-stage t2, a third sub-stage t3, a fourth sub-stage t4, and a fifth sub-stage t5.

[0150] In the third mode, a cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' via a corresponding second light-emitting control signal line em2 among multiple second light-emitting control signal lines, thereby cutting off the auxiliary fourth transistor T4'. In the third mode, the second sub-circuit SC2 is not configured to provide drive current to the light-emitting element LE.

[0151] In the first sub-stage t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to turn on the first reset transistor Tr1; allowing the initialization voltage signal from the corresponding first reset signal line Vint1 among a plurality of first reset signal lines to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to the fourth node N4. The anode of the light-emitting element LE is initialized. In the first sub-stage t1, a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via a second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2 and the auxiliary second transistor T2'.

[0152] In the second sub-stage t2, a turn-on reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, to turn on the second reset transistor Tr2 and the auxiliary second reset transistor Tr2'; a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via the corresponding second gate line GL2 among the plurality of second gate lines, to turn on the second transistor T2 and the auxiliary second transistor T2'; thereby allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the second reset transistor Tr2 and the second transistor T2, and sequentially to the first node N1; and allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the auxiliary second reset transistor Tr2' and the auxiliary second transistor T2', and sequentially to the auxiliary first node N1'. The gate of the driving transistor Td is initialized. The gate of the auxiliary driving transistor Td' is initialized. The third node N3 is initialized. The auxiliary third node N3' is initialized.

[0153] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2; and a turn-off control signal is provided to the gate of the second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the second reset transistor Tr2. The second electrode of the driving transistor Td is connected to the first electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the third sub-stage t3, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thereby putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, in the third sub-stage t3, the voltage level at the first node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. In the third sub-stage t3, a high voltage signal is provided on the corresponding third light-emitting control signal line em3 to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the fourth transistor T4 via the corresponding first light-emitting control signal line em1 among the multiple first light-emitting control signal lines to turn off the fourth transistor T4.

[0154] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the auxiliary second transistor T2' through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the auxiliary second transistor T2'; and a cut-off control signal is provided to the gate of the auxiliary second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the auxiliary second reset transistor Tr2. The second electrode of the auxiliary driving transistor Td' is connected to the first electrode of the auxiliary second transistor T2'. The gate of the auxiliary driving transistor Td' is electrically connected to the second electrode of the auxiliary second transistor T2'. Since the auxiliary second transistor T2' is turned on in the third sub-stage t3, the gate of the auxiliary driving transistor Td' is connected to the second electrode and short-circuited, so only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is effective, thereby putting the auxiliary driving transistor Td' in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the auxiliary driving transistor Td', which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the auxiliary driving transistor Td' has the voltage level of the data voltage signal. Since only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is active, in the third sub-stage t3, the voltage level at the auxiliary first node N1' gradually increases to (Vdata + Vth'), where Vdata is the voltage level of the data voltage signal and Vth' is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the auxiliary first capacitor electrode Ce1' and the auxiliary second capacitor electrode Ce2' decreases to a relatively small value, the auxiliary storage capacitor Cst' discharges. In the third sub-stage t3, the corresponding third light-emitting control signal line em3 provides a high voltage signal to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light emission control signal line em2 among the multiple second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0155] In the fourth sub-stage t4, a cutoff control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to cut off the second transistor T2, and to the gate of the auxiliary second transistor T2' to cut off the auxiliary second transistor T2'. A cutoff control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to cut off the first transistor T1. A cutoff reset control signal is provided to the gate of the first reset transistor Tr1 through a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to cut off the first reset transistor Tr1. A cutoff reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines. A cutoff control signal is provided to the gate of the fourth transistor T4 through a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines to cut off the fourth transistor T4. A cutoff control signal is provided to the gate of the third transistor T3 through a corresponding third light emission control signal line em3 among a plurality of third light emission control signal lines to cut off the third transistor T3. A cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' through a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0156] In the fifth sub-stage t5, a low voltage signal is provided to the corresponding third light-emitting control signal line em3 among the plurality of third light-emitting control signal lines to turn on the third transistor T3, and a low voltage signal is provided to the corresponding first light-emitting control signal line em1 among the plurality of first light-emitting control signal lines to turn on the fourth transistor T4. In the fifth sub-stage t5, the voltage level at the first node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, and the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the third node N3, connected to the second electrode of the driving transistor Td, is equal to the light-emitting voltage of the light-emitting element LE.

[0157] In the fifth sub-stage t5, the cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light-emitting control signal line em2 among the multiple second light-emitting control signal lines, thereby turning off the auxiliary fourth transistor T4'. No drive current is provided from the auxiliary drive transistor Td' to the light-emitting element LE.

[0158] In some embodiments, the pixel driving circuit operates in a fourth mode. In some embodiments, in the fourth mode, only one of the plurality of light-emitting control transistors connected to the anode of the light-emitting element LE is configured to be turned on to allow drive current to flow, while the other light-emitting control transistors connected to the anode of the light-emitting element LE are configured to be turned off. Figure 5C This is a timing diagram illustrating the operation of a pixel driving circuit in a fourth mode according to some embodiments of the present disclosure. (Refer to...) Figure 5A and Figure 5C During one frame of an image, the operation of the pixel driving circuit in the fourth mode includes a first sub-stage t1, a second sub-stage t2, a third sub-stage t3, a fourth sub-stage t4, and a fifth sub-stage t5.

[0159] In the fourth mode, a cutoff control signal is provided to the gate of the fourth transistor T4 via a corresponding first light-emitting control signal line em1 among a plurality of first light-emitting control signal lines, thereby cutting off the fourth transistor T4. In the fourth mode, the second sub-circuit SC2 is configured to provide drive current to the light-emitting element LE.

[0160] In the first sub-stage t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to turn on the first reset transistor Tr1; allowing the initialization voltage signal from the corresponding first reset signal line Vint1 among a plurality of first reset signal lines to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to the fourth node N4. The anode of the light-emitting element LE is initialized. In the first sub-stage t1, a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via a corresponding second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2 and the auxiliary second transistor T2'.

[0161] In the second sub-stage t2, a turn-on reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' via the corresponding second reset control signal line rst2 among the plurality of second reset control signal lines, to turn on the second reset transistor Tr2 and the auxiliary second reset transistor Tr2'; a turn-on control signal is provided to the gates of the second transistor T2 and the auxiliary second transistor T2' via the corresponding second gate line GL2 among the plurality of second gate lines, to turn on the second transistor T2 and the auxiliary second transistor T2'; thereby allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the second reset transistor Tr2 and the second transistor T2, and sequentially to the first node N1; and allowing the initialization voltage signal from the corresponding second reset signal line Vint2 among the plurality of second reset signal lines to pass through the auxiliary second reset transistor Tr2' and the auxiliary second transistor T2', and sequentially to the auxiliary first node N1'. The gate of the driving transistor Td is initialized. The gate of the auxiliary driving transistor Td' is initialized. The third node N3 is initialized. The auxiliary third node N3' is initialized.

[0162] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the second transistor T2; and a turn-off control signal is provided to the gate of the second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the second reset transistor Tr2. The second electrode of the driving transistor Td is connected to the first electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the third sub-stage t3, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thereby putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the third sub-stage t3, the voltage level at the first node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. In the third sub-stage t3, the corresponding third light emission control signal line em3 provides a high voltage signal to turn off the third transistor T3. In the third sub-stage t3, the cutoff reset control signal is provided to the gate of the fourth transistor T4 via the corresponding first light emission control signal line em1 among the multiple first light emission control signal lines to turn off the fourth transistor T4. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the auxiliary fourth transistor T4' through the corresponding second light emission control signal line em2 among the multiple second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0163] In the third sub-stage t3, a turn-on control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to turn on the first transistor T1; a turn-on control signal is provided to the gate of the auxiliary second transistor T2' through a corresponding second gate line GL2 among a plurality of second gate lines to turn on the auxiliary second transistor T2'; and a cut-off control signal is provided to the gate of the auxiliary second reset transistor Tr2 through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines to turn off the auxiliary second reset transistor Tr2. The second electrode of the auxiliary driving transistor Td' is connected to the first electrode of the auxiliary second transistor T2'. The gate of the auxiliary driving transistor Td' is electrically connected to the second electrode of the auxiliary second transistor T2'. Since the auxiliary second transistor T2' is turned on in the third sub-stage t3, the gate of the auxiliary driving transistor Td' is connected to the second electrode and short-circuited, so only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is effective, thereby putting the auxiliary driving transistor Td' in diode connection mode. The first transistor T1 is turned on in the third sub-stage t3. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the auxiliary driving transistor Td', which is connected to the second electrode of the first transistor T1. The second node N2 connected to the first electrode of the auxiliary driving transistor Td' has the voltage level of the data voltage signal. Since only the PN junction between the gate of the auxiliary driving transistor Td' and the first electrode is effective, in the third sub-stage t3, the voltage level at the auxiliary first node N1' gradually increases to (Vdata + Vth'), where Vdata is the voltage level of the data voltage signal and Vth' is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the auxiliary first capacitor electrode Ce1' and the auxiliary second capacitor electrode Ce2' decreases to a relatively small value, the auxiliary storage capacitor Cst' discharges. In the third sub-stage t3, the corresponding third light-emitting control signal line em3 provides a high voltage signal to turn off the third transistor T3. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the auxiliary fourth transistor T4' via the corresponding second light-emitting control signal line em2 among the multiple second light-emitting control signal lines to turn off the auxiliary fourth transistor T4'. In the third sub-stage t3, a cutoff reset control signal is provided to the gate of the fourth transistor T4 through the corresponding first light emission control signal line em1 among the multiple first light emission control signal lines, so as to cut off the fourth transistor T4.

[0164] In the fourth sub-stage t4, a cutoff control signal is provided to the gate of the second transistor T2 through a corresponding second gate line GL2 among a plurality of second gate lines to cut off the second transistor T2, and to the gate of the auxiliary second transistor T2' to cut off the auxiliary second transistor T2'. A cutoff control signal is provided to the gate of the first transistor T1 through a corresponding first gate line GL1 among a plurality of first gate lines to cut off the first transistor T1. A cutoff reset control signal is provided to the gate of the first reset transistor Tr1 through a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines to cut off the first reset transistor Tr1. A cutoff reset control signal is provided to the gates of the second reset transistor Tr2 and the auxiliary second reset transistor Tr2' through a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines. A cutoff control signal is provided to the gate of the fourth transistor T4 through a corresponding first light emission control signal line em1 among a plurality of first light emission control signal lines to cut off the fourth transistor T4. A cutoff control signal is provided to the gate of the third transistor T3 through a corresponding third light emission control signal line em3 among a plurality of third light emission control signal lines to cut off the third transistor T3. A cutoff control signal is provided to the gate of the auxiliary fourth transistor T4' through a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, so as to cut off the auxiliary fourth transistor T4'.

[0165] In the fifth sub-stage t5, a low voltage signal is provided on the corresponding third light-emitting control signal line em3 among the plurality of third light-emitting control signal lines to turn on the third transistor T3, and a low voltage signal is provided on the corresponding second light-emitting control signal line em2 among the plurality of second light-emitting control signal lines to turn on the auxiliary fourth transistor T4'. In the fifth sub-stage t5, the voltage level at the first node N1 is maintained at (Vdata+Vth'), and the auxiliary driving transistor Td' is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the auxiliary driving transistor Td', the auxiliary fourth transistor T4' to the light-emitting element LE. The auxiliary driving transistor Td' generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the auxiliary third node N3' connected to the second electrode of the auxiliary driving transistor Td' is equal to the light-emitting voltage of the light-emitting element LE.

[0166] In the fifth sub-stage t5, a cutoff control signal is provided to the gate of the fourth transistor T4 via the corresponding first light-emitting control signal line em1 among multiple first light-emitting control signal lines to turn off the fourth transistor T4. No drive current is supplied from the drive transistor Td to the light-emitting element LE.

[0167] In some embodiments, the driving transistor Td has a first ratio of the channel width to the channel length of the channel portion of the driving transistor Td; the auxiliary driving transistor Td' has a second ratio of the channel width to the channel length of the auxiliary driving transistor Td'. In some embodiments, the first ratio is less than or equal to the second ratio.

[0168] In some embodiments, the first ratio is less than the second ratio. The inventors of this disclosure have discovered that by providing drive current to the light-emitting element LE with an auxiliary drive transistor Td' (which has a large channel width to channel length ratio), a smaller voltage drop can be achieved, thereby reducing power consumption and heat generation in the display device.

[0169] The inventors of this disclosure have also discovered that, by having a first sub-circuit and a second sub-circuit, the array substrate can emit light even if one of the sub-circuits is defective.

[0170] Figure 6A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 6B yes Figure 6A The diagram shows the arrangement of pixel driving circuits in the array substrate. Figure 6C It is shown Figure 6A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0171] Figure 6D It is shown Figure 6A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate. Figure 6E It is shown Figure 6A A schematic diagram of the structure of the second gate metal layer in the array substrate shown. Figure 6F It is shown Figure 6A A schematic diagram of a via extending through an interlayer dielectric layer in an array substrate shown. Figure 6G It is shown Figure 6A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 6H It is shown Figure 6A A schematic diagram of a via extending through a passivation layer in an array substrate shown. Figure 6I It is shown Figure 6A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 6J It is shown Figure 6A A schematic diagram of a via extending through a planarization layer in an array substrate shown. Figure 7A It is along Figure 6A A cross-sectional view of the E-E' line in the diagram. Figure 7B It is along Figure 6A A cross-sectional view of line F-F' in the diagram. Figure 7C It is along Figure 6AA cross-sectional view of the G-G' line in the diagram. Figure 7D It is along Figure 6A A cross-sectional view of the H-H' line in the diagram. Figures 6A to 6J A portion of an array substrate with two pixel driving circuits (including PDC1 and PDC2) is shown.

[0172] Reference Figures 6A to 6J ,as well as Figures 7A to 7D In some embodiments, the array substrate includes a substrate BS; a buffer layer BUF located on the substrate BS; a semiconductor material layer SML located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; and a second gate metal layer Gate2 located on the side of the buffer layer BUF away from the substrate BS. Layer IN is located on the side away from the first gate metal layer Gate1; interlayer dielectric layer ILD is located on the side of the second gate metal layer Gate2 away from the insulating layer IN; first signal line layer SD1 is located on the side of the interlayer dielectric layer away from the second gate metal layer Gate2; passivation layer PVX is located on the side of the first signal line layer SD1 away from the interlayer dielectric layer ILD; second signal line layer SD2 is located on the side of the passivation layer PVX away from the first signal line layer SD1; and planarization layer PLN is located on the side of the second signal line layer SD2 away from the passivation layer PVX.

[0173] Reference Figure 5A , Figure 6A , Figure 6C as well as Figures 7A to 7DIn some embodiments, the semiconductor material layer SML includes at least an active layer of a plurality of transistors of the pixel driving circuit (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a driving transistor Td, an auxiliary second transistor T2', an auxiliary fourth transistor T4', an auxiliary second reset transistor Tr2', and an auxiliary driving transistor Td'). Optionally, the semiconductor material layer SML also includes at least a corresponding portion of the first electrode of the plurality of transistors of the pixel driving circuit (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a driving transistor Td, an auxiliary second transistor T2', an auxiliary fourth transistor T4', an auxiliary second reset transistor Tr2', and an auxiliary driving transistor Td'). Optionally, the semiconductor material layer SML further includes at least a corresponding portion of the second electrode of the plurality of transistors of the pixel driving circuit (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, driving transistor Td, auxiliary second transistor T2', auxiliary fourth transistor T4', auxiliary second reset transistor Tr2', and auxiliary driving transistor Td'). Optionally, the semiconductor material layer SML includes an active layer, a first electrode, and a second electrode of the plurality of transistors of the pixel driving circuit (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, driving transistor Td, auxiliary second transistor T2', auxiliary fourth transistor T4', auxiliary second reset transistor Tr2', and auxiliary driving transistor Td').

[0174] exist Figure 6C In, corresponding to Figure 6BThe pixel driving circuit of PDC2 is labeled with a tag indicating the components of each of the multiple transistors (T1, T2, T3, T4, Tr1, Tr2, Td, T2', T4', Tr2', and Td') in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd. The auxiliary second transistor T2' includes an active layer ACT2', a first electrode S2', and a second electrode D2'. The auxiliary fourth transistor T4' includes an active layer ACT4', a first electrode S4', and a second electrode D4'. The auxiliary second reset transistor Tr2' includes an active layer ACTr2', a first electrode Sr2', and a second electrode Dr2'. The auxiliary drive transistor Td includes an active layer ACTd', a first electrode Sd', and a second electrode Dd'.

[0175] Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACTr1, ACTr2, Td, T2', T4', Tr2' and Td') of each transistor (T1, T2, T3, T4, Tr1, Tr2, Td, T2', T4', Tr2' and Td'), the first electrode (S1, S2, S3, S4, Sr1, Sr2, Sd, S2', S4', Sr2' and Sd'), and the second electrode (D1, D2, D3, D4, Dr1, Dr2, Dd, D2', D4', Dr2' and Dd') are located on the same layer.

[0176] Reference Figure 5A , Figure 6A , Figure 6D as well as Figures 7A to 7DIn some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of second gate lines (e.g., corresponding second gate line GL2), a plurality of first light emission control signal lines (e.g., corresponding first light emission control signal line em1), a plurality of second light emission control signal lines (e.g., corresponding second light emission control signal line em2), a plurality of third light emission control signal lines (e.g., corresponding third light emission control signal line em3), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a first capacitor electrode Ce1 of the storage capacitor Cst, and an auxiliary first capacitor electrode Ce1' of the auxiliary storage capacitor Cst'.

[0177] Reference Figure 5A , Figure 6A , Figure 6E as well as Figures 7A to 7D In some embodiments, the second gate metal layer Gate2 includes a second node connection line Cln2, a second capacitor electrode Ce2 of the storage capacitor Cst, and an auxiliary second capacitor electrode Ce2' of the auxiliary storage capacitor Cst'.

[0178] In some embodiments, a portion of the second capacitor electrode Ce2 is absent in the hole region H. Optionally, except for the portion of the hole region H where the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is greater than the orthographic projection of the first capacitor electrode Ce1 on the substrate BS. In some embodiments, a portion of the auxiliary second capacitor electrode Ce2' is absent in the auxiliary hole region H'. Optionally, except for the portion of the auxiliary second capacitor electrode Ce2' being absent in the auxiliary hole region H', the orthographic projection of the auxiliary second capacitor electrode Ce2' on the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is greater than the orthographic projection of the auxiliary first capacitor electrode Ce1' on the substrate BS.

[0179] Figure 6F The image shows a via extending through the interlayer dielectric layer (ILD).

[0180] refer to Figure 5A , Figure 6A , Figure 6G and Figures 7A to 7DIn some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines (e.g., a corresponding first reset signal line Vint1), a plurality of second reset signal lines (e.g., a corresponding second reset signal line Vint2), a first node connection line Cln1, a voltage connection pad VCP, a third node connection line Cln3, a fourth node connection line Cln4, an auxiliary first node connection line Cln1', an auxiliary third node connection line Cln3', and a data connection pad DCP.

[0181] Figure 6H The image shows a via extending through the passivation layer PVX.

[0182] refer to Figure 5A , Figure 6A , Figure 6I and Figures 7A to 7D In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., corresponding first voltage supply line Vdd1), a plurality of data lines (e.g., corresponding data line DL), a plurality of second voltage supply lines (e.g., corresponding second voltage supply line Vdd2), and an anode contact pad ACP.

[0183] Figure 6J The image shows a via extending through the planarization layer PLN.

[0184] In some embodiments, reference Figures 6A to 6J ,as well as Figures 7A to 7D A first node connection line Cln1 is connected to a first capacitor electrode Ce1 and to a second electrode D2 of a second transistor T2. In some embodiments, the first node connection line Cln1 is connected to the second electrode D2 of the second transistor T2 through a first via v1 and to the first capacitor electrode Ce1 through a second via v2. In one example, the first via v1 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In another example, the second via v2 extends through at least one of the interlayer dielectric layer ILD and the insulating layer IN.

[0185] In some embodiments, the auxiliary first node connection line Cln1' is connected to the auxiliary first capacitor electrode Ce1' and to the second electrode D2' of the auxiliary second transistor T2'. In some embodiments, the first node connection line Cln1 is connected to the second electrode D2' of the auxiliary second transistor T2' through a via extending through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI, and is connected to the auxiliary first capacitor electrode Ce1' through a via extending through at least one of the interlayer dielectric layer ILD and the insulating layer IN.

[0186] In some embodiments, the corresponding first voltage supply line Vdd1 is connected to the voltage connection pad VCP, and the voltage connection pad VCP is connected to the first electrode S3 of the third transistor T3. In some embodiments, the corresponding first voltage supply line Vdd1 is connected to the voltage connection pad VCP through a third via v3, and the voltage connection pad VCP is connected to the first electrode S3 of the third transistor T3 through a fourth via v4. In one example, the third via v3 extends at least through the passivation layer PVX. In another example, the fourth via v4 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0187] In some embodiments, the corresponding second voltage supply line Vdd2 is connected to the voltage connection pad VCP, for example, via a via extending through at least the passivation layer PVX.

[0188] In some embodiments, the second node connection line Cln2 is connected to the first electrodes (Sd and Sd') of the driving transistor Td and the auxiliary driving transistor Td', and to the second electrode D3 of the third transistor T3. In some embodiments, the second node connection line Cln2 is connected to the first electrodes (Sd and Sd') of the driving transistor Td and the auxiliary driving transistor Td' through an eleventh via v11, and to the second electrode D3 of the third transistor T3 through a twelfth via v12. In one example, the eleventh via v11 extends through at least one of the insulating layer IN and the gate insulating layer GI. In another example, the twelfth via v12 extends through at least one of the insulating layer IN and the gate insulating layer GI.

[0189] In some embodiments, the third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 and the first electrode S2 of the second transistor T2, and also to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4. In some embodiments, the third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 and the first electrode S2 of the second transistor T2 through a fifth via v5, and to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 through a sixth via v6. In one example, the fifth via v5 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In another example, the sixth via v6 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0190] In some embodiments, the auxiliary third node connection line Cln3' is connected to the second electrode Dr2' of the auxiliary second reset transistor Tr2' and the first electrode S2' of the auxiliary second transistor T2', and is also connected to the second electrode Dd' of the auxiliary driving transistor Td' and the first electrode S4' of the auxiliary fourth transistor T4'. In some embodiments, the auxiliary third node connection line Cln3' is connected to the second electrode Dr2' of the auxiliary second reset transistor Tr2' and the first electrode S2' of the auxiliary second transistor T2' through a via extending through at least one of the interlayer dielectric layer ILD, insulating layer IN, and gate insulating layer GI, and is also connected to the second electrode Dd' of the auxiliary driving transistor Td' and the first electrode S4' of the auxiliary fourth transistor T4' through a via extending through at least one of the interlayer dielectric layer ILD, insulating layer IN, and gate insulating layer GI.

[0191] In some embodiments, the fourth node connection line Cln4 is connected to the second electrode D4 of the fourth transistor T4, to the second electrode Dr1 of the first reset transistor Tr1, and to the second electrode D4' of the auxiliary fourth transistor T4'. In some embodiments, the fourth node connection line Cln4 is connected to the second electrode D4 of the fourth transistor T4 through a seventh via v7, to the second electrode Dr1 of the first reset transistor Tr1 through an eighth via v8, and to the second electrode D4' of the auxiliary fourth transistor T4' through a ninth via v9. In one example, the seventh via v7 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In one example, the eighth via v8 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. In one example, the ninth via v9 extends through at least one of the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0192] In some embodiments, the anode connection pad ACP is connected to the fourth node connection line Cln4. In some embodiments, the anode connection pad ACP is connected to the fourth node connection line Cln4 via a tenth via v10. In one example, the tenth via v10 extends at least through the passivation layer PVX. In some embodiments, the anode is connected to the anode connection pad ACP, for example, via a via extending at least through the planarization layer PLN.

[0193] In some embodiments, the combination of the first node connection line Cln1, the auxiliary first node connection line Cln1', the second node connection line Cln2, the voltage connection pad VCP, the first capacitor electrode Ce1, the auxiliary first capacitor electrode Ce1', the second capacitor electrode Ce2, the auxiliary second capacitor electrode Ce2', the data connection pad DCP, the corresponding first voltage supply line Vdd1, the corresponding second voltage supply line Vdd2, and the corresponding data line DL has substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) mirror symmetry about a surface that intersects with the corresponding data line DL and the voltage connection pad VCP, is parallel to the second direction DR2, and is perpendicular to the substrate BS.

[0194] In some embodiments, the third node connection line Cln3 and the auxiliary third node connection line Cln3' are mirror-asymmetrical about the surface of the substrate BS, which intersects the corresponding data line DL and voltage connection pad VCP, is parallel to the second direction DR2, and is perpendicular to the substrate BS. In some embodiments, the auxiliary third node connection line Cln3' intersects the corresponding first light emission control signal line em1 and the corresponding third light emission control signal line em3, while the third node connection line Cln3 does not intersect the corresponding first light emission control signal line em1 or the corresponding third light emission control signal line em3. In some embodiments, the orthographic projection of the auxiliary third node connection line Cln3' on the substrate BS at least partially overlaps with the orthographic projection of the corresponding first light emission control signal line em1 on the substrate BS and at least partially overlaps with the orthographic projection of the corresponding third light emission control signal line em3 on the substrate BS, while the orthographic projection of the third node connection line Cln3 on the substrate does not overlap with the orthographic projection of the corresponding first light emission control signal line em1 on the substrate BS and does not overlap with the orthographic projection of the corresponding third light emission control signal line em3 on the substrate BS. In some embodiments, the orthographic projection of the auxiliary third node connection line Cln3' on the substrate BS at least partially overlaps with the orthographic projection of the corresponding first gate line GL1 on the substrate BS, and at least partially overlaps with the orthographic projection of the corresponding second gate line GL2 on the substrate BS.

[0195] In some embodiments, the fourth node connection line Cln4 is mirror-asymmetric about the surface of the substrate BS that intersects with the corresponding data line DL and voltage connection pad VCP, is parallel to the second direction DR2, and is perpendicular to the substrate BS.

[0196] In some embodiments, refer to Figure 2A and Figure 5AThe driving transistor Td and the auxiliary driving transistor Td' are two separate transistors. In some embodiments, the driving transistor Td is a low-temperature polysilicon transistor, and the auxiliary driving transistor Td' is a low-temperature metal-oxide transistor.

[0197] In an alternative embodiment, the driving transistor Td and the auxiliary driving transistor Td' are part of a top-bottom dual-gate transistor.

[0198] In another aspect, the present invention provides a pixel driving circuit. Optionally, the pixel driving circuit includes a driving transistor; an auxiliary driving transistor; a first light-emitting control transistor; a second light-emitting control transistor; and an auxiliary second light-emitting control transistor. Optionally, the first electrodes of the driving transistor and the auxiliary driving transistor are connected to the second electrode of the first light-emitting control transistor. Optionally, the second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor. Optionally, the second electrode of the auxiliary driving transistor is connected to the first electrode of the auxiliary second light-emitting control transistor. Optionally, the gate of the second light-emitting control transistor is connected to a corresponding first light-emitting control signal line. Optionally, the gate of the auxiliary second light-emitting control transistor is connected to a corresponding second light-emitting control signal line. Optionally, the second electrodes of the second light-emitting control transistor and the auxiliary second light-emitting control transistor are connected to each other.

[0199] In another aspect, the present invention provides a method for operating a pixel driving circuit. In some embodiments, the method includes providing different light emission control signals to the gate of a second light emission control transistor and the gate of an auxiliary second light emission control transistor, respectively, in at least one operating mode.

[0200] In some embodiments, the method includes, in a first mode, providing an on control signal to the gate of a first light-emitting control transistor and a second light-emitting control transistor during a light-emitting sub-phase of a frame image; and, during the light-emitting sub-phase, providing an off control signal to the gate of an auxiliary second light-emitting control transistor.

[0201] In some embodiments, the method includes, in a second mode, providing a turn-on control signal to the gates of a first light-emitting control transistor and a second light-emitting control transistor during a light-emitting sub-phase of a frame image; and providing a turn-on control signal to the gate of an auxiliary second light-emitting control transistor during the light-emitting sub-phase.

[0202] In some embodiments, the method includes, in a third mode, providing an on control signal to the gate of a second light-emitting control transistor during a light-emitting phase of a frame image; providing an off control signal to the gate of an auxiliary second light-emitting control transistor during the light-emitting phase; and providing an on control signal to the gate of a first light-emitting control transistor during the light-emitting phase.

[0203] In some embodiments, the method includes, in a fourth mode, providing a cutoff control signal to the gate of a second light-emitting control transistor during a light-emitting phase of a frame image; providing an on control signal to the gate of an auxiliary second light-emitting control transistor during the light-emitting phase; and providing an on control signal to the gate of a first light-emitting control transistor during the light-emitting phase.

[0204] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate.

[0205] Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0206] In another aspect, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a pixel driving circuit. Optionally, forming the pixel driving circuit includes forming a third node connection line; forming an auxiliary third node connection line; forming a driving transistor; forming an auxiliary driving transistor; forming a compensation transistor; forming an auxiliary compensation transistor; forming a second light-emitting control transistor; forming an auxiliary second light-emitting control transistor; forming a second reset transistor; and forming an auxiliary second reset transistor. Optionally, the third node connection line is connected to the second electrode of the second reset transistor and the first electrode of the compensation transistor, and is also connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor. Optionally, the auxiliary third node connection line is connected to the second electrode of the auxiliary second reset transistor and the first electrode of the auxiliary compensation transistor, and is also connected to the second electrode of the auxiliary driving transistor and the first electrode of the auxiliary second light-emitting control transistor. Optionally, the orthographic projection of the auxiliary third node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate. Optionally, the orthographic projection of the third node connection line on the substrate does not overlap with the orthographic projection of the corresponding first light-emitting control signal line on the substrate.

[0207] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising a plurality of pixel driving circuits arranged in an array, the array comprising a plurality of rows and a plurality of columns; in, The pixel driving circuit includes: Third node connecting line; Auxiliary third node connection line; Drive transistors; Auxiliary drive transistor; Compensating transistor; Auxiliary compensation transistor; Second light-emitting control transistor; Auxiliary second light-emitting control transistor; The second reset transistor; and Auxiliary second reset transistor; The third node connection line is connected to the second electrode of the second reset transistor and the first electrode of the compensation transistor, and is also connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor. The auxiliary third node connection line is connected to the second electrode of the auxiliary second reset transistor and the first electrode of the auxiliary compensation transistor, and is also connected to the second electrode of the auxiliary driving transistor and the first electrode of the auxiliary second light-emitting control transistor; The orthographic projection of the auxiliary third node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding first light-emitting control signal line on the substrate; and The orthographic projection of the third node connection line on the substrate does not overlap with the orthographic projection of the corresponding first light-emitting control signal line on the substrate. Wherein, the corresponding first light emission control signal line extends along a first direction; The third node connecting line and the auxiliary third node connecting line extend along the second direction; The first direction is the row direction of the array; The second direction is the column direction of the array; and The first direction and the second direction intersect each other.

2. The array substrate according to claim 1, wherein, The pixel driving circuit also includes a first light-emitting control transistor; Wherein, the gates of the first light-emitting control transistor and the second light-emitting control transistor are connected to the corresponding first light-emitting control signal line; and The gate of the auxiliary second light-emitting control transistor is connected to the corresponding second light-emitting control signal line.

3. The array substrate according to claim 1, wherein, The orthographic projection of the auxiliary third node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding third light emission control signal line on the substrate.

4. The array substrate according to claim 3, wherein, The pixel driving circuit also includes a first light-emitting control transistor; Wherein, the gate of the second light-emitting control transistor is connected to the corresponding first light-emitting control signal line; The gate of the first light-emitting control transistor is connected to the corresponding third light-emitting control signal line; and The gate of the auxiliary second light-emitting control transistor is connected to the corresponding second light-emitting control signal line.

5. The array substrate according to any one of claims 1 to 3, wherein, The pixel driving circuit also includes: First light-emitting control transistor; First node connection line; Auxiliary first node connection line; Voltage connection pads; A storage capacitor, comprising a first capacitor electrode and a second capacitor electrode; and An auxiliary storage capacitor, comprising an auxiliary first capacitor electrode and an auxiliary second capacitor electrode; The first node connection line is connected to the first capacitor electrode and to the second electrode of the compensation transistor. The auxiliary first node connection line is connected to the auxiliary first capacitor electrode and to the second electrode of the auxiliary compensation transistor; The voltage connection pad is connected to the first electrode of the first light-emitting control transistor; The corresponding first voltage supply line is connected to the voltage connection pad; The corresponding second voltage supply line is connected to the voltage connection pad; and The corresponding first voltage supply line and the corresponding second voltage supply line extend along the second direction.

6. The array substrate according to claim 5, wherein, The combination of the first node connection line, the auxiliary first node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, and the auxiliary second capacitor electrode has substantially mirror symmetry with respect to a mirror surface that intersects the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

7. The array substrate of claim 5, further comprising corresponding data lines configured to provide data signals to the pixel driving circuit; in, The pixel driving circuit also includes: Data is written to transistors; and Data connection pads connect the corresponding data lines to the data write transistor; The combination of the first node connection line, the auxiliary first node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, the auxiliary second capacitor electrode, the data connection pad, the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding data line has substantially mirror symmetry with respect to a mirror surface that intersects with the corresponding data line and the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

8. The array substrate according to claim 5, wherein, The pixel driving circuit further includes a second node connection line, which is connected to the first electrode of the driving transistor and the auxiliary driving transistor, and to the second electrode of the first light-emitting control transistor.

9. The array substrate according to claim 8, wherein, The orthographic projection of the second node connection line on the substrate at least partially overlaps with the orthographic projection of the corresponding first light emission control signal line on the substrate, and at least partially overlaps with the orthographic projection of the corresponding third light emission control signal line on the substrate.

10. The array substrate according to claim 8, wherein, The combination of the first node connection line, the auxiliary first node connection line, the second node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, and the auxiliary second capacitor electrode has substantially mirror symmetry with respect to a mirror surface that intersects the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

11. The array substrate of claim 8, further comprising corresponding data lines configured to provide data signals to the pixel driving circuit; in, The pixel driving circuit also includes: Data is written to transistors; and Data connection pads connect the corresponding data lines to the data write transistor; The combination of the first node connection line, the auxiliary first node connection line, the second node connection line, the voltage connection pad, the first capacitor electrode, the auxiliary first capacitor electrode, the second capacitor electrode, the auxiliary second capacitor electrode, the data connection pad, the corresponding first voltage supply line, the corresponding second voltage supply line, and the corresponding data line has substantially mirror symmetry with respect to a mirror surface that intersects with the corresponding data line, the second node connection line, and the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

12. The array substrate according to any one of claims 5 to 11, wherein, The pixel driving circuit also includes: First reset transistor; and The fourth node connection line is connected to the second electrode of the second light-emitting control transistor, the second electrode of the first reset transistor, and the second electrode of the auxiliary second light-emitting control transistor.

13. The array substrate according to claim 12, wherein, The fourth node connection line is asymmetrical about a mirror surface that intersects with the corresponding data line and the voltage connection pad, is parallel to the second direction, and is perpendicular to the surface of the substrate.

14. A display device comprising an array substrate according to any one of claims 1 to 13, and one or more integrated circuits connected to the array substrate.

15. A method for operating a pixel driving circuit, in, The pixel driving circuit includes: Drive transistors; Auxiliary drive transistor; First light-emitting control transistor; The second light-emitting control transistor; and Auxiliary second light-emitting control transistor; The first electrode of the driving transistor and the auxiliary driving transistor are connected to the second electrode of the first light-emitting control transistor; The second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor; The second electrode of the auxiliary driving transistor is connected to the first electrode of the auxiliary second light-emitting control transistor; The gate of the second light-emitting control transistor is connected to the corresponding first light-emitting control signal line; The gate of the auxiliary second light-emitting control transistor is connected to the corresponding second light-emitting control signal line; and The second light-emitting control transistor and the second electrode of the auxiliary second light-emitting control transistor are connected to each other; The method includes providing different light-emitting control signals to the gate of the second light-emitting control transistor and the gate of the auxiliary second light-emitting control transistor in at least one operating mode.

16. The method according to claim 15, wherein, The method includes, in a first mode: In the light-emitting stage of a frame image, a turn-on control signal is provided to the gates of the first light-emitting control transistor and the second light-emitting control transistor; as well as During the light-emitting phase, a cutoff control signal is provided to the gate of the auxiliary second light-emitting control transistor.

17. The method according to claim 15, wherein, The method includes, in a second mode: In the light-emitting stage of a frame image, a turn-on control signal is provided to the gates of the first light-emitting control transistor and the second light-emitting control transistor; as well as During the light-emitting phase, a conduction control signal is provided to the gate of the auxiliary second light-emitting control transistor.

18. The method according to claim 15, wherein, The method includes, in the third mode: In the light-emitting stage of a frame image, a conduction control signal is provided to the gate of the second light-emitting control transistor; During the light-emitting phase, a cutoff control signal is provided to the gate of the auxiliary second light-emitting control transistor; as well as During the light-emitting phase, a turn-on control signal is provided to the gate of the first light-emitting control transistor.

19. The method according to claim 15, wherein, The method includes, in the fourth mode: During the light-emitting phase of a frame image, a cutoff control signal is provided to the gate of the second light-emitting control transistor; During the light-emitting phase, a turn-on control signal is provided to the gate of the auxiliary second light-emitting control transistor; as well as During the light-emitting phase, a turn-on control signal is provided to the gate of the first light-emitting control transistor.

20. A pixel driving circuit, comprising: Drive transistors; Auxiliary drive transistor; First light-emitting control transistor; Second light-emitting control transistor; as well as Auxiliary second light-emitting control transistor; The first electrode of the driving transistor and the auxiliary driving transistor are connected to the second electrode of the first light-emitting control transistor; The second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor; The second electrode of the auxiliary driving transistor is connected to the first electrode of the auxiliary second light-emitting control transistor; The gate of the second light-emitting control transistor is connected to the corresponding first light-emitting control signal line; The gate of the auxiliary second light-emitting control transistor is connected to the corresponding second light-emitting control signal line; and The second light-emitting control transistor and the second electrode of the auxiliary second light-emitting control transistor are connected to each other.

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