Wiring circuit board, semiconductor package substrate, electronic device, and method for manufacturing wiring circuit board

Abstract

The rewiring substrate has a structure in which a plurality of first insulating layers, second insulating layers, third insulating layers, and fourth insulating layers are laminated on a support layer. A plurality of through-holes are formed in the uppermost first insulating layer among the plurality of insulating layers. A third conductor layer is formed so as to fill the through-holes. A terminal portion is formed on a terminal forming portion located at an upper end portion of the third conductor layer. The plurality of through holes includes a first through hole and a second through hole. The taper angle between the inner peripheral surface of the first through hole and the one surface of the first insulating layer and the taper angle between the inner peripheral surface of the second through hole and the one surface of the first insulating layer are different from each other.

Description

Technical Field

[0001] This invention relates to wiring circuit boards, semiconductor packaging substrates, electronic devices, and methods for manufacturing wiring circuit boards. Background Technology

[0002] Wiring circuit boards are used to transmit and receive electrical signals between multiple electronic components. When electronic components such as semiconductor chips are mounted on the wiring circuit board, the connection between the wiring circuit board and the electronic components requires high reliability.

[0003] In a wiring circuit board capable of flip-chip mounting semiconductor chips, multiple terminals corresponding to multiple terminals of the semiconductor chip are provided on one side (the mounting surface of the semiconductor chip). Here, the positions of various portions of the wiring circuit board in the thickness direction are referred to as height positions.

[0004] If there is a significant deviation in the height position of multiple terminals, the reliability of the electrical connection between the semiconductor chip and the wiring circuit board cannot be guaranteed. Deviations in the height position of multiple terminals are particularly likely to occur between multiple terminals formed on multiple vias. A wiring circuit board that takes this problem into account is proposed.

[0005] Patent Document 1 describes a wiring substrate comprising multiple wiring layers formed between multiple insulating layers. A portion of these wiring layers is located near one side of the wiring substrate. Multiple surface treatment layers are formed on this portion of the wiring layer as multiple terminal portions. The height of each surface treatment layer is determined according to the thickness direction of the wiring layer on which it is formed. Therefore, in the aforementioned wiring substrate, a process is implemented to ensure that the thickness of the multiple wiring layers is consistent in the thickness direction.

[0006] First, the wiring section is composed of a pad structure comprising three metal layers (a first metal layer, a second metal layer, and a third metal layer). The first, second, and third metal layers are arranged in this order from bottom to top. During the formation of the pad structure, firstly, a first metal layer is formed as a seed layer on the inner wall of a via formed in an insulating layer and on the surface of other wiring layers exposed at the lower end of the via. Next, a second metal layer is formed on the first metal layer. Furthermore, the second metal layer is thinned such that its entire upper surface is covered by the second metal layer, which has a constant thickness. Then, the third metal layer is formed on the second metal layer.

[0007] Patent Document 1: Japanese Patent Application Publication No. 2020-155631 Summary of the Invention The problem that the invention aims to solve As with the wiring substrate described above, if the pad structure connecting the semiconductor chip can be formed by multiple metal layers, and the thickness of a portion of these metal layers can be accurately uniformized through thinning, then the deviation in the height position of multiple terminals can be reduced. However, thinning such metal layers requires high-precision etching, polishing, or chemical mechanical polishing, leading to an increase in the number of manufacturing steps.

[0008] Furthermore, in the manufacturing method of the wiring substrate described in Patent Document 1, the thickness of the second metal layer is adjusted, but the thickness of the third metal layer is not adjusted. Therefore, in practice, the thickness of the third metal layer may deviate during its formation.

[0009] The object of the present invention is to provide a wiring circuit board and a method thereof that can suppress the increase of the number of manufacturing steps and make the height position of the terminal portions formed on multiple vias uniform.

[0010] Technical solutions for solving the problem According to one aspect of the present invention, a wiring circuit board comprises: a first insulating layer having a first surface and a second surface facing opposite directions in the thickness direction, and having a first through hole and a second through hole respectively penetrating from the first surface to the second surface; a first via portion disposed inside the first through hole of the first insulating layer; and a second via portion disposed inside the second through hole of the first insulating layer, wherein at least a portion of the inner peripheral surface of the first through hole forms a first angle with the first surface and at least a portion of the inner peripheral surface of the second through hole forms a second angle with the first surface, which are different from each other.

[0011] According to another aspect of the present invention, a semiconductor packaging substrate includes the wiring circuit substrate described above.

[0012] An electronic device according to another aspect of the present invention includes the above-described semiconductor packaging substrate.

[0013] A method for manufacturing a wiring circuit board according to another aspect of the present invention includes: a step of forming a first insulating layer having a first surface and a second surface facing opposite directions in the thickness direction, and having a first through hole and a second through hole respectively penetrating from the first surface to the second surface; and a step of forming a first via portion inside the first through hole of the first insulating layer by plating, and forming a second via portion inside the second through hole of the first insulating layer by plating, wherein at least a portion of the inner peripheral surface of the first through hole forms a first angle with the first surface and at least a portion of the inner peripheral surface of the second through hole forms a second angle with the first surface, wherein at least a portion of the inner peripheral surface of the second through hole forms a second angle with the first surface.

[0014] Invention Effects According to the present invention, it is possible to suppress the increase in the number of manufacturing steps and to uniformly position the height of the terminal portions formed on multiple vias. Furthermore, it is possible to obtain a semiconductor packaging substrate and an electronic device with high reliability. Attached Figure Description

[0015] Figure 1 This is a longitudinal sectional view of a redistribution substrate according to an embodiment of the present invention.

[0016] Figure 2 yes Figure 1 Top view of the redistribution substrate.

[0017] Figure 3 yes Figure 1 A bottom view of the redistribution substrate.

[0018] Figure 4 This is a diagram used to illustrate the shape deviations of the terminal forming portions of multiple third conductor layers.

[0019] Figure 5 It is a diagram used to illustrate the shape of the through hole and the growth tendency of the coating formed in the through hole.

[0020] Figure 6 It is a diagram used to illustrate the shape of the through hole and the growth tendency of the coating formed in the through hole.

[0021] Figure 7 It is a longitudinal sectional view showing the shape of two through holes formed with different sizes in a redistribution substrate and the two third conductor layers generated inside them.

[0022] Figure 8 This is a schematic side view showing an example of a roll-to-roll device used in the manufacturing process of a redistribution board.

[0023] Figure 9 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0024] Figure 10 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0025] Figure 11 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0026] Figure 12 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0027] Figure 13 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0028] Figure 14 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0029] Figure 15 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0030] Figure 16 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0031] Figure 17 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0032] Figure 18 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0033] Figure 19 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate.

[0034] Figure 20 This is a diagram illustrating the exposure conditions of a temporary insulating layer that affect the cone angle of each through-hole formed in the first insulating layer.

[0035] Figure 21 This is a diagram illustrating the exposure conditions of a temporary insulating layer that affect the cone angle of each through-hole formed in the first insulating layer.

[0036] Figure 22 This is a diagram representing an example of a mask that contains multiple masks.

[0037] Figure 23 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0038] Figure 24 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0039] Figure 25 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0040] Figure 26 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0041] Figure 27 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0042] Figure 28 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0043] Figure 29 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0044] Figure 30 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0045] Figure 31 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0046] Figure 32 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0047] Figure 33 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0048] Figure 34 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0049] Figure 35 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0050] Figure 36 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0051] Figure 37 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate according to other embodiments.

[0052] Figure 38 This is a longitudinal sectional view showing a structural example of a redistribution substrate involved in the reference method. Detailed Implementation

[0053] Hereinafter, a wiring circuit board, a semiconductor packaging substrate, an electronic device, and a method for manufacturing a wiring circuit board according to an embodiment of the present invention will be described with reference to the accompanying drawings. As an example of a wiring circuit board, a rewiring board will be described. The rewiring board is disposed, for example, between electronic components such as semiconductor elements and other wiring circuit boards such as rigid printed wiring circuit boards (hereinafter referred to as rigid boards), and serves to convert the pitch of the fine patterns of the electronic components with the coarse patterns of other wiring circuit boards. The rewiring board is also referred to as an interposer substrate.

[0054] 1. Basic structure of redistribution substrate Figure 1 This is a longitudinal sectional view of a redistribution substrate according to an embodiment of the present invention. Figure 2 yes Figure 1 A top view of the redistribution substrate 100. Figure 3 yes Figure 1 Bottom view of the redistribution substrate 100. Figure 1 express Figure 2 as well as Figure 3 The AA line profile. For example... Figure 1 As shown, the redistribution substrate 100 has a first surface (upper surface in this example) 101 and a second surface (lower surface in this example) 102 that face opposite directions in its thickness direction DT. Figure 1 In the diagram, the thickness direction DT of the redistribution substrate 100 is indicated by an upward arrow. In the following description, in... Figure 1 In the redistribution substrate 100, the direction in which the first surface 101 faces is appropriately referred to as the upper part of the redistribution substrate 100, and the direction in which the second surface 102 faces is appropriately referred to as the lower part of the redistribution substrate 100.

[0055] A redistribution substrate 100 is disposed between a semiconductor chip 200 and a rigid substrate 300 along its thickness direction DT. A plurality of terminal portions T1 are formed on a first surface 101. The semiconductor chip 200 has a counter surface 211 that faces the redistribution substrate 100 when mounted on it. Additionally, the semiconductor chip 200 has a plurality of columnar bonding portions 220 formed protruding a certain length from the counter surface 211. The front ends of the columnar bonding portions 220 constitute connection terminals of the semiconductor chip 200 and are bonded to the corresponding terminal portions T1 of the redistribution substrate 100 via solder S.

[0056] A bottom filler 290 is filled between the opposing surface 211 of the semiconductor chip 200 and the first surface 101 of the redistribution substrate 100. The bottom filler 290 is, for example, formed of epoxy resin. Alternatively, a cover member (not shown) covering the semiconductor chip 200 may be provided on the first surface 101 of the redistribution substrate 100.Figure 1 as well as Figure 2 In the diagram, a single-dot dashed line represents the semiconductor chip 200. The semiconductor element 200 is mounted on the first surface 101 of the redistribution substrate 100 and further sealed with resin, thereby forming a semiconductor packaging substrate 400.

[0057] Examples of semiconductor packaging include FC-CSP (Flip Chip-Chip Scale Package), MIS-BGA (Molded Interconnect Substrate-Ball Grid Array) packaging, ETS-BGA (Embedded Trace Substrate-Ball Grid Array) packaging, Fan-out WLP (Wafer Level Package), Fan-in WLP, Fan-out PLP (Panel Level Package), Fan-in PLP, FC-BGA (Flip Chip-Chip, Ball Grid Array), and high-end 2.5D and 3D packaging.

[0058] A plurality of terminal portions T2 are formed on the second surface 102 of the redistribution substrate 100. The terminal portions T2 are circular in shape. The terminal portions T2 are larger than the terminal portions T1. The rigid substrate 300 has a plurality of electrode pads 301 serving as multiple connection terminals of the rigid substrate 300. The electrode pads 301 are bonded to the corresponding terminal portions T2 of the redistribution substrate 100 via solder S. Figures 1-3 In the diagram, a double-dotted line represents the rigid substrate 300. For example... Figure 1 As shown by the thick dashed line, the semiconductor packaging substrate 400 is assembled to the electronic device 800, for example, by being mounted on a rigid substrate 300. In this embodiment, the electronic device 800 is, for example, a mobile terminal such as a smartphone, tablet, or wearable device. Alternatively, the electronic device 800 is, for example, a stationary or laptop-type personal computer.

[0059] It should be noted that in this embodiment, solder balls are provided on a plurality of terminal portions T2 of the redistribution substrate 100. As a result, a BGA (Ball Grid Array) is formed, for example, on the second surface 102 of the redistribution substrate 100.

[0060] The redistribution substrate 100 is mainly composed of a support layer 10, multiple insulating layers, and multiple conductor layers. The support layer 10 has higher rigidity than the multiple insulating layers. In addition, the support layer 10 is located approximately at the center of the redistribution substrate 100 in the thickness direction DT and has a third surface s1 and a fourth surface s2 facing opposite directions in the thickness direction DT. The third surface s1 is opposite to the first surface 101, and the fourth surface s2 is opposite to the second surface 102.

[0061] Specifically, the support layer 10 involved in this embodiment includes a metal support body 110 and an insulating coating layer 120. The metal support body 110 has a fifth surface 110a and a sixth surface 110b facing opposite directions. Circular through holes are formed in a plurality of portions of the metal support body 110.

[0062] The metal support 110 is made of, for example, stainless steel. It should be noted that the metal support 110 may also be made of any of copper, copper alloys, aluminum, titanium, or alloys containing iron and nickel, instead of stainless steel. Examples of alloys containing iron and nickel include Invar, Alloy 42, Permalloy 45, and Kova alloy. The thickness of the metal support 110 is 10 μm or more and 100 μm or less.

[0063] The insulating coating layer 120 is formed to cover the fifth surface 110a and the sixth surface 110b of the metal support 110, and to cover the inner peripheral surface of the plurality of through holes of the metal support 110. In a plurality of portions of the support layer 10, a plurality of circular through holes are formed such that they pass through the plurality of through holes of the metal support 110 in the thickness direction DT.

[0064] The insulating coating 120 is formed, for example, of a photosensitive polyimide, having a thickness of 3 μm or more and 20 μm or less. It should be noted that the insulating coating 120 may also be formed of other photosensitive materials instead of photosensitive polyimide. Examples of such other photosensitive materials include, for instance, photosensitive resins such as acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, or polyvinyl chloride resin.

[0065] Materials other than photosensitive materials can be used as the material for the insulating coating layer 120. For example, inorganic or organic insulating materials can be used as the material for the insulating coating layer 120. Specifically, silicon carbide, silicon dioxide, aluminum nitride, or aluminum oxide can also be used as the material for the insulating coating layer 120.

[0066] Figure 1 The redistribution substrate 100 includes five insulating layers. Three of the five insulating layers are stacked and formed on the third surface s1 of the support layer 10. The remaining two of the four insulating layers are stacked and formed on the fourth surface s2 of the support layer 10. In the following description, the components are...Figure 1 When the five insulating layers of the redistribution substrate 100 are distinguished, they are referred to as the cover insulating layer 40, the first insulating layer 50, the second insulating layer 60, the third insulating layer 70, and the fourth insulating layer 80. The second insulating layer 60, the first insulating layer 50, and the cover insulating layer 40 are stacked upwards from the third surface s1 of the support layer 10 in this order. The third insulating layer 70 and the fourth insulating layer 80 are stacked downwards from the fourth surface s2 of the support layer 10 in this order.

[0067] Five insulating layers (40, 50, 60, 70, 80) are each formed of a photosensitive material. For example, photosensitive polyimide is used as the photosensitive material for the five insulating layers (40, 50, 60, 70, 80). It should be noted that the insulating layers (40, 50, 60, 70, 80) can also be formed of other photosensitive resins (acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, or polyvinyl chloride resin, etc.) instead of photosensitive polyimide. The thickness of each insulating layer (40, 50, 60, 70, 80) is 3 μm or more and 20 μm or less.

[0068] The multiple conductor layers include multiple first conductor layers 1, multiple second conductor layers 2, multiple third conductor layers 3, and multiple fourth conductor layers 4. Figure 1 In the example, multiple first conductor layers 1 are formed in such a way that they correspond to multiple through holes in the support layer 10. Each first conductor layer 1 includes a portion (via portion) that extends along the thickness direction DT through the through hole in the corresponding support layer 10, and portions (wiring portions) that are formed in a given pattern on the third surface s1 and the fourth surface s2, respectively.

[0069] The second insulating layer 60 is formed on the third surface s1 of the support layer 10 in such a way that it covers the portion of the plurality of first conductor layers 1 located on the third surface s1 of the support layer 10. The second insulating layer 60 has a plurality of (three in this example) circular through holes extending along the thickness direction DT as vias. One end of each through hole (in...) Figure 1 In the example, the lower end is located on multiple first conductor layers 1.

[0070] A plurality of second conductor layers 2 (five in this example) are formed in a manner corresponding to the second insulating layer 60. A portion of the plurality of second conductor layers 2 is formed on the second insulating layer 60 as a wiring portion in a given pattern. On the other hand, the remaining portions of the plurality of second conductor layers 2 include portions extending along the thickness direction DT through through holes in the second insulating layer 60 (via portions), and portions formed on the second insulating layer 60 in a given pattern (wiring portions).

[0071] A first insulating layer 50 is formed on a second insulating layer 60 such that it covers a plurality of second conductor layers 2. A plurality of circular through holes (three in this example) extending along the thickness direction DT are formed in the first insulating layer 50 as through holes. One end of each through hole (in...) Figure 1 In the example, the lower end is located on multiple second conductor layers 2.

[0072] Multiple third conductor layers 3 are formed as vias by filling multiple through holes in the first insulating layer 50. In a portion of the multiple third conductor layers 3 (in... Figure 1 In the example, the upper end portion has multiple terminal portions T1. Each terminal portion T1 can be formed by a portion of the third conductor layer 3, or by performing a surface treatment on that portion of the third conductor layer 3. For example, each terminal portion T1 can also be formed by growing a plating of a metal with excellent corrosion resistance, such as gold, on a portion of the third conductor layer 3.

[0073] An insulating layer 40 is formed on a first insulating layer 50 such that multiple terminal portions T1 are exposed upwards and a portion of multiple third conductor layers 3 is covered, thereby protecting the third conductor layers 3 formed on the first insulating layer 50. One side (upper surface) of the insulating layer 40 is exposed outside the redistribution substrate 100. This side of the insulating layer 40 forms the first surface 101 of the redistribution substrate 100.

[0074] The third insulating layer 70 is formed on the fourth surface s2 of the support layer 10 in such a way that it covers the portion of the plurality of first conductor layers 1 located on the fourth surface s2 of the support layer 10. A plurality of circular through holes (two in this example) extending along the thickness direction DT are formed in the third insulating layer 70 as through holes. One end of each through hole (in...) Figure 1 In the example, the upper end is located on multiple first conductor layers 1.

[0075] Multiple fourth conductor layers 4 are formed as vias by filling multiple through holes in the third insulating layer 70. In a portion of the multiple fourth conductor layers 4 (in... Figure 1 In the example, the lower end has multiple terminal portions T2. Each terminal portion T2 can be formed from this portion of the fourth conductor layer 4, or it can be formed by performing a surface treatment on this portion of the fourth conductor layer 4. For example, each terminal portion T2 can also be formed by growing a plating of a metal with excellent corrosion resistance, such as gold, on a portion of the fourth conductor layer 4.

[0076] A fourth insulating layer 80 is formed on the third insulating layer 70 such that multiple terminal portions T2 are exposed downwards and a portion of multiple fourth conductor layers 4 are covered, and functions as a covering insulating layer to protect the fourth conductor layers 4 formed on the third insulating layer 70. One side (lower surface) of the fourth insulating layer 80 is exposed outside the redistribution substrate 100. This side of the fourth insulating layer 80 forms the second surface 102 of the redistribution substrate 100.

[0077] The aforementioned conductor layers (1, 2, 3, 4) are formed by growing a plating layer on the seed layer using an electrolytic plating method. The seed layer forming the conductor layer is, for example, composed of a chromium thin film and a copper thin film. Alternatively, the seed layer may be composed of a copper thin film. Alternatively, the seed layer may also contain either nickel or palladium. On the other hand, the plating layer is formed of one or more metals or alloys containing copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, and ruthenium. In this embodiment, the plating layer is copper.

[0078] The thickness of the portions (wiring portions) of the plurality of first conductor layers 1 formed on the third surface s1 and the fourth surface s2 of the support layer 10 is 3 μm or more and 10 μm or less. In addition, the thickness of the portions (wiring portions) of the plurality of conductor layers (2, 3, 4) formed on the surface of any one of the four insulating layers (50, 60, 70, 80) is 3 μm or more and 10 μm or less.

[0079] It should be noted that in this embodiment, the number of multiple terminal portions T1 located on the first surface 101 of the redistribution substrate 100 is the same as the number of multiple terminal portions T2 located on the second surface 102 of the redistribution substrate 100, but the present invention is not limited thereto. The number of multiple terminal portions T1 located on the first surface 101 of the redistribution substrate 100 and the number of multiple terminal portions T2 located on the second surface 102 of the redistribution substrate 100 may also be different.

[0080] 2. Deviation in height position of the multiple terminals T1 connected to the semiconductor chip 200 In the following description, the position of each portion of the redistribution substrate 100 in the thickness direction DT is appropriately referred to as the height position of that portion. Figure 1 In the redistribution substrate 100, a semiconductor chip 200 is mounted on its first surface 101. Therefore, as explained in the background art, if there is a large deviation in the height position of the multiple terminal portions T1, the reliability of the electrical connection between the semiconductor chip 200 and the redistribution substrate 100 cannot be ensured.

[0081] Multiple terminal portions T1 are formed on predetermined surface portions (hereinafter referred to as terminal forming portions) in the third conductor layer 3. In this embodiment, the terminal forming portion is provided at the center of the upper end surface of the third conductor layer 3. In this case, the deviation in the height position of the multiple terminal portions T1 is caused by the deviation in the shape (height position deviation) of the multiple terminal forming portions of the third conductor layer 3.

[0082] Figure 4 This is a diagram illustrating the shape deviations of the terminal forming portions of the multiple third conductor layers 3. Figure 4 The top section, shown in a longitudinal sectional view, may have been formed in Figure 1 An example of the shape of the third conductor layer 3 of the redistribution substrate 100. This third conductor layer 3 is formed on the second conductor layer 2 formed on the second insulating layer 60, by filling the through-holes THe of the first insulating layer 50. Furthermore, in Figure 4 In the example of the uppermost section, the height position HP of the terminal forming part 3T is located above the distance d1 from the first surface 101, and the upper end surface of the third conductor layer 3 is generally flat.

[0083] Here, as described above, the third conductor layer 3 is formed by electrolytic plating. Therefore, between the multiple third conductor layers 3 located in mutually separated positions, shape deviations occur due to deviations in plating processing conditions, such as deviations in the concentration distribution of various components in the plating solution in the plating bath or deviations in the distribution of electric field lines in the plating bath.

[0084] For example, consider a case where the degree of plating growth within a through-hole THe of the first insulating layer 50 is locally low due to deviations in the plating process conditions. In this case, such as Figure 4 As shown in the longitudinal sectional view of the second segment from the top, the height position HP of the terminal forming portion 3T of the third conductor layer 3 formed by the through hole THE may become lower than the first surface 101 of the first insulating layer 50.

[0085] Furthermore, consider the case where, due to deviations in the plating processing conditions, the degree of plating growth is locally higher within a through-hole THe of the first insulating layer 50. In this case, such as... Figure 4 As shown in the longitudinal sectional view of the third segment from the top, the height position HP of the terminal forming portion 3T of the third conductor layer 3 formed by the through hole THE may become significantly higher than the first surface 101 of the first insulating layer 50. Figure 4 In the example of the third longitudinal sectional view from the top, the height position HP of the terminal forming portion 3T is located above the first surface 101 at a distance d2. The distance d2 is greater than the distance d1 shown in the example of the topmost section.

[0086] The shape deviations among the multiple third conductor layers 3 arise not only from the plating process conditions but also from the shapes of the multiple second conductor layers 2 formed beneath each of the multiple third conductor layers 3. For example, as Figure 4 As shown in the bottom paragraph, consider the case where the second conductor layer 2 disposed below the third conductor layer 3 is a via. In this case, the shape of the third conductor layer 3 may differ from the shape of other third conductor layers 3 formed on the second conductor layer 2 that do not constitute vias.

[0087] However, regarding the shape deviations that may occur between the multiple third conductor layers 3 as described above, these deviations can be controlled to some extent for each of the multiple third conductor layers 3 in the redistribution substrate 100 through prior simulation or experimentation. Furthermore, when using the electroplating method as described above, the degree of plating growth within each through-hole THe of the first insulating layer 50 can be adjusted according to the shape of the through-hole THe. Therefore, the inventors have devised a method in which, based on prior knowledge of the shape deviations that may occur between the multiple third conductor layers 3 of the redistribution substrate 100, the shape of each of the multiple through-holes THe is set so that the occurrence of these deviations is reduced while plating grows.

[0088] Figure 5 as well as Figure 6 This is a diagram used to illustrate the shape of the through-hole THe and the growth tendency of the coating formed in the through-hole THe. Figure 5 as well as Figure 6 The diagram shows multiple longitudinal sectional views of a through-hole THe in the redistribution substrate 100 and its surrounding portion. In these longitudinal sectional views, the diagram of the covering insulating layer 40 is omitted for ease of understanding of the shape of the through-hole THe. Figure 5 As shown in the longitudinal sectional view of the upper section, for example in a longitudinal section parallel to the thickness direction DT of the redistribution substrate 100, the angle (hereinafter referred to as the cone angle) α between the inner peripheral surface of the through hole THe and one side (upper or lower surface) of the first insulating layer 50 is considered.

[0089] In this case, the growth of the coating formed inside a through-hole THe tends to decrease as the cone angle α decreases. Therefore, if the cone angle α is set relatively small for a through-hole THe, then... Figure 5 As shown in the longitudinal sectional view of the middle section, the height HP at the terminal forming portion 3T of the third conductor layer 3 formed in the through-hole THe tends to be lower. On the other hand, the growth degree of the plating layer formed inside the through-hole THe tends to be higher as the taper angle α increases. Therefore, if the taper angle α is set to be large for a through-hole THe, then as... Figure 5As shown in the lower longitudinal sectional view, HP tends to be higher at the height of the terminal forming portion 3T of the third conductor layer 3 formed by the through hole THE.

[0090] In addition, such as Figure 6 As shown in the longitudinal sectional view of the upper section, for example in a longitudinal section parallel to the thickness direction DT of the redistribution substrate 100, the dimensions of the bottom of the through-holes THe are considered. Specifically, the bottom opening of each through-hole THe is closed by the second conductor layer 2. The dimension of the inner diameter of this bottom opening (hereinafter referred to as the bottom dimension) BD is considered.

[0091] In this case, the growth degree of the coating formed inside a through-hole THe tends to be higher as the bottom dimension BD becomes smaller. Therefore, if the bottom dimension BD is set to be smaller for a through-hole THe, then as... Figure 6 As shown in the longitudinal sectional view of the middle section, HP tends to be higher at the height of the terminal forming portion 3T of the third conductor layer 3 formed in the through-hole THe. On the other hand, the growth degree of the plating layer formed inside a through-hole THe tends to be lower as the bottom dimension BD increases. Therefore, if the bottom dimension BD is set to be large for a through-hole THe, then as... Figure 6 As shown in the lower longitudinal sectional view, HP tends to decrease at the height of the terminal forming portion 3T of the third conductor layer 3 formed by the through hole THE.

[0092] In view of the above aspects, in the redistribution substrate 100 according to this embodiment, a cone angle α and a bottom dimension BD are respectively set for the plurality of through holes THe in the first insulating layer 50. It should be noted that in the redistribution substrate 100 according to this embodiment, the cone angle α of each of the plurality of through holes THe is preferably set to 55° or more, more preferably set to 60° or more, and even more preferably set to 65° or more.

[0093] Figure 7 This is a longitudinal sectional view showing the shapes of two through-holes THe formed with different dimensions in the redistribution substrate 100 and the two third conductor layers 3 formed inside them. Figure 7 In the middle, a longitudinal cross-sectional view showing the entire redistribution substrate 100. Figure 1 The dialog box then zooms in to show a portion of the longitudinal section view (the part with the thick dashed line). Figure 7 In the description, as shown in the dialog box, a through-hole THe on the second conductor layer 2 where a via is formed is appropriately referred to as the first through-hole TH1, and other through-holes THe on the second conductor layer 2 where no via is formed are appropriately referred to as the second through-hole TH2.

[0094] Before fabricating the redistribution substrate 100 in this example, potential shape deviations in the multiple third conductor layers 3 of the redistribution substrate 100 were determined through prior simulations or experiments. Based on this, the cone angle α and bottom dimension BD of the multiple through-holes THe were set according to prior information obtained through simulations or experiments, so as to reduce these shape deviations. Here, the prior information included "the height position HP of the terminal portion T1 on the second conductor layer 2 where the via is formed tends to be higher than the height position HP of the terminal portion T1 on the second conductor layer 2 where the via is not formed".

[0095] exist Figure 7 In the example of the first insulating layer 50, two adjacent vias THe are formed with different cone angles α and bottom dimensions BD. Specifically, the cone angle α1 of the first via TH1 on the second conductor layer 2 forming the via is larger than the cone angle α2 of the second via TH2 on the other second conductor layer 2 where no via is formed. In addition, the bottom dimension BD1 of the first via TH1 on the second conductor layer 2 forming the via is smaller than the bottom dimension BD2 of the second via TH2 on the other second conductor layer 2 where no via is formed.

[0096] In this case, during the formation of multiple third conductor layers 3, the growth degree of the third conductor layer 3 formed in the first through-hole TH1 is higher than that of the third conductor layer 3 formed in the second through-hole TH2. As a result, the height position HP of the terminal forming portion 3T of the two third conductor layers 3 formed in the two through-holes THe (the first through-hole TH1 and the second through-hole TH2) is ultimately adjusted to be equal to each other.

[0097] 3. Method for manufacturing the redistribution substrate 100 In this embodiment, the redistribution substrate 100 is manufactured, for example, by a roll-to-roll method. Figure 8 This is a schematic side view showing an example of a roll-to-roll device 500 used in the manufacturing process of the redistribution substrate 100.

[0098] like Figure 8 As shown, the roll-to-roll device 500 includes an unwinding section 501, a winding section 502, and multiple processing sections 510, 520, ... First, a roll (feeding roll) R1 with a long strip of metal support 110 wound on it is prepared and placed in the unwinding section 501 of the roll-to-roll device 500.

[0099] The metal support 110 is fed out from the prepared feed roller R1. The fed metal support 110 is as follows: Figure 8 As indicated by the dashed arrow, the winding is performed on another roller (winding roller) R2 provided in the winding section 502.

[0100] In the roll-to-roll assembly 500, multiple processing units 510, 520, ... are arranged between two rolls (R1, R2) in a manner that follows the moving direction of the metal support 110. The multiple processing units 510, 520, ... form an insulating coating layer 120 on the elongated metal support 110 that moves between the two rolls (R1, R2). Furthermore, the aforementioned multiple insulating layers and multiple conductor layers are formed in each region of the metal support 110 on which the insulating coating layer 120 is formed. Thus, multiple redistribution substrates 100 are formed on the metal support 110 wound onto the take-up roll R2. The manufacturing method of the redistribution substrate 100 will be described in detail below.

[0101] Figures 9-19 It is used for explanation Figure 1 A schematic cross-sectional view of an example of a method for manufacturing a redistribution substrate 100. Figures 9-19 The schematic cross-sectional view shown is Figure 1 The schematic cross-sectional view corresponds to the redistribution substrate 100. Figures 9-19 The figures show Figure 1 DT in the thickness direction.

[0102] As described above, the feed roller R1, on which the metal support 110 is prepared, is... Figure 8 The metal support 110 is fed out from the feed roller R1. Figure 9 The image shows a cross-section of a portion of the delivered metal support 110. As described above, the metal support 110 has a fifth surface 110a and a sixth surface 110b that are oriented in opposite directions in the thickness direction DT.

[0103] First, a photosensitive polyimide precursor is coated onto the sixth surface 110b of the metal support 110, covering the entire surface. Then, the coated photosensitive polyimide precursor is exposed and developed. Thus, as... Figure 10 As shown, a first temporary coating layer 121 is formed on the sixth surface 110b of the metal support 110. The formed first temporary coating layer 121 is then cured. It should be noted that the first temporary coating layer 121 can also be formed by attaching a carrier film made of photosensitive polyimide to the sixth surface 110b instead of coating the precursor of photosensitive polyimide.

[0104] Next, an etching resist with a given pattern is formed on the fifth surface 110a of the metal support 110. Furthermore, the portion of the fifth surface 110a of the metal support 110 exposed through the openings in the etching resist is etched. Afterward, the etching resist is peeled off from the metal support 110. Thus, as... Figure 11 As shown, multiple through holes THa are formed in the metal support 110.

[0105] As described above, the metal support 110 is etched from the fifth surface 110a toward the sixth surface 110b. In this case, each through-hole THa is formed such that its inner diameter gradually decreases from the fifth surface 110a toward the sixth surface 110b. The etching solution used in the etching of the metal support 110 does not dissolve the first temporary coating layer 121. Therefore, one end of each through-hole THa is closed by the first temporary coating layer 121.

[0106] It should be noted that the plurality of through holes THa of the metal support 110 are not limited to being formed by etching, but may also be formed by laser processing, for example. In this case, the laser irradiates the metal support 110 in a manner that travels from the fifth surface 110a toward the sixth surface 110b and does not penetrate the first temporary coating layer 121.

[0107] Next, a photosensitive polyimide precursor is coated onto the fifth surface 110a, covering the entire fifth surface 110a of the metal support 110 and extending into the interior of each through-hole THa. The coated photosensitive polyimide precursor is then exposed and developed. Thus, as... Figure 12 As shown, a second temporary coating layer 122 is formed by covering the fifth surface 110a of the metal support 110 and the inner peripheral surface of the plurality of through holes THa, and by filling the plurality of through holes THa. The formed second temporary coating layer 122 is then cured. It should be noted that, similarly to the first temporary coating layer 121, the second temporary coating layer 122 can also be formed by attaching a carrier film made of photosensitive polyimide to the fifth surface 110a instead of coating a precursor of photosensitive polyimide.

[0108] After that, as Figure 13 As shown, multiple through holes THb are formed in multiple portions of the metal support 110, extending through the interior of each through hole THa and along the thickness direction DT. These multiple through holes THb are formed, for example, by etching or laser processing. In this way, the support layer 10 is completed.

[0109] Next, a seed layer is formed in a predetermined region on the third surface s1 of the support layer 10, a predetermined region on the fourth surface s2 of the support layer 10, and the inner peripheral surface of the through hole THb, and a plating layer is formed on the seed layer. Thus, as... Figure 14 As shown, multiple first conductor layers 1 are formed inside the main through-holes THb.

[0110] Next, as Figure 15As shown, a second insulating layer 60 is formed on the third surface s1 of the support layer 10, covering the portions of the plurality of first conductor layers 1 exposed on the third surface s1. At this time, a plurality of through-holes THc are formed in the second insulating layer 60, with portions of the upper ends of the plurality of first conductor layers 1 exposed upwards. Furthermore, a third insulating layer 70 is formed on the fourth surface s2 of the support layer 10, covering the portions of the plurality of first conductor layers 1 exposed on the fourth surface s2. At this time, a plurality of through-holes THd are formed in the third insulating layer 70, with portions of the lower ends of the plurality of first conductor layers 1 exposed downwards. In this embodiment, the second insulating layer 60 and the third insulating layer 70 are formed of a photosensitive material. Therefore, photolithography is used in the formation of these second insulating layers 60 and the third insulating layer 70.

[0111] Next, seed layers are formed in predetermined areas on the exposed surface of the second insulating layer 60 and in predetermined areas on the exposed surface of the third insulating layer 70. Additionally, seed layers are formed on the inner peripheral surfaces of the plurality of through holes THc and THd and in exposed portions of the plurality of first conductor layers 1. A plating layer is formed on the formed seed layers. Thus, as... Figure 16 As shown, multiple second conductor layers 2 and multiple fourth conductor layers 4 are formed. A portion of the multiple second conductor layers 2 (via portions) is buried in multiple through-holes THc formed in the second insulating layer 60. Another portion of the multiple second conductor layers 2 (wiring portions) is formed on the second insulating layer 60 in a given pattern. Multiple fourth conductor layers 4 are buried in multiple through-holes THd formed in the third insulating layer 70.

[0112] Next, as Figure 17 As shown, a first insulating layer 50 is formed on a second insulating layer 60 to cover the portions of the plurality of second conductor layers 2 exposed on the second insulating layer 60. At this time, a plurality of through-holes THe are formed in the first insulating layer 50 such that a portion of the upper end of the plurality of second conductor layers 2 is exposed upwards. Furthermore, a fourth insulating layer 80 is formed on a third insulating layer 70 to cover the portions of the plurality of fourth conductor layers 4 exposed on the third insulating layer 70. At this time, a plurality of through-holes THf are formed in the fourth insulating layer 80 such that a portion of the lower end of the plurality of fourth conductor layers 4 is exposed downwards. In this embodiment, the first insulating layer 50 and the fourth insulating layer 80 are formed of a photosensitive material. Therefore, photolithography is used in the formation of these first insulating layers 50 and fourth insulating layers 80.

[0113] In the first insulating layer 50 of this embodiment, as described above, in order to reduce the deviation in the height position of the plurality of terminal portions T1, the cone angle α and bottom dimension BD of each of the plurality of through holes THe are individually set. Therefore, during the formation of the first insulating layer 50, the photolithography processing conditions are adjusted so that the cone angle α and bottom dimension BD of each of the plurality of through holes THe are values ​​set corresponding to the through hole THe. The adjustment of the photolithography processing conditions will be described later.

[0114] Next, a seed layer is formed in a predetermined area on the first insulating layer 50. Additionally, seed layers are formed on the inner peripheral surfaces of the plurality of through-holes THe and on the exposed portions of the plurality of second conductor layers 2. A plating layer is then formed on the formed seed layer. Thus, as... Figure 18 As shown, multiple third conductor layers 3 are formed inside the main through-holes THb.

[0115] Next, as Figure 19 As shown, a covering insulating layer 40 is formed on the first insulating layer 50 to cover the portions of the plurality of third conductor layers 3 that are exposed on the first insulating layer 50. At this time, a plurality of through holes THe are formed in the covering insulating layer 40 such that a portion of the upper end of the plurality of third conductor layers 3 is exposed upwards. In this state, each of the plurality of third conductor layers 3 has an upwardly exposed terminal forming portion 3T. Figure 4 (etc.). It should be noted that the insulating cover 40 is formed of a photosensitive material. Therefore, photolithography is used in the formation of the insulating cover 40.

[0116] Finally, multiple terminal portions T1 are formed on the terminal forming portions 3T of the multiple third conductor layers 3. Additionally, multiple terminal portions T2 are formed on the portions of the multiple fourth conductor layers 4 exposed through the multiple through holes THf. Thus, the process is completed. Figure 1 The redistribution substrate 100.

[0117] 4. Adjustment of photolithography processing conditions corresponding to the shape of the through-hole THe When the first insulating layer 50 is formed using photolithography, Figure 16 A precursor of a photosensitive material (in this example, photosensitive polyimide) is coated onto the second insulating layer 60. Alternatively, in Figure 16 A carrier film containing a precursor of the photosensitive material is adhered to the second insulating layer 60. Thus, the layer containing the precursor of the photosensitive material formed on the second insulating layer 60 is called a temporary insulating layer.

[0118] Then, exposure light is irradiated onto the temporary insulating layer from the light source located above the second insulating layer 60 through a mask with a light-transmitting portion formed with a given pattern. As a result, the temporary insulating layer is exposed with a pattern opposite to the pattern of the light-transmitting portion of the mask. Furthermore, the exposed temporary insulating layer is developed to form the first insulating layer 50.

[0119] The shapes of each part of the through hole (THe) Figure 5 The cone angle α and Figure 6 The bottom dimension (BD, etc.) is one of the processing conditions for photolithography, and can be adjusted by appropriately setting the exposure processing conditions of the temporary insulating layer.

[0120] The bottom size BD of each through-hole THe formed in the first insulating layer 50 is determined according to the size of the pattern of the exposure light irradiating the temporary insulating layer. Therefore, when forming the first insulating layer 50, a mask with a pattern of multiple light-transmitting portions having multiple sizes corresponding to the bottom sizes BD of the multiple through-holes THe is used. As a result, multiple through-holes THe with different bottom sizes BD can be formed in a single exposure process.

[0121] Next, the cone angle α of each through hole THe formed in the first insulating layer 50 will be explained. Figure 20 and Figure 21 This diagram illustrates the exposure conditions of the temporary insulating layer that affect the cone angle α of each through-hole THe formed in the first insulating layer 50. Figure 20 The diagram schematically illustrates the structure used for the 50x exposure process of the temporary insulating layer. Figure 20 As shown, when the temporary insulating layer 50x is irradiated with exposure light EL in a given pattern, a mask 610 is arranged above the temporary insulating layer 50x at a predetermined distance. Alternatively, the mask 610 is arranged in contact with the upper surface of the temporary insulating layer 50x.

[0122] Furthermore, a light source unit 600 is positioned above the mask 610 at a predetermined distance. The light source unit 600 includes a light generating unit that generates exposure light EL, various optical systems that guide and converge the exposure light EL toward the mask 610, and various driving units for adjusting the emission direction and focus of the exposure light EL.

[0123] Here, in the photolithography exposure process described above, the angle at which the light source section 600 is viewed from the mask 610 can be expressed as the collimation half-angle β. The collimation half-angle β is also called the viewing angle. Furthermore, in the following explanation, the distance between the mask and the temporary insulating layer is referred to as the mask distance MD.

[0124] The cone angle α of each through hole THe formed in the first insulating layer 50 is determined based on the collimation half angle β of the exposure light EL irradiating the temporary insulating layer, the mask distance MD, and the wavelength of the exposure light EL. Figure 21 The table shows a summary of the relationship between the collimation half-angle β, mask distance MD, and wavelength of the exposure light EL and the cone angle α of the through-hole THe during the exposure process.

[0125] like Figure 20 As shown in the table, the cone angle α of the through-hole THe tends to decrease as the collimation half-angle β increases, and increase as the collimation half-angle β decreases. The collimation half-angle β can be adjusted, for example, by switching the aperture or the like in the optical system of the light source unit 600. It should be noted that the collimation half-angle β can be adjusted, for example, within a range of 0.25° to 5°.

[0126] Furthermore, the cone angle α of the through hole THe tends to decrease as the mask distance MD increases and increase as the mask distance MD decreases. The mask distance MD can be adjusted by using a moving device that moves the member supporting the mask 610 relative to the member supporting the object including the temporary insulating layer 50x. It should be noted that the mask distance MD can be adjusted, for example, within a range of 0 μm or more and 250 μm or less.

[0127] Furthermore, the cone angle α of the through-hole THe tends to be larger as the wavelength of the exposure light EL decreases and smaller as the wavelength of the exposure light EL increases. Therefore, when exposure processing is performed using an exposure light EL with only the i-line emission spectrum, the cone angle α of the through-hole THe tends to be larger compared to the case where exposure processing is performed using an exposure light EL with emission spectra of g-line, h-line, and i-line. This is because the wavelength of light corresponding to the emission spectrum of i-line is shorter than the wavelength of light corresponding to the emission spectra of g-line and h-line. The wavelength of the exposure light EL can be adjusted, for example, by providing multiple light generating units that generate light in different wavelength regions in the light source unit 600 and switching the operating states of these multiple light generating units.

[0128] In the exposure process of the temporary insulating layer 50x, any one of a variety of masks, such as a grayscale mask, a halftone mask, and a phase-shift mask, can be used as the mask 610. Alternatively, a mask that combines any two or more of the aforementioned masks can be used as the mask 610.

[0129] According to the grayscale mask, the contour portion (edge ​​portion) between the illuminated and unilluminated areas of the exposure light EL in the temporary insulating layer 50x, as one of the forms of the exposure light EL, has a relatively low contrast. Therefore, the cone angle α of the through-hole THe formed by the grayscale mask tends to decrease.

[0130] On the other hand, based on the halftone mask and the phase-shift mask, the contour portion (edge ​​portion) between the illuminated and unilluminated areas of the exposure light EL in the temporary insulating layer 50x, as one of the forms of the exposure light EL, exhibits higher contrast. Therefore, the cone angle α of the through-hole THe formed by the halftone mask and the phase-shift mask tends to increase.

[0131] Figure 22 This is a diagram representing an example of a mask 610 that contains multiple masks. Figure 22 The mask 610 includes a first mask portion 611 composed of a gray-toned mask and a second mask portion 612 composed of a halftone mask. Thus, a plurality of through-holes THE with different taper angles α can be formed in multiple portions of the redistribution substrate 100 using a single mask 610. It should be noted that... Figure 22 Mask 610 is a mask corresponding to an insulating layer having positive photosensitive properties. A mask corresponding to an insulating layer having negative photosensitive properties, for example, has a... Figure 22 The mask 610 has a structure of inverted intensity.

[0132] 5. Effects (a) In the redistribution substrate 100 described above, a plurality of third conductor layers 3 are formed in such a way that a plurality of through holes THe formed in the first insulating layer 50 are filled. A terminal portion T1 is formed on the terminal forming portion 3T of each third conductor layer 3.

[0133] The third conductor layer 3 is formed inside the through-hole THe by electrolytic plating while the bottom opening of the through-hole THe is closed by the second conductor layer 2. In this case, the height position HP of the terminal forming portion 3T formed inside the through-hole THe is determined according to the shape of the through-hole THe.

[0134] Based on the above structure, the cone angle α and bottom dimension BD of each of the multiple through holes THe are adjusted to reduce the range of deviation in the height position HP of the multiple terminal forming portions 3T of the multiple third conductor layers 3. Therefore, the cone angle α and bottom dimension BD of one of the multiple through holes THe are set to be different from the cone angle α and bottom dimension BD of the other through holes THe.

[0135] By forming multiple third conductor layers 3, each with an individually set cone angle α and bottom dimension BD, the deviation in the height position HP of the terminal forming portions 3T of these multiple third conductor layers 3 is reduced. In this case, during the fabrication of the redistribution substrate 100, it is not necessary to perform etching, grinding, or cutting processes on the upper ends of the multiple third conductor layers 3 to ensure that the height positions HP of the terminal forming portions 3T are consistent. Therefore, it is possible to suppress the increase in the number of manufacturing steps and to uniformize the height positions of the multiple terminal portions T1 on the multiple third conductor layers 3. As a result, the semiconductor packaging substrate 400 and the electronic device 800 including the redistribution substrate 100 have high reliability.

[0136] (b) As described above, the first insulating layer 50 is made of a photosensitive material. Therefore, by forming the first insulating layer 50 using photolithography, a plurality of through-holes THe can be easily formed without machining. Furthermore, by adjusting the photolithography processing conditions, each of the plurality of through-holes THe can be formed according to a set size.

[0137] (c) The redistribution substrate 100 according to this embodiment is manufactured by a roll-to-roll process, and has overall flexibility. Even in this case, the redistribution substrate 100 includes a support layer 10 comprising a metal support 110. The support layer 10 has higher rigidity than the plurality of insulating layers and the plurality of conductor layers. Therefore, the structure of each part of the redistribution substrate 100 is supported by the support layer 10, thereby improving the reliability of the redistribution substrate 100. In addition, the operability of the redistribution substrate 100 is improved.

[0138] 6. Other implementation methods (a) In the redistribution substrate 100 according to the above embodiment, in order to reduce the deviation of the height position of the plurality of terminal portions T1, the size of the plurality of through holes THe formed in the first insulating layer 50 is set individually, but the present invention is not limited thereto.

[0139] In the aforementioned redistribution substrate 100, in order to reduce the deviation in the height position of the multiple terminal portions T2, multiple through holes THd formed in the third insulating layer 70 can also be individually provided. Figure 15 The dimensions of the redistribution substrate 100 and the rigid substrate 300 are as follows. Figure 1 The reliability of the electrical connection between them is improved.

[0140] Furthermore, in the redistribution substrate 100 described above, the dimensions of at least one of the plurality of through holes THb and THc formed in the support layer 10 and the second insulating layer 60 can be set individually. In this case, the height position deviations of the upper and lower ends of the plurality of first conductor layers 1 formed in the support layer 10 are reduced respectively. Additionally, the height position deviation of the upper ends of the plurality of second conductor layers 2 formed in the second insulating layer 60 is reduced.

[0141] (b) In the above embodiments, in Figure 7 In the example, the cone angle α and the bottom dimension BD are set to be different between the first through hole TH1 and the second through hole TH2 among multiple through holes THe, but the present invention is not limited to this. It is sufficient that at least the cone angle α is different between the first through hole TH1 and the second through hole TH2.

[0142] (c) In the above embodiments, in Figure 7 In the example described, an example was given in which two of the multiple through holes THE (first through hole TH1 and second through hole TH2) have different shapes, but the present invention is not limited thereto. In the redistribution substrate 100, it is also possible to set three or more of the multiple through holes THE to have different shapes.

[0143] (d) The redistribution substrate 100 according to the above embodiment has a structure in which three insulating layers (60, 50, 40) are stacked on the third surface s1 of the support layer 10 and two insulating layers (70, 80) are stacked on the fourth surface s2 of the support layer 10, but the present invention is not limited thereto. The redistribution substrate 100 may also have a structure in which one or more insulating layers are stacked on the third surface s1 of the support layer 10. In addition, the redistribution substrate 100 may also have a structure in which one or more insulating layers are stacked on the fourth surface s2 of the support layer 10. In this case, a plurality of through holes with a shape taking into account the height position of the terminal portion T1 are formed in the uppermost insulating layer on the third surface s1 of the support layer 10.

[0144] (e) The support layer 10 described in the above embodiment is formed of a metal support 110 and an insulating coating layer 120, but the present invention is not limited thereto. The support layer 10 may be formed of a single component made of a single material, as long as it has a higher rigidity than the plurality of insulating layers (40, 50, 60, 70, 80). Examples of such materials include organic materials, inorganic materials, organic-inorganic mixed materials, or composite materials that have a higher rigidity than the plurality of insulating layers (40, 50, 60, 70, 80).

[0145] In this case, polyimide and the like can be used as organic materials. Alternatively, ceramics and the like can be used as inorganic materials. Ceramic, for example, is glass. Furthermore, glass epoxy resin and the like can be used as organic-inorganic mixed materials and composite materials.

[0146] In addition to the above, the support layer 10 can also be made of a material such as FR4, which is produced by impregnating epoxy resin in a cloth made of glass fiber and then curing it. In this case, the process of covering the metal support 110 with the insulating coating layer 120 is not required. Alternatively, ready-made products can be used. This simplifies the manufacturing process of the support layer 10.

[0147] (f) The redistribution substrate 100 involved in the above embodiments is not limited to Figures 9-19 The example shown can also be manufactured using the following method. It should be noted that in the manufacturing method of the redistribution substrate 100 described below, the redistribution substrate 100 is also manufactured, for example, by a roll-to-roll method.

[0148] Figures 23-37 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a redistribution substrate 100 according to other embodiments. Figures 23-37 The schematic cross-sectional view shown is Figures 9-19 Similarly, with Figure 1 The schematic cross-sectional view corresponds to the redistribution substrate 100. Figures 23-37 The figures show Figure 1 DT in the thickness direction. Figures 23-37 The direction of the arrow in the thickness direction DT is set to the direction from the rigid substrate 300 toward the semiconductor chip 200 when the redistribution substrate 100 is disposed between the semiconductor chip 200 and the rigid substrate 300.

[0149] First, prepare the fifth face 110a and the sixth face 110b. Figure 9 The metal support 110. Next, as... Figure 23 As shown, a first temporary coating layer 123 is formed on the fifth surface 110a of the metal support 110. Furthermore, a plurality of through holes THg are formed in the first temporary coating layer 123. The exposed surface of the first temporary coating layer 121 becomes the third surface s1 of the support layer 10.

[0150] The first temporary coating layer 123 is formed by coating a precursor of photosensitive polyimide onto the fifth surface 110a or by attaching a carrier film made of photosensitive polyimide. Multiple through-holes THg can be formed by exposing and developing the photosensitive polyimide using a given photomask, or by etching or laser processing a portion of the cured first temporary coating layer 123.

[0151] Next, a seed layer is formed in a predetermined area in the third surface s1 and on the inner peripheral surface of the through hole THg, and a plating layer is formed on the seed layer. Thus, as... Figure 24 As shown, multiple partial conductor layers 1a are formed on a portion of the third surface s1 to fill the interior of multiple through holes THg. After the formation of the partial conductor layers 1a, the seed layer is removed.

[0152] Next, as Figure 25 As shown, a second insulating layer 60 is formed on the third surface s1 in such a way that it covers the portion of the conductor layer 1a that is exposed on the third surface s1. In addition, a plurality of through holes THh are formed in the second insulating layer 60 such that a portion of a plurality of conductor layers 1a is exposed onto the second insulating layer 60.

[0153] Next, a seed layer is formed in a predetermined area on the exposed surface of the second insulating layer 60. Additionally, seed layers are formed on the inner peripheral surfaces of the plurality of through-holes THh and in the exposed portions of the plurality of partial conductor layers 1a. A plating layer is then formed on the formed seed layer. Thus, as... Figure 26 As shown, a plurality of second conductor layers 2 are formed on the second insulating layer 60. After the formation of the second conductor layers 2, the seed layer is removed. A portion of the plurality of second conductor layers 2 (via portions) is filled with a plurality of through holes THh formed in the second insulating layer 60. Another portion of the plurality of second conductor layers 2 (wiring portions) is formed on the second insulating layer 60 in a given pattern.

[0154] Next, as Figure 27 As shown, a first insulating layer 50 is formed on the second insulating layer 60 in such a way that it covers the portions of the plurality of second conductor layers 2 that are exposed on the second insulating layer 60. Furthermore, a plurality of through-holes THi are formed in the first insulating layer 50 such that portions of the plurality of second conductor layers 2 are exposed onto the first insulating layer 50. In this example of the first insulating layer 50, similarly to the example of the first insulating layer 50 described in the above embodiment, in order to reduce the deviation in the height position of the plurality of terminal portions T1 of the redistribution substrate 100, the cone angle α and the bottom dimension BD of each of the plurality of through-holes THi are individually set.

[0155] Next, a seed layer is formed in a predetermined area on the exposed surface of the first insulating layer 50. Additionally, seed layers are formed on the inner peripheral surfaces of the plurality of through-holes THi and in the exposed portions of the plurality of second conductor layers 2. A plating layer is then formed on the formed seed layer. Thus, as... Figure 28 As shown, a plurality of third conductor layers 3 are formed on the first insulating layer 50. After the formation of the third conductor layers 3, the seed layer is removed. A portion of the plurality of third conductor layers 3 (via portions) is used to fill the plurality of through holes THi formed in the first insulating layer 50. Another portion of the plurality of third conductor layers 3 (wiring portions) is formed on the first insulating layer 50 in a given pattern.

[0156] Next, as Figure 29 As shown, a cover insulating layer 40 is formed on the first insulating layer 50 in such a way that it covers the portions of the plurality of third conductor layers 3 that are exposed on the first insulating layer 50. Furthermore, a plurality of through-holes THj are formed in the cover insulating layer 40 such that portions of the plurality of third conductor layers 3 are exposed onto the cover insulating layer 40. Similar to the example of the embodiment described above, the second insulating layer 60, the first insulating layer 50, and the cover insulating layer 40 are formed of a photosensitive material. Therefore, photolithography is used in the formation of these insulating layers.

[0157] After that, as Figure 30 As shown, a terminal portion T1 is formed in the portion of the plurality of third conductor layers 3 exposed through a plurality of through holes THj. Through the above... Figures 23-30 The processing completes the portion of the redistribution substrate 100 located on the fifth surface 110a of the metal support 110. Figure 1 (The semiconductor chip 200 side portion).

[0158] Next, the portion of the redistribution substrate 100 located on the sixth surface 110b of the metal support 110 is fabricated. Figures 31-37 (The portion of the rigid substrate 300 side). In Figures 23-30 In order to facilitate understanding of the portion on the rigid substrate 300 side of the fabrication of the redistribution substrate 100, the orientation of the thickness direction DT in the schematic cross-sectional view is relative to... Figure 31 The schematic sectional view is reversed in the vertical direction.

[0159] First, such as Figure 32 As shown, multiple through holes THk are formed in predetermined portions of the metal support 110. The multiple through holes THk expose a portion of the multiple partial conductor layers 1a to the sixth surface 110b of the metal support 110 through the through holes THk.

[0160] Here, the method for forming the plurality of through holes THk of the metal support 110 is the same as the method for forming the plurality of through holes THa of the metal support 110 described in the above embodiment. Therefore, each through hole THk is formed such that its inner diameter gradually decreases from the sixth surface 110b toward the fifth surface 110a.

[0161] Next, a second temporary coating layer 124 is formed on the sixth surface 110b of the metal support 110, covering the entire sixth surface 110b and filling multiple through holes THk. Furthermore, through holes TH1 are also formed within portions of the second temporary coating layer 124 within each through hole THk. Thus, as... Figure 31As shown, the fifth surface 110a, the sixth surface 110b of the metal support 110, and the through hole THk of the metal support 110 are completed. Figure 33 The insulating coating 120 covers the inner circumferential surface of the ).

[0162] A support layer 10 is formed by a metal support 110 and an insulating coating layer 120. The exposed side of the second temporary coating layer 124 becomes the fourth surface s2 of the support layer 10. Inside each through-hole TH1, a portion of the conductor layer 1a formed within the through-hole THg of the first temporary coating layer 123 is exposed. It should be noted that the method of forming the second temporary coating layer 124 and the method of forming the plurality of through-holes TH1 are substantially the same as the method of forming the first temporary coating layer 123 and the method of forming the plurality of through-holes THg.

[0163] Next, a seed layer is formed in the predetermined area of ​​the fourth surface s2, the inner peripheral surface of the plurality of through holes TH1, and the portion of the conductor layer 1a exposed in each through hole TH1. A plating layer is then formed on the seed layer. Thus, as... Figure 34 As shown, multiple partial conductor layers 1b are formed on the fourth surface s2. After the partial conductor layers 1b are formed, the seed layer is removed. A portion of the multiple partial conductor layers 1b (via portions) is filled with multiple through holes THl. Another portion of the multiple partial conductor layers 1b (wiring portions) is formed on the fourth surface s2 in a given pattern.

[0164] Here, multiple partial conductor layers 1b are electrically connected to multiple partial conductor layers 1a located at one end of multiple through holes TH1. The first conductor layer 1 according to the above embodiment is formed by a pair of mutually electrically connected partial conductor layers 1a and partial conductor layers 1b.

[0165] Next, as Figure 35 As shown, a third insulating layer 70 is formed on the fourth surface s2 in such a way that it covers the portion of the conductor layer 1b that is exposed on the fourth surface s2. In addition, a plurality of through holes THm are formed in the third insulating layer 70 such that a portion of a plurality of conductor layers 1b is exposed onto the third insulating layer 70.

[0166] Next, a seed layer is formed in a predetermined area on the exposed surface of the third insulating layer 70. Additionally, seed layers are formed on the inner peripheral surfaces of the plurality of through-holes THm and in the exposed portions of the plurality of partial conductor layers 1b. A plating layer is then formed on the formed seed layer. Thus, as... Figure 36 As shown, a plurality of fourth conductor layers 4 are formed on the third insulating layer 70. After the formation of the fourth conductor layers 4, the seed layer is removed. A portion of the plurality of fourth conductor layers 4 (via portions) fills the plurality of through holes THm formed in the third insulating layer 70. Another portion of the plurality of fourth conductor layers 4 (wiring portions) is formed on the third insulating layer 70 in a given pattern.

[0167] Next, as Figure 37 As shown, a fourth insulating layer 80 is formed on the third insulating layer 70 in such a way that it covers the portions of the plurality of fourth conductor layers 4 that are exposed on the third insulating layer 70. In addition, a plurality of through holes THn are formed in the fourth insulating layer 80 such that portions of the plurality of fourth conductor layers 4 are exposed onto the fourth insulating layer 80.

[0168] After that, as Figures 23-37 As shown, terminal portions T2 are formed in portions of the plurality of fourth conductor layers 4 exposed through the plurality of through holes THn. Thus, the redistribution substrate 100 according to other embodiments is completed.

[0169] It should be noted that in the manufacturing method of the redistribution substrate 100 in this example, the method of forming multiple insulating layers (40, 50, 60, 70, 80) and the method of forming multiple through holes (THh, THi, THj, THm, THn) of each insulating layer are basically the same as the method of forming the first temporary cover layer 121 and the method of forming multiple through holes THg.

[0170] according to Figures 23-37 The manufacturing method separately forms the semiconductor chip 200 side portion of the redistribution substrate 100 based on the metal support 110, and the rigid substrate 300 side portion of the redistribution substrate 100 based on the metal support 110. Therefore, compared to the case where both the semiconductor chip 200 side portion and the rigid substrate 300 side portion of the redistribution substrate 100 are formed simultaneously, the positioning and adjustment of processing conditions during the formation of each part become easier. As a result, each part can be formed with high precision relative to the design dimensions. Furthermore, since complex processing is not required, expensive manufacturing equipment is not needed.

[0171] As mentioned above, in Figure 38 In the example of the manufacturing method shown, the portion of the redistribution substrate 100 on the semiconductor chip 200 side and the portion on the rigid substrate 300 side are formed essentially by alternately forming conductor layers and insulating layers. However, it is also possible to use a dry film resist in at least a portion of the redistribution substrate 100 to form a plurality of conductor layers that are continuous along the thickness direction DT, thereby forming conductor layers that penetrate a plurality of insulating layers.

[0172] (g) In the redistribution substrate 100 described in the above embodiments, the plurality of through holes THe are formed by photolithography, but they can also be formed by laser processing.

[0173] (h) In the redistribution substrate 100 according to the above embodiments, the plurality of through holes THa to THf formed on the support layer 10 and the plurality of insulating layers (50, 60, 70, 80) each have a circular shape when viewed from above, but the present invention is not limited thereto. The plurality of through holes THa to THf may also have a shape other than a circular shape (elliptical shape or polygonal shape) when viewed from above.

[0174] (i) In the above embodiment, the redistribution substrate 100 is manufactured by a roll-to-roll method, but the present invention is not limited thereto. The redistribution substrate 100 may also be manufactured by methods other than the roll-to-roll method. For example, it may be manufactured by a single-sheet method that processes a sheet sequentially. In this case, the redistribution substrate 100 may also be a rigid substrate that does not have flexibility.

[0175] (j) The above embodiments are examples of applying the present invention to a redistribution substrate, but are not limited thereto. The present invention can also be applied to other wiring circuit substrates having multiple insulating layers and multiple conductor layers stacked together.

[0176] 7. Reference Method Figure 38 This is a longitudinal sectional view showing a structural example of the redistribution substrate 100 involved in the reference method. Regarding... Figure 7 The redistribution substrate 100, for use with Figure 7 The different points of the redistribution substrate 100 are explained.

[0177] exist Figure 38 In the redistribution substrate 100, one of the multiple through holes THe formed in the first insulating layer 50 (first through hole TH1) is formed with other through holes THe (second through hole TH2) at different cone angles α1 and α2.

[0178] In contrast, the reference method involved in this method Figure 38 In the redistribution substrate 100, a plurality of through holes THe formed in the first insulating layer 50 are formed with a common cone angle α1. On the other hand, the cone angle α3 of each through hole THc in the second insulating layer 60 is smaller than the cone angle α1 of each through hole THe in the first insulating layer 50.

[0179] In this way, for each insulating layer in the stacked configuration, the shape (taper angle) of the through-hole formed in that insulating layer is set. This allows adjustment of the shape of the conductor layer in which the through-hole is formed in each insulating layer. It should be noted that in... ​ In the example, the cone angle α3 of each through hole THc in the second insulating layer 60 is smaller than the cone angle α1 of each through hole THe in the first insulating layer 50, but the cone angle α3 of each through hole THc in the second insulating layer 60 can also be larger than the cone angle α1 of each through hole THe in the first insulating layer 50.

[0180] 8. The correspondence between the constituent elements of the scope of the patent claim and the various parts of the implementation method. Hereinafter, examples will be described corresponding to the elements of the claims and the elements of the embodiments, but the present invention is not limited to the examples described below. Various other elements having the structure or function described in the claims can also be used as the elements of the claims.

[0181] In the above embodiments, the redistribution substrate 100 is an example of a wiring circuit substrate, the first insulating layer 50 is an example of a first insulating layer, the upper surface of the first insulating layer 50 is an example of a first surface, the lower surface of the first insulating layer 50 is an example of a second surface, the through-hole THe (first through-hole TH1) formed on the second conductor layer 2 where vias are formed is an example of a first through-hole, and the through-hole THe (second through-hole TH2) formed on the second conductor layer 2 where no vias are formed is an example of a second through-hole.

[0182] Furthermore, the third conductor layer 3, which is filled with the through-hole THe formed on the second conductor layer 2 where the via is formed, is an example of the first via portion, and the third conductor layer 3, which is filled with the through-hole THe formed on the second conductor layer 2 where no via is formed, is an example of the second via portion. The cone angle α1 is an example of the first angle, and the cone angle α2 is an example of the second angle.

[0183] Furthermore, the portion of the plurality of second conductor layers 2 formed on the second insulating layer 60 is an example of a first wiring layer and a second wiring layer; the bottom opening of the through hole THe formed on the second conductor layer 2 where the via is formed is an example of a first bottom opening; the bottom opening of the through hole THe formed on the second conductor layer 2 where no via is formed is an example of a second bottom opening; the bottom dimension BD1 is an example of the size of the first bottom opening; and the bottom dimension BD2 is an example of the size of the second bottom opening.

[0184] In addition, the second insulating layer 60 is an example of a second insulating layer, the upper surface of the second insulating layer 60 is an example of a third surface, the lower surface of the second insulating layer 60 is an example of a fourth surface, the support layer 10 is an example of a support layer, the mask 610 is an example of a mask, the light source portion 600 is an example of a light source portion, the first mask portion 611 is an example of a first mask portion, the second mask portion 612 is an example of a second mask portion, the semiconductor packaging substrate 400 is an example of a semiconductor packaging substrate, and the electronic device 800 is an example of an electronic device.

[0185] 9. Summary of Implementation Methods (Item 1) The wiring circuit board involved in Item 1 has the following features: The first insulating layer has a first surface and a second surface that are oriented in opposite directions in the thickness direction, and has a first through hole and a second through hole that respectively penetrate from the first surface to the second surface. A first via portion is disposed inside the first through hole in the first insulating layer; and The second via is disposed inside the second through hole of the first insulating layer. The first angle formed by at least a portion of the inner circumferential surface of the first through hole and the first surface, and the second angle formed by at least a portion of the inner circumferential surface of the second through hole and the first surface, are different from each other.

[0186] In the aforementioned wiring circuit board, it is envisioned that a first via portion is formed by plating inside the first through hole while the opening on the second side of the first through hole is closed. In this case, the height position of the first via portion in the thickness direction in the direction facing the first surface is determined according to the shape of the first through hole. Furthermore, it is envisioned that a second via portion is formed by plating inside the second through hole while the opening on the second side of the second through hole is closed. In this case, the height position of the second via portion in the thickness direction in the direction facing the first surface is determined according to the shape of the second through hole.

[0187] According to the above structure, the first angle determining the shape of the first through-hole is different from the second angle determining the shape of the second through-hole. Therefore, even if there are deviations in the formation state of the plating in multiple portions of the first insulating layer, the first through-hole and the second through-hole are appropriately formed in multiple portions to reduce the range of the deviation. In this case, during the fabrication of the wiring circuit board, a process for making the height of the multiple via portions consistent is not required. Therefore, it is possible to suppress the increase in the number of manufacturing steps and to uniformize the height positions of the multiple terminal portions located on the multiple via portions.

[0188] (Second item) In the wiring circuit board described in the first item, it may also be, The wiring circuit board also includes a first wiring layer and a second wiring layer formed on one surface. The first insulating layer is formed such that the second surface contacts and covers both the first wiring layer and the second wiring layer. The first through hole has a first bottom opening, which is closed by the first wiring layer on the second side of the first insulating layer. The second through-hole has a second bottom opening, which is closed by the second wiring layer on the second side of the first insulating layer. The first via is formed within the first through hole on the first wiring layer. The second via is formed within the second through hole on the second wiring layer. The size of the first bottom opening is different from the size of the second bottom opening.

[0189] Based on the above structure, the size of the first bottom opening, which determines the shape of the first through-hole, is different from the size of the second bottom opening, which determines the shape of the second through-hole. Therefore, taking into account these differences in shape, the first and second through-holes are appropriately formed in multiple portions of the first insulating layer. This allows for a more uniform height distribution of the multiple via portions.

[0190] (Third item) In the wiring circuit board described in the first or second item, it may also be, The wiring circuit board further includes a second insulating layer, which has a third and a fourth surface facing opposite directions in the thickness direction, and is disposed on the second surface of the first insulating layer such that the third surface contacts the second surface.

[0191] In this case, a through-hole can be formed in the second insulating layer, and a further via portion can be formed within the through-hole. This increases the freedom of design for wiring in the wiring circuit board.

[0192] (Fourth item) In the wiring circuit board described in the third item, it may also be, The wiring circuit board also includes a support layer, which is disposed directly or indirectly on the fourth surface of the second insulating layer and has a higher rigidity than the first insulating layer and the second insulating layer.

[0193] In this case, the structure of the wiring circuit, including the first via and the second via, is supported by the support layer, thus improving the reliability of the wiring circuit board. Furthermore, even when the wiring circuit board is flexible overall, the operability of the wiring circuit board is improved due to the support layer.

[0194] (Fifth item) In the wiring circuit board described in the first or second item, it may also be, The first insulating layer is made of a photosensitive material.

[0195] In this case, the first through-hole and the second through-hole can be formed in the first insulating layer by photolithography. This allows for the uniformity of the height positions of multiple vias without the need for machining.

[0196] (Sixth item) The semiconductor packaging substrate involved in the sixth item includes the wiring circuit substrate mentioned in any one of the first to fifth items.

[0197] (Seventh item) The electronic equipment covered by the seventh item includes the semiconductor packaging substrate described in the sixth item.

[0198] (Item 8) The method for manufacturing the wiring circuit board involved in Item 8 includes: The process of forming a first insulating layer, wherein the first insulating layer has a first surface and a second surface facing opposite directions in the thickness direction, and has a first through hole and a second through hole respectively penetrating from the first surface to the second surface; and The process of forming a first via portion inside the first through hole of the first insulating layer by plating, and forming a second via portion inside the second through hole of the first insulating layer by plating. The first angle formed by at least a portion of the inner circumferential surface of the first through hole and the first surface, and the second angle formed by at least a portion of the inner circumferential surface of the second through hole and the first surface, are different from each other.

[0199] In the wiring circuit board manufactured using the above-described manufacturing method, it is envisioned that a first via portion is formed by plating inside the first through hole while the opening on the second side of the first through hole is closed. In this case, the height position of the first via portion in the thickness direction in the direction facing the first surface is determined according to the shape of the first through hole. Furthermore, it is envisioned that a second via portion is formed by plating inside the second through hole while the opening on the second side of the second through hole is closed. In this case, the height position of the second via portion in the thickness direction in the direction facing the first surface is determined according to the shape of the second through hole.

[0200] According to the above structure, the first angle determining the shape of the first through-hole is different from the second angle determining the shape of the second through-hole. Therefore, even if there are deviations in the formation state of the plating in multiple portions of the first insulating layer, the first through-hole and the second through-hole are appropriately formed in multiple portions to reduce the range of the deviation. In this case, during the fabrication of the wiring circuit board, a process for making the height of the multiple via portions consistent is not required. Therefore, it is possible to suppress the increase in the number of manufacturing steps and to uniformize the height positions of the multiple terminal portions located on the multiple via portions.

[0201] (Item 9) In the method for manufacturing the wiring circuit board described in Item 8, it may also be that... The process of forming the first insulating layer includes: The process of forming a temporary insulating layer composed of a precursor of a photosensitive material on a given surface; The process of exposing the temporary insulating layer by irradiating it with exposure light from a position opposite to the given face, via a mask having a pattern corresponding to the first through-hole and the second through-hole; and The process of developing the exposed temporary insulating layer.

[0202] In this case, a first insulating layer having a first through hole and a second through hole can be easily fabricated by photolithography.

[0203] (Item 10) In the method for manufacturing the wiring circuit board described in Item 9, it may also be that... The exposure light includes: The first exposure light corresponds to the first through hole; and The second exposure light corresponds to the second through hole. The process of exposing the temporary insulating layer includes: From the light source, through the mask, the first exposure light is irradiated onto the first portion of the temporary insulating layer to form the first through-hole, or the portion surrounding the first portion; and The second exposure light is emitted from the light source, through the mask, onto the second portion of the temporary insulating layer where the second through-hole is to be formed, or onto the portion surrounding the second portion. The first collimation half-angle, expressed as an angle, of the size of the light source portion of the first exposure light obtained from the mask is different from the second collimation half-angle, expressed as an angle, of the size of the light source portion of the second exposure light obtained from the mask.

[0204] Imagine a scenario where exposure light is irradiated onto a temporary insulating layer through a mask, followed by development, thereby forming an insulating layer with a through-hole. In this case, the angle between the inner circumferential surface of the through-hole and one side of the insulating layer varies according to the collimation half-angle, expressed as an angle, representing the size of the light source portion of the exposure light obtained from the mask. According to the method described above, the first collimation half-angle corresponding to the first exposure light used to form the first through-hole and the second collimation half-angle corresponding to the second exposure light used to form the second through-hole are different. Therefore, the first angle and the second angle can be made different through a simple adjustment operation.

[0205] (Item 11) In the method for manufacturing the wiring circuit board described in Item 9, it may also be that... The process of exposing the temporary insulating layer includes: For the first portion of the temporary insulating layer to form the first through-hole, or the portion surrounding the first portion, the mask is positioned at a first distance apart and illuminated with exposure light; and For the second portion of the temporary insulating layer to form the second through hole or the portion surrounding the second portion, the mask is positioned at a second distance different from the first distance and is illuminated with the exposure light.

[0206] Imagine a scenario where an exposure light is shone onto a temporary insulating layer through a mask, followed by development, thereby forming an insulating layer with a through-hole. In this case, the angle between the inner circumferential surface of the through-hole and one side of the insulating layer varies depending on the distance between the mask and the temporary insulating layer during the exposure. According to this method, the distance between the mask and the temporary insulating layer differs between the exposure used to form the first through-hole and the exposure used to form the second through-hole. Therefore, the first angle and the second angle can be made different through a simple adjustment.

[0207] (Item 12) In the method for manufacturing the wiring circuit board described in Item 9, it may also be that... The exposure light includes: The third exposure light consists of light from one of a predetermined wavelength region among multiple wavelength regions; and The fourth exposure light consists of light from two or more wavelength regions among the multiple wavelength regions. The process of exposing the temporary insulating layer includes: The third exposure light is irradiated onto the first portion of the temporary insulating layer to form the first through-hole, or the portion surrounding the first portion. The fourth exposure light is irradiated onto the second portion of the temporary insulating layer to form the second through hole or the portion surrounding the second portion.

[0208] Imagine a scenario where exposure light is irradiated onto a temporary insulating layer through a mask, followed by development, thereby forming an insulating layer with a through-hole. In this case, the angle between the inner circumferential surface of the through-hole and one side of the insulating layer varies depending on the wavelength distribution of the light constituting the exposure light. According to the method described above, the wavelength distribution of the third exposure light used to form the first through-hole differs from the wavelength distribution of the fourth exposure light used to form the second through-hole. Therefore, the first angle and the second angle can be made different through a simple adjustment operation.

[0209] (Item 13) In the method for manufacturing the wiring circuit board described in Item 9, it may also be that... The mask includes: The first mask portion has the structure of one of the following masks: a grayscale mask, a halftone mask, and a phase-shifting mask, and corresponds to the first through-hole; and The second mask portion has the structure of the grayscale mask, the halftone mask, and other masks among the phase-shift masks, and corresponds to the second through-hole. The process of exposing the temporary insulating layer includes: Exposure light is emitted from the light source portion, through the first mask portion of the mask, onto the first portion of the temporary insulating layer to form the first through-hole, or onto the portion surrounding the first portion; and The exposure light is emitted from the light source portion, through the second mask portion of the mask, onto the second portion of the temporary insulating layer to form the second through hole, or onto the portion surrounding the second portion.

[0210] Imagine a scenario where exposure light is irradiated onto a temporary insulating layer through a mask, followed by development, thereby forming an insulating layer with a through-hole. In this case, the angle between the inner circumferential surface of the through-hole and one side of the insulating layer varies depending on the shape (intensity distribution and diffusion, etc.) of the light incident on the temporary insulating layer through the mask. In the above method, the structures of the first mask portion and the second mask portion are different. Therefore, the shape of the light irradiated onto the temporary insulating layer through the first mask portion to form the first through-hole is different from the shape of the light irradiated onto the temporary insulating layer through the second mask portion to form the second through-hole. Therefore, by using a mask including both the first and second mask portions, it is easy to make the first angle and the second angle different.

Claims

1. A wiring circuit board, comprising: The first insulating layer has a first surface and a second surface that are oriented in opposite directions in the thickness direction, and has a first through hole and a second through hole that respectively penetrate from the first surface to the second surface. The first via is disposed inside the first through hole of the first insulating layer; as well as The second via is disposed inside the second through hole of the first insulating layer. The first angle formed by at least a portion of the inner circumferential surface of the first through hole and the first surface, and the second angle formed by at least a portion of the inner circumferential surface of the second through hole and the first surface, are different from each other.

2. The wiring circuit board according to claim 1, wherein, The wiring circuit board also includes a first wiring layer and a second wiring layer formed on one surface. The first insulating layer is formed such that the second surface contacts and covers both the first wiring layer and the second wiring layer. The first through hole has a first bottom opening, which is closed by the first wiring layer on the second side of the first insulating layer. The second through-hole has a second bottom opening, which is closed by the second wiring layer on the second side of the first insulating layer. The first via is formed within the first through hole on the first wiring layer. The second via is formed within the second through hole on the second wiring layer. The size of the first bottom opening is different from the size of the second bottom opening.

3. The wiring circuit board according to claim 1 or 2, wherein, The wiring circuit board further includes a second insulating layer, which has a third and a fourth surface facing opposite directions in the thickness direction, and is disposed on the second surface of the first insulating layer such that the third surface contacts the second surface.

4. The wiring circuit board according to claim 3, wherein, The wiring circuit board also includes a support layer, which is disposed directly or indirectly on the fourth surface of the second insulating layer and has a higher rigidity than the first insulating layer and the second insulating layer.

5. The wiring circuit board according to claim 1 or 2, wherein, The first insulating layer is made of a photosensitive material.

6. A semiconductor packaging substrate comprising the wiring circuit substrate according to any one of claims 1 to 5.

7. An electronic device comprising the semiconductor packaging substrate of claim 6.

8. A method for manufacturing a wiring circuit board, comprising: The process of forming a first insulating layer, wherein the first insulating layer has a first surface and a second surface that are oriented in opposite directions in the thickness direction, and has a first through hole and a second through hole that respectively penetrate from the first surface to the second surface; as well as The process of forming a first via portion inside the first through hole of the first insulating layer by plating, and forming a second via portion inside the second through hole of the first insulating layer by plating. The first angle formed by at least a portion of the inner circumferential surface of the first through hole and the first surface, and the second angle formed by at least a portion of the inner circumferential surface of the second through hole and the first surface, are different from each other.

9. The method for manufacturing a wiring circuit board according to claim 8, wherein, The process of forming the first insulating layer includes: The process of forming a temporary insulating layer composed of a precursor of a photosensitive material on a given surface; The process of exposing the temporary insulating layer by irradiating it with exposure light from a position opposite to the given face, via a mask having a pattern corresponding to the first through-hole and the second through-hole; and The process of developing the exposed temporary insulating layer.

10. The method for manufacturing a wiring circuit board according to claim 9, wherein, The exposure light includes: The first exposure light corresponds to the first through hole; and The second exposure light corresponds to the second through hole. The process of exposing the temporary insulating layer includes: From the light source, through the mask, the first exposure light is irradiated onto the first portion of the temporary insulating layer to form the first through-hole, or the portion surrounding the first portion; and The second exposure light is emitted from the light source, through the mask, onto the second portion of the temporary insulating layer where the second through-hole is to be formed, or onto the portion surrounding the second portion. The first collimation half-angle, expressed as an angle, of the size of the light source portion of the first exposure light obtained from the mask is different from the second collimation half-angle, expressed as an angle, of the size of the light source portion of the second exposure light obtained from the mask.

11. The method for manufacturing a wiring circuit board according to claim 9, wherein, The process of exposing the temporary insulating layer includes: For the first portion of the temporary insulating layer to form the first through-hole, or the portion surrounding the first portion, the mask is positioned at a first distance apart and illuminated with exposure light; and For the second portion of the temporary insulating layer to form the second through hole or the portion surrounding the second portion, the mask is positioned at a second distance different from the first distance and is illuminated with the exposure light.

12. The method for manufacturing a wiring circuit board according to claim 9, wherein, The exposure light includes: The third exposure light consists of light from one of a predetermined wavelength region among multiple wavelength regions; and The fourth exposure light consists of light from two or more wavelength regions among the multiple wavelength regions. The process of exposing the temporary insulating layer includes: The third exposure light is irradiated onto the first portion of the temporary insulating layer to form the first through-hole, or the portion surrounding the first portion. The fourth exposure light is irradiated onto the second portion of the temporary insulating layer to form the second through hole or the portion surrounding the second portion.

13. The method for manufacturing a wiring circuit board according to claim 9, wherein, The mask includes: The first mask portion has the structure of one of the following masks: a grayscale mask, a halftone mask, and a phase-shifting mask, and corresponds to the first through-hole; and The second mask portion has the structure of the grayscale mask, the halftone mask, and other masks among the phase-shift masks, and corresponds to the second through-hole. The process of exposing the temporary insulating layer includes: Exposure light is emitted from the light source portion, through the first mask portion of the mask, onto the first portion of the temporary insulating layer to form the first through-hole, or onto the portion surrounding the first portion; and The exposure light is emitted from the light source portion, through the second mask portion of the mask, onto the second portion of the temporary insulating layer to form the second through hole, or onto the portion surrounding the second portion.

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