Semiconductor device

Abstract

The present invention is provided with: a silicon carbide layer including a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type, and a third silicon carbide region of the first conductivity type, and having a first surface and a second surface; a first gate electrode and a second gate electrode extending in a first direction; a first electrode on a first surface side including a first portion in contact with the second silicon carbide region and the third silicon carbide region between the first gate electrode and the second gate electrode, and a second portion in contact with the first silicon carbide region between the first gate electrode and the second gate electrode and provided in a first direction of the first portion; and a second electrode on the second surface side, the distribution of the first conductivity-type impurity concentration in the direction from the first surface to the second surface of the third silicon carbide region including a plurality of inflection points on the first surface side at a first position where the distribution shows the maximum impurity concentration when the first conductivity-type impurity concentration is represented by a logarithmic scale.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] As a material for a semiconductor device, silicon carbide is known. Silicon carbide has superior physical properties such as a band gap of about three times, a breakdown field strength of about ten times, and a thermal conductivity of about three times, as compared with silicon. If these properties are utilized, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) that is high in withstand voltage, low in loss, and capable of high-temperature operation can be realized.

[0003] A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even if the MOSFET is in an off state, a backflow current can flow by using the pn junction diode.

[0004] However, if the backflow current flows using a pn junction diode that operates in a bipolar manner, a stacking fault grows in a silicon carbide layer due to recombination energy of carriers. If a stacking fault grows in the silicon carbide layer, a problem of an increase in on-resistance of the MOSFET occurs. The increase in on-resistance of the MOSFET leads to a decrease in reliability of the MOSFET. For example, by providing a Schottky Barrier Diode (SBD) that operates in a unipolar manner as a built-in diode in the MOSFET, growth of a stacking fault in the silicon carbide layer can be suppressed.

[0005] PRIOR ART DOCUMENTS PATENT DOCUMENTS Patent Document 1: Japanese Patent Application Publication No. 2020-47680 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION The present application has been made to solve the problem of providing a semiconductor device capable of increasing on-current.

[0007] MEANS FOR SOLVING THE PROBLEMS The semiconductor device of one embodiment of the present application includes a silicon carbide layer including a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type extending in a first direction parallel to a first surface of the silicon carbide layer, and a third silicon carbide region of the first conductivity type extending in the first direction between the second silicon carbide region and the first surface, a first gate electrode extending in the first direction and facing the second silicon carbide region and the third silicon carbide region, a second gate electrode extending in the first direction and facing the second silicon carbide region and the third silicon carbide region, a first gate insulating layer provided between the second silicon carbide region and the third silicon carbide region and the first gate electrode, a second gate insulating layer provided between the second silicon carbide region and the third silicon carbide region and the second gate electrode, a first electrode provided on the first surface side of the silicon carbide layer, and a second electrode provided on a second surface side of the silicon carbide layer opposite to the first surface. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device of a first embodiment.

[0009] Figure 2 FIG. 2 is a schematic top view of the semiconductor device of the first embodiment.

[0010] Figure 3 FIG. 3 is an enlarged schematic cross-sectional view of the semiconductor device of the first embodiment.

[0011] Figure 4 FIG. 4 is an enlarged schematic cross-sectional view of the semiconductor device of the first embodiment.

[0012] Figure 5 FIG. 5 is an enlarged schematic cross-sectional view of the semiconductor device of the first embodiment.

[0013] Figure 6 is an enlarged schematic plan view of the semiconductor device of the first embodiment.

[0014] Figure 7 is a graph showing the impurity concentration distribution of the semiconductor device of the first embodiment.

[0015] Figure 8 is an equivalent circuit diagram of the semiconductor device of the first embodiment.

[0016] Figure 9 is a diagram for explaining the problem of the semiconductor device of the first embodiment.

[0017] Figure 10 is a graph showing the impurity concentration distribution of the semiconductor device of the comparative example.

[0018] Figure 11 is a graph showing the impurity concentration distribution of the semiconductor device of the modified example of the first embodiment.

[0019] Figure 12 is a graph showing the impurity concentration distribution of the semiconductor device of the second embodiment.

[0020] Figure 13 is a graph showing the impurity concentration distribution of the semiconductor device of the modified example of the second embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, an embodiment of the present application will be described with reference to the drawings. In addition, in the following description, the same or similar components, etc. are denoted by the same reference numerals, and the description of the components, etc. described once is sometimes appropriately omitted.

[0022] In addition, in the following description, in the case where the marks of n + , n, n - and p + , p, p - are used, these marks indicate the relative levels of the impurity concentrations in the respective conductive types. That is, n + indicates that the n-type impurity concentration is relatively higher than n, and n - indicates that the n-type impurity concentration is relatively lower than n. In addition, p + indicates that the p-type impurity concentration is relatively higher than p, and p - indicates that the p-type impurity concentration is relatively lower than p. Furthermore, the n + -type and the n - -type are sometimes simply denoted as the n-type, and the p + -type and the p - -type are sometimes simply denoted as the p-type.

[0023] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). In addition, the relative magnitude of the impurity concentration can be determined, for example, from the magnitude of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). In addition, the distance such as the width and depth of the impurity region can be obtained by SIMS. In addition, the distance such as the width and depth of the impurity region can be obtained, for example, from the image of SCM, the image of Scanning Electron Microscope (SEM), or the like. In addition, the thickness of the insulating layer or the like can be measured on the image of SIMS, SEM, or Transmission Electron Microscope (TEM).

[0024] Further, in this specification, the "p-type impurity concentration" of a p-type silicon carbide region means the net p-type impurity concentration obtained by subtracting the n-type impurity concentration of the region from the p-type impurity concentration of the region. In addition, the "n-type impurity concentration" of an n-type silicon carbide region means the net n-type impurity concentration obtained by subtracting the p-type impurity concentration of the region from the n-type impurity concentration of the region.

[0025] In addition, in this specification, unless specifically stated otherwise, the impurity concentration of a specific region means the maximum impurity concentration of the region.

[0026] (First Embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface and a second surface opposite to the first surface, the silicon carbide layer including a first silicon carbide region of a first conductivity type having a region in contact with the first surface, a second silicon carbide region of a second conductivity type extending in a first direction parallel to the first surface, provided between the first silicon carbide region and the first surface, and a third silicon carbide region of the first conductivity type extending in the first direction, provided between the second silicon carbide region and the first surface, the first conductivity type impurity concentration of the third silicon carbide region being higher than the first conductivity type impurity concentration of the first silicon carbide region; a first gate electrode extending in the first direction, opposite to the second silicon carbide region and the third silicon carbide region; a second gate electrode extending in the first direction, provided in a second direction perpendicular to the first direction, parallel to the first surface, with respect to the first gate electrode, opposite to the second silicon carbide region and the third silicon carbide region; a first gate insulating layer provided between the second silicon carbide region and the third silicon carbide region and the first gate electrode; a second gate insulating layer provided between the second silicon carbide region and the third silicon carbide region and the second gate electrode; a first electrode provided on the first surface side of the silicon carbide layer, the first electrode including a first portion provided between the first gate electrode and the second gate electrode, in contact with the second silicon carbide region and the third silicon carbide region, and a second portion provided between the first gate electrode and the second gate electrode, in the first direction of the first portion, in contact with the region of the first silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer, the distribution of the first conductivity type impurity concentration of the third silicon carbide region in a direction from the first surface toward the second surface includes a plurality of inflection points at positions on the first surface side of a first position at which the distribution shows a maximum impurity concentration, in a case where the first conductivity type impurity concentration is expressed on a logarithmic scale. The distribution of the first conductivity type impurity concentration of the third silicon carbide region in a direction from the first surface toward the second surface includes a plurality of inflection points at positions on the first surface side of a first position at which the distribution shows a maximum impurity concentration, in a case where the first conductivity type impurity concentration is expressed on a logarithmic scale.

[0027] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. In addition, the MOSFET 100 of the first embodiment includes an SBD as a built-in diode.

[0028] Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described. The MOSFET 100 is an n-channel type MOSFET of a vertical type using an electron as a carrier.

[0029] Figure 1This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 This is a schematic top view of the semiconductor device according to the first embodiment. Figure 2 This is a schematic diagram showing the pattern of the gate electrode and source electrode on the upper surface of the silicon carbide layer. Figure 1 yes Figure 2 AA' cross-section.

[0030] Figure 3 , Figure 4 as well as Figure 5 This is an enlarged schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 6 This is an enlarged schematic top view of the semiconductor device according to the first embodiment. Figure 6 It is a diagram showing the pattern of the semiconductor region on the surface of a silicon carbide layer. Figure 3 yes Figure 6 BB' cross-sectional view. Figure 4 yes Figure 6 CC' cross-section. Figure 5 yes Figure 6 DD' cross-sectional view.

[0031] MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The source electrode 12 includes a contact electrode portion 12x (first portion) and a diode electrode portion 12y (second portion). The gate insulating layer 16 includes a first gate insulating layer 16a, a second gate insulating layer 16b, and a third gate insulating layer 16c. The gate electrode 18 includes a first gate electrode 18a, a second gate electrode 18b, and a third gate electrode 18c.

[0032] In the silicon carbide layer 10, n + Type 22, n drain region - Type 24 drift region (first silicon carbide region), p-type bulk region 26 (second silicon carbide region), n + The source region 30 (third silicon carbide region) is of the p-type type. The bulk region 26 of the p-type type includes the low-concentration region 26a of the p-type type and the p-type bulk region 26a. + High concentration region 26b of type.

[0033] Drift region 24 includes JBS region 24x (region) and JFET region 24y. Furthermore, JBS is an abbreviation of Junction Barrier Schottky. Additionally, JFET is an abbreviation of Junction Field Effect Transistor.

[0034] A silicon carbide layer 10 is disposed between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is a single crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0035] The silicon carbide layer 10 has a first surface ( Figure 1 "F1" in the middle and the second side ( Figure 1 (Referring to "F2" in the original text). Hereinafter, the first surface F1 will sometimes be referred to as the surface, and the second surface F2 will sometimes be referred to as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 are opposite each other. Furthermore, hereafter, "depth" refers to the depth in the direction from the first surface toward the second surface.

[0036] The first direction and the second direction are parallel to the first surface F1. The second direction is perpendicular to the first direction.

[0037] The first face F1 is, for example, a face tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (0001) face. The second face F2 is, for example, a face tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (000-1) face. The (0001) face is called the silicon face. The (000-1) face is called the carbon face.

[0038] n + A drain region 22 is disposed on the back side of the silicon carbide layer 10. The drain region 22 includes, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0039] n - The drift region 24 is located between the drain region 22 and the first surface F1. - A drift region 24 is disposed between the source electrode 12 and the drain electrode 14. - A type of drift region 24 is disposed between the gate electrode 18 and the drain electrode 14.

[0040] n - A type-n drift region 24 is disposed on the drain region 22. The drift region 24 includes, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 24 is lower than that in the drain region 22. For example, the n-type impurity concentration in the drift region 24 is 4 × 10⁻⁶. 14 cm -3 Above and 5×10 17 cm -3 The thickness of the drift region 24 is, for example, 3 μm or more and 150 μm or less.

[0041] The drift region 24 includes the JBS region 24x. The JBS region 24x is connected to the first surface F1. The JBS region 24x is surrounded by the volume region 26.

[0042] JBS region 24x is connected to the diode electrode portion 12y of the source electrode 12. JBS region 24x functions as the cathode region of the SBD.

[0043] The drift region 24 includes a JFET region 24y. The JFET region 24y is in contact with the first surface F1. The JFET region 24y is sandwiched between two body regions 26 in the second direction.

[0044] JFET region 24y is opposite to gate electrode 18. JFET region 24y functions as a path for conduction current when MOSFET100 is in the on state.

[0045] A p-type body region 26 is disposed between the drift region 24 and the first surface F1. The body region 26 extends along the first direction. The body region 26 functions as the channel region of the MOSFET 100.

[0046] Body region 26 includes, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in body region 26 is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 5×10 20 cm -3 the following.

[0047] The depth of the body region 26 is, for example, greater than 0.4 μm and less than 2 μm.

[0048] Body region 26 is connected to source electrode 12. Body region 26 is connected to the contact electrode portion 12x of source electrode 12. Body region 26 is electrically connected to source electrode 12. The contact between body region 26 and source electrode 12 is, for example, an ohmic contact. Body region 26 is fixed to the potential of source electrode 12.

[0049] A portion of body region 26 is connected to the first surface F1. A portion of body region 26 is opposite to the gate electrode 18. A portion of body region 26 forms the channel region of MOSFET 100. A gate insulating layer 16 is sandwiched between a portion of body region 26 and the gate electrode 18.

[0050] Body region 26 includes low concentration regions 26a and p-type. + High concentration region 26b of type.

[0051] A portion of the low-concentration region 26a is connected to the first surface F1. A portion of the low-concentration region 26a is opposite to the gate electrode 18. A portion of the low-concentration region 26a forms the channel region of the MOSFET 100. A gate insulating layer 16 is sandwiched between a portion of the low-concentration region 26a and the gate electrode 18.

[0052] Low-concentration region 26a includes, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in low-concentration region 26a is, for example, 5 × 10⁻⁶. 16 cm -3 Above and 5×10 18 cm -3 the following.

[0053] A high-concentration region 26b is disposed between the low-concentration region 26a and the first surface F1. The high-concentration region 26b is connected to the source electrode 12. The high-concentration region 26b is connected to the contact electrode portion 12x of the source electrode 12.

[0054] The concentration of p-type impurities in the high-concentration region 26b is higher than that in the low-concentration region 26a.

[0055] High-concentration region 26b includes, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in high-concentration region 26b is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 5×10 20 cm -3 the following.

[0056] The depth of the high-concentration region 26b is, for example, above 0.2 μm and below 0.7 μm.

[0057] n + The source region 30 of the type is disposed between the body region 26 and the first surface F1.

[0058] Source region 30 may include phosphorus (P) or nitrogen (N) as n-type impurities, for example. The concentration of n-type impurities in source region 30 is higher than that in drift region 24.

[0059] The n-type impurity concentration in source region 30 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 The depth of the source region 30 is shallower than the depth of the bulk region 26. The depth of the source region 30 is, for example, 0.1 μm or more and 0.4 μm or less.

[0060] Source region 30 is connected to source electrode 12. Source region 30 is connected to the contact electrode portion 12x of source electrode 12. Source region 30 is electrically connected to source electrode 12. The contact between source region 30 and source electrode 12 is, for example, an ohmic contact. Source region 30 is fixed to the potential of source electrode 12.

[0061] The source region 30 is formed, for example, by multiple ion implantations of n-type impurities at different acceleration energies.

[0062] Figure 7 This is a graph showing the impurity concentration distribution of the semiconductor device according to the first embodiment. Figure 7 This is a graph showing the distribution of n-type impurity concentration along the depth direction of the source region 30. Figure 7 In the middle, the position with zero depth corresponds to the position of the first face F1. Figure 7 In the figure, the concentration of n-type impurities on the vertical axis is represented using a logarithmic scale.

[0063] The distribution of n-type impurity concentration in source region 30 is such that the maximum impurity concentration is represented by the first position P1. The depth of the first position P1, representing the maximum impurity concentration, is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1, representing the maximum impurity concentration, is, for example, 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 the following.

[0064] The n-type impurity concentration distribution in the source region 30 has two inflection points on the side closer to the first surface F1 than the first position P1. These two inflection points are the first inflection point IP1 and the second inflection point IP2. The first inflection point IP1 is located deeper than the second inflection point IP2. The first inflection point IP1 is also closer to the first position P1 than the second inflection point IP2.

[0065] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0066] The concentration of n-type impurities at the first inflection point IP1 is, for example, higher than the concentration of n-type impurities at the second inflection point IP2. The concentration of n-type impurities at the first inflection point IP1 is, for example, more than 1.5 times and less than 10 times the concentration of n-type impurities at the second inflection point IP2.

[0067] The depth of the second inflection point IP2 is, for example, less than 0.15 μm.

[0068] The n-type impurity concentration at the second inflection point IP2 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 3×10 19 cm -3 the following.

[0069] like Figure 7 As shown, the n-type impurity concentration distribution in the source region 30 has a first peak PK1 and a second peak PK2. The first peak PK1 is located at a first position P1. The second peak PK2 is located at a second position P2. The second position P2 is located between the first position P1 and the first surface F1.

[0070] The depth of the first position P1 is, for example, 0.15 μm or more. The depth of the second position P2 is, for example, 0.1 μm or less.

[0071] The concentration of the first conductivity type impurity in the second peak PK2 is lower than the concentration of the n-type impurity in the first peak PK1. The concentration of the n-type impurity in the first peak PK1 is, for example, 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 Below. Additionally, the concentration of the first conductivity type impurity in the second peak PK2 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 3×10 19 cm -3 the following.

[0072] also, Figure 7 A graph showing the distribution of n-type impurity concentration in the depth direction of the source region 30, as shown, can be obtained, for example, by fitting the logarithm of the measured values ​​of n-type impurity concentration in the depth direction of the source region 30 with a higher-order function of depth as the variable.

[0073] A gate electrode 18 is disposed on the first surface F1 side of the silicon carbide layer 10. The gate electrode 18 extends along a first direction. A plurality of gate electrodes 18 are arranged in parallel to each other along a second direction. The gate electrode 18 is opposite to the JFET region 24y, the body region 26 and the source region 30 in the first surface F1.

[0074] The first gate electrode 18a extends along a first direction. The first gate electrode 18a is opposite to the JFET region 24y, the body region 26 and the source region 30 in the first surface F1.

[0075] The second gate electrode 18b extends along a first direction. The second gate electrode 18b is disposed relative to the first gate electrode 18a along a second direction. The second gate electrode 18b is opposite to the JFET region 24y, the body region 26, and the source region 30 in the first surface F1.

[0076] The third gate electrode 18c extends along a first direction. The third gate electrode 18c is disposed along a second direction relative to the second gate electrode 18b. The second gate electrode 18b is disposed between the first gate electrode 18a and the third gate electrode 18c. The third gate electrode 18c is opposite to the JFET region 24y, the body region 26 and the source region 30 in the first surface F1.

[0077] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polysilicon containing p-type or n-type impurities.

[0078] A gate insulating layer 16 is disposed between the gate electrode 18 and the JFET region 24y, body region 26, and source region 30. A first gate insulating layer 16a is disposed between the first gate electrode 18a and the JFET region 24y, body region 26, and source region 30. A second gate insulating layer 16b is disposed between the second gate electrode 18b and the JFET region 24y, body region 26, and source region 30. A third gate insulating layer 16c is disposed between the third gate electrode 18c and the JFET region 24y, body region 26, and source region 30.

[0079] The gate insulating layer 16 may include, for example, silicon oxide. The gate insulating layer 16 may also be made of a high-dielectric-constant insulating material. Furthermore, the gate insulating layer 16 may also be constructed using a stacked structure of a silicon oxide layer and a high-dielectric-constant insulating layer.

[0080] The thickness of the gate insulating layer 16 is, for example, 30 nm or more and 100 nm or less.

[0081] An interlayer insulating layer 20 is disposed on the gate electrode 18. The interlayer insulating layer 20 is disposed between the gate electrode 18 and the source electrode 12.

[0082] Interlayer insulating layer 20 electrically separates the gate electrode 18 from the source electrode 12. Interlayer insulating layer 20 includes, for example, silicon oxide. Interlayer insulating layer 20 is, for example, a silicon oxide layer.

[0083] The source electrode 12 is disposed on the first surface F1 side of the silicon carbide layer 10. The source electrode 12 is connected to the silicon carbide layer 10. The source electrode 12 is connected to the body region 26 and the source region 30.

[0084] The source electrode 12 includes a contact electrode portion 12x and a diode electrode portion 12y.

[0085] A contact electrode portion 12x is disposed between two gate electrodes 18. For example, the contact electrode portion 12x is disposed between a first gate electrode 18a and a second gate electrode 18b. The contact electrode portion 12x is connected to the body region 26 and the source region 30.

[0086] For example, the interface between the contact electrode portion 12x and the body region 26 is located on the side closer to the second surface F2 than the first surface F1 in a third direction perpendicular to the first surface F1. For example, the contact electrode portion 12x is in contact with the source region 30 in the second direction.

[0087] A diode electrode portion 12y is disposed between two gate electrodes 18. For example, the diode electrode portion 12y is disposed between a first gate electrode 18a and a second gate electrode 18b. The diode electrode portion 12y is disposed in a first direction of the contact electrode portion 12x.

[0088] The contact electrode portion 12x and the diode electrode portion 12y are alternately and repeatedly arranged between the same two gate electrodes 18 along a first direction.

[0089] The diode electrode portion 12y is connected to the JBS region 24x of the drift region 24. The diode electrode portion 12y functions as the anode electrode of the SBD.

[0090] In MOSFET 100, diode electrode portion 12y and contact electrode portion 12x are adjacent to each other along a second direction. The first-direction configuration of contact electrode portion 12x and diode electrode portion 12y is such that it is staggered by half a cycle relative to the first-direction configuration of the contact electrode portion 12x and diode electrode portion 12y adjacent to each other along the second direction.

[0091] In MOSFET100, the diode electrode portion 12y and the contact electrode portion 12x are configured in a checkerboard pattern.

[0092] The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The metal silicide layer 12s is disposed between the silicon carbide layer 10 and the metal layer 12m.

[0093] The metal silicide layer 12s is connected to the bulk region 26. The metal silicide layer 12s is connected to the source region 30.

[0094] The metal silicide layer 12s includes, for example, nickel (Ni), titanium (Ti), or cobalt (Co). The metal silicide layer 12s is, for example, a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer.

[0095] The metal layer 12m comprises metal. The metal layer 12m may, for example, have a laminated structure of barrier metal films and metal films.

[0096] The barrier metal film includes, for example, titanium (Ti), tungsten (W), or tantalum (Ta). The barrier metal film is, for example, a titanium film, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

[0097] Metal films include, for example, aluminum (Al). A metal film is, for example, an aluminum film.

[0098] The contact electrode portion 12x includes a metal silicide layer 12s. Through the contact electrode portion 12x including the metal silicide layer 12s, an ohmic contact is formed between the source electrode 12 and the bulk region 26, and between the source electrode 12 and the source region 30.

[0099] The diode electrode portion 12y includes, for example, a blocking metal film.

[0100] For example, by including a blocking metal film in the diode electrode portion 12y, a Schottky contact is formed between the source electrode 12 and the JBS region 24x.

[0101] The drain electrode 14 is disposed on the second surface F2 side of the silicon carbide layer 10. The drain electrode 14 is disposed on the second surface F2 of the silicon carbide layer 10. The drain electrode 14 is connected to the second surface F2.

[0102] The drain electrode 14 may include, for example, a metal or a metal semiconductor compound. The drain electrode 14 may include, for example, a nickel silicide layer, a titanium layer, a nickel layer, a silver layer, or a gold layer.

[0103] Drain electrode 14 is electrically connected to drain region 22. For example, drain electrode 14 is connected to drain region 22.

[0104] Next, the function and effects of the MOSFET 100 in the first embodiment will be explained.

[0105] Figure 8 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment. In the MOSFET 100, a pn diode and an SBD are connected in parallel with the transistor as built-in diodes between the source electrode 12 and the drain electrode 14. The body region 26 is the anode region of the pn junction diode, and the drift region 24 is the cathode region of the pn junction diode. In addition, the source electrode 12 is the anode electrode of the SBD, and the JBS region 24x becomes the cathode region of the SBD.

[0106] For example, consider the case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, due to the induced current caused by the inductive load, a voltage that is positive relative to the drain electrode 14 is sometimes applied to the source electrode 12. In this case, forward current flows through the built-in diode. This state is also known as the reverse conduction state.

[0107] Assuming the MOSFET lacks a Switched Grid Diode (SBD), forward current flows through the pn junction diode. The pn junction diode operates bipolarly. If a bipolar-operated pn junction diode carries back current, stacking faults will grow in the silicon carbide layer due to the recombination energy of charge carriers. The growth of stacking faults in the silicon carbide layer leads to an increase in the MOSFET's on-resistance. This increased on-resistance reduces the MOSFET's reliability.

[0108] The MOSFET100 features a forward bias diode (SBD). The forward voltage (Vf) at which forward current begins to flow in the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, forward current flows through the SBD before the pn junction diode.

[0109] The forward voltage (Vf) of an SBD is, for example, above 1.0V and below 2.0V. The forward voltage (Vf) of a pn junction diode is, for example, above 2.0V and below 3.0V.

[0110] The SBD operates as a single-pole device. Therefore, even with forward current flow, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy. This suppresses the increase in the on-resistance of the MOSFET 100, thereby improving the reliability of the MOSFET 100.

[0111] Figure 9 This is an explanatory diagram of the semiconductor device according to the first embodiment. Figure 9 It is the same as the first embodiment. Figure 6 The corresponding diagram.

[0112] Figure 9 This indicates the current path of the conduction current flowing near the first surface F1 of MOSFET100 when MOSFET100 is turned on. The current path of the conduction current is indicated by an arrow.

[0113] like Figure 9 As shown, in the second direction, between the JBS region 24x and the JFET region 24y, there is no portion of the contact electrode portion 12x that connects to the source region 30. Therefore, as Figure 9 As shown, the conduction current flows from the contact electrode portion 12x to the source region 30 in the first direction, and then flows through the body region 26, which becomes the channel region, to the JFET region 24y.

[0114] If the resistance of the source region 30 increases, the parasitic resistance of the MOSFET 100 increases, and the on-current of the MOSFET 100 decreases. In particular, when the distance between adjacent contact electrode portions 12x along the first direction increases, the current path flowing in the source region 30 along the first direction becomes longer. Therefore, the increase in parasitic resistance becomes significant, and the decrease in the on-current of the MOSFET 100 becomes significant.

[0115] Figure 10 This is a graph showing the impurity concentration distribution of the semiconductor device in the comparative example. Figure 10 This is a graph showing the distribution of n-type impurity concentration along the depth direction of the source region 30. Figure 10 In the middle, the position with zero depth corresponds to the position of the first face F1. Figure 10 In the figure, the concentration of n-type impurities on the vertical axis is represented using a logarithmic scale.

[0116] exist Figure 10 In the diagram, dashed lines represent the distribution of n-type impurity concentration in the comparative example semiconductor device. Figure 10 In the diagram, the distribution of n-type impurity concentration in the semiconductor device of the first embodiment is also represented by a solid line.

[0117] like Figure 10 As shown, the distribution of n-type impurity concentration in the comparative example's semiconductor device has a peak Pkx at position Px. The distribution of n-type impurity concentration in the comparative example's semiconductor device at position Px represents the maximum impurity concentration. The distribution of n-type impurity concentration in the comparative example's semiconductor device does not have an inflection point on the side closer to the first surface F1 than position Px.

[0118] In the comparative example semiconductor device, for example, if the n-type impurity concentration at position Px is increased, the resistance of the source region decreases. Therefore, the parasitic resistance of the MOSFET decreases, and the MOSFET's on-state current increases.

[0119] However, as the concentration of n-type impurities in the source region increases, the defect density in the source region also increases. These defects in the source region are generated, for example, by ion implantation used to form the n-type impurities in the source region.

[0120] In particular, if the n-type impurity concentration and defect density increase in the source region adjacent to the gate insulating layer, the reliability of the gate insulating layer above the source region decreases. If the defect density in the source region near the first surface F1 increases, the reliability of the gate insulating layer above the source region decreases. Specifically, for example, the time-dependent dielectric breakdown (TDDB) characteristics of the gate insulating layer deteriorate.

[0121] The distribution of n-type impurity concentration in the MOSFET 100 of the first embodiment has two inflection points at a position closer to the first surface F1 than the first position P1, which represents the maximum impurity concentration. By having two inflection points in the distribution of n-type impurity concentration, a low impurity concentration region with a predetermined width having an n-type impurity concentration of at least a predetermined concentration can be formed on the side closer to the first surface F1 compared to the first position P1.

[0122] In the first embodiment, the MOSFET 100 reduces the resistance of the source region 30 by increasing the n-type impurity concentration at the first position P1. Therefore, the parasitic resistance of the MOSFET 100 decreases, and the on-state current of the MOSFET 100 increases.

[0123] The MOSFET 100 of the first embodiment has a low-impurity region of a predetermined width located on the first surface F1 side closer to the first position P1. Therefore, the n-type impurity concentration in the source region 30 adjacent to the gate insulating layer 16 is low, and the defect density is reduced. In other words, the defect density of the source region 30 near the first surface F1 is lower. Therefore, the reliability of the gate insulating layer above the source region 30 is improved.

[0124] Furthermore, the low impurity concentration region of the MOSFET 100 in the first embodiment has an n-type impurity concentration of at least a predetermined concentration by having two inflection points. In other words, a certain level of n-type impurity concentration is maintained in the low impurity concentration region. Therefore, the decrease in resistance of the source region 30 near the first surface F1 is suppressed. As a result, the parasitic resistance of the MOSFET 100 decreases, and the on-state current of the MOSFET 100 increases.

[0125] According to the first embodiment, by having a low impurity concentration region of a predetermined width with an n-type impurity concentration of a predetermined concentration or higher on the surface side of the source region 30 at the position where the n-type impurity concentration is the largest, a MOSFET 100 that can balance the increase of conduction current and the improvement of gate insulation layer reliability can be realized.

[0126] From the viewpoint of increasing the on-state current of MOSFET100, it is preferable to have a high maximum impurity concentration at the first position P1. The n-type impurity concentration at the first position P1 is preferably 3 × 10⁻⁶. 19 cm -3 The above is preferred, with 5×10 being more ideal. 19 cm -3 The above is further optimized to 8×10 19 cm -3 above.

[0127] From the viewpoint of increasing the on-current of MOSFET100, it is preferable that the n-type impurity concentration at the first inflection point IP1 is higher than that at the second inflection point IP2.

[0128] From the viewpoint of increasing the on-state current of MOSFET 100, a high n-type impurity concentration at the second inflection point IP2 is preferable. The n-type impurity concentration at the second inflection point IP2 is preferably 1 × 10⁻⁶. 19 cm -3 The above is preferred to be 2×10 19 cm -3 above.

[0129] From the viewpoint of increasing the on-current of MOSFET 100, it is preferable that the depth of the second inflection point IP2 is shallow. The depth of the second inflection point IP2 is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0130] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET 100, it is preferable that the depth of the first position P1, which represents the maximum impurity concentration, is deep. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0131] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET 100, it is preferable that the depth of the first inflection point IP1 is deep. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0132] From the viewpoint of improving the reliability of the gate insulating layer 16 of MOSFET 100, it is preferable to have a low n-type impurity concentration at the second inflection point IP2. The n-type impurity concentration at the second inflection point IP2 is preferably 3 × 10⁻⁶. 19 cm -3 The following is more preferably 2×10 19 cm -3 the following.

[0133] From the viewpoint of balancing the increase in the on-current of MOSFET100 and the reliability of the gate insulation layer 16, the n-type impurity concentration of the first inflection point IP1 is preferably more than 1.5 times and less than 10 times the n-type impurity concentration of the second inflection point IP2, and more preferably more than 2 times and less than 5 times.

[0134] From the viewpoint of increasing the on-state current of MOSFET100, a high n-type impurity concentration in the first peak PK1 is preferred. The preferred n-type impurity concentration in the first peak PK1 is 3 × 10⁻⁶. 19 cm -3 The above is preferred, with 5×10 being more ideal. 19 cm -3 The above is further optimized to 8×10 19 cm -3 above.

[0135] From the viewpoint of increasing the on-current of MOSFET100, a high n-type impurity concentration in the second peak PK2 is preferred. The preferred n-type impurity concentration in the second peak PK2 is 1×10⁻⁶. 19 cm -3 The above is preferred to be 2×10 19 cm -3 above.

[0136] From the viewpoint of increasing the on-current of MOSFET100, it is preferable that the depth of the second peak PK2 is shallow. The depth of the second peak PK2 is preferably 0.1 μm or less, and more preferably 0.08 μm or less.

[0137] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET 100, it is preferable to set the depth of the first position P1 of the first peak PK1 to be greater than 0.15 μm. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0138] From the viewpoint of improving the reliability of the gate insulating layer 16 of MOSFET100, it is preferable to have a low n-type impurity concentration in the second peak PK2. The preferred n-type impurity concentration in the second peak PK2 is 3 × 10⁻⁶. 19 cm -3 The following is more preferably 2×10 19 cm -3 above.

[0139] (Variation example) The semiconductor device of the modified example of the first embodiment differs from the semiconductor device of the first embodiment in that the distribution of the concentration of the first conductivity type impurity in the direction from the first surface of the third silicon carbide region toward the second surface includes four inflection points and three peaks.

[0140] Figure 11 This is a graph showing the impurity concentration distribution of a semiconductor device in a modified example of the first embodiment. Figure 11 This is a graph showing the distribution of n-type impurity concentration along the depth direction of the source region 30. Figure 11 In the middle, the position with zero depth corresponds to the position of the first face F1. Figure 11 In the figure, the concentration of n-type impurities on the vertical axis is represented using a logarithmic scale.

[0141] The distribution of n-type impurity concentration in source region 30 is such that the maximum impurity concentration is represented by the first position P1. The depth of the first position P1, representing the maximum impurity concentration, is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1, representing the maximum impurity concentration, is, for example, 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 the following.

[0142] The n-type impurity concentration distribution in the source region 30 has four inflection points on the side closer to the first surface F1 than the first position P1. The four inflection points are the first inflection point IP1, the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0143] The first inflection point IP1 is located deeper than the second inflection point IP2. The second inflection point IP2 is located deeper than the third inflection point IP3. The third inflection point IP3 is deeper than the fourth inflection point IP4.

[0144] The first inflection point IP1 is closest to the first position P1. The fourth inflection point IP4 is closest to the first face F1.

[0145] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0146] The n-type impurity concentration at the first inflection point IP1 is, for example, higher than the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4. The n-type impurity concentration at the first inflection point IP1 is, for example, more than 1.5 times and less than 10 times the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0147] The depth of the fourth inflection point IP4 is, for example, less than 0.15 μm.

[0148] The concentration of n-type impurities in the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 3×10 19 cm -3 the following.

[0149] like Figure 11 As shown, the n-type impurity concentration distribution in source region 30 has a first peak PK1, a second peak PK2, and a third peak PK3. The first peak PK1 is located at the first position P1. The second peak PK2 is located at the second position P2. The third peak PK3 is located at the third position P3.

[0150] The second position P2 is located between the first position P1 and the first surface F1. The third position P3 is located between the second position P2 and the first surface F1.

[0151] The third peak, PK3, is the closest to the first peak, F1.

[0152] The depth of the first position P1 is, for example, 0.15 μm or more. Furthermore, the depth of the third position P3 is, for example, 0.1 μm or less.

[0153] The concentrations of n-type impurities in the second peak PK2 and the third peak PK3 are lower than those in the first peak PK1. The concentration of n-type impurities in the first peak PK1 is 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 Below. Additionally, the concentration of n-type impurities in the second peak PK2 and the third peak PK3 is 1 × 10⁻⁶. 19 cm -3 Above 3×10 19 cm -3 the following.

[0154] According to a variation of the first embodiment, similarly to the first embodiment, by having a low impurity concentration region of a predetermined width with an n-type impurity concentration of a predetermined concentration or higher on the surface side of the source region 30 at a position where the n-type impurity concentration is the largest, a MOSFET that can balance the increase in conduction current and the improvement in the reliability of the gate insulating layer can be realized.

[0155] From the viewpoint of increasing the on-current of the modified MOSFET, a high maximum impurity concentration at the first position P1 is preferable. The n-type impurity concentration at the first position P1 is preferably 3 × 10⁻⁶. 19 cm -3 The above is preferred, with 5×10 being more ideal. 19 cm -3 The above is further optimized to 8×10 19 cm -3 above.

[0156] From the viewpoint of increasing the on-current of the MOSFET in the modified example, it is preferable that the n-type impurity concentration at the first inflection point IP1 is higher than that at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0157] From the viewpoint of increasing the on-current of the MOSFET in the modified example, it is preferable that the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are high. The n-type impurity concentration at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 is preferably 1 × 10⁻⁶. 19 cm -3 The above is preferred to be 2×10 19 cm -3 above.

[0158] From the viewpoint of increasing the on-current of the MOSFET in the modified example, it is preferable that the depth of the fourth inflection point IP4 is shallow. The depth of the fourth inflection point IP4 is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0159] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the depth of the first position P1, which represents the maximum impurity concentration, is deep. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0160] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the depth of the first inflection point IP1 is deep. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0161] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are low. The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are preferably 3 × 10⁻⁶. 19 cm -3 The following is more preferably 2×10 19 cm -3 the following.

[0162] From the viewpoint of balancing the increase in the on-current of the MOSFET in the modified example and the improvement in the reliability of the gate insulating layer 16, the n-type impurity concentration of the first inflection point IP1 is preferably more than 1.5 times and less than 10 times the n-type impurity concentration of the second inflection point IP2, the third inflection point IP3 and the fourth inflection point IP4, and more preferably more than 2 times and less than 5 times.

[0163] From the viewpoint of increasing the on-current of the modified MOSFET, a high n-type impurity concentration in the first peak PK1 is preferred. The preferred n-type impurity concentration in the first peak PK1 is 3 × 10⁻⁶. 19 cm -3 The above is preferred, with 5×10 being more ideal. 19 cm -3 The above is further optimized to 8×10 19 cm -3 above.

[0164] From the viewpoint of increasing the on-current of the modified MOSFET, it is preferable to have a high concentration of n-type impurities in the second peak PK2 and the third peak. The preferred n-type impurity concentration in the second peak PK2 and the third peak is 1×10⁻⁶. 19 cm -3 The above is preferred to be 2×10 19 cm -3 above.

[0165] From the viewpoint of increasing the on-current of the modified MOSFET, it is preferable that the depth of the third peak PK3 is relatively shallow. The depth of the third peak PK3 is preferably 0.1 μm or less, and more preferably 0.08 μm or less.

[0166] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable to set the depth of the first position P1 of the first peak PK1 to be deeper. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0167] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable to have low n-type impurity concentrations in the second peak PK2 and the third peak PK3. The preferred n-type impurity concentrations in the second peak PK2 and the third peak PK3 are 3 × 10⁻⁶. 19 cm -3 The following is more preferably 2×10 19 cm -3 above.

[0168] Based on the first embodiment and its variations, a MOSFET is realized that can balance the increase in conduction current and the improvement in the reliability of the gate insulating layer.

[0169] (Second Implementation) The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that the distribution of the concentration of the first conductivity type impurity in the direction from the first surface of the third silicon carbide region toward the second surface does not have multiple peaks. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0170] Figure 12 This is a graph showing the impurity concentration distribution of the semiconductor device according to the second embodiment. Figure 12 This is a graph showing the distribution of n-type impurity concentration along the depth direction of the source region 30. Figure 12 In the middle, the position with zero depth corresponds to the position of the first face F1. Figure 12 In the figure, the concentration of n-type impurities on the vertical axis is represented using a logarithmic scale.

[0171] The distribution of n-type impurity concentration in source region 30 is such that the maximum impurity concentration is represented by the first position P1. The depth of the first position P1, representing the maximum impurity concentration, is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1, representing the maximum impurity concentration, is, for example, 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 the following.

[0172] The n-type impurity concentration distribution in the source region 30 has two inflection points on the side closer to the first surface F1 than the first position P1. These two inflection points are the first inflection point IP1 and the second inflection point IP2. The first inflection point IP1 is located deeper than the second inflection point IP2. The first inflection point IP1 is also closer to the first position P1 than the second inflection point IP2.

[0173] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0174] The concentration of n-type impurities at the first inflection point IP1 is, for example, higher than the concentration of n-type impurities at the second inflection point IP2. The concentration of n-type impurities at the first inflection point IP1 is, for example, more than 1.5 times and less than 10 times the concentration of n-type impurities at the second inflection point IP2.

[0175] The depth of the second inflection point IP2 is, for example, less than 0.15 μm.

[0176] The n-type impurity concentration at the second inflection point IP2 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 3×10 19 cm -3 the following.

[0177] like Figure 12 As shown, the n-type impurity concentration distribution in the source region 30 has a first peak PK1. The first peak PK1 is located at a first position P1. The depth of the first position P1 is, for example, 0.15 μm or more.

[0178] According to the second embodiment, similarly to the first embodiment, by having a low impurity concentration region of a predetermined width with an n-type impurity concentration of a predetermined concentration or higher on the surface side of the source region 30 at the position where the n-type impurity concentration is the largest, a MOSFET that can balance the increase in conduction current and the improvement in the reliability of the gate insulating layer can be realized.

[0179] From the viewpoint of increasing the on-current of the MOSFET in the second embodiment, it is preferable to have a high maximum impurity concentration at the first position P1. The n-type impurity concentration at the first position P1 is preferably 3 × 10⁻⁶. 19 cm -3 The above is preferred, with 5×10 being more ideal. 19 cm -3 The above is further optimized to 8×10 19 cm -3 above.

[0180] From the viewpoint of increasing the on-current of the MOSFET, it is preferable that the n-type impurity concentration at the first inflection point IP1 is higher than that at the second inflection point IP2.

[0181] From the viewpoint of increasing the on-state current of the MOSFET, a high n-type impurity concentration is preferred for the second inflection point IP2. The preferred n-type impurity concentration for the second inflection point IP2 is 1 × 10⁻⁶. 19 cm -3 The above is preferred to be 2×10 19 cm -3 above.

[0182] From the viewpoint of increasing the on-current of the MOSFET, it is preferable that the depth of the second inflection point IP2 is shallow. The depth of the second inflection point IP2 is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0183] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET, it is preferable that the depth of the first position P1, which represents the maximum impurity concentration, is deep. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0184] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET, it is preferable that the depth of the first inflection point IP1 is deep. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0185] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET, it is preferable to have a low n-type impurity concentration at the second inflection point IP2. The n-type impurity concentration at the second inflection point IP2 is preferably 3 × 10⁻⁶. 19 cm -3 The following is more preferably 2×10 19 cm -3 the following.

[0186] From the viewpoint of balancing the increase in MOSFET on-current and the improvement in the reliability of the gate insulation layer 16, the n-type impurity concentration of the first inflection point IP1 is preferably 1.5 times or more and 10 times or less than the n-type impurity concentration of the second inflection point IP2, and more preferably 2 times or more and 5 times or less.

[0187] (Variation example) The semiconductor device of the modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the distribution of the concentration of the first conductivity type impurity in the direction from the first surface of the third silicon carbide region toward the second surface includes four inflection points.

[0188] Figure 13 This is a graph showing the impurity concentration distribution of a semiconductor device in a modified example of the second embodiment. Figure 13 This is a graph showing the distribution of n-type impurity concentration along the depth direction of the source region 30. Figure 13 In the middle, the position with zero depth corresponds to the position of the first face F1. Figure 13In the figure, the concentration of n-type impurities on the vertical axis is represented using a logarithmic scale.

[0189] The distribution of n-type impurity concentration in source region 30 is such that the maximum impurity concentration is represented by the first position P1. The depth of the first position P1, representing the maximum impurity concentration, is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1, representing the maximum impurity concentration, is, for example, 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 the following.

[0190] The n-type impurity concentration distribution in the source region 30 has four inflection points on the side closer to the first surface F1 than the first position P1. The four inflection points are the first inflection point IP1, the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0191] The first inflection point IP1 is located deeper than the second inflection point IP2. The second inflection point IP2 is located deeper than the third inflection point IP3. The third inflection point IP3 is deeper than the fourth inflection point IP4.

[0192] The first inflection point IP1 is closest to the first position P1. The fourth inflection point IP4 is closest to the first face F1.

[0193] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0194] The n-type impurity concentration at the first inflection point IP1 is, for example, higher than the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4. The n-type impurity concentration at the first inflection point IP1 is, for example, more than 1.5 times and less than 10 times the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0195] The depth of the fourth inflection point IP4 is, for example, less than 0.15 μm.

[0196] The concentration of n-type impurities in the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 is, for example, 1 × 10⁻⁶. 19 cm -3 Above and 3×10 19 cm -3 the following.

[0197] According to a variation of the second embodiment, similarly to the second embodiment, by having a low impurity concentration region of a predetermined width with an n-type impurity concentration of a predetermined concentration or higher on the surface side of the source region 30 at a position where the n-type impurity concentration is the largest, a MOSFET that can balance the increase in conduction current and the improvement in the reliability of the gate insulating layer can be realized.

[0198] From the viewpoint of increasing the on-current of the modified MOSFET, a high maximum impurity concentration at the first position P1 is preferable. The n-type impurity concentration at the first position P1 is preferably 3 × 10⁻⁶. 19 cm -3 The above is preferred, with 5×10 being more ideal. 19 cm -3 The above is further optimized to 8×10 19 cm -3 above.

[0199] From the viewpoint of increasing the on-current of the MOSFET in the modified example, it is preferable that the n-type impurity concentration at the first inflection point IP1 is higher than that at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0200] From the viewpoint of increasing the on-current of the MOSFET in the modified example, it is preferable that the n-type impurity concentration at the second inflection point IP2 is high. The n-type impurity concentration at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 is preferably 1 × 10⁻⁶. 19 cm -3 The above is preferred to be 2×10 19 cm -3 above.

[0201] From the viewpoint of increasing the on-current of the MOSFET in the modified example, it is preferable that the depth of the fourth inflection point IP4 is shallow. The depth of the fourth inflection point IP4 is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0202] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the depth of the first position P1, which represents the maximum impurity concentration, is deep. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0203] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the depth of the first inflection point IP1 is deep. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0204] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are low. The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are preferably 3 × 10⁻⁶. 19 cm -3 The following is more preferably 2×10 19 cm -3 the following.

[0205] From the viewpoint of balancing the increase in the on-current of the MOSFET in the modified example and the improvement in the reliability of the gate insulating layer 16, the n-type impurity concentration of the first inflection point IP1 is preferably more than 1.5 times and less than 10 times the n-type impurity concentration of the second inflection point IP2, the third inflection point IP3 and the fourth inflection point IP4, and more preferably more than 2 times and less than 5 times.

[0206] Based on the second embodiment and its variations, a MOSFET is realized that can balance the increase in conduction current and the improvement in the reliability of the gate insulating layer.

[0207] In the first and second embodiments, examples were given with two or four inflection points, but the number of inflection points is not particularly limited as long as there are two or more. Similarly, in the first embodiment, examples were given with two or three peaks, but the number of peaks is not particularly limited as long as there are two or more.

[0208] In the first and second embodiments, 4H-SiC was used as an example of the crystal structure of SiC, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. In addition, it can also be applied to surfaces other than the (0001) surface on the surface of the silicon carbide layer 10.

[0209] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type is used as an example for explanation. However, the first conductivity type can also be set to p-type and the second conductivity type to n-type.

[0210] In the first and second embodiments, aluminum (Al) is exemplified as a p-type impurity, but boron (B) can also be used. Additionally, nitrogen (N) and phosphorus (P) are exemplified as n-type impurities, but arsenic (As), antimony (Sb), and the like can also be used.

[0211] In addition, the present invention can also be applied to Insulated Gate Bipolar Transistor (IGBT).

[0212] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the claims and their equivalents.

[0213] Explanation of reference numerals in the attached figures 10 silicon carbide layers 12 Source electrode (first electrode) 12x Contact Electrode Section (Part 1) 12y diode electrode section (part two) 14 Drain electrode (second electrode) 16a First gate insulating layer 16b Second gate insulating layer 18a First gate electrode 18b Second gate electrode 24 Drift Region (First Silicon Carbide Region) 24x JBS area (region) 26-body region (second silicon carbide region) 30 Source region (third silicon carbide region) 100 MOSFET (Semiconductor Device) F1 First Side F2 Second Side IP1 First Inflection Point P1 First Position PK1 First Peak

Claims

1. A semiconductor device comprising: A silicon carbide layer has a first surface and a second surface facing the first surface. The silicon carbide layer includes a first silicon carbide region of a first conductivity type having a region in contact with the first surface, a second silicon carbide region of a second conductivity type disposed between the first silicon carbide region and the first surface and extending along a first direction parallel to the first surface, and a third silicon carbide region of a first conductivity type disposed between the second silicon carbide region and the first surface and extending along the first direction, wherein the impurity concentration of the first conductivity type is higher than that of the first silicon carbide region of the first conductivity type. A first gate electrode extends along the first direction and is opposite to the second silicon carbide region and the third silicon carbide region; The second gate electrode extends along the first direction and is disposed relative to the first gate electrode along a second direction perpendicular to the first direction, and is opposite to the second silicon carbide region and the third silicon carbide region; A first gate insulating layer is disposed between the second silicon carbide region and the third silicon carbide region and the first gate electrode; A second gate insulating layer is disposed between the second silicon carbide region and the third silicon carbide region and the second gate electrode; A first electrode is disposed on the first surface side of the silicon carbide layer. The first electrode includes a first portion disposed between the first gate electrode and the second gate electrode and connected to the second silicon carbide region and the third silicon carbide region, and a second portion disposed between the first gate electrode and the second gate electrode, disposed along the first direction of the first portion and connected to the region of the first silicon carbide region. as well as The second electrode is disposed on the second surface side of the silicon carbide layer. The distribution of the first conductivity type impurity concentration in the third silicon carbide region in the direction from the first surface toward the second surface, when expressed on a logarithmic scale, includes multiple inflection points on the first surface side closer to the first position where the distribution shows the maximum impurity concentration.

2. The semiconductor device according to claim 1, The concentration of the first conductive impurity at the first inflection point, which is closest to the first position among the plurality of inflection points, is higher than the concentration of the first conductive impurity at the other inflection points.

3. The semiconductor device according to claim 2, The concentration of the first conductivity type impurity at the first inflection point is more than 1.5 times and less than 10 times the concentration of the first conductivity type impurity at other inflection points.

4. The semiconductor device according to claim 1, The depth of the first location is 0.15 μm or more.

5. The semiconductor device according to claim 1, The depth of the first inflection point, which is closest to the first position among the plurality of inflection points, is greater than 0.15 μm.

6. The semiconductor device according to claim 1, The maximum impurity concentration is 3 × 10⁻⁶. 19 cm -3 above.

7. The semiconductor device according to claim 1, The depth of the inflection point closest to the first surface among the plurality of inflection points is less than 0.15 μm.

8. The semiconductor device according to claim 1, The n-type impurity concentration at the inflection point other than the first inflection point closest to the first position among the plurality of inflection points is 1×10. 19 cm -3 Above and 3×10 19 cm -3 the following.

9. The semiconductor device according to claim 1, The distribution has multiple peaks, including a first peak. The first peak is set at the first position.

10. The semiconductor device according to claim 9, The depth at the first location is 0.15 μm or more. Among the plurality of peaks, the position of the peak closest to the first surface is set at a depth of less than 0.1 μm.

11. The semiconductor device according to claim 9, The concentration of the first conductivity type impurity in the first peak is 3 × 10⁻⁶. 19 cm -3 Above and 1×10 20 cm -3 the following, The concentration of the first conductivity type impurity in the peaks other than the first peak among the plurality of peaks is 1×10. 19 cm -3 Above and 3×10 19 cm -3 the following.

12. The semiconductor device according to claim 1, The depth of the third silicon carbide region is less than 0.4 μm.

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