Selective capping for gate-all-around field effect transistors

Abstract

Embodiments of the present disclosure include a method of forming a gate-around (GAA) contact structure on a semiconductor substrate. A method will include: removing material from a surface of features formed in a surface of a substrate including a plurality of features, each including a plurality of source / drain contact surfaces; selectively forming a reaction product material over a surface of each of the plurality of source / drain contact surfaces; heating the substrate to a first temperature to remove reaction product material from a surface of each of the plurality of contacts; selectively forming a first metal layer on a surface of each of the plurality of contacts; selectively forming a second metal layer on the first metal layer; and filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo).

Description

TECHNICAL FIELD

[0001] Embodiments described herein relate generally to semiconductor device manufacturing, and more particularly, to systems and methods of forming gate contact structures in wrap-around gate field effect transistors. BACKGROUND

[0002] Integrated circuits have evolved into complex devices that can include billions of transistors, capacitors, and resistors on a single chip. In the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased.

[0003] Microelectronic devices are fabricated as integrated circuits on semiconductor substrates, where various conductive layers are interconnected to one another to allow electronic signals to propagate within the device. Examples of such devices can include high-performance computing, mobile devices, internet of things (IoT) devices, memory (e.g., DRAM (dynamic random access memory)), and logic devices, including both planar and three-dimensional structures. Three-dimensional structures include finFETs (fin field effect transistors), MOSFET (metal oxide semiconductor field effect transistor) devices, or GAA FET (gate-all-around field effect transistor) devices.

[0004] GAA FETs are an improved transistor design that provides improved performance and power efficiency compared to traditional FETs such as finFETs (fin field effect transistors), MOSFETs (metal oxide semiconductor field effect transistors). They consist of a channel region surrounded by a gate structure on all sides, providing excellent control over electron flow. The GAA architecture allows for enhanced electrostatic control and reduced leakage current, enabling higher switching speed, lower power consumption, and improved scalability. With their three-dimensional gate configuration, GAA FETs exhibit superior control over short channel effects, enabling highly compact and efficient electronic device designs for a wide range of applications, including high-performance computing, mobile devices, and internet of things (IoT) devices.

[0005] Example GAA FET devices include a channel region surrounded by a gate structure on all sides, providing excellent control over electron flow. Source / drain regions are provided at opposite ends of the gate structure. The source and drain regions are typically heavily doped regions of the semiconductor substrate. A silicide layer (e.g., a titanium silicide layer) is generally needed to form reliable contact structures at the formed source and drain regions.

[0006] In a conventional middle-end-of-the-line (MEOL) contact junction formation process, features such as vias or trenches are fabricated in a semiconductor substrate. A contact region comprising silicon (Si) or silicon / germanium (SiGe) is formed in the bottom of the trench or via. The MEOL contact junction allows for a connection between a front-end-of-the-line (FEOL) semiconductor structure and a back-end-of-the-line (BEOL) interconnect. Contacts having low resistivity are desirable in semiconductor devices. However, when the MEOL contact junction has a relatively high resistance, poor connections are created at the MEOL contact junction, which reduces the overall performance of the packaged semiconductor structure.

[0007] In 3D device structures such as FinFETs, silicide contacts need to be formed on exposed portions of silicon-based source / drain layers formed on the sidewalls of deep high-aspect-ratio (HAR) holes or deep HAR trenches, leaving little to no space to reliably form GAA gate contact structures. Conventional deposition techniques typically form a silicide layer at one particular and optimized depth, but the concentration gradients of species created during transport in deep holes / trenches will inherently cause non-uniformity in the deposition. The HAR holes or deep HAR trenches further amplify the non-uniformity in the deposition. Conventional approaches for forming a silicide layer in features result in variations in the silicide layer properties, which especially results in variations in the electrical properties of 3D devices.

[0008] Thus, there is a need in the art for a selective process for efficiently and quickly forming reliable low-resistance contact structures for GAAFET devices. SUMMARY

[0009] Embodiments described herein generally relate to semiconductor device fabrication, and more particularly, to systems and methods of forming gate contact structures in wrap-around gate field effect transistors. A method includes the following operations.

[0010] removing material from a surface of a feature formed in a surface of a substrate, wherein the feature includes a plurality of contact structures disposed within a feature formed in the substrate, the contact structures including a plurality of contacts each including silicon (Si) or silicon germanium (SiGe), and each of the plurality of contacts is spaced apart in a first direction by a dielectric layer. The method of removing material includes selectively forming a reaction product material over a surface of each of the plurality of contacts, followed by heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts.

[0011] A first metal layer is selectively formed on a surface of each of the plurality of contacts. A second metal layer is formed on the first metal layer, wherein forming the second metal layer on the first metal layer comprises selectively depositing the second metal layer on the first metal layer, and selectively forming the second metal layer comprises exposing the surface of the selectively formed first metal layer to a precursor containing a fluorine-free metal to form the second metal layer.

[0012] Filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo), and depositing a capping layer on the conductor material. BRIEF DESCRIPTION OF DRAWINGS

[0013] To enable a detailed understanding of the manner in which the n above-described feature of the present disclosure are used, a more particular description of the present disclosure, briefly summarized above, can be had by reference to the embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings

[0014] Figure 1 A schematic top view of a multi-chamber processing system according to embodiments described herein is shown.

[0015] Figure 2 A process flow diagram of a method of forming a semiconductor structure according to embodiments described herein is depicted.

[0016] Figure 3 A schematic isometric view of an example GAA FET semiconductor structure according to embodiments described herein.

[0017] Figures 4A to 4J A schematic cross-sectional view of a portion of a semiconductor structure according to embodiments described herein.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It can be anticipated that mechanisms and features of one embodiment can be advantageously DETAILED DESCRIPTION

[0019] In the following disclosure, reference can be made to one or more embodiments. However, those skilled in the art will understand that the present disclosure is not limited to the described embodiments. Rather, any combination of features and devices, whether described or not, is contemplated and provided by one or more embodiments of the present disclosure, whether in relation to different embodiments or not. Moreover, whether or not a given embodiment realizes a particular advantage, the present disclosure is not limited in this regard. The aspects, features, embodiments, and advantages provided are merely illustrative. Unless explicitly recited in one or more claims, none of these are to be considered an element or limitation of the appended claims. Likewise, those skilled in the art should not interpret reference to "the present disclosure" as a generalization of any disclosed subject matter.

[0020] As used in this application, "substrate" can represent a substrate or a surface of material formed on a substrate on which film processing is performed during a fabrication process. For example, a processable substrate surface can be comprised of materials such as, but not limited to, silicon (Si), silicon oxide (SiO2), strained Si, Si on insulator (SOI), carbon doped silicon oxides (SiOx), amorphous Si, doped Si, pre-amorphization implantation (PAI) Si, germanium (Ge), PAI-SiGe, gallium arsenide (GaAs), glass, sapphire, and any other conductive material (depending on the application), such as metals, metal nitrides, and metal alloys. By way of example and not limitation, a substrate includes a semiconductor wafer. A substrate can be exposed to a processing procedure to polish, etch, reduce, oxidize, or anneal a substrate surface.

[0021] As used in this application, the terms "precursor," "reactant," "reactive gas," and like such terms representing chemical species can represent one or more chemical species that can react with one or more exposed surfaces of a substrate or with each other and whose products subsequently react with an exposed surface of a substrate.

[0022] The terms “CPU,” “processor,” “at least one processor,” or “one or more processors” generally refer to a single processor configured to perform one or more operations, or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, the execution of one or more operations may be divided among different processors, but one processor may execute multiple operations, and multiple processors may collectively execute a single operation. Similarly, “memory,” “at least one memory,” or “one or more memory” generally refer to a single memory configured to store data and / or instructions, or multiple memories configured to collectively store data and / or instructions.

[0023] Processing System Instances

[0024] Figure 1 A schematic representation of a processing system 100 for use with one or more embodiments of the present disclosure is shown. In one or more embodiments, the processing system 100 can be used to perform... Figure 2 Method 200, in whole or in part.

[0025] As detailed below, substrates in processing system 100 can be processed in individual chambers and transferred between chambers without exposing the substrates to the surrounding environment outside processing system 100 (e.g., the atmospheric environment, such as that present in a wafer fab). For example, substrates can be processed in individual chambers maintained at low pressure (e.g., less than or equal to about 300 Torr) or subatmospheric pressure (such as a vacuum environment) and transferred between chambers without disrupting the reduced relative pressure or vacuum environment between processes performed on the substrates in processing chamber 100. Thus, processing system 100 can provide an integrated solution for some processing of substrates.

[0026] Examples of processing systems that can be appropriately modified based on the provided teachings include Endura. ® Integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California, USA. It is conceivable that other processing systems (including those from other manufacturers) may be suitable for benefiting from the described aspects.

[0027] Figure 1A schematic top view of a processing system 100 (also referred to as a “processing platform”) according to embodiments described herein. As described in detail below, the processing system 100 generally includes an equipment front-end module (EFEM) 102 for loading substrates into the processing system 100, a first load lock chamber 104 coupled to the EFEM 102, a transfer chamber 108 coupled to the first load lock chamber 104, and a plurality of other chambers coupled to the transfer chamber 108. The EFEM 102 generally includes one or more robots 105 configured to transfer substrates from front opening unified pods (FOUPs) 103 to at least one of the first load lock chamber 104 or the second load lock chamber 106. Proceeding counterclockwise from a buffer portion 108A of the first load lock chamber 104 around the transfer chamber 108, the processing system 100 includes a first dedicated purge chamber 109, a first preclean chamber 110, a first through chamber 112, a second through chamber 113, a second preclean chamber 114, a second purge chamber 116, and the second load lock chamber 106. The buffer portion 108A of the transfer chamber 108 includes a first robot 115 configured to transfer substrates to each of the load lock chambers 104 and 106, the purge chambers 109 and 116, the preclean chambers 110 and 114, and the through chambers 112 and 113.

[0028] The back end portion 108B of the transfer chamber 108 includes a second robot 135 configured to transfer substrates to processing chambers coupled to the back end portion 108B of the processing system 100 and through each of the chambers 112, 113. The processing chambers can include a first processing chamber 132, a second processing chamber 134, a third processing chamber 136, a fourth processing chamber 138, and a fifth processing chamber 140. Generally, the processing chambers 132, 134, 136, 138, 140 can include at least one of an atomic layer deposition (ALD) chamber, a chemical vapor deposition (CVD) chamber, a physical vapor deposition (PVD) chamber, an etch chamber, a degas chamber, an anneal chamber, and other types of semiconductor substrate processing chambers. In some embodiments, one or more of the processing chambers 132, 134, 136, 138, 140 are PVD chambers. In some examples, the processing chamber 110 can be capable of performing an etch process, the processing chamber 114 can be capable of performing a clean process or an anneal process, and the processing chambers 132, 134, 136, 138, 140 can be capable of performing respective CVD or ALD deposition processes. In one example, the processing chamber 110 or 114 can be a Selectra™ etch chamber available from Applied Materials, Inc., of Santa Clara, Calif. In one example, the processing chamber 110 or 114 can be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc., of Santa Clara, Calif. In one example, the processing chamber 132, 134, 136, 138, or 140 can be a Volta™ CVD / ALD chamber, or an Encore™ PVD chamber available from Applied Materials, Inc., of Santa Clara, Calif.

[0029] The buffer portion 108A and the back end portion 108B of the transfer chamber 108, as well as each chamber coupled to the transfer chamber 108, can be maintained in a vacuum state. As used herein, the term "vacuum" can represent a pressure less than 760 Torr, and will generally be maintained at a pressure of near 10 -5 Torr (i.e., ~10 -3 Pa). However, some high vacuum systems can operate at less than near 10 -7 Torr (i.e., ~10 -5 Pa). In certain embodiments, the vacuum is created using a roughing pump and / or a turbo molecular pump coupled to each of the transfer chamber 108 and one or more processing chambers (e.g., processing chambers 109-140). However, other types of vacuum pumps are also contemplated.

[0030] A system controller 126, such as a programmable design computer, is coupled to the processing system 100 for controlling one or more components therein. For example, the system controller 126 can control operation of one or more process chambers, such as process chambers 132, 134, 136, 138, 140. In operation, the system controller 126 implements data collection and feedback from respective components to coordinate processing in the processing system 100.

[0031] The system controller 126 includes a programmable design central processing unit (CPU) 126A, which can operate in conjunction with a memory 126B (e.g., non-volatile memory) and support circuits 126C. The support circuits 126C (e.g., cache memory, clock circuits, input / output subsystems, power supplies, and the like, and combinations thereof) are coupled to the CPU 126A in a conventional manner and to various components within the processing system 100.

[0032] In some embodiments, the CPU 126A is one of any form of general- purpose computer processor used in an industrial setting for controlling various monitoring system components and sub-processors, such as a programmable logic controller (PLC). The memory 126B coupled to the CPU 126A is non-transitory and typically one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drives, hard drives, or any other form of digital storage, local or remote.

[0033] In this document, the memory 126B is in the form of a computer- readable storage medium (e.g., non-volatile memory) containing instructions that, when executed by the CPU 126A, facilitate the operation of the processing system 100. The instructions in the memory 126B are in the form of a program product, such as a program (e.g., intermediate software application, equipment software application, etc.) implementing methods of the present disclosure. The program code can be in any of a variety of different programming languages, in one example, the present disclosure can be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program code of the program product defines functions of embodiments of the implementations (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non- writeable storage media (e.g., read-only memory devices within a computer, such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writeable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random access semiconductor memory) on which alterable information is stored. Such computer-readable storage media when carrying computer-readable instructions which direct the functions of the methods described herein are embodiments of the present disclosure. The various methods disclosed herein can typically be implemented by the CPU 126A executing computer instructions code (e.g., as a software routine) stored in the memory 126B (or in the memory of a particular processing chamber) under control of the CPU 126A. When the computer instructions code is executed by the CPU 126A, the CPU 126A controls the chamber to perform processes according to the various methods.

[0034] Surrounding gate field effect transistor structure

[0035] Figure 3 An example surrounding gate field effect transistor (GAA FET) semiconductor structure 300 includes a substrate 302 having a first GAA FET module TR1 formed thereon and a second GAA FET module TR2 formed thereon. The GAA FET module TR1 and the GAAFET module TR2 are electrically isolated from each other by an inter-module insulating layer 304, and are electrically isolated from other GAA FET modules in the semiconductor structure 300, not shown in FIG. 3. Figure 3 A portion of a GAA FET module TR3 is illustrated in cross-section that will share a portion of the substrate 302 with TR1 and TR2 and form an opening described later between TR2 and TR3.

[0036] As used herein, the term "substrate" refers to a layer of material used as the base for subsequent processing operations and comprising the surface to be cleaned. Substrate 302 may, as needed, be a silicon-based material or any suitable insulating or conductive material. Substrate 302 may include materials such as crystalline silicon (e.g., Si). <100> or Si <111> The inter-module insulating layer 304 may be formed of a silicon-containing dielectric material, such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0037] Figure 3 Each of the GAA FET modules TR1 and TR2 shown includes a channel region CH and a source / drain region SD separated from the channel region CH in the X direction. The source / drain region SD may be wider than the channel region CH in the Y direction. The source / drain region SD may be separated from other source / drain regions SD in the X, Y, and / or Z directions by the inter-module insulating layer 304.

[0038] For the purpose of discussion, Figure 3 The source / drain (SD) region shown includes an exposed portion of the silicon-containing contact structure 308, which has a HAR opening (e.g., within the semiconductor structure 300 formed above the region of the substrate 302) within it. Figure 4A and Figure 4G The opening 401 in the FET is exposed. In this example, GAA FET modules TR1 and TR2 each contain three SD regions; however, more or fewer SD regions can be formed in various types of FET devices. In some embodiments, there may be as few as one SD region or hundreds of SD regions oriented in the X, Y, and / or Z directions. Silicon-containing contacts (such as silicon-containing contact 308) may include materials that can be used to form the contacts, such as silicon-based materials or silicon-containing materials, such as silicon / germanium (SiGe)-based materials. One or more of the silicon-containing contacts 308 may additionally or alternatively include materials comprising dopant atoms (such as n-type or p-type dopants).

[0039] The channel region CH of each of GAA FET module TR1 and TR2 can include adjacent parallel gate structures 310 extending along the X-direction within the inter- module insulating layer 304. Each gate structure 310 can include a gate metal layer and a gate dielectric layer disposed between the channel region CH and the gate metal layer. In some embodiments, the gate dielectric can include a dielectric material having a dielectric constant (K) higher than silicon dioxide (Si02) (e.g., K = 3.9) (e.g., hafnium dioxide (Hf02), zirconium dioxide (Zr02), and / or titanium dioxide (Ti02)). In some embodiments, the dielectric material can be referred to as a high-k dielectric. In some embodiments, the gate metal layer itself can be formed of multiple metal layers, each metal layer including an electrically conductive material. The electrically conductive material can include various metal alloys, metals, or electrically conductive ceramics, including but not limited to one or more of aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and combinations thereof.

[0040] Processing sequence examples

[0041] Embodiments of the present disclosure include a method 200 of forming a semiconductor device, constructed in accordance with the information provided in processing system 100 and Figure 1 , Figure 2 and Figure 3 Embodiments of the present disclosure include a method 200 of forming a semiconductor device, constructed in accordance with the information provided in processing system 100 and Figures 4A to 4F are semiconductor substrates undergoing the processes disclosed in method 200 Figure 3 is a schematic diagram of a side cross-sectional view of a portion of a semiconductor substrate as shown in Figures 4A to 4F is a view of a portion of semiconductor structure 300 from 4X to 4X’ in Figure 3 is a view of a portion of semiconductor structure 300 from 4X to 4X’ in Figures 4A to 4F is a view of a portion of semiconductor structure 300 from 4X to 4X’ in Figure 2 is a process flow diagram of method 200 as depicted in Figures 4G to 4I , and Figure 4J is a process flow diagram of method 200 as depicted in Figure 2 is a process flow diagram of method 200 as depicted in

[0042] Prior to first operation 210 of method 200, surface contamination can be present on the boundary surfaces of the device features. Such surface contaminants, such as native oxides, can form on one or more surfaces of the device features, such as silicon dioxide formed on exposed surfaces. Surface contaminants can also have varying thicknesses, depending on the formation environment, such as exposure to atmosphere or oxygen when the substrate is at high temperature.

[0043] The first operation 210 of the method 200 includes exposing each contact structure 308 within the plurality of stacked contact structures 308 disposed within the opening 401 formed in the semiconductor substrate 400 to a pre-clean process, where the exposed surface includes silicon, and each of the plurality of stacked contact structures 308 is spaced apart in a first direction within the opening 401. Figure 4A The exposure of each contact structure 308 within the plurality of stacked contact structures begins with a cleaning process performed during the first operation 210 of the method 200, which can be performed in a processing chamber, such as the processing chambers 110 or 114 within the processing system 100. In one example, the cleaning process converts all exposed silicon-containing oxide materials, including any semiconductor substrate silicon dioxide exposed within the device features, to a cleaning process reaction product material that will include a hydrated silicon salt-containing material, which is referred to for simplicity purposes as “silicon salt” in the remainder of the present application. In another example, the cleaning process performed in the first operation 210 of the method 200 includes utilizing an etching process, such as an ammonium fluoride dry etching process. Both ammonium fluoride and ammonium hydrogen fluoride react with silicon oxide using a dry etching process in a range from about -30 °C to about 100 °C relative to other silicon-containing materials. For purposes of the present disclosure, utilizing either or both of ammonium fluoride (NH4F) or ammonium hydrogen fluoride (NH4F•HF) is collectively referred to as “ammonium fluoride.” Likewise, using either or both of ammonium fluoride or ammonium hydrogen fluoride in an etching process is referred to as an “ammonium fluoride etching process.”

[0044] The exposure of each contact structure 308 within the plurality of stacked contact structures begins with a cleaning process performed during the first operation 210 of the method 200, which can be performed in a processing chamber, such as the processing chambers 110 or 114 within the processing system 100. In one example, the cleaning process converts all exposed silicon-containing oxide materials, including any semiconductor substrate silicon dioxide exposed within the device features, to a cleaning process reaction product material that will include a hydrated silicon salt-containing material, which is referred to for simplicity purposes as “silicon salt” in the remainder of the present application. In another example, the cleaning process performed in the first operation 210 of the method 200 includes utilizing an etching process, such as an ammonium fluoride dry etching process. Both ammonium fluoride and ammonium hydrogen fluoride react with silicon oxide using a dry etching process in a range from about -30 °C to about 100 °C relative to other silicon-containing materials. For purposes of the present disclosure, utilizing either or both of ammonium fluoride (NH4F) or ammonium hydrogen fluoride (NH4F•HF) is collectively referred to as “ammonium fluoride.” Likewise, using either or both of ammonium fluoride or ammonium hydrogen fluoride in an etching process is referred to as an “ammonium fluoride etching process.”

[0045] In one example, the cleaning process performed in the first operation 210 of the method 200 includes introducing both a hydrogen-containing precursor and a fluorine-containing precursor into a plasma / carrier gas. For example, ammonia (NH3) can be the hydrogen-containing precursor and nitrogen trifluoride (NF3) can be the fluorine-containing precursor introduced into the plasma / carrier gas mixture. Introducing both the hydrogen-containing precursor and the fluorine-containing precursor into the plasma / carrier gas results in both precursors being excited on a molecular level. In this excited state, the precursors dissociate in the carrier gas, thereby forming a first plasma-dissociated hydrogen-containing precursor and a first plasma-dissociated fluorine-containing precursor. The dissociated atomic species then recombine in the carrier gas (gas phase) to form one or both of ammonium fluoride (NH4F) or ammonium hydrogen fluoride (NH4F•HF) species. In one or more embodiments, the combined flow rate of the hydrogen-containing precursor and the fluorine-containing precursor is in a range from about 1 volume percent (vol.%) to 70 vol.%, including the end point values and all values therebetween, of the total gas mixture, while the remainder of the gas mixture comprises, consists of, or consists essentially of the carrier gas. In one or more embodiments, a purge gas or carrier gas is first introduced into the plasma generation region prior to providing the reactive gas.

[0046] In one example, the cleaning process, such as the first operation 210 of the method 200, includes maintaining an etch rate of the ammonium fluoride etch process based on a ratio of the hydrogen-containing precursor to the fluorine-containing precursor. A greater ratio of the fluorine-containing precursor to the hydrogen-containing precursor will result in an ammonium fluoride etchant with a relatively greater reactivity. In one or more embodiments, the molar ratio of the hydrogen-containing precursor to the fluorine-containing precursor introduced is in a range from about 1 :3 to 3: 1, such as from about 1 :3, 1 :2.5, 1 :2, 1 : 1.5, or 1 : 1 to about 1.5: 1, 2: 1, 2.5: 1, or 3: 1, including the endpoint values and all values therebetween. The molar ratio of the hydrogen-containing precursor to the fluorine-containing precursor in the etch gas mixture can be set to uniformly remove silicon oxide from all types of different semiconductor substrate trench junction surfaces.

[0047] In one or more embodiments, the cleaning process, such as the first operation 210 of the method 200, further includes maintaining the semiconductor substrate at a first deposition temperature. The first deposition temperature allows the ammonium fluoride etchant to condense out of the plasma / carrier gas and deposit as a solid into the device features, including along the feature sidewalls and feature bottoms. In one or more embodiments, the first deposition temperature can be at a value that prevents substantial reaction of the deposited ammonium fluoride etchant with native oxides present during deposition. The semiconductor substrate temperature can then be increased after deposition to facilitate tuning the reaction rate of the deposited ammonium fluoride etchant. In one or more embodiments, the first deposition temperature can be at a value that the ammonium fluoride etchant deposits on the semiconductor substrate surface and immediately or nearly immediately reacts with silicon oxide present on the surface. The first deposition temperature can depend on other process conditions, such as the pressure surrounding the semiconductor substrate. In one or more embodiments, the semiconductor substrate can be maintained at a first deposition temperature of less than 120 °C, such as in a range from about -30 °C to 120 °C, such as from about -30 °C, -20 °C, -10 °C, 0 °C, 10 °C, 20 °C, 30 °C, 40 °C, 50 °C, and 60 °C to 70 °C, 75 °C, 80 °C, 85 °C, 90 °C, 95 °C, 100 °C, 105 °C, 110 °C, 115 °C, and 120 °C, such as in a range from about 0 °C to 75 °C, including the endpoint values and all values therebetween.

[0048] Silicon salts are formed when the ammonium fluoride etchant reacts with native oxides. In one example of a silicon salt formed, ammonium hexafluorosilicate hydrate ((NH4)2SiF6*H2O) is present as a reaction product on the surface of the semiconductor substrate, which is the result in the presence of native oxide layers and bare silicon dioxide. Water, molecular hydrogen, and ammonia can also be present in the gas phase with the carrier gas, depending on the ratio of reactants introduced into the carrier gas / plasma. In some embodiments, the silicon salt formed on the exposed surface is removed by heating the substrate to cause the silicon salt material formed to sublimate and remove the undesirable material formed thereon.

[0049] In another example, the cleaning process performed in the first operation 210 of the method 200 includes generating a plasma formed with a carrier gas. The plasma / carrier gas combination can then be introduced to the surface of the semiconductor substrate with or without a bias. In one or more embodiments, the carrier gas can include, consist of, or consist essentially of an inert gas, such as argon, neon, and helium, and combinations thereof. In some examples, a hydrogen-containing gas, such as H2, and a carrier gas, such as argon (Ar), are provided to the surface of the semiconductor substrate while a bias is applied to the substrate.

[0050] Continuing from the end of the first operation 210 of the method 200, Figure 4B The second operation 220 of the method 200 shown includes forming a metal silicide layer on the exposed surface of each of the plurality of stacked contact structures 308, where forming the metal silicide layer on the exposed surface includes selectively depositing a first metal layer on the exposed surface.

[0051] In Figure 4B In the middle, a metal silicide layer 402 is shown formed on the top of the contact structures 308 and the top of the substrate 302 by the first metal deposition process. Forming the metal silicide layer 402 on the exposed surface of each of the stacked contact structures includes selectively depositing a first metal layer on the exposed contact structures 308. In one or more embodiments, the first metal for the first metal deposition process includes titanium (Ti). In other embodiments, where the source / drain regions of the stacked contact structures 308 can be silicon germanium (SiGe) or other p-type material, the first metal for the first metal deposition process can include molybdenum silicide (MoSi x ) in other embodiments, Mo or W can be interchanged, or a combination of both materials is employed.

[0052] In one or more embodiments, which can be combined with other embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing a metal silicide layer 402, such as titanium, by any suitable chemical deposition technique, including but not limited to a CVD or ALD process. In one or more embodiments, which can be combined with other embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing a metal silicide layer 402 using a metal-containing precursor gas and plasma. In some embodiments, the metal-containing precursor is selected from the group including titanium chloride (TiCl4), molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), molybdenum oxytetrachloride (MoOCl4), tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten pentabromide (WBr5), tungsten hexabromide (WBr6), or tris(3-hexynyl)carbonyl tungsten (W(CO(CH3CH2C≡CCH2CH3)3). In some embodiments, the first metal deposition process is selective to the surface of the contact structures 308 relative to the dielectric material of the intermodule insulating layer 304, which can be formed of a silicon-containing dielectric material such as silicon oxide or silicon nitride. While not wanting to be bound by theory, it is believed that the selective metal silicide deposition process has a selectivity to silicon (Si) or silicon / germanium (SiGe) in a range of about from 1.5: 1 to greater than 30: 1 relative to silicon oxide (SiO2) and silicon nitride (Si3N4). x N y ) having a selectivity to silicon (Si) or silicon / germanium (SiGe) in a range of about from 1.5: 1 to greater than 30: 1.

[0053] In one or more embodiments, the metal silicide layer 402 can include a metal, such as titanium (Ti), molybdenum (Mo), cobalt (Co), nickel (Ni), or tungsten (W), formed on top of the surface of the contact structure 308, and can have a thickness in a range from about 1 to 30 nm (about 10 to 300 A), such as in a range from about 3 to 20 nm (about 30 to 200 A), such as in a range from about 4 to about 25 nm (about 40 to 260 A of method 200), such as in a range from about 5 to about 20 nm (about 50 to 20 A), and such as about 10 nm (about 100 A). In one or more embodiments, which can be combined with other embodiments, a thickness of the metal silicide-containing material layer on top of the silicon dioxide substrate can be in a range from about 0.1 to 3 nm (about 1 to 30 A). In one or more embodiments, a target thickness of the metal silicide layer 402 (first metal layer formed on the exposed contact structure 308) has a thickness greater than or equal to about three nanometers. In one or more embodiments, a target thickness of the metal silicide layer 402 formed on top of the contact structure 308 can be determined based on a desired corresponding Schottky barrier height. In one or more embodiments, a target thickness of the metal silicide layer 402 formed on top of the contact structure 308 can be determined based on a desired corresponding gate structure contact resistance (Rc).

[0054] In some embodiments, as part of the process of depositing the metal silicide layer 402, a reducing agent to react with the metal-containing precursor is introduced into the carrier gas along with the metal-containing precursor. The reducing agent can be a hydrogen-containing composition, such as molecular hydrogen (H2), ammonia (NH3), hydrazine (N2H4), silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ), or combinations thereof. The reducing agent acts as a proton donor to cause the metal-containing precursor to form a metal film comprising the metal on top of the contact structure 308.

[0055] Continuing from the end of the second operation 220 of the method 200, Figure 4C The third operation 230 of the illustrated method 200 includes forming a second metal layer on the metal silicide layer 402, where forming the second metal layer on the first metal layer comprises selectively depositing a second metal layer 404 on the metal silicide layer 402. In one or more embodiments, the second metal layer 404 formed on top of the metal silicide layer 402 can be at least about 3 nm thick. In one or more embodiments, the second metal layer 404 acts as a seed layer to improve formation of one or more layers disposed above the second metal layer 404, for example, acts as a seed layer to improve formation of a third metal layer material or a conductor material disposed on the second metal layer 404.

[0056] InFigure 4C In some embodiments, a second metal layer 404 is formed on top of the metal silicide layer 402 by a second metal deposition process. In one or more embodiments, the metal used for the second metal deposition process can include a precursor containing fluorine-free tungsten (FFW). In one or more embodiments, the precursor containing FFW can include tungsten pentachloride (WC15), tungsten hexachloride (WC16), tungsten oxotetrachloride (WOC14), tungsten dioxide dichloride (W02C12), tungsten pentabromide (WBr5), tungsten hexabromide (WBr6), or combinations thereof. In one or more embodiments, the metal-containing precursor includes a fluorine-free metal organic, such as tris(3-hexynyl)carbonyltungsten (W(CO)(CH2CH2C≡CCH2CH3)3). In yet other embodiments, the metal used for the second metal deposition process can include molybdenum (Mo) formed by using a molybdenum-containing precursor, such as molybdenum pentachloride (M0C15), molybdenum hexachloride (M0C16), or molybdenum oxotetrachloride (M0OC14).

[0057] In one or more embodiments, which can be combined with other embodiments, the second metal deposition process, such as the third operation 230 of the method 200, includes selectively depositing the second metal layer 404, such as FFW, by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the chemical deposition technique can include a halide-based CVD or ALD, for example WC15plus diatomic hydrogen (H2). In one or more embodiments, which can be combined with other embodiments, the second metal deposition process, such as the second operation 220 of the method 200, includes selectively depositing the second metal layer 404 with a plasma and a carrier gas. The plasma / carrier gas can then be introduced toward the surface of the semiconductor substrate. In one or more embodiments, which can be combined with other embodiments, the carrier gas includes, consists of, or consists essentially of an inert gas, such as argon, neon, and helium, and combinations thereof.

[0058] Continuing from the end of the third operation 230 of the method 200, Figure 4D The fourth operation 240 of the illustrated method 200 includes forming a third metal layer 409 on the second metal layer 404, where forming the third metal layer 409 on the second metal layer 404 includes conformally depositing the third metal layer 409 on the second metal layer 404.

[0059] In Figure 4DIn some embodiments, a third metal layer 409 is formed on top of the second metal layer 404 by a third metal deposition process. In one or more embodiments, the metal used for the third metal deposition process can be comprised of a conductive material. The conductive material can include various metal alloys, metals, or conductive ceramics, including but not limited to one or more of aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and combinations thereof.

[0060] In one or more embodiments, which can be combined with other embodiments, the third metal deposition process, such as the fourth operation 240 of the method 200, includes selectively depositing the third metal layer 409 by any suitable chemical conformal deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the thickness of the third metal layer 409 formed on top of the second metal layer 404 can be at least about 5 nanometers (nm).

[0061] In one or more embodiments, the third metal layer 409 acts as a seed layer to improve formation of one or more layers disposed on the third metal layer 409, for example, to improve formation of a subsequent metal layer material or conductor material disposed on the third metal layer 409.

[0062] Continuing from the fourth operation 240 of the method 200, in which the third metal layer 409 has been deposited on top of the second metal layer 404, Figure 4E The fifth operation 250 of the method 200, as shown, includes filling the opening 401 with a conductor material.

[0063] In Figure 4E In some embodiments, a third metal layer 409 is formed on top of the second metal layer 404 by a third metal deposition process. In one or more embodiments, the metal used for the third metal deposition process can be comprised of a conductive material. The conductive material can include various metal alloys, metals, or conductive ceramics, including but not limited to one or more of aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and combinations thereof.

[0064] In one or more embodiments, which can be combined with other embodiments, the fourth metal deposition process (such as the fifth operation 250 of the method 200) includes selectively depositing the conductor material 406 by any suitable chemical deposition technique, including but not limited to CVD or ALD. In other embodiments, which can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the opening 401 with the conductor material.

[0065] In yet other embodiments, which can be combined with other embodiments, the fourth metal deposition process (such as the fifth operation 250 of the method 200) includes using PVD, PVD and pullback, or PVD and direct selective fill to selectively deposit the conductor material 406 that fills the opening 401.

[0066] Continuing from the fifth operation 250 of the method 200, Figure 4F The sixth operation 260 of the illustrated method 200 includes depositing a cap layer 408 on the conductor material 406. In Figure 4F In one or more embodiments, which can be combined with other embodiments, the material used for the fourth metal deposition process can include tungsten (W). In other embodiments, which can be combined with other embodiments, the conductor material used for the second metal deposition process can include molybdenum (Mo).

[0067] In one or more embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the sixth operation 260 of the method 200) includes selectively depositing the cap layer 408 on top of the conductor material 406 that fills the opening 401 by any suitable chemical deposition technique, including but not limited to CVD or ALD. In other embodiments, which can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to deposit the cap layer 408.

[0068] In yet other embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the sixth operation 260 of the method 200) includes depositing the cap layer 408 on top of the conductor material 406 that fills the opening 401 using a metal-containing precursor gas and plasma.

[0069] In yet other embodiments, the fourth metal deposition process (such as the fifth operation 250 of the method 200) includes using PVD, PVD and pullback, or PVD and direct selective fill to selectively deposit the conductor material 406 that fills the opening 401.

[0070] First alternative fill process

[0071] Reference Figures 4G to 4I Best mode understanding of alternative embodiments of the method 200. Figure 2 of the method 200. Figures 4G to 4I A cross-sectional view of a portion of a semiconductor structure 300 is shown in accordance with embodiments described herein. The cross-sectional view is taken along the Y direction of view in the semiconductor structure 300. Figures 4G to 4I , a view of a portion of the semiconductor structure 300 from 4X to 4X' in the semiconductor structure 300. Figure 3 Continuing from the previous reference to the third operation 230 of the method 200 described above,

[0072] The fourth operation 240 of the method 200 shown includes forming a third metal layer 409 on the second metal layer 404, where forming the third metal layer 409 on the first metal layer includes depositing the third metal layer 409 on the second metal layer 404 and the substrate 302 by using a physical vapor deposition (PVD) process. Figure 4C Figure 4G In one or more embodiments, the metal used for the third metal deposition process can include a conductive material. The conductive material can include various metal alloys, metals, or conductive ceramics, including but not limited to one or more of aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and combinations thereof.

[0073] In one or more embodiments, which can be combined with other embodiments, the third metal deposition process (such as the fourth operation 240 of the method 200) includes selectively depositing the third metal layer 409 by any suitable deposition technique, including but not limited to PVD, CVD, or ALD. In one or more embodiments, the thickness of the third metal layer 409 formed on top of the second metal layer 404 can be at least about 5 nanometers (nm).

[0074] In one or more embodiments,

[0075] In one or more embodiments, Figure 4G ​In some embodiments, a third metal deposition process is used to deposit a metal layer on top of the second metal layer 404 and the top of the substrate 302. In one or more embodiments, the metal used for the third metal deposition process can include a conductive material. The conductive material can include various metal alloys, metals, or conductive ceramics, including but not limited to one or more of aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and combinations thereof.

[0076] The third metal deposition process, such as the fourth operation 240 of the method 200, includes depositing a third metal layer 409 by using a PVD deposition technique. In one or more embodiments, which can be combined with other embodiments, the third metal deposition process, such as the fourth operation 240 of the method 200, includes sputtering material from a target containing a metal or metal alloy including W, Mo, Co, Ti, Ru, Cu, or other useful metals to form the third metal layer 409. In one example, the third metal layer 409 includes W or Mo. In some embodiments, a bias is applied to the substrate during the third metal deposition process to improve the bottom coverage of the third metal layer 409 (i.e., the third metal layer 409 at the bottom of the opening 401) formed. The substrate bias process is performed by grounding an electrode disposed within a substrate support above which the substrate is positioned below the PVD target during the sputter deposition process. The thickness of the third metal layer 409 formed on top of the second metal layer 404 and the top of the substrate 302 can be at least about 5 nm. Figure 4G

[0077] From the fourth operation 240 of the method 200 described in Figure 4G where the third metal layer 409 has been deposited on top of the second metal layer 404, Figure 4H The fifth operation 250 of the method 200 shown includes filling the opening 401 with a conductor material 406.

[0078] In some embodiments, the fifth operation 250 of the method 200 includes depositing a third metal layer 409 on top of the second metal layer 404 and the top of the substrate 302. In one or more embodiments, the third metal layer 409 can include a conductive material. The conductive material can include various metal alloys, metals, or conductive ceramics, including but not limited to one or more of aluminum (Al), chromium (Cr), cobalt (Co), copper (Cu), gold (Au), hafnium (Hf), iridium (Ir), iron (Fe), lanthanum (La), manganese (Mn), molybdenum (Mo), niobium (Nb), platinum (Pt), rhodium (Rh), ruthenium (Ru), silver (Si), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), vanadium (V), yttrium (Y), zirconium (Zr), and combinations thereof. Figure 4H ​In some embodiments, the fifth operation 250 of the method 200 continues with depositing a conductor material 406 to fill the opening 401. In one or more embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the fifth operation 250 of the method 200) includes depositing the conductor material 406 by any suitable chemical deposition technique, including but not limited to CVD or ALD. In other embodiments, which can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the opening 401 with the conductor material.

[0079] In one or more embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the fifth operation 250 of the method 200) includes depositing the conductor material 406 by any suitable chemical deposition technique, including but not limited to CVD or ALD, such as a precursor including WF6. In other embodiments, which can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the opening 401 with the conductor material.

[0080] In yet other embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the fifth operation 250 of the method 200) includes using PVD, PVD and pullback, or PVD and direct selective fill to selectively deposit the conductor material 406 to fill the opening 401.

[0081] From Figure 4H The fifth operation 250 of the method 200 continues with depositing a conductor material 406 to fill the opening 401. In one or more embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the fifth operation 250 of the method 200) includes depositing the conductor material 406 by any suitable chemical deposition technique, including but not limited to CVD or ALD. In other embodiments, which can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to fill the opening 401 with the conductor material. Figure 4I The sixth operation 260 of the method 200, shown in FIG. 2B, includes depositing a cap layer 408 over the conductor material 406. In one or more embodiments, which can be combined with other embodiments, the fifth metal deposition process (such as the sixth operation 260 of the method 200) includes depositing the cap layer 408 by any suitable chemical deposition technique, including but not limited to CVD or ALD, over the top of the conductor material 406 that fills the opening 401. In other embodiments, which can be combined with other embodiments, a conventional conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process is used to deposit the cap layer 408.

[0082] In one embodiment, which can be combined with other embodiments, the fifth metal deposition process (such as the sixth operation 260 of the method 200) includes depositing the cap layer 408 by using a metal-containing precursor gas and plasma over the top of the conductor material 406 that fills the opening 401.

[0083] Second Alternative Fill Process

[0084] Reference is made to Figure 4J Best Mode for Understanding Figure 2 Another alternative embodiment of the method 200. Figure 4J A cross-sectional view of a portion of a semiconductor structure 300 is shown in accordance with embodiments described herein. Figure 4J A cross-sectional view of a portion of the semiconductor structure 300 from 4X to 4X' is illustrated in accordance with embodiments described herein. Figure 3 A cross-sectional view of a portion of the semiconductor structure 300 from 4X to 4X' is illustrated in accordance with embodiments described herein.

[0085] Continuing from the end of the first operation 210 described above, Figure 4J The second operation 220 of the method 200 shown in FIG. 2B includes forming a metal silicide layer on the exposed surface of each of the plurality of stacked contact structures 308 and on the surface of the substrate 302, where forming the metal silicide layer on the exposed surface includes selectively depositing a first metal layer on the exposed surface. Additionally in Figure 4J In one or more embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing the metal silicide layer 402 by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing the metal silicide layer 402 with a metal-containing precursor gas and plasma.

[0086] In Figure 4J In one or more embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing the metal silicide layer 402 by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing the metal silicide layer 402 with a metal-containing precursor gas and plasma. x In other embodiments, Mo or W can be interchanged, or a combination of both materials is employed.

[0087] In one or more embodiments, which can be combined with other embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing the metal silicide layer 402, such as titanium, by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, which can be combined with other embodiments, the first metal deposition process (such as the second operation 220 of the method 200) includes selectively depositing the metal silicide layer 402 with a metal-containing precursor gas and plasma.

[0088] The first metal deposition process is selective to the contact structures 308 and the substrate 302 relative to the dielectric material of the intermodule insulating layer 304, which can be formed of a silicon-containing dielectric material such as silicon oxide or silicon nitride. While not wanting to be bound by theory, it is believed that the selective metal silicide deposition process has a selectivity to silicon (Si) or silicon / germanium (SiGe) in a range of about from 1.5: 1 to greater than 30: 1 relative to silicon oxide (Si02) and silicon nitride (Si3N4). x N y ) in a range of about from 1.5: 1 to greater than 30: 1.

[0089] In one or more embodiments, the thickness of the metal silicide layer 402 formed on top of the contact structures 308 and the substrate 302 can be in a range of from about 1 to 30 nm (about 10 to 300 A), such as in a range of from about 3 to 20 nm (about 30 to 200 A), such as in a range of from about 4 to about 25 nm (about 40 to 260 of method 200A), such as in a range of from about 5 to about 20 nm (about 50 to 20 A), and such as about 10 nm (about 100 Angstroms). In one or more embodiments, which can be combined with other embodiments, the thickness of the metal silicide-containing material layer on top of the silicon dioxide substrate can be in a range of from about 0.1 to 3 nm (about 1 to 30 A). In one or more embodiments, the target thickness of the metal silicide layer 402 formed on top of the contact structures 308 can be determined based on a desired corresponding Schottky barrier height. In one or more embodiments, the target thickness of the metal silicide layer 402 formed on top of the contact structures 308 can be determined based on a desired corresponding gate structure contact resistance (Rc).

[0090] In one or more embodiments, the deposition time of the first metal deposition process, such as the second operation 220 of method 200, which includes selectively depositing the metal silicide layer 402, can take less than about 100 seconds.

[0091] The illustrated second metal layer 404 is formed on top of the metal silicide layer 402 by a second metal deposition process. In one or more embodiments, the metal used for the second metal deposition process can include a precursor containing fluorine-free tungsten (FFW). In one or more embodiments, the precursor containing FFW can include tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten pentabromide (WBr5), or tungsten hexabromide (WBr6). In yet other embodiments, the metal precursor used for the second metal deposition process can include molybdenum (Mo), such as a precursor including molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), or molybdenum oxytetrachloride (MoOCl4). The second metal deposition process is selective to the metal silicide layer 402, which can be formed of titanium silicide (TiSi2). While not wanting to be bound by theory, it is believed that the selective second metal deposition process has a selectivity to TiSi2in a range of about from 1.5: 1 to greater than 30: 1 relative to silicon oxide (SiO2) and silicon nitride (Si3N4). In one or more embodiments, the thickness of the second metal layer 404 formed on top of the metal silicide layer 402 can be at least about 3 nm. x N y ) has a selectivity to TiSi2in a range of about from 1.5: 1 to greater than 30: 1. In one or more embodiments, the thickness of the second metal layer 404 formed on top of the metal silicide layer 402 can be at least about 3 nm.

[0092] In one or more embodiments, which can be combined with other embodiments, the second metal deposition process, such as the third operation 230 of the method 200, includes selectively depositing the second metal layer 404, such as FFW, by any suitable chemical deposition technique, including but not limited to CVD or ALD. In one or more embodiments, the chemical deposition technique can include a halide-based CVD or ALD, for example WCl5plus diatomic hydrogen (H2). In one or more embodiments, which can be combined with other embodiments, the second metal deposition process, such as the second operation 220 of the method 200, includes selectively depositing the second metal layer 404 with a metal-containing precursor gas and a plasma. The plasma / carrier gas can then be introduced toward the surface of the semiconductor substrate.

[0093] Following the second operation 220 of the method 200 and the third operation 230 of the method 200 within the second alternative fill process sequence discussed above with respect to Figure 4J Following the second operation 220 of the method 200 and the third operation 230 of the method 200 within the second alternative fill process sequence discussed above with respect to

[0094] As can be appreciated by one of ordinary skill in the art, one or more configurations of semiconductor substrates or other portions and features of the same semiconductor substrate, such as contact junctions, can benefit from the described processes and methods.

[0095] Although this specification contains many specifics, these should not be construed as limiting the scope of the application but merely as describing a particular implementation thereof. Some features described in the context of separate implementations can also be implemented together in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented separately or in any suitable subcombination. Moreover, although previously described features can be described as acting in certain combinations and even initially claimed as such, in some cases, the present application can from the claimed combination, and the claimed combination can be directed to a subcombination or variation of a subcombination.

[0096] Particular implementations of the subject matter have been described. Other implementations, alterations, and permutations of the described implementations are within the scope of the following claims as will be apparent to those skilled in the art. While operations are depicted in the drawings or claims in a particular, chronological order, this should not be understood as requiring or implying that such operations be performed in that order, or performed at all, unless the order or

[0097] Furthermore, any claimed implementation is considered applicable to at least one of (a) a computer-implemented method; (b) a non-transitory computer-readable medium storing computer-readable instructions to perform the computer-implemented method; and (c) a computer system comprising computer memory interoperability coupled with a hardware processor configured to perform the computer-implemented method or the instructions stored on the non-transitory computer-readable medium.

[0098] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these systems, devices, methods, processes, and compositions belong.

[0099] In this disclosure, the terms "top," "bottom," "side," "over," "under," "upper," "lower," "upward," "downward," "horizontal," "vertical," and like terms, do not denote absolute directions. Rather, these terms denote directions relative to an unspecified reference plane. This unspecified reference plane can be vertical, horizontal, or other angular orientation.

[0100] The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Within the claims, reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more." Unless otherwise specifically stated, the term "some" refers to one or more.

[0101] Embodiments of the present disclosure can suitably "comprise," "consist of," or "consist essentially of," the disclosed limiting features and can be practiced without the disclosed limiting features. As used herein and in the appended claims, the words "comprise," "have," and "include," and all grammatical variations thereof, are each intended to have an open, non-limiting meaning that does not preclude the addition of one or more additional elements or steps.

[0102] "Optional" or "optionally" means that the subsequently described material, event, or circumstance can or can not occur or exist.

[0103] As used, the term "determining" encompasses a wide variety of actions. For example, "determining" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, "determining" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, "determining" can include resolving, selecting, choosing, and the like.

[0104] When the word "about" or "approximately" is used, the term can mean that the value in question differs from a stated value by no more than 10%, by no more than 5%, by no more than 2%, by no more than 1%, by no more than 0.5%, by no more than 0.1%, or by no more than 0.01%.

[0105] Ranges can be expressed as from about one particular value to about another particular value. When such a range is expressed, it is to be understood that another embodiment is from the one particular value to the other particular value, along with all the intervening values and combinations thereof.

[0106] As used, terms such as "first" and "second" are arbitrarily assigned and are merely intended to differentiate between two or more components of a system, device, or composition. It will be appreciated that the words "first" and "second" are not intended to denote a sequential order or a relative position or location of the components, and are merely intended to differentiate between two or more components of a system, device, or composition. Furthermore, it will be appreciated that the use of the terms "first" and "second" does not require the presence of any "third" component, although that possibility is contemplated within the scope of the various embodiments described.

[0107] While only a few example embodiments have been described in detail, it will be appreciated that modifications to the described embodiments can be made without departing from the scope of the disclosed application. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures. Applicants note that 35 U.S.C. § 112, paragraph 6 does not require that the structure be the only way to implement the function and thus the claim limits the scope of the technology to the plain and ordinary meaning of the language used in the claims.

[0108] The following claims are not intended to be limited to the embodiments provided, but rather are intended to be accorded the full scope consistent with the language of the claims.

Claims

1. A method for forming a contact structure on a semiconductor substrate, comprising the following steps: Material is removed from the surface of a feature formed on the surface of a substrate, wherein The feature includes a plurality of contact structures disposed within the feature formed in the substrate. The contact structure includes multiple contacts, each of which contains silicon (Si) or silicon-germanium (SiGe). Each of the plurality of contacts is spaced apart by a dielectric layer in a first direction, and The method for removing material includes the following steps: A reaction product material is selectively formed above the surface of each of the plurality of contacts; as well as The substrate is heated to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts; A first metal layer is selectively formed on the surface of each of the plurality of contacts; Forming a second metal layer on the first metal layer, wherein forming the second metal layer on the first metal layer includes selectively depositing the second metal layer on the first metal layer, and the step of selectively forming the second metal layer includes the step of exposing the surface of the selectively formed first metal layer to a precursor containing a fluorine-free metal to form the second metal layer; The feature is filled with a conductive material, wherein the conductive material comprises tungsten (W) or molybdenum (Mo); as well as A capping layer is deposited on the conductor material.

2. The method of claim 1, wherein the reaction product material comprises a material containing a silicon salt.

3. The method of claim 2, wherein the silicon salt-containing material comprises ammonium hexafluorosilicate.

4. The method of claim 3, wherein the first metal layer comprises a metal silicide layer, the metal silicide layer comprising titanium.

5. The method of claim 1, wherein the precursor containing a fluorine-free metal comprises tungsten and a halogen-containing gas.

6. The method of claim 5, wherein the precursor containing a fluorine-free metal is selected from the group consisting of tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten pentabromide (WBr5), and tungsten hexabromide (WBr6).

7. The method of claim 1, wherein the precursor containing a fluorine-free metal comprises molybdenum and a halogen-containing gas.

8. The method of claim 7, wherein the precursor containing a fluorine-free metal is selected from the group consisting of molybdenum pentachloride (MoCl5), molybdenum hexachloride (MoCl6), and molybdenum oxychloride (MoOCl4).

9. The method of claim 8, wherein the step of filling the feature with the conductor material comprises the step of selectively forming the conductor material on the first metal layer, which comprises exposing the first metal layer to a fluorine-containing precursor.

10. The method of claim 9, wherein the step of selectively forming the conductor material comprises the step of exposing the second metal layer to a metal precursor comprising molybdenum (Mo).

11. The method of claim 9, wherein the step of selectively forming the conductor material comprises the step of exposing the second metal layer to a metal precursor comprising tungsten hexafluoride (WF6).

12. The method of claim 1, wherein the first metal layer formed on the exposed surface has a thickness of about three nanometers or more.

13. The method of claim 12, wherein the first metal layer on the exposed surface comprises a first metal layer target thickness determined by a corresponding Schottky barrier height (SBH).

14. The method of claim 1, wherein the step of selectively depositing the second metal layer on the outer surface of the first metal layer on the exposed surface comprises a second metal layer thickness greater than or equal to about three nanometers.

15. The method of claim 1, wherein the step of selectively forming a first metal layer on the plurality of contacts comprises the step of introducing a hydrogen-containing reducing agent and a first metal-containing precursor into the contact surface such that the first metal layer is formed on top of the contact surface comprising silicon or silicon-germanium.

16. The method of claim 15, wherein the hydrogen-containing reducing agent comprises molecular hydrogen (H2).

17. The method of claim 12, wherein the first metal layer on the exposed surface comprises a first metal layer target thickness determined by the corresponding gate contact structure resistance (Rc).

18. The method of claim 1, wherein the second metal layer provides an oxygen (O) barrier, or a fluorine (F) barrier, or both an O and a F barrier.

19. The method of claim 1, wherein the second metal layer serves as a seed layer for the conductor material.

20. The method of claim 1, further comprising the step of: forming a third metal layer on the second metal layer, wherein the step of forming the third metal layer on the second metal layer comprises the step of: selectively depositing the third metal layer on the second metal layer.

Images