Grinding control methods, grinding control systems, and grinding methods

Abstract

This application provides a grinding control method, a grinding control system, and a grinding method. The grinding control method is applied to a grinding process that grinds a semiconductor structure obtained from a preceding grinding process. This grinding process includes a first sub-grinding process and a second sub-grinding process. The grinding control method includes: obtaining the preceding thickness and the remaining thickness of the semiconductor structure before and after performing the first sub-grinding process; determining the compensation grinding time and compensation grinding pressure for multiple grinding regions in the second sub-grinding process based on the preceding thickness, the remaining thickness, a first preset grinding parameter, and a second preset grinding parameter, combined with a grinding time compensation coefficient determination rule and a grinding pressure compensation coefficient determination rule; and controlling the execution of the second sub-grinding process based on the compensation grinding time and the compensation grinding pressure for multiple grinding regions. Through the embodiments of this application, the overall thickness uniformity of the ground semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments in the present application relate to the technical field of semiconductor technology, and in particular to a control method of grinding, a control system of grinding and a grinding method. BACKGROUND

[0002] Chemical mechanical polishing (CMP) process is a key process in semiconductor manufacturing, which is widely used in the planarization of metal material layers such as aluminum (Al), copper (Cu) and tungsten (W), and dielectric layers such as silicon oxide (SiO2) and silicon nitride (SiN). With the development of semiconductor devices towards high integration and miniaturization, the micro-topography control of wafer surface has important influence on the performance, reliability and production yield of devices.

[0003] In the process of grinding a multi-layer semiconductor structure formed by metal material and non-metal material by using chemical mechanical polishing process, in order to improve the overall grinding efficiency under the premise of meeting the process precision requirement, the grinding process is usually divided into two stages of primary grinding and fine grinding.

[0004] However, in the existing chemical mechanical polishing process, the topography defects in the primary grinding stage may be inherited to the fine grinding stage, and the topography defects are difficult to be eliminated in the fine grinding stage, resulting in low thickness uniformity of the overall semiconductor structure obtained by grinding. SUMMARY

[0005] Therefore, embodiments of the present application provide a control method of grinding, a control system of grinding and a grinding method to improve the thickness uniformity of the overall semiconductor structure obtained by grinding.

[0006] In one aspect, one embodiment of the present application provides a control method of polishing, which is applied to a polishing process, wherein the polishing process is used to polish a semiconductor structure prepared by a previous process of the polishing process, and the polishing process comprises a first sub-polishing process and a second sub-polishing process, wherein the polishing accuracy of the first sub-polishing process is less than that of the second sub-polishing process; the control method of polishing comprises: obtaining a pre-process thickness before the first sub-polishing process is performed on the semiconductor structure and a remaining thickness after the first sub-polishing process is performed on the semiconductor structure, wherein the pre-process thickness and the remaining thickness each comprise thicknesses of regions corresponding to a plurality of polishing regions in the semiconductor structure; determining a compensation polishing time of the second sub-polishing process according to the pre-process thickness, the remaining thickness, and a first preset polishing parameter, in combination with a polishing time compensation coefficient determination rule; determining a compensation polishing pressure of the plurality of polishing regions during the execution of the second sub-polishing process according to the pre-process thickness, the remaining thickness, and a second preset polishing parameter, in combination with a polishing pressure compensation coefficient determination rule, with a polishing pressure of a reference polishing region as a reference; and controlling the execution of the second sub-polishing process based on the compensation polishing time and the compensation polishing pressure of the plurality of polishing regions.

[0007] Optionally, the step of obtaining the pre-process thickness before the first sub-polishing process is performed on the semiconductor structure and the remaining thickness after the first sub-polishing process is performed on the semiconductor structure comprises: measuring thicknesses of regions corresponding to a plurality of polishing regions in the semiconductor structure before the first sub-polishing process is performed on the semiconductor structure to obtain the pre-process thickness; obtaining coordinate information of polishing end points of regions corresponding to a plurality of polishing regions in the semiconductor structure in a first sub-polishing coordinate system after the first sub-polishing process is performed on the semiconductor structure; and processing the coordinate information to obtain the remaining thickness.

[0008] Optionally, the remaining thickness comprises a remaining thickness of the reference polishing region after the first sub-polishing process is performed on the semiconductor structure, the reference polishing region is a polishing region with the smallest change in average thickness after polishing among a plurality of batches of historical polishing process data, and the polishing pressure of the reference polishing region is a preset constant pressure.

[0009] Optionally, the first preset grinding parameter comprises a first preset target thickness and a preset grinding rate; wherein the first preset target thickness is a preset remaining thickness average of the semiconductor structure as a whole after performing the previous process; and the step of determining the compensation grinding time of the second sub-grinding process based on the previous thickness, the remaining thickness and the first preset grinding parameter, and combining a grinding time compensation coefficient determination rule comprises: obtaining a previous thickness average and a remaining thickness average before and after performing the first sub-grinding process on the semiconductor structure based on the previous thickness and the remaining thickness; calculating a first expected grinding time of the second sub-grinding process according to the previous thickness average, the first preset target thickness and the preset grinding removal rate; calculating a second expected grinding time of the second sub-grinding process according to the remaining thickness average, the remaining thickness of the reference grinding area and the preset grinding removal rate; determining the grinding time compensation coefficient according to the grinding time compensation coefficient determination rule; and summing the first expected grinding time and the second expected grinding time based on the grinding time compensation coefficient to obtain the compensation grinding time of the second sub-grinding process.

[0010] Optionally, the grinding time compensation coefficient comprises a first time compensation coefficient corresponding to the first expected grinding time and a second time compensation coefficient corresponding to the second expected grinding time; wherein the ratio of the second time compensation coefficient to the first time compensation coefficient is the ratio of the grinding removal rate of the metal material to the non-metal material under the same grinding condition; and the value range of the first time compensation coefficient and the value range of the second time compensation coefficient both fall within the ratio range of the process window of the grinding process to the process error of the previous process.

[0011] Optionally, the second preset grinding parameters include a second preset target thickness, a preset grinding time, a preset relative speed between the semiconductor structure and the grinding pad, and a grinding base coefficient; wherein the second preset target thickness includes preset remaining thicknesses of regions corresponding to the plurality of grinding regions in the semiconductor structure after the previous process is performed; based on the previous thicknesses, the remaining thicknesses, and the second preset grinding parameters, and taking the grinding pressure of the reference grinding region as a reference, the compensation grinding pressure of the plurality of grinding regions during the second sub-grinding process is determined by combining a grinding pressure compensation coefficient determination rule, including: repeatedly performing the following sub-steps until the compensation grinding pressure of the plurality of grinding regions except the reference grinding region is determined; the sub-steps include: for any grinding region except the reference grinding region, calculating a first expected grinding pressure of the grinding region during the second sub-grinding process according to the previous thickness of the grinding region, the second preset target thickness of the grinding region, the preset grinding time, the compensation grinding time, the preset relative speed, and the grinding base coefficient; calculating a second expected grinding pressure of the grinding region during the second sub-grinding process according to the remaining thickness of the grinding region, the remaining thickness of the reference grinding region, the second preset target thickness of the grinding region, the preset grinding time, the compensation grinding time, the preset relative speed, and the grinding base coefficient; determining the grinding pressure compensation coefficient by using the grinding pressure compensation coefficient determination rule; and summing the first expected grinding pressure, the second expected grinding pressure, and the preset grinding pressure of the remaining grinding regions except the grinding region to obtain the compensation grinding pressure of the grinding region based on the grinding pressure compensation coefficient.

[0012] Optionally, the step of determining the grinding pressure compensation coefficient by using the grinding pressure compensation coefficient determination rule includes: establishing a second mapping relationship between grinding removal rate variation and grinding pressure variation based on a first mapping relationship between grinding removal rate and grinding pressure; taking each grinding region as a target grinding region, adjusting the grinding pressure of the target grinding region based on the grinding pressure of the reference grinding region, and measuring the grinding removal rate of the target grinding region and the grinding removal rate of the non-target grinding region to obtain a grinding pressure variation set and a grinding removal rate variation set; and calculating the grinding pressure compensation coefficient based on the grinding pressure variation set, the grinding removal rate variation set, and the second mapping relationship.

[0013] Optionally, the control method of the polishing further comprises: constructing an optimization model of a compensation polishing pressure of the polishing region for any polishing region except the reference polishing region; wherein, an optimization objective of the optimization model is that a sum of deviations of polishing removal rates of the plurality of polishing regions is minimum; a constraint condition of the optimization model is that the deviations of the polishing removal rates of the plurality of polishing regions do not exceed a specified threshold; and the optimization model is solved by using a linear programming algorithm or a sequential quadratic programming algorithm to obtain the optimized compensation polishing pressure of the polishing region.

[0014] In another aspect, one embodiment of the present application provides a control system of a polishing process, the polishing process being used to polish a semiconductor structure prepared by a previous process of the polishing process, the polishing process comprising a first sub-polishing process and a second sub-polishing process, wherein a polishing accuracy of the first sub-polishing process is less than a polishing accuracy of the second sub-polishing process; the control system of the polishing process comprising: a thickness acquisition module, configured to acquire a pre-sequencing thickness before the first sub-polishing process is performed on the semiconductor structure and a remaining thickness after the first sub-polishing process is performed on the semiconductor structure; wherein the pre-sequencing thickness and the remaining thickness both comprise thicknesses of regions corresponding to a plurality of polishing regions in the semiconductor structure, respectively; a second sub-polishing process pre-feedback module, configured to determine a compensation polishing time of the second sub-polishing process according to the pre-sequencing thickness, the remaining thickness and a first preset polishing parameter, in combination with a polishing time compensation coefficient determination rule; and determine a compensation polishing pressure of the plurality of polishing regions during the execution of the second sub-polishing process according to the pre-sequencing thickness, the remaining thickness and a second preset polishing parameter, in combination with a polishing pressure compensation coefficient determination rule, with a polishing pressure of a reference polishing region as a benchmark; and a second sub-polishing process control module, configured to control the execution of the second sub-polishing process based on the compensation polishing time and the compensation polishing pressure of the plurality of polishing regions.

[0015] In yet another aspect, one embodiment of the present application provides a polishing method, which is controlled by the control method of the polishing as described in the above embodiments, or the polishing method is controlled by the control system of the polishing as described in the above embodiments.

[0016] In the embodiments provided in the present application, by acquiring a pre-sequencing thickness before performing a first sub-grinding process on a semiconductor structure and a remaining thickness after performing the first sub-grinding process, wherein the pre-sequencing thickness and the remaining thickness each include the thickness of a region in the semiconductor structure corresponding to a plurality of grinding regions, then according to the pre-sequencing thickness, the remaining thickness, and a first preset grinding parameter, a compensation grinding time of a second sub-grinding process is determined in combination with a grinding time compensation coefficient determination rule, and a compensation grinding pressure of the plurality of grinding regions is determined according to the pre-sequencing thickness, the remaining thickness, and a second preset grinding parameter with reference to the grinding pressure of a reference grinding region in combination with a grinding pressure compensation coefficient determination rule, and the execution of the second sub-grinding process is controlled based on the compensation grinding time and the compensation grinding pressure, and the unexpected effects achieved include: due to the compensation of the grinding time of the second sub-grinding process and the grinding pressure of different regions based on the pre-sequencing thickness and the remaining thickness, the regional topography defects left after the completion of the first sub-grinding process are corrected in the process of executing the second sub-grinding process, thereby reducing the retention of thickness deviation caused by the insufficient planarization degree of the first sub-grinding process, and improving the thickness uniformity of the semiconductor structure as a whole. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Figure 1 For the process diagram of the structure wafer provided in the related art for grinding in stages, Figure 1 Fig. (a) is a diagram of a structure wafer prepared by a pre-process of grinding provided in the related art, Figure 1 Fig. (b) is a diagram of a structure wafer performing a preliminary planarization process step provided in the related art, Figure 1 Fig. (c) is a diagram of a structure wafer performing an over-grinding process step provided in the related art, Figure 1 Fig. (d) is a diagram of a structure wafer performing a fine grinding provided in the related art.

[0019] Figure 2 For the diagram of the etching defects caused after grinding by using the grinding method provided in the related art.

[0020] Figure 3 For the diagram of the interconnection structure missing defects caused after grinding by using the grinding method provided in the related art.

[0021] Figure 4A schematic diagram of a contact structure missing defect caused by a grinding method provided by the related art.

[0022] Figure 5 A schematic diagram of a force distribution of a grinding process provided by the related art.

[0023] Figure 6 A schematic diagram of a flow of a control method of grinding provided by an embodiment of the present application.

[0024] Figure 7 A schematic diagram of a flow of obtaining a pre-sequencing thickness and a reserved thickness provided by an embodiment of the present application.

[0025] Figure 8 A schematic diagram of a cross-sectional structure of a grinding head having multiple grinding chambers provided by an embodiment of the present application.

[0026] Figure 9 A schematic diagram of a three-dimensional structure of a grinding head having multiple grinding chambers provided by an embodiment of the present application.

[0027] Figure 10 A schematic diagram of a signal of a grinding endpoint of a first sub-grinding process obtained by an embodiment of the present application.

[0028] Figure 11 A schematic diagram of coordinate information of a grinding endpoint of a first sub-grinding process in a first sub-grinding coordinate system provided by an embodiment of the present application.

[0029] Figure 12 A schematic diagram of a flow of determining a compensation grinding time of a second sub-grinding process provided by an embodiment of the present application.

[0030] Figure 13 A schematic diagram of a distribution of multiple regions in a semiconductor structure provided by an embodiment of the present application.

[0031] Figure 14 A schematic diagram of a flow of determining a compensation grinding pressure of any grinding region except a reference grinding region during a second sub-grinding process provided by an embodiment of the present application.

[0032] Figure 15 A schematic diagram of a flow of determining a grinding pressure compensation coefficient provided by an embodiment of the present application.

[0033] Figure 16 A schematic diagram of a structure of a control system of grinding provided by another embodiment of the present application.

[0034] Figure 17 A comparative schematic diagram of thickness uniformity of a semiconductor structure obtained by a grinding method provided by the related art and thickness uniformity of a semiconductor structure obtained by a grinding method provided by an embodiment of the present application.

[0035] STRUCTURE LABEL EXPLANATION

[0036] 101, metal layer; 102, isolation layer; 103, dielectric layer. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments of the present application.

[0038] The drawings provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the drawings, not the number, shape and size of the components when actually implemented. The shape, number and proportion of each component can be changed when actually implemented, and the component layout form can also be more complex.

[0039] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application, and do not indicate or imply that the indicated device or component must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include one or more of the features.

[0040] In the related art, after receiving a structure wafer prepared by a previous process of grinding, in order to balance the grinding efficiency and grinding process precision, and also to reduce the process complexity of grinding to remove different materials on the structure wafer, the grinding process is usually divided into two stages of primary grinding and fine grinding. In the primary grinding stage, most of the target materials (for example, metal materials and / or non-metal materials) are quickly removed through a higher grinding rate to preliminarily realize the planarization of the surface of the structure wafer. In the fine grinding stage, the local topography of the structure wafer surface is further corrected through methods of controlling the grinding parameters such as controlling the grinding pressure and optimizing the distribution of the grinding liquid in different regions, so that the thickness and surface topography of the ground structure wafer can meet the design requirements.

[0041] Please refer to Figure 1For a structure wafer, taking grinding the metal material layer to a target thickness as a grinding target, a specific grinding process of the phased grinding in the related art is as follows. Specifically, the structure wafer can include a metal layer 101, an isolation layer 102, and a dielectric layer 103, where the isolation layer 102 and the dielectric layer 103 can be formed of non-metal materials. For example, the material of the metal layer 101 can be copper, the material of the isolation layer 102 can be nitride, and the material of the dielectric layer 103 can be oxide.

[0042] Please refer to Figure 1 (a) to Figure 1 (c) in the foregoing description. Taking the normal direction of the structure wafer as the thickness direction, since the thickness of the metal layer 101 is larger than that of the isolation layer 102 and the dielectric layer 103, a part of the metal layer 101 can be removed by using a primary grinding. The primary grinding stage can be divided into two process steps of preliminary planarization and over polish. The preliminary planarization process step can be used to remove the fin part of the metal layer 101 to speed up the removal rate of the metal layer 101 in the subsequent process. The over polish process step can be used to reduce the residue of the metal layer 101 on the surface of the dielectric layer 103. Specifically, the over polish process step can use an endpoint detection (EPD) method to infer that the dielectric layer 103 has been exposed when a rapid change in reflection intensity is detected. Since the grinding objects of the preliminary planarization process step and the over polish process step are both the metal layer 101, the grinding parameters of the two process steps can be the same or similar, thereby saving the process time required in the primary grinding stage.

[0043] Please refer to Figure 1 (c) and Figure 1 (d) in the foregoing description. After removing most of the metal layer 101 by using the primary grinding, the structure wafer can be thinned to a target thickness by using a fine grinding. Since the metal layer 101, the isolation layer 102, and the dielectric layer 103 need to be removed in the fine grinding stage, and the materials of the three structures are different, the grinding parameters of the fine grinding, including the grinding pressure, the type of grinding liquid, the grinding rate, etc., are different from those of the primary grinding.

[0044] Please refer to Figures 2 to 4 In an ideal state, the above phased grinding method can take into account the process efficiency and the process accuracy, and achieve the optimization of the overall thickness uniformity (U%) of the structure wafer. However, in the actual production process of semiconductor devices, researchers have found that the structure wafer ground by using the phased grinding method provided in the related art has various defects (such as the non-uniformity of the thickness of the metal layer 101, the non-uniformity of the thickness of the isolation layer 102, and the non-uniformity of the thickness of the dielectric layer 103). Figures 2 to 4The defects are mainly manifested by erosion, loss, depression, and scratches of metal materials or oxide materials. These defects can cause an increase in leakage current and a decrease in functional stability, resulting in a decrease in device performance and reliability, and can also reduce the production yield of the device. For example, metal material erosion can cause abnormal resistance of metal lines, leading to device short circuit and even burning.

[0045] To reduce the above defects, researchers need to optimize the chemical mechanical polishing process. Specifically, the chemical mechanical polishing process is a synergistic process of chemical corrosion and mechanical removal. In the chemical mechanical polishing process, when mechanical removal plays a dominant role, the removal ability of residual metal materials on the wafer surface is strong, the long distance planarization ability is strong, and the corrosion defects are less. However, the tolerance to over-polishing is low, and the process window is small. Conversely, when chemical corrosion plays a dominant role, the scratch defects are less, the process window of over-polishing is large, but the removal ability of residual metal materials on the wafer surface is weak, the corrosion defects are more, and the service life of the polishing liquid is short. Since the target materials removed in the primary polishing and fine polishing stages are different, and the removal efficiency of chemical corrosion and mechanical removal for different materials is different, therefore, the key to optimizing the chemical mechanical polishing is to determine the balance point of chemical corrosion and mechanical removal in different polishing stages to improve the planarization effect of the chemical mechanical polishing process.

[0046] Please refer to Figure 5 . To determine the cause of the above defects of the structure wafer and to provide a direction for optimizing the chemical mechanical polishing, researchers analyzed the stress distribution of the polishing process provided in the related art. It can be known from Figure 5 that in the process of polishing by using the polishing method provided in the related art, the structure wafer is mainly subjected to the forces from the polishing pressure and the polishing pad and the slurry. The polishing pressure is applied to the structure wafer along the normal direction of the structure wafer through the polishing head and is transmitted to the polishing pad through the structure wafer. While the polishing head applies the polishing pressure to the structure wafer, the structure wafer is subjected to the reaction force from the polishing pad, thereby forming a contact between the structure wafer and the polishing pad. The size of the reaction force will directly affect the size of the polishing removal rate and the uniformity of the polishing removal. The slurry fills the gap between the structure wafer and the polishing pad and removes the material through the synergistic effect of chemical corrosion and mechanical friction.

[0047] Due to the pattern on the surface of the structure wafer, such as metal lines, isolation grooves, etc., local protrusions or depressions are formed on the surface of the structure wafer, so that the contact surface between the polishing pad and the structure wafer forms non-uniform contact points. Specifically, the polishing pad is in close contact with the protrusion area, and the stress is concentrated, so that the material removal rate of the protrusion area is faster. While the polishing pad is loosely contacted with the depression area, the stress is dispersed, so that the material removal rate of the depression area is lower. Therefore, after a long period of use, the degree of wear of the surface of the polishing pad is difficult to maintain uniform, thereby further intensifying the stress concentration, resulting in differences in planarization in different areas.

[0048] In addition, since the pattern on the surface of the structure wafer is formed by different materials, and the selectivity of the polishing liquid to different materials can cause differences in the material removal rate. For example, please refer to Figure 1 (b) and Figure 1 (c) in the detailed description. In order to improve the connection effect between different conductive interconnection layers, in the ideal state, the surface of the metal layer 101 protrudes above the surface of the dielectric layer 103 after the primary stage polishing and the fine stage polishing are completed. Therefore, during the fine polishing stage, the polishing liquid used to remove the isolation layer 102 and the dielectric layer 103 has a certain degree of inhibition effect on the removal of the metal layer 101, so that the surface of the metal layer 101 and the surface of the dielectric layer 103 in the structure wafer after polishing tend to be in the ideal state, and the risk of defects such as depression and erosion of the metal layer 101 is reduced. However, in the case where the material of the metal layer 101 is copper (Cu) and the material of the dielectric layer 103 is silicon oxide (SiO2), after the primary polishing stage is completed, there may be a problem of uneven polishing, that is, in the area where the dielectric layer 103 needs to be exposed, the surface of the dielectric layer 103 may be left with metal material. During the fine polishing stage, due to the characteristics of the fine polishing stage polishing liquid described above, the metal material left on the surface of the dielectric layer 103 is difficult to be effectively removed by the polishing system composed of the polishing liquid, the polishing pad, the polishing planarizer and other polishing elements, and this part of the residual metal material may interfere with the removal of the isolation layer 102 and the dielectric layer 103, thereby intensifying the degree of uneven polishing, and even may affect the conductive interconnection performance and production yield of the whole semiconductor device.

[0049] The force distribution of the grinding process is combined with the stage grinding method provided in the related art for analysis. It can be known that, in the primary grinding stage, under the two conditions of using fixed grinding time and grinding pressure, or using fixed grinding time and real-time changing grinding pressure, the influence of the coupling between different grinding elements in the grinding system, after the primary grinding is completed, the surface of the structure wafer is prone to have the morphology defects of the insufficient grinding of the metal material in some areas and the excessive grinding of the metal material in some areas, and the defects may be inherited to the fine grinding stage. However, due to the different grinding parameters of the fine grinding stage and the primary grinding stage, the defects are difficult to eliminate in the fine grinding stage, and even the defects may be further amplified due to the selectivity of the grinding liquid for the metal material and the non-metal material in the fine grinding stage, and finally cause the deterioration of the overall thickness uniformity of the structure wafer.

[0050] In addition, in the related art, the pre-measured thickness data (Pre Layer Thickness) obtained before the structure wafer is ground is mainly used as the basis for determining the grinding parameters of the fine grinding stage, and the difference in the planarization degree between different areas of the structure wafer after the primary grinding stage is not considered, which causes the process fluctuation in the primary grinding stage to be difficult to correct through the fine grinding stage, thereby limiting the improvement of the overall planarization effect of the structure wafer.

[0051] Therefore, it is necessary to provide a grinding control method, which can eliminate the regional planarization degree unevenness problem of the semiconductor structure formed in the primary grinding stage, i.e., the "pre-difference", through the control of the grinding time and the grinding pressure in the fine grinding stage, i.e., the "post-supplement", so as to improve the thickness uniformity of the overall semiconductor structure obtained by grinding.

[0052] Please refer to Figure 6One embodiment of the present disclosure provides a control method of polishing. The control method of polishing can be applied to a polishing process. The polishing process can be used to polish a semiconductor structure prepared by a previous process of the polishing process. Specifically, the semiconductor structure can include a first material layer and a second material layer, and the material of the first material layer is different from the material of the second material layer. For example, the material of the first material layer can be metal, and the material of the second material layer can be non-metal. Accordingly, the first material layer after polishing can be used as a contact structure, and the second material layer can be used as a dielectric layer between the contact structures. Alternatively, the material of the first material layer and the material of the second material layer are different non-metals. Accordingly, the first material layer after polishing can be used as a shallow trench isolation (STI) structure, and the second material layer can be used as a dielectric layer between the STI structures. The following description takes the material of the first material layer as metal and the material of the second material layer as non-metal as an example to describe the control method of polishing provided by the embodiment of the present disclosure.

[0053] In the embodiment, the polishing process can include a first sub-polishing process and a second sub-polishing process. The polishing accuracy of the first sub-polishing process is less than the polishing accuracy of the second sub-polishing process. Specifically, the first sub-polishing process can be used to remove the first material layer, and the second sub-polishing process can be used to remove the first material layer and the second material layer. The control method of polishing can include steps S110, S120, S130 and S140.

[0054] S110: Obtain a pre-process thickness of the semiconductor structure before performing the first sub-polishing process and a remaining thickness of the semiconductor structure after performing the first sub-polishing process.

[0055] Since the polishing pressure can be controlled for different polishing areas during the second sub-polishing process, in order to introduce the polishing result of the first sub-polishing process into the determination process of the polishing parameters of the second sub-polishing process to improve the elimination effect of the defects caused by the first sub-polishing process on the second sub-polishing process, in the embodiment, before determining the polishing parameters of the second sub-polishing process, the thicknesses of the regions corresponding to the multiple polishing areas in the semiconductor structure before and after performing the first sub-polishing process on the semiconductor structure can be obtained.

[0056] Please refer to Figure 7 In some embodiments, the step of obtaining the pre-process thickness and the remaining thickness can include sub-steps S111, S112 and S113.

[0057] S111: Before performing the first sub-polishing process on the semiconductor structure, measure the thicknesses of the regions corresponding to the multiple polishing areas in the semiconductor structure to obtain the pre-process thickness.

[0058] Please refer to Figure 8 and Figure 9 In the embodiment, the polishing region can be a polishing range that the polishing equipment can independently control. Specifically, a single polishing head with multiple polishing chambers can be used to polish the semiconductor structure. The polishing head can be divided into multiple polishing chambers in a ring distribution, each of which is defined and separated by an elastic membrane and controlled by an independent air path or an independent hydraulic system. During the polishing process, the polishing pressure of each polishing chamber can be controlled by the independent air path or the independent hydraulic system, thereby forming a polishing region corresponding to each polishing chamber. The radii of different polishing chambers are different. For example, a polishing head with five polishing chambers has diameters of D1, D2, D3, D4, and D5, respectively, and five polishing regions Z1, Z2, Z3, Z4, and Z5 are formed correspondingly during the polishing process.

[0059] In the embodiment, the region corresponding to the polishing region can be a physical region in the semiconductor structure that bears the polishing pressure of each polishing region. Specifically, since the polishing regions are in a ring distribution, the regions corresponding to the polishing regions in the semiconductor structure can also be in a ring distribution.

[0060] In the embodiment, to improve the accuracy of the thickness of the semiconductor structure reflected by the pre-sequencing thickness, the pre-sequencing thickness can be obtained by a thickness measurement tool. Therefore, the pre-sequencing thickness can include the measured thickness of the regions in the semiconductor structure corresponding to the multiple polishing regions before the first sub-polishing process is performed on the semiconductor structure. Specifically, the pre-sequencing thickness can be the thickness of the regions in the semiconductor structure corresponding to the multiple polishing regions, respectively.

[0061] S112: After the first sub-polishing process is performed on the semiconductor structure, the coordinate information of the polishing end points of the regions in the semiconductor structure corresponding to the multiple polishing regions in the first sub-polishing coordinate system is obtained.

[0062] Please refer to Figure 10 and Figure 11 Since the first sub-polishing process and the second sub-polishing process are performed in the same polishing equipment, to save polishing time and simplify the complexity of obtaining the reserved thickness, in the embodiment, after the first sub-polishing process is completed, a first sub-polishing coordinate system can be established with the radius of the semiconductor structure as the horizontal coordinate and the polishing end point signal value of the first sub-polishing process as the vertical coordinate. Then, based on the first sub-polishing coordinate system, the photoelectric signal output by the polishing equipment reflecting the polishing result of the first sub-polishing process is converted into coordinate information.

[0063] S113: The coordinate information is processed to obtain the reserved thickness.

[0064] After the coordinate information is obtained based on the first sub-polishing coordinate system, the coordinate information can be further processed to obtain a remaining thickness. The remaining thickness can include the thickness of the regions corresponding to the plurality of polishing regions in the semiconductor structure after the first sub-polishing process. Specifically, the remaining thickness can be the thickness of the regions corresponding to the plurality of polishing regions in the first material layer of the semiconductor structure after the first sub-polishing process. It should be noted that, since the above-mentioned remaining thickness is obtained by a data processing method, compared with the actual thickness of the plurality of regions of the semiconductor structure after the first sub-polishing process, there can be a certain error. According to the actual measurement of the researchers, the error range is about 0 Å~ 10 Å, which is within the process error range allowed by the first sub-polishing process, so the error has a weak negative impact on the grinding effect of the subsequent second sub-polishing process.

[0065] S120: According to the pre-sequencing thickness, the remaining thickness and the first preset polishing parameter, the compensation polishing time of the second sub-polishing process is determined according to the compensation polishing time determination rule.

[0066] In the polishing parameters of the second sub-polishing process, the polishing time is the overall time for executing the second sub-polishing process, which is difficult to adjust for different regions. Therefore, in the embodiment, in order to improve the control ability of the second sub-polishing process and improve the elimination effect of the defects caused by the first sub-polishing process, the compensation polishing time for adjusting the polishing time of the second sub-polishing process can be determined according to the obtained pre-sequencing thickness, remaining thickness and first preset polishing parameter.

[0067] In the embodiment, the first preset polishing parameter can include a first preset target thickness and a preset polishing rate. Specifically, the first preset target thickness can be a preset remaining thickness average of the entire semiconductor structure after the execution of the previous process, that is, the target value of the thickness average of the semiconductor structure before the first sub-polishing process after the execution of the previous process.

[0068] Please refer to Figure 12 In some embodiments, the step of determining the compensation polishing time of the second sub-polishing process can include sub-steps S121, S122, S123, S124 and S125.

[0069] S121: Based on the pre-sequencing thickness and the remaining thickness, the pre-sequencing thickness average and the remaining thickness average before and after the execution of the first sub-polishing process on the semiconductor structure are obtained.

[0070] Since the pre-sequencing thickness and the reserved thickness correspond to layer structures of different materials in the semiconductor structure respectively, and the pre-sequencing thickness and the reserved thickness can include thicknesses of multiple regions in the semiconductor structure, in this embodiment, the pre-sequencing thicknesses of the multiple regions and the reserved thicknesses of the multiple regions can be averaged respectively to obtain the pre-sequencing thickness average and the reserved thickness average, thereby improving the accuracy of subsequent calculation.

[0071] S122: calculating a first expected polishing time of the second sub-polishing process according to the pre-sequencing thickness average, the first preset target thickness, and a preset polishing removal rate.

[0072] In this embodiment, the first expected polishing time can represent an expected polishing time required to eliminate process errors of the previous process. Specifically, the first expected polishing time can be calculated based on the following formula 1.

[0073] Formula 1

[0074] wherein, represents the first expected polishing time, and the unit can be seconds (s), represents the pre-sequencing thickness average, and the unit can be nanometers (nm), represents the preset polishing removal rate, and the unit can be nanometers per second (nm / s), represents the first preset target thickness, and the unit can be nanometers (nm).

[0075] S123: calculating a second expected polishing time of the second sub-polishing process according to the reserved thickness average, the reserved thickness of the reference polishing region, and the preset polishing removal rate.

[0076] Since the reserved thickness includes reserved thicknesses of multiple regions in the semiconductor structure, and the reserved thicknesses of different regions can be different. In order to provide a calculation benchmark of the reserved thicknesses of the multiple regions in the calculation of the second expected polishing time and the subsequent compensation of the polishing pressure, in this embodiment, the reserved thickness can include the reserved thickness of the reference polishing region after the first sub-polishing process is performed on the semiconductor structure. Specifically, the reference polishing region can be a polishing region with the smallest change in the polishing thickness average among the historical polishing process data of multiple batches.

[0077] In this embodiment, the second expected polishing time can represent an expected polishing time required to eliminate the difference in the planarization degree of each region of the semiconductor structure caused by the first sub-polishing process. Specifically, the second expected polishing time can be calculated based on the following formula 2.

[0078] Formula 2

[0079] wherein, represents the second expected polishing time, and the unit can be second (s), represents the average reserved thickness, and the unit can be nanometer (nm), represents the preset polishing removal rate, and the unit can be nanometer per second (nm / s), represents the reserved thickness of the reference region, and the unit can be nanometer (nm).

[0080] S124: determining the polishing time compensation coefficient according to the polishing time compensation coefficient determination rule.

[0081] To improve the compensation accuracy of the compensation polishing time, in the embodiment, the polishing time compensation coefficient can be determined first, and then the compensation polishing time is calculated based on the polishing time compensation coefficient.

[0082] In the embodiment, the polishing time compensation coefficient can be used to reflect the influence degree of the first expected polishing time and the second expected polishing time on the compensation polishing time of the second sub-polishing process. Specifically, the polishing time compensation coefficient can include a first time compensation coefficient corresponding to the first expected polishing time and a second time compensation coefficient corresponding to the second expected polishing time.

[0083] In the embodiment, the polishing time compensation coefficient determination rule can be determined according to the number of polishes on the semiconductor structure with the specified pattern. The specific determination rule of the polishing time compensation coefficient is as follows.

[0084] In the case of first performing the polishing process on the semiconductor structure with the specified pattern, since the polishing parameters such as the polishing equipment state, the polishing consumable consumption condition, and the polishing liquid type are set for the first time, the polishing process stability still needs to be verified by the actual polishing process, and therefore, the polishing time compensation coefficient can be directly set as a specified constant. The ratio of the second time compensation coefficient to the first time compensation coefficient can be the ratio of the polishing removal rates of the polishing metal material and the polishing non-metal material under the same polishing condition. The same polishing condition can include the same polishing equipment, the same polishing consumable, and the same polishing liquid. For example, the specified constant can be 1, that is, in the case of first performing the polishing process on the semiconductor structure with the specified pattern, the value of the first time compensation coefficient can be 1, and the value of the second time compensation coefficient can be the ratio of the polishing removal rates of the polishing metal material and the polishing non-metal material.

[0085] In a case that the grinding process has reached a relatively stable state, the grinding time compensation coefficient can be set to fine-tune around a specified constant to expand the value range of the grinding time compensation coefficient in a case that the grinding process is performed multiple times on the semiconductor structure with the specified pattern based on the same grinding parameters. The value range of the first time compensation coefficient and the value range of the second time compensation coefficient can both fall within a value range of a ratio of a process window of the grinding process to a process error of the previous process. Specifically, the process window of the grinding process can be a difference between a mean value of the remaining thickness after the grinding process is performed on the semiconductor structure and a target remaining thickness corresponding to the grinding process. The process error of the previous process can be a difference between a mean value range of the measured thickness before the grinding process is performed on the semiconductor structure and a target mean value of the thickness corresponding to the previous process.

[0086] S125: Sum the first expected grinding time and the second expected grinding time based on the grinding time compensation coefficient to obtain a compensation grinding time of the second sub-grinding process.

[0087] In the embodiment, the compensation grinding time can be calculated based on the following formula 3.

[0088] Formula 3

[0089] wherein, the compensation grinding time, the first time compensation coefficient, the second time compensation coefficient, the first expected grinding time, the second expected grinding time, wherein, , and The units of and can both be seconds (s).

[0090] S130: Determine the compensation grinding pressure of the plurality of grinding areas in the second sub-grinding process based on the pre-sequencing thickness, the reserved thickness, and the second preset grinding parameters, with the grinding pressure of the reference grinding area as a reference, and in combination with a grinding pressure compensation coefficient determination rule.

[0091] Please refer to Figure 13 . Since the semiconductor structure is to be subsequently divided into a plurality of integrated circuit chips, there are a plurality of rectangular division areas on the semiconductor structure. The rectangular division areas falling within the same circle or annulus are areas corresponding to the same grinding area.

[0092] Since the polishing pressures of different polishing chambers can be independently controlled, in the polishing parameters of the second sub-polishing process, the polishing pressures can be adjusted for different polishing regions. By adjusting the polishing pressures applied to different regions in the semiconductor structure, the polishing removal rates of different regions can be controlled, thereby improving the control accuracy of the polishing removal amount and planarization degree of the surface material of the semiconductor structure. However, since the remaining thickness of the semiconductor structure is small after the first sub-polishing process is completed, for example, the remaining thickness range can be 100 Å ~ 300 Å, the polishing time available for removing the remaining material during the execution of the second sub-polishing process is short, and the control of the polishing removal rate is difficult, and it is difficult to realize real-time adjustment of the polishing pressures of different regions. Therefore, in the embodiment, in order to improve the control ability of the second sub-polishing process, after the compensation polishing time of the second sub-polishing process is determined, the compensation polishing pressures for adjusting the polishing pressures of multiple regions during the execution of the second sub-polishing process can be determined according to the previous thickness, the reserved thickness, and the second preset polishing parameters, and the polishing pressures of the reference polishing regions are taken as the reference.

[0093] After analyzing the actual polishing process, researchers found that since different polishing chambers belong to the same polishing head, and different polishing chambers are separated by an elastic diaphragm, the adjustment of the polishing pressure for a single polishing region can cause mechanical deformation of the elastic diaphragm, thereby changing the polishing pressure distribution of other polishing regions. Therefore, in order to improve the control ability of the second sub-polishing process, in the embodiment, the polishing pressure compensation coefficient can be used to represent the degree of mutual influence between different polishing regions during the polishing process.

[0094] In the embodiment, the second preset polishing parameters can include a second preset target thickness, a preset polishing time, a preset relative speed between the semiconductor structure and the polishing pad, and a polishing base coefficient. Specifically, the second preset target thickness can include preset remaining thicknesses of regions in the semiconductor structure corresponding to multiple polishing regions, respectively, after the execution of the previous process and before the first sub-polishing process. The preset polishing time can be a preset polishing time required for the execution of the second sub-polishing process. The preset relative speed between the semiconductor structure and the polishing pad can be a preset relative movement speed between the semiconductor structure and the polishing pad during the polishing process. The polishing base coefficient can be determined by the material of the polishing pad, the type of polishing liquid, and the corresponding chemical properties, etc.

[0095] Please refer to Figure 14To improve the grinding effect of each grinding area during the second sub-grinding process, in some embodiments, the compensating grinding pressure can be calculated separately for each grinding area. That is, the step of determining the compensating grinding pressure of multiple grinding areas during the second sub-grinding process may include: repeatedly performing the following sub-steps until the compensating grinding pressure of multiple grinding areas other than the reference grinding area is determined; the sub-steps S131, S132, S133 and S134.

[0096] To provide a calculation benchmark for compensating for the grinding pressure in a single grinding zone, in this embodiment, the grinding pressure of the reference grinding zone is a preset constant pressure.

[0097] Please continue reading. Figure 8 Using the fifth grinding region Z5 in the figure as the reference grinding region, and taking the first grinding region Z1 in the figure as an example, the process of calculating the compensating grinding pressure for any grinding region other than the reference grinding region is introduced.

[0098] S131: For any grinding area other than the reference grinding area, calculate the first expected grinding pressure of the grinding area during the execution of the second sub-grinding process based on the preceding thickness of the grinding area, the second preset target thickness of the grinding area, the preset grinding time, the compensation grinding time, the preset relative speed and the grinding base coefficient.

[0099] In this embodiment, the first expected grinding pressure can represent the expected grinding pressure required to eliminate process errors in the preceding process within the grinding area. Specifically, the first expected grinding pressure can be calculated based on the following formula 4.

[0100] Formula 4

[0101] in, This indicates the first expected grinding pressure, and the unit can be hectopascals (hPa) or pounds per square inch (psi). This indicates the preceding thickness of the first grinding region. This indicates the second preset target thickness of the first grinding area. and The unit can be nanometer (nm). Indicates the basic grinding coefficient. This indicates the preset relative velocity between the semiconductor structure and the polishing pad. Indicates the preset grinding time. Indicates the compensation grinding time. and The unit can be seconds (s).

[0102] S132: Calculate the second expected grinding pressure of the grinding area during the second sub-grinding process based on the retained thickness of the grinding area, the retained thickness of the reference grinding area, the second preset target thickness of the grinding area, the preset grinding time, the compensation grinding time, the preset relative speed, and the grinding base coefficient.

[0103] In this embodiment, the second expected grinding pressure can represent the expected grinding pressure required to eliminate the planarization differences caused by the first sub-grinding process in the grinding area. Specifically, the second expected grinding pressure can be calculated based on the following formula 5.

[0104] Formula 5

[0105] in, This indicates the second expected grinding pressure, and the unit can be hectopascals (hPa) or pounds per square inch (psi). Indicates the remaining thickness of the first grinding area. Indicates the retained thickness of the reference grinding area. and The unit can be nanometer (nm). Indicates the basic grinding coefficient. This indicates the preset relative velocity between the semiconductor structure and the polishing pad. Indicates the preset grinding time. Indicates the compensation grinding time. and The unit can be seconds (s).

[0106] S133: Determine the grinding pressure compensation coefficient using the grinding pressure compensation coefficient determination rule.

[0107] To improve the accuracy of compensation for grinding pressure, the grinding pressure compensation coefficients for different grinding zones can be determined first, and then the compensation grinding pressure for a single grinding zone can be calculated based on these coefficients. For details, please refer to [link to relevant documentation]. Figure 15 In this embodiment, the step of determining the grinding pressure compensation coefficient may include sub-steps S1331, S1332, and S1333.

[0108] S1331: Based on the first mapping relationship between the grinding removal rate and the grinding pressure, establish a second mapping relationship between the change in the grinding removal rate and the change in the grinding pressure.

[0109] In this embodiment, please refer to Equation 6. The first mapping relationship can be the Preston equation. As can be seen from Equation 6, the polishing removal rate is proportional to the polishing pressure applied to the semiconductor structure and the relative moving speed between the semiconductor structure and the polishing pad.

[0110] Formula 6

[0111] in, This indicates the rate of removal by grinding, and the unit can be nanometers per second (nm / s). This represents the basic grinding coefficient, and the unit can be 10. -6 / hPa or 10 -6 / psi, This indicates the grinding pressure, and the unit can be hectopascals (hPa) or pounds-forces per square inch (psi). This indicates the relative movement speed between the semiconductor structure and the polishing pad, and the unit can be centimeters per second (cm / s).

[0112] In this embodiment, please refer to Equation 7. The second mapping relationship can be a modified form of the Preston equation. As can be seen from Equation 7, the change in the polishing removal rate is proportional to the change in the polishing pressure applied to the semiconductor structure.

[0113] Formula 7

[0114] in, This indicates the change in the grinding removal rate, and the unit can be nanometers per second (nm / s). The coupling influence coefficient of the grinding region can be used to represent the degree of mutual influence between different grinding regions during the grinding process. The unit is nanometers per second (nm / (s·%)). This indicates the change in grinding pressure, expressed as a percentage (%).

[0115] S1332: Take each grinding area as the target grinding area, adjust the grinding pressure of the target grinding area based on the grinding pressure of the reference grinding area, and measure the grinding removal rate of the target grinding area and the grinding removal rate of the non-target grinding area to obtain the set of grinding pressure change and the set of grinding removal rate change.

[0116] In this embodiment, a univariate perturbation experiment can be used, where the grinding pressure of each grinding region is taken as the perturbation variable, and a second sub-grinding process is performed on the test wafer to obtain the set of grinding pressure changes and the set of grinding removal rate changes. The specific experimental procedure of the univariate perturbation experiment is as follows.

[0117] First, a benchmark calibration test can be performed. Using the grinding pressure of the reference grinding area as a benchmark, the grinding pressure of all grinding areas is set to the benchmark grinding pressure, and a second sub-grinding test is performed on the test wafer. Except for the grinding pressure of each grinding area, all other grinding parameters in the second sub-grinding test are the same as those in the second sub-grinding test. After the second sub-grinding test is completed, the amount of material removed from the area corresponding to each grinding area on the test wafer is measured and used as the benchmark removal amount. Combined with the grinding time of the second sub-grinding test, the benchmark removal rate of each grinding area is calculated, with units in nanometers per second (nm / s).

[0118] Subsequently, each grinding area was designated as a target grinding area. The grinding pressure of the target grinding area was adjusted based on the reference grinding pressure, while maintaining the reference grinding pressure in the remaining grinding areas. The test wafer was then replaced, and a second sub-grinding test was performed on the replaced test wafer. After the second sub-grinding test was completed, the amount of material removed was measured in the areas corresponding to the target grinding areas and the areas corresponding to the other grinding areas on the test wafer. Combined with the grinding time of the second sub-grinding test, the grinding removal rate of each grinding area was calculated, with units in nanometers per second (nm / s).

[0119] Please continue reading. Figure 8 Taking the first grinding region Z1 in the diagram as the target grinding region as an example. Let the reference grinding pressure be P1. Then, a grinding pressure value within the range of 0.9 to 1.1 times P1 can be determined as the grinding pressure P2 for the target grinding region Z1. For example, P2 = 0.9P1. At this point, the grinding pressures of each grinding region, in the order of Z1 to Z5, are (P2, P1, P1, P1, P1). The ratio of the difference between the grinding pressure of each grinding region and the reference grinding pressure to the reference grinding pressure is taken as the grinding pressure change, resulting in the first grinding pressure change. The first grinding pressure change can be represented as a 1×n vector, where n represents the number of grinding regions. Each element in this vector represents the change in grinding pressure of each grinding region relative to the reference grinding pressure when the grinding pressure of the first grinding region Z1 changes from P1 to P2, expressed as a percentage (%). For example, the first grinding pressure change can be (-10, 0, 0, 0, 0), where the element "-10" can represent that the grinding pressure of the first grinding region Z1 is reduced by 10% relative to the reference grinding pressure.

[0120] Subsequently, a second sub-grinding process can be performed on the replaced test wafer. After the second sub-grinding process is completed, the amount of material removed from the test wafer corresponding to each grinding area is measured. Combined with the grinding time of the second sub-grinding process, the grinding removal rate of each grinding area is calculated. The difference between this grinding removal rate and the reference grinding removal rate is taken as the first grinding removal rate change. The first grinding removal rate change can be represented as a 1×n vector, where n can represent the number of grinding areas. Each element in this vector represents the change in the grinding removal rate of each grinding area relative to the reference grinding removal rate when the grinding pressure of the first grinding area Z1 changes from P1 to P2.

[0121] Repeat the above process, adjusting the grinding pressure of the target grinding area each time within the range of 0.9 to 1.1 times the baseline grinding pressure, until the grinding pressure of all grinding areas has been adjusted, resulting in a set of grinding pressure changes and a set of grinding removal rate changes. The set of grinding pressure changes includes multiple grinding pressure changes equal to the number of grinding areas, and the set of grinding removal rate changes includes multiple grinding removal rate changes equal to the number of grinding areas.

[0122] S1333: Calculate the grinding pressure compensation coefficient based on the set of grinding pressure changes, the set of grinding removal rate changes, and the second mapping relationship.

[0123] To simplify calculations and improve efficiency, in this embodiment, the sets of grinding pressure changes and grinding removal rate changes can each be represented as an n×n matrix. Substituting these two matrices into the second mapping relationship yields the grinding region coupling influence coefficient. Here, n represents the number of grinding regions. Since only one grinding region's grinding pressure is adjusted at a time, the set of grinding pressure changes can be represented as an n×n diagonal matrix. The calculated grinding region coupling influence coefficient can be an n×n matrix, where the element in the i-th row and j-th column represents the degree of influence of the grinding pressure change in the i-th grinding region on the grinding removal rate of the j-th grinding region. The unit of this element can be nanometers per second (nm / (s·%)). Taking 5 grinding regions as an example, the sets of grinding pressure changes and grinding removal rate changes can each be represented as a 5×5 matrix. Substituting these two 5×5 matrices into Formula 7 above yields the grinding region coupling influence coefficient. An example of the grinding region coupling influence coefficient is as follows:

[0124]

[0125] Since compensating for grinding pressure has two functions: firstly, it reduces the coupling effect between different grinding areas after the grinding pressure changes in a single grinding area; secondly, it enhances the elimination effect of the second sub-grinding process on the defects caused by the first sub-grinding process. Therefore, in this embodiment, the grinding pressure compensation coefficient can include a first pressure compensation coefficient and a second pressure compensation coefficient. The first pressure compensation coefficient can be used to adjust the coupling effect between different grinding areas, and the second pressure compensation coefficient can be used to adjust the grinding pressure required to eliminate the defects caused by the first sub-grinding process. Specifically, the number of first pressure compensation coefficients is the same as the number of grinding areas, and the first pressure compensation coefficient can be calculated based on the following formula 8.

[0126] Formula 8

[0127] in, This represents the i-th first pressure compensation coefficient. This represents the element in the i-th row and j-th column of the coupling influence coefficient matrix of the grinding region. This represents the element in the i-th row and i-th column of the coupling influence coefficient matrix of the grinding region. and All units can be nanometers per second·percentage (nm / (s·%)).

[0128] The value of the second pressure compensation coefficient can be determined based on the number of times the semiconductor structure with the specified pattern is polished. Specifically, when performing a polishing process on the semiconductor structure with the specified pattern for the first time, the value of the second pressure compensation coefficient can be the product of the ratio of the polishing removal rate of the metal material and the polishing removal rate of the non-metal material under the same polishing conditions and a specified constant. The same polishing conditions can include the same polishing equipment, the same polishing consumables, and the same polishing slurry. For example, the specified constant can be 1, that is, when performing a polishing process on the semiconductor structure with the specified pattern for the first time, the value of the second pressure compensation coefficient can be the ratio of the polishing removal rate of the metal material and the polishing removal rate of the non-metal material.

[0129] When performing polishing processes on a semiconductor structure with a specified pattern multiple times using the same polishing parameters, since the polishing process has reached a relatively stable state, the value of a specified constant can be finely adjusted around the value of "1" to expand the range of the second pressure compensation coefficient. Specifically, the range of the specified constant can fall within the ratio of the process window of the polishing process to the process error of the preceding process. Specifically, the process window of the polishing process can be the difference between the average remaining thickness after polishing the semiconductor structure and the target remaining thickness corresponding to the polishing process. The process error of the preceding process can be the difference between the range of the average measured thickness before polishing the semiconductor structure and the average target thickness corresponding to the preceding process.

[0130] S134: Based on the grinding pressure compensation coefficient, the first expected grinding pressure, the second expected grinding pressure, and the preset grinding pressure of the other grinding areas excluding this grinding area are summed to obtain the compensated grinding pressure of this grinding area.

[0131] In this embodiment, the compensation grinding pressure can be calculated based on the following formula 9.

[0132] Formula 9

[0133] in, This indicates the compensating grinding pressure in the grinding area. This indicates the grinding pressure in the reference grinding area. This represents the first pressure compensation coefficient. This represents the second pressure compensation coefficient. This indicates the first expected grinding pressure in the grinding zone. This indicates the second expected grinding pressure in the grinding area. This indicates the preset grinding pressure for the remaining grinding areas other than the specified grinding area. The units for each of the above grinding pressure parameters can be hectopascals (hPa) or pounds-forces per square inch (psi). In this embodiment, the preset grinding pressure for the remaining grinding areas other than the specified grinding area can be set based on historical grinding pressure data.

[0134] To further enhance the control capability of the second sub-grinding process, reduce interference from other grinding areas during the grinding of a single grinding area, and improve the grinding accuracy of the second sub-grinding process, in some embodiments, the grinding control method provided in this application may further include: constructing an optimization model for the compensation grinding pressure of any grinding area other than the reference grinding area; and solving the optimization model using a linear programming algorithm or a sequential quadratic programming algorithm to obtain the optimized compensation grinding pressure of the grinding area.

[0135] Please refer to Formulas 10 and 11. In this embodiment, the optimization model can be a quadratic programming model with constraints. Specifically, the optimization objective of this model can be to minimize the sum of deviations in the grinding removal rates of multiple grinding zones, that is, to minimize the influence of the target grinding removal rate of each grinding zone on the target grinding removal rates of other grinding zones, and the target grinding removal amount of each grinding zone can be reflected by the grinding pressure change corresponding to the coupling influence coefficient of the grinding zone. The constraint of this optimization model can be that the deviation of the grinding removal rates of multiple grinding zones does not exceed a specified threshold, for example, the specified threshold can be 5%.

[0136] Formula 10

[0137] Formula 11

[0138] in, This indicates the change in grinding pressure across multiple grinding zones, and the unit can be a percentage (%). The optimization model function representing the compensation for grinding pressure is... This represents the measured change in the grinding removal rate in the i-th grinding region. This represents the change in the target grinding removal rate of the i-th grinding region, where the units of both of the above grinding removal rate change parameters can be nanometers per second (nm / s).

[0139] In this embodiment, after the optimization model for compensating grinding pressure is constructed, a linear programming algorithm or a sequence quadratic programming (SQP) algorithm can be used to solve the optimization model to obtain the optimal grinding pressure change for each grinding region. Subsequently, based on the first expected grinding pressure of the grinding region and the preset grinding pressures and optimal grinding pressure changes of the other grinding regions, the optimal first expected grinding pressure of the grinding region and the optimal preset grinding pressures of the other grinding regions can be calculated. Substituting the optimal first expected grinding pressure of the grinding region and the optimal preset grinding pressures of the other grinding regions into Formula 9 above, the optimized compensated grinding pressure for each grinding region during the execution of the second sub-grinding process can be calculated.

[0140] S140: Based on the compensation grinding time and the compensation grinding pressure of multiple grinding zones, control the execution of the second sub-grinding process.

[0141] Please refer to Formulas 12 and 13. After determining the compensation grinding time for the second sub-grinding process and the compensation grinding pressure for multiple grinding areas, the overall grinding time for the second sub-grinding process and the grinding pressure for multiple grinding areas can be determined based on these two compensation grinding parameters. This enhances the ability of the second sub-grinding process to eliminate regional planarization unevenness defects caused by the first sub-grinding process, achieving "pre-difference compensation" in the grinding process and improving the overall thickness uniformity of the semiconductor structure obtained by grinding.

[0142] Formula 12

[0143] Formula 13

[0144] Please see Figure 16 Another embodiment of this application provides a grinding control system. The grinding control system may include a thickness acquisition module, a pre-grinding feedback module for the second sub-grinding process, and a second sub-grinding process control module. Specifically, the functions of each part are described below.

[0145] The thickness acquisition module can be used to acquire the preceding thickness and the retained thickness. Specifically, after receiving the semiconductor structure fabricated by the preceding process, the thickness acquisition module can first measure the thickness of the regions corresponding to multiple polishing areas in the semiconductor structure to obtain the preceding thickness. Subsequently, a first sub-polishing process can be performed on the semiconductor structure using polishing equipment. After the first sub-polishing process is completed, the thickness acquisition module can obtain the retained thickness based on the polishing endpoint signals of multiple regions in the semiconductor structure during the first sub-polishing process.

[0146] The pre-processing feedback module for the second sub-grinding step can be used to determine the compensation grinding time and compensation grinding pressure for multiple grinding areas in the second sub-grinding step. Specifically, after obtaining the preceding thickness and the retained thickness, the thickness acquisition module can transmit these thicknesses to the pre-processing feedback module for the second sub-grinding step. Upon receiving the preceding thickness and the retained thickness, the pre-processing feedback module for the second sub-grinding step can calculate the compensation grinding time and compensation grinding pressure for multiple grinding areas based on the preceding thickness, the retained thickness, preset grinding parameters, preset grinding time compensation coefficient determination rules, and preset grinding pressure compensation coefficient determination rules. The pre-processing feedback module for the second sub-grinding step can obtain the preset grinding parameters, preset grinding time compensation coefficient determination rules, and preset grinding pressure compensation coefficient determination rules through local or cloud-based methods.

[0147] After receiving the compensation grinding time and compensation grinding pressure output by the feedback module before the second sub-grinding process, the control module for the second sub-grinding process can control the execution of the second sub-grinding process based on the compensation grinding time and the compensation grinding pressure of multiple grinding areas, thereby obtaining the ground semiconductor structure.

[0148] In another embodiment of this application, a grinding method is provided. This grinding method can be controlled by the grinding control method described in the above embodiments, or the grinding method can be controlled by the grinding control system described in the above embodiments.

[0149] For other technical effects of the grinding control system and grinding method described in the above embodiments, please refer to other embodiments of this application for comparison and explanation, and they will not be repeated here.

[0150] Please see Figure 17 Researchers established a two-dimensional coordinate system with the radius of the semiconductor structure as the abscissa and the thickness of the polished semiconductor structure as the ordinate. The thicknesses of the semiconductor structures polished using methods provided in related technologies and those polished using the methods provided in this application are compared and displayed in this two-dimensional coordinate system. Figure 17 It is evident that, compared to semiconductor structures obtained using grinding methods provided by related technologies, the semiconductor structures obtained using the grinding method provided in this application exhibit smaller thickness differences in different regions, i.e., better thickness uniformity. Therefore, the grinding control method provided in this application can improve the thickness uniformity of the semiconductor structure after grinding.

[0151] In the grinding control method provided in this application embodiment, the preceding thickness and the retained thickness before performing the first sub-grinding process on the semiconductor structure are obtained. The preceding thickness and the retained thickness both include the thickness of the regions in the semiconductor structure corresponding to multiple grinding regions. Then, based on the preceding thickness, the retained thickness, and the first preset grinding parameters, combined with the grinding time compensation coefficient determination rule, the compensation grinding time of the second sub-grinding process is determined. Based on the preceding thickness, the retained thickness, and the second preset grinding parameters, and using the grinding pressure of the reference grinding region as a benchmark, combined with the grinding pressure compensation coefficient determination rule, the compensation grinding pressure of multiple grinding regions is determined. Then, the execution of the second sub-grinding process is controlled based on the compensation grinding time and compensation grinding pressure. The unexpected effects achieved include: since the grinding time of the second sub-grinding process and the grinding pressure of different regions are compensated based on the preceding thickness and the retained thickness, the regional morphological defects left after the completion of the first sub-grinding process can be specifically corrected during the execution of the second sub-grinding process. That is, the "previous difference and subsequent compensation" of the grinding process is realized, thereby reducing the retention of thickness deviation caused by insufficient flattening of the first sub-grinding process and improving the overall thickness uniformity of the semiconductor structure.

[0152] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0153] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0154] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0155] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0156] As will be understood from the several embodiments provided in this application, the disclosed grinding control system can be implemented in other ways. For example, the embodiments of the grinding control system described above are merely illustrative.

[0157] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A control method of polishing, characterized by, The control method of the grinding process is applied to a grinding process; the grinding process is used for grinding a semiconductor structure prepared by a previous process of the grinding process; the grinding process includes a first sub-grinding process and a second sub-grinding process; wherein the grinding accuracy of the first sub-grinding process is less than the grinding accuracy of the second sub-grinding process; the control method of the grinding process includes: obtaining a pre-sequencing thickness before the first sub-grinding process is performed on the semiconductor structure and a remaining thickness after the first sub-grinding process is performed on the semiconductor structure; wherein the pre-sequencing thickness and the remaining thickness each include the thickness of a region corresponding to each of a plurality of grinding regions in the semiconductor structure; determining a compensation grinding time of the second sub-grinding process according to the pre-sequencing thickness, the remaining thickness, and a first preset grinding parameter, in combination with a grinding time compensation coefficient determination rule; determining a compensation grinding pressure of a plurality of grinding regions during the execution of the second sub-grinding process according to the pre-sequencing thickness, the remaining thickness, and a second preset grinding parameter, taking the grinding pressure of a reference grinding region as a reference, in combination with a grinding pressure compensation coefficient determination rule; controlling the execution of the second sub-grinding process based on the compensation grinding time and the compensation grinding pressure of the plurality of grinding regions.

2. The control method of polishing according to claim 1, wherein, The step of obtaining a pre-sequencing thickness before the first sub-grinding process is performed on the semiconductor structure and a remaining thickness after the first sub-grinding process is performed on the semiconductor structure includes: measuring the thickness of a region corresponding to each of a plurality of grinding regions in the semiconductor structure before the first sub-grinding process is performed on the semiconductor structure to obtain the pre-sequencing thickness; obtaining coordinate information of a grinding endpoint of a region corresponding to each of a plurality of grinding regions in the semiconductor structure in a first sub-grinding coordinate system after the first sub-grinding process is performed on the semiconductor structure; performing data processing on the coordinate information to obtain the remaining thickness.

3. The control method of polishing according to claim 1, wherein The remaining thickness includes a remaining thickness of the reference grinding region after the first sub-grinding process is performed on the semiconductor structure; The reference grinding region is a grinding region with the smallest change in average post-grinding thickness among a plurality of batches of historical grinding process data; The grinding pressure of the reference grinding region is a preset constant pressure.

4. The control method of polishing according to claim 3, wherein The first preset grinding parameter includes a first preset target thickness and a preset grinding rate; wherein the first preset target thickness is a preset average remaining thickness of the semiconductor structure as a whole after the previous process is performed; the step of determining a compensation grinding time of the second sub-grinding process based on the pre-sequencing thickness, the remaining thickness, and a first preset grinding parameter, in combination with a grinding time compensation coefficient determination rule, includes: obtaining a pre-sequencing thickness average and a remaining thickness average before and after the first sub-grinding process is performed on the semiconductor structure based on the pre-sequencing thickness and the remaining thickness; calculating a first expected grinding time of the second sub-grinding process according to the pre-sequencing thickness average, the first preset target thickness, and the preset grinding removal rate; calculating a second expected polishing time of the second sub-polishing process according to the average of the reserved thickness, the reserved thickness of the reference polishing area, and the preset polishing removal rate; determining the polishing time compensation coefficient according to the polishing time compensation coefficient determination rule; summing the first expected polishing time and the second expected polishing time based on the polishing time compensation coefficient to obtain a compensated polishing time of the second sub-polishing process.

5. The control method of polishing according to claim 4, wherein The polishing time compensation coefficient includes a first time compensation coefficient corresponding to the first expected polishing time and a second time compensation coefficient corresponding to the second expected polishing time; wherein the ratio of the second time compensation coefficient to the first time compensation coefficient is the ratio of the polishing removal rates of the metal material and the non-metal material under the same polishing condition; the value range of the first time compensation coefficient and the value range of the second time compensation coefficient both fall within the ratio range of the process window of the polishing process and the process error of the previous process.

6. The control method of polishing according to claim 3, wherein The second preset polishing parameter includes a second preset target thickness, a preset polishing time, a preset relative speed of the semiconductor structure and the polishing pad, and a polishing base coefficient; wherein the second preset target thickness includes preset remaining thicknesses of regions corresponding to a plurality of polishing areas in the semiconductor structure after the previous process is performed; based on the previous thickness, the reserved thickness, and the second preset polishing parameter, and taking the polishing pressure of the reference polishing area as a reference, the step of determining the compensated polishing pressure of the plurality of polishing areas during the execution of the second sub-polishing process in combination with the polishing pressure compensation coefficient determination rule includes: repeating the following sub-steps until the compensated polishing pressure of the plurality of polishing areas except the reference polishing area is determined; the sub-steps include: for any polishing area except the reference polishing area, calculating a first expected polishing pressure of the polishing area during the execution of the second sub-polishing process according to the previous thickness of the polishing area, the second preset target thickness of the polishing area, the preset polishing time, the compensated polishing time, the preset relative speed, and the polishing base coefficient; calculating a second expected polishing pressure of the polishing area during the execution of the second sub-polishing process according to the reserved thickness of the polishing area, the reserved thickness of the reference polishing area, the second preset target thickness of the polishing area, the preset polishing time, the compensated polishing time, the preset relative speed, and the polishing base coefficient; determining the polishing pressure compensation coefficient using the polishing pressure compensation coefficient determination rule; summing the first expected polishing pressure, the second expected polishing pressure, and the preset polishing pressure of the remaining polishing areas except the polishing area based on the polishing pressure compensation coefficient to obtain the compensated polishing pressure of the polishing area.

7. The control method of grinding according to claim 6, wherein, The step of determining the polishing pressure compensation coefficient using the polishing pressure compensation coefficient determination rule includes: establish a second mapping relationship between a variation of the polishing removal rate and a variation of the polishing pressure based on a first mapping relationship between the polishing removal rate and the polishing pressure; adjust the polishing pressure of each polishing region as a target polishing region based on the polishing pressure of the reference polishing region, measure the polishing removal rate of the target polishing region and the polishing removal rate of a non-target polishing region, and obtain a set of variations of the polishing pressure and a set of variations of the polishing removal rate; calculate the polishing pressure compensation coefficient based on the set of variations of the polishing pressure, the set of variations of the polishing removal rate, and the second mapping relationship.

8. The control method of polishing according to claim 6, wherein The control method of the polishing further comprises: for any polishing region except the reference polishing region, constructing an optimization model of the compensation polishing pressure of the polishing region; wherein the optimization objective of the optimization model is that the sum of the deviations of the polishing removal rates of the plurality of polishing regions is minimum; the constraint condition of the optimization model is that the deviation of the polishing removal rates of the plurality of polishing regions does not exceed a specified threshold; solving the optimization model by using a linear programming algorithm or a sequential quadratic programming algorithm to obtain the optimized compensation polishing pressure of the polishing region.

9. A control system for grinding, characterized in that The control system of the polishing is used to control a polishing process; the polishing process is used to polish a semiconductor structure prepared by a previous process of the polishing process; the polishing process comprises a first sub-polishing process and a second sub-polishing process; wherein the polishing accuracy of the first sub-polishing process is less than that of the second sub-polishing process; the control system of the polishing process comprises: a thickness acquisition module, configured to acquire a pre-sequence thickness before the first sub-polishing process is performed on the semiconductor structure and a remaining thickness after the first sub-polishing process is performed on the semiconductor structure; wherein the pre-sequence thickness and the remaining thickness both comprise the thicknesses of regions corresponding to a plurality of polishing regions in the semiconductor structure; a second sub-polishing process pre-feedback module, configured to determine a compensation polishing time of the second sub-polishing process according to the pre-sequence thickness, the remaining thickness, and a first preset polishing parameter, in combination with a polishing time compensation coefficient determination rule; and determine compensation polishing pressures of a plurality of polishing regions during the execution of the second sub-polishing process according to the pre-sequence thickness, the remaining thickness, and a second preset polishing parameter, in combination with a polishing pressure compensation coefficient determination rule, with the polishing pressure of a reference polishing region as a reference; a second sub-polishing process control module, configured to control the execution of the second sub-polishing process based on the compensation polishing time and the compensation polishing pressures of the plurality of polishing regions.

10. A polishing method characterized by, The polishing method is controlled by the control method of the polishing of any one of claims 1 to 8, or the polishing method is controlled by the control system of the polishing of claim 9.

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