Static reactive compensation device fault ride-through capability testing device, method and system

Abstract

The present application relates to static reactive power compensation device fault ride-through capability testing device, method and system, testing device is connected with the static reactive power compensation device SVG to be measured, the SVG to be measured is connected with the regulation and control system, the regulation and control system is connected with grid-connected transformer, and the grid-connected transformer is connected with the power grid and the SVG to be measured respectively, the device includes: first processor, second processor and first high-voltage side acquisition end;First processor is connected with the regulation and control system and second processor respectively, and the first high-voltage side acquisition end is connected between the high-voltage side of grid-connected transformer and the power grid, and the second processor is connected with the first high-voltage side acquisition end.The present application not only practically guarantees the safety of SVG and power grid operation during on-line testing, but also improves the synchronization efficiency of the output test voltage of the testing device and the voltage of the SVG grid-connected point, so that the port voltage of the SVG to be measured can reach the set variation range under any condition.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of grid-connected control of power electronic equipment, and particularly relates to a static var compensator fault ride-through capability testing device, method and system. BACKGROUND

[0002] The SVG plays a crucial role in improving the voltage operation stability of the grid-connected point of the new energy and energy storage power station, especially in weak grid areas. The basic working principle is that, in normal operation, the SVG responds to the reactive power / voltage adjustment instructions issued by the control system, and the control mode is generally divided into constant reactive power and constant voltage modes; in fault conditions, the SVG performs fault ride-through control and autonomously supports the fault voltage.

[0003] At present, the fault ride-through capability of the SVG is generally verified through isolated grid type field testing and semi-physical simulation testing. The isolated grid type field testing is carried out by isolating the SVG to be tested from the real power grid and connecting the SVG to a power grid simulation source. However, due to the terrain conditions of the field testing and the volume of the power grid simulation source, the existing isolated grid testing equipment cannot meet the testing capacity requirements of the large-capacity SVG in complex terrain. The semi-physical simulation testing is carried out by connecting the SVG to a real-time simulator with a test power grid model. Although it is not affected by the capacity of the simulation power grid source, it is a non-power type test and cannot verify the power response dynamic behavior of the static var compensator. Therefore, it is urgent to develop an online testing method for the fault ride-through capability of the large-capacity SVG in complex terrain. SUMMARY

[0004] To overcome the problems in the related art, the present application provides a static var compensator fault ride-through capability testing device, method and system.

[0005] According to a first aspect of an embodiment of the present application, a static var compensator fault ride-through capability testing device is provided, which is connected to a static var compensator to be tested (SVG), the SVG to be tested is connected to a control system, the control system is connected to a grid-connected transformer, the grid-connected transformer is connected to a power grid and the SVG to be tested respectively, and the testing device comprises a first processor, a second processor and a first high-voltage side acquisition end.

[0006] The first processor is connected to the control system and the second processor respectively, and is configured to send a recording instruction corresponding to each target reactive power instruction to the first high-voltage side acquisition end when receiving each target reactive power instruction issued by the control system.

[0007] The first high-voltage side acquisition end is connected between the grid-connected transformer and the power grid, and is configured to acquire target current data and target voltage data between the to-be-tested SVG and the grid-connected transformer when receiving the recording instruction, and send the target current data and the target voltage data to the second processor;

[0008] The second processor is connected with the first high-voltage side acquisition end, and is configured to determine an online test working condition set by using the target current data and the target voltage data, to set a fault ride-through control coefficient of the to-be-tested SVG according to the online test working condition set; and is further configured to synchronize the voltage of a grid connection point of the test device and the to-be-tested SVG by using a pre-established linear interpolation model; and is further configured to determine a deviation coefficient by using a segmented amplitude coefficient compensation strategy, to determine a final output voltage according to the deviation coefficient, so that the to-be-tested SVG provides reactive power support for fault ride-through by using the final output voltage.

[0009] Preferably, the device further comprises a first low-voltage side acquisition end, an AD module, a DA module and a test voltage output end.

[0010] The AD module is connected with the first high-voltage side acquisition end, the first low-voltage side acquisition end and the second processor respectively; and the DA module is connected with the second processor and the test voltage output end respectively.

[0011] Preferably, the AD module is configured to perform analog-to-digital conversion.

[0012] The DA module is configured to perform power amplification on a digital signal.

[0013] Preferably, the first high-voltage side acquisition end is connected with a first current transformer through a first current clamp meter, and is connected with a first voltage transformer.

[0014] The first low-voltage side acquisition end is connected with a second current transformer through a second current clamp meter, and is connected with a second voltage transformer.

[0015] Preferably, the first current transformer and the first voltage transformer are arranged on an electrical primary wiring between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on an electrical primary wiring between the grid-connected transformer and the to-be-tested SVG.

[0016] Preferably, the static reactive compensation device comprises a second high-voltage side acquisition end and a second low-voltage side acquisition end.

[0017] The second high-voltage side acquisition end is connected with the first current transformer through the first current clamp meter, and is connected with the first voltage transformer.

[0018] The second low-voltage side acquisition end is connected with the second current transformer through a second current clamp meter, and the second low-voltage side acquisition end is connected with the second voltage transformer;

[0019] The first current transformer and the first voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the SVG to be tested.

[0020] Preferably, the target reactive power instructions include a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction and an initial reactive power instruction.

[0021] The target reactive power instructions are issued in the following order: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction and the initial reactive power instruction.

[0022] Preferably, the regulation system is configured to send the target reactive power instructions to the SVG to be tested and the first processor respectively according to the issuing order of the target reactive power instructions, and the issuing time interval between the target reactive power instructions is a preset time interval.

[0023] The SVG to be tested is configured to send the target reactive power instructions to the power grid when the target reactive power instructions are received, and the maintenance time of the target reactive power instructions is a preset time interval.

[0024] Preferably, the first high-voltage side acquisition end is specifically configured to:

[0025] When the recording wave instruction corresponding to the target reactive power instruction is received, the current data and the voltage data between the SVG to be tested and the grid-connected transformer are recorded.

[0026] The current data and the voltage data in the preset time window in the maintenance time corresponding to the target reactive power instruction are selected as target current data and target voltage data, and the target current data and the target voltage data are sent to the second processor.

[0027] Preferably, the second processor includes:

[0028] The first calculation unit is configured to calculate the voltage effective value and the actual output reactive power by using the target current data and the target voltage data.

[0029] The second calculation unit is configured to calculate the grid reactance of the SVG to be tested by using the voltage effective value and the actual output reactive power.

[0030] The third calculation unit is configured to calculate the online test working condition set by using the grid reactance of the SVG to be tested and a preset safe operation boundary.

[0031] The voltage effective value includes a maximum test calculated per-unit voltage effective value of inductive reactive power and a maximum test calculated per-unit voltage effective value of capacitive reactive power, and the actual output reactive power includes a maximum test calculated per-unit actual output reactive power of inductive reactive power and a maximum test calculated per-unit actual output reactive power of capacitive reactive power.

[0032] The preset safe operation boundary includes a deviation of grid point voltage, an action threshold of low voltage ride through of the SVG to be tested, and an action threshold of high voltage ride through of the SVG to be tested.

[0033] Preferably, the third calculation unit comprises:

[0034] The first calculation module is configured to calculate a maximum actual allowable value of reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary.

[0035] The second calculation module is configured to calculate a low voltage fault ride through control coefficient during the online test and a high voltage fault ride through control coefficient during the online test by using the maximum actual allowable value of reactive power during the online test, and the low voltage fault ride through control coefficient during the online test and the high voltage fault ride through control coefficient during the online test are the online test working condition set.

[0036] Preferably, the first calculation module is specifically configured to:

[0037] The first calculation module is configured to calculate a maximum theoretical allowable value of reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary.

[0038] The first calculation module is configured to calculate the maximum actual allowable value of reactive power during the online test by using the maximum theoretical allowable value of reactive power during the online test.

[0039] Preferably, the first processor further comprises:

[0040] The control unit is configured to control the first high voltage side acquisition end or the first low voltage side acquisition end to acquire an actual output voltage value of the test device according to a test requirement after the fault ride through control coefficient of the SVG to be tested is set, and send the actual output voltage value of the test device to the second processor.

[0041] Preferably, the second processor further comprises:

[0042] a fourth calculation unit, configured to, after setting the fault ride-through control coefficient of the to-be-tested SVG, calculate an output voltage reference value of the test device at a next moment based on an actual output voltage value of the test device and by using a pre-established linear interpolation model;

[0043] a voltage synchronization unit, configured to, when output voltage errors of the test device at a continuous preset number of moments are all less than or equal to a maximum allowed error of the test device, send the output voltage reference value of the test device at the next moment to the DA module for power amplification, to obtain an output test voltage of the test device, so that the DA module sends the output test voltage to a test voltage output end, and the test voltage output end inputs the output test voltage to a low-voltage side voltage acquisition end of the SVG to synchronize the grid-connected point voltage of the test device with the to-be-tested SVG.

[0044] Preferably, the second processor further comprises:

[0045] a fifth calculation unit, configured to calculate a deviation coefficient by using the actual output voltage value of the test device;

[0046] a compensation unit, configured to, after voltage synchronization is completed, determine whether to compensate for an output signal amplitude of the DA module by using a current state of the preset SVG high-low on-line test signal sequence sent by the first processor, if no compensation is needed, send the current state of the SVG high-low on-line test signal sequence to the DA module, so that the DA module determines the final output voltage according to the current state, and if compensation is needed, calculate a compensation coefficient by using the deviation coefficient, and send the compensation coefficient and the current state to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0047] Preferably, the compensation unit is specifically configured to:

[0048] if the current state of the SVG high-low on-line test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module, and if the current state of the SVG high-low on-line test signal sequence is 0, K u compensation is needed for the output signal amplitude of the DA module.

[0049] Preferably, the DA module is further configured to:

[0050] send the final output voltage to the test voltage output end, so that the test voltage output end sends the final output voltage to the to-be-tested SVG, and then the to-be-tested SVG uses the final output voltage to provide reactive power support for fault ride-through.

[0051] Preferably, the calculation formula of the grid reactance of the SVG to be tested comprises:

[0052]

[0053] In the above formula, X grid is the grid reactance of the SVG to be tested, V 1 is the per-unit voltage effective value calculated by the maximum test of inductive reactive power, V 2 is the per-unit voltage effective value calculated by the maximum test of capacitive reactive power, Q 1 is the per-unit actual output reactive power calculated by the maximum test of inductive reactive power, Q 2 is the per-unit actual output reactive power calculated by the maximum test of capacitive reactive power.

[0054] Preferably, the calculation formula of the theoretical maximum allowed value of the reactive power during the online test comprises:

[0055]

[0056] The calculation formula of the actual maximum allowed value of the reactive power during the online test comprises:

[0057]

[0058] In the above formula, Q Em is the theoretical maximum allowed value of the reactive power during the online test, X grid is the grid reactance of the SVG to be tested, K B is the deviation of the grid voltage, Q m is the actual maximum allowed value of the reactive power during the online test, K is the maximum reactive power overload multiple of the SVG to be tested, Q N is the rated power of the SVG to be tested.

[0059] Preferably, the calculation formula of the low-voltage fault ride-through control coefficient during the online test comprises:

[0060]

[0061] The calculation formula of the high-voltage fault ride-through control coefficient during the online test comprises:

[0062]

[0063] In the above formula, K La low-voltage fault ride-through control coefficient during online testing, U L a voltage value after voltage drop at the grid-connected point, Q m an actual maximum allowed value of reactive power during online testing, ω 1 is an action threshold for the SVG to be tested to enter low-voltage ride-through, ω 2 is an action threshold for the SVG to be tested to enter high-voltage ride-through, K H a high-voltage fault ride-through control coefficient during online testing, U H a voltage value after voltage drop at the grid-connected point.

[0064] Preferably, the calculation formula of the linear interpolation model comprises:

[0065]

[0066] In the above formula, , T test is the total testing time, U a is the output voltage reference value of the testing device at time k +1, k +1 is the output voltage reference value of the testing device at time N d is the interval value matching the control time delay of the testing device, U r is the actual output voltage value of the testing device, e is the output voltage error of the testing device, e max is the maximum allowed error of the testing device.

[0067] Preferably, the calculation formula of the interval value matching the control time delay of the testing device comprises:

[0068]

[0069] The calculation formula of the output voltage error of the testing device comprises:

[0070]

[0071] The calculation formula of the maximum allowed error of the testing device comprises:

[0072]

[0073] In the above formula, , T test is the total testing time, Td To match the control delay of the test equipment, T s For signal output period, U a ( k-N d +1) is ( k-N d The output voltage reference value at time +1) U r ( k-N d +1) is ( k-N d Measured output voltage at time +1) U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage. f 0 represents frequency.

[0074] Preferably, the formula for calculating the deviation coefficient includes:

[0075]

[0076] In the above formula, K 1 represents the deviation coefficient. U r This represents the actual output voltage value of the testing device. U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage.

[0077] Preferably, the SVG high-low penetration online test signal sequence is as follows:

[0078]

[0079] In the above formula, , T test To test the total time, S ( k )for k SVG high-low crossover online test signal sequence, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

[0080] Preferably, the formula for calculating the compensation coefficient includes:

[0081] K BC = K u / K 1

[0082] In the above formula, KBC is a compensation coefficient, K u is a drop / rise amplitude of the final output voltage compared with a secondary voltage rating of the SVG grid-connected point voltage, K 1 is a deviation coefficient.

[0083] Preferably, the calculation formula of the final output voltage comprises:

[0084]

[0085] In the above formula, U O is the final output voltage at the moment, k is an output voltage reference value of the test device at the moment, k Ua is an SVG high-low penetration online test signal sequence at the moment, k k S k k K BC is a compensation coefficient.

[0086] According to a second aspect of the embodiment of the present application, a static reactive power compensation device fault ride-through capability online test method is provided, which is suitable for the static reactive power compensation device fault ride-through capability test device, and comprises:

[0087] When the first processor receives each target reactive power instruction issued by the regulation and control system, the first processor sends a recording wave instruction corresponding to each target reactive power instruction to the first high-voltage side collection end;

[0088] When the first high-voltage side collection end receives the recording wave instruction, the first high-voltage side collection end collects target current data and target voltage data between the SVG to be tested and the grid-connected transformer, and sends the target current data and target voltage data to the second processor;

[0089] The second processor determines an online test working condition set according to the target current data and target voltage data, so as to set a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set;

[0090] After setting the fault ride-through control coefficient of the SVG to be tested, the second processor synchronizes the grid-connected point voltage of the test device and the SVG to be tested by using a pre-established linear interpolation model;

[0091] ​​​​​​After voltage synchronization is completed, the second processor uses a segmented amplitude coefficient compensation strategy to determine the deviation coefficient, and determines the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to provide reactive power support for fault ride-through.

[0092] According to a third aspect of the present invention, an online testing system for the fault ride-through capability of a static var compensator (SVG) is provided, comprising: a control system, an SVG under test, and a fault ride-through capability testing device for the SVG; the control system is connected to the testing device and the SVG under test, and the SVG under test, a grid-connected transformer, and a power grid are connected in sequence; the control system is used to send target reactive power commands to the SVG under test and a first processor in the testing device, respectively.

[0093] The SVG under test is used to send reactive power corresponding to the target reactive power command to the power grid when it receives the target reactive power command, and the duration of sending reactive power is a preset time interval.

[0094] The first processor in the testing device is used to send the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal in the testing device when it receives each target reactive power command issued by the control system.

[0095] The first high-voltage side acquisition terminal in the test device is used to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer when the waveform recording command is received, and send the target current data and target voltage data to the second processor in the test device;

[0096] The second processor in the testing device is used to determine an online test condition set using the target current data and target voltage data, so as to set the fault ride-through control coefficient of the SVG under test according to the online test condition set; and to synchronize the grid connection point voltage of the testing device and the SVG under test using a pre-established linear interpolation model; and to determine the deviation coefficient using a segmented amplitude coefficient compensation strategy, so as to determine the final output voltage according to the deviation coefficient, so that the SVG under test can use the final output voltage for reactive power support during fault ride-through.

[0097] According to a fourth aspect of the present invention, an electronic device is provided, comprising: at least one processor and a memory; the memory and the processor are connected via a bus;

[0098] The memory is used to store one or more programs;

[0099] When the one or more programs are executed by the at least one processor, the static reactive power compensation device fault ride-through capability online testing method is implemented.

[0100] According to a fifth aspect of the embodiments of the present application, a readable storage medium is provided, which has an execution program stored thereon, and the execution program, when executed, implements the static reactive power compensation device fault ride-through capability online testing method.

[0101] The technical solution provided by the present application has the following beneficial effects:

[0102] The static reactive power compensation device fault ride-through capability testing device, method and system provided by the present application, the testing device is connected with the static reactive power compensation device SVG to be tested, the SVG to be tested is connected with a control system, the control system is connected with a grid-connected transformer, the grid-connected transformer is connected with a power grid and the SVG to be tested respectively, and the testing device is characterized in that it comprises a first processor, a second processor and a first high-voltage side acquisition end; the first processor is connected with the control system and the second processor respectively, and is used for sending a recording wave instruction corresponding to each target reactive power instruction to the first high-voltage side acquisition end when receiving each target reactive power instruction issued by the control system; the first high-voltage side acquisition end is connected between a high-voltage side of the grid-connected transformer and the power grid, and is used for collecting target current data and target voltage data between the SVG to be tested and the grid-connected transformer when receiving the recording wave instruction, and sending the target current data and the target voltage data to the second processor; the second processor is connected with the first high-voltage side acquisition end, and is used for determining an online testing working condition set by using the target current data and the target voltage data, setting a fault ride-through control coefficient of the SVG to be tested according to the online testing working condition set, and ensuring the safety of the SVG and the power grid during online testing; the second processor is also used for synchronizing the voltage of a grid-connected point of the testing device and the SVG to be tested by using a linear interpolation model established in advance, improving the synchronization efficiency of the output test voltage of the testing device and the voltage of the grid-connected point of the SVG; the second processor is also used for determining a deviation coefficient by using a segmented amplitude coefficient compensation strategy, determining a final output voltage according to the deviation coefficient, making the SVG to be tested support reactive power by using the final output voltage during fault ride-through, and enabling the testing device to make the output test voltage reach a set change amplitude under any condition of the port voltage of the SVG to be tested, ensuring the compliance of the test signal and the reliability of the test result; and the present application is also applicable to the online testing of the fault ride-through capability of a large-capacity SVG facing complex terrain. BRIEF DESCRIPTION OF DRAWINGS

[0103] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative work based on these drawings also belong to the protection scope of the present application.

[0104] Figure 1 is a structural block diagram of a static reactive power compensation device fault ride-through capability test device provided by the embodiments of the present application;

[0105] Figure 2 is a flow chart of an online test method of static reactive power compensation device fault ride-through capability provided by the embodiments of the present application;

[0106] Figure 3 is a flow chart of an online test system of static reactive power compensation device fault ride-through capability provided by the embodiments of the present application;

[0107] Figure 4 is a capacitive reactive power / voltage control test waveform diagram of SVG provided by the embodiments of the present application;

[0108] Figure 5 is an inductive reactive power / voltage control test waveform diagram of SVG provided by the embodiments of the present application;

[0109] Figure 6 is a fast synchronization waveform diagram of the test device provided by the embodiments of the present application;

[0110] Figure 7 is a SVG fault ride-through test waveform diagram after segment amplitude coefficient compensation provided by the embodiments of the present application;

[0111] Figure 8 is a structural block diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0112] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative work based on these drawings also belong to the protection scope of the present application.

[0113] Embodiment one

[0114] To solve the problem that the fault ride-through capability of large-capacity SVG under current complex terrain conditions is difficult to carry out power type test, the application provides a static var compensator fault ride-through capability test device, the test device is connected with the static var compensator SVG to be tested, the SVG to be tested is connected with a regulation and control system, the regulation and control system is connected with a grid-connected transformer, the grid-connected transformer is connected with a power grid and the SVG to be tested respectively, as shown in Figure 1 The test device comprises a first processor, a second processor and a first high-voltage side acquisition end.

[0115] The first processor is connected with the regulation and control system and the second processor respectively, and is used for sending a recording instruction corresponding to each target reactive instruction to the first high-voltage side acquisition end when receiving each target reactive instruction issued by the regulation and control system.

[0116] The first high-voltage side acquisition end is connected between the grid-connected transformer and the power grid, and is used for collecting target current data and target voltage data between the SVG to be tested and the grid-connected transformer when receiving the recording instruction, and sending the target current data and the target voltage data to the second processor.

[0117] The second processor is connected with the first high-voltage side acquisition end, and is used for determining an online test working condition set by using the target current data and the target voltage data, setting a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set, using a pre-established linear interpolation model to synchronize the voltage of the grid-connected point of the test device and the SVG to be tested, and using a segmented amplitude coefficient compensation strategy to determine a deviation coefficient, so as to determine a final output voltage according to the deviation coefficient, and make the SVG to be tested support reactive power by using the final output voltage.

[0118] It should be noted that the high-voltage side of the grid-connected transformer is connected with the power grid, and the low-voltage side of the grid-connected transformer is connected with the SVG to be tested, therefore, the first high-voltage side acquisition end is connected between the high-voltage side of the grid-connected transformer and the power grid, and the first high-voltage side acquisition end collects the target current data and the target voltage data between the SVG to be tested and the high-voltage side of the grid-connected transformer.

[0119] In some embodiments, the first processor can be but is not limited to a CPU processor, and the second processor can be but is not limited to an FPGA processor. The SVG to be tested, the grid-connected transformer and the power grid are connected in sequence through electrical primary wiring, and the regulation and control system is connected with the SVG to be tested and the test device through communication wiring respectively.

[0120] It should be noted that after receiving the final output voltage, the SVG to be tested supports reactive power according to its fault ride-through control logic.

[0121] Further, the device further comprises a first low-voltage side acquisition end, an AD module, a DA module and a test voltage output end.

[0122] The AD module is connected with the first high-voltage side acquisition end, the first low-voltage side acquisition end and the second processor respectively; and the DA module is connected with the second processor and the test voltage output end respectively.

[0123] Further, the AD module is used for analog-digital conversion.

[0124] The DA module is used for power amplification of the digital signal.

[0125] Further, the first high-voltage side acquisition end is connected with the first current transformer through the first current clamp meter, and the first high-voltage side acquisition end is connected with the first voltage transformer.

[0126] The first low-voltage side acquisition end is connected with the second current transformer through the second current clamp meter, and the first low-voltage side acquisition end is connected with the second voltage transformer.

[0127] The first current transformer and the first voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the SVG to be tested.

[0128] Further, the static reactive power compensation device comprises a second high-voltage side acquisition end and a second low-voltage side acquisition end.

[0129] The second high-voltage side acquisition end is connected with the first current transformer through the first current clamp meter, and the second high-voltage side acquisition end is connected with the first voltage transformer.

[0130] The second low-voltage side acquisition end is connected with the second current transformer through the second current clamp meter, and the second low-voltage side acquisition end is connected with the second voltage transformer.

[0131] The first current transformer and the first voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the SVG to be tested.

[0132] In some embodiments, the high-voltage side acquisition end of the SVG to be tested, the first current clamp meter and the first current transformer are sequentially connected through the electrical secondary wiring, the test device, the first current clamp meter and the first current transformer are sequentially connected through the electrical secondary wiring, the low-voltage side acquisition end of the SVG to be tested, the second current clamp meter and the second current transformer are sequentially connected through the electrical secondary wiring, the low-voltage side acquisition end of the test device, the second current clamp meter and the second current transformer are sequentially connected through the electrical secondary wiring, the high-voltage side acquisition end of the SVG to be tested and the first voltage transformer are connected through the electrical secondary wiring, and the low-voltage side acquisition end of the SVG to be tested and the first voltage transformer are connected through the electrical secondary wiring.

[0133] Further, the target reactive power instructions include: a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction and an initial reactive power instruction.

[0134] The sequence of issuing the target reactive power instructions is: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction and the initial reactive power instruction.

[0135] Further, the regulation system is configured to send the target reactive power instructions to the SVG under test and the first processor according to the sequence of issuing the target reactive power instructions, and the time interval between the target reactive power instructions is a preset time interval.

[0136] The SVG under test is configured to send the target reactive power instructions to the power grid when receiving the target reactive power instructions, and the maintenance time of the target reactive power instructions is a preset time interval, so as to respond to the instructions of the regulation system.

[0137] It should be noted that the present application does not limit the "preset time interval", which can be set by the person skilled in the art according to the engineering requirements, expert experience or experimental data.

[0138] Further, the first high-voltage side acquisition end is specifically configured to:

[0139] When receiving the recording wave instruction corresponding to the target reactive power instruction, the current data and the voltage data between the SVG under test and the grid-connected transformer are recorded.

[0140] The current data and the voltage data in the preset time window in the maintenance time corresponding to the target reactive power instruction are selected as the target current data and the target voltage data, and the target current data and the target voltage data are sent to the second processor.

[0141] It can be understood that when receiving the recording wave instruction corresponding to the target reactive power instruction, the current data and the voltage data between the SVG under test and the high-voltage side of the grid-connected transformer are recorded.

[0142] It should be noted that the present application does not limit the "preset time window", which can be set by the person skilled in the art according to the engineering requirements, expert experience or experimental data.

[0143] For example, 1) the capacitive maximum reactive power instruction is issued to the SVG under test through the regulation system; after maintaining for 2 minutes, the inductive maximum reactive power instruction is issued to the SVG under test; after maintaining for 2 minutes, the initial reactive power instruction is issued to the SVG under test; when the regulation system issues the control instruction to the SVG under test, the test device is forwarded synchronously to trigger the recording wave function of the test device;

[0144] 2) During the test, the test device records the voltage and current data of the high-voltage side of the grid-connected transformer, and selects the data of the last 30 seconds of each instruction maintenance to perform voltage effective valueV actual output reactive power Q calculating.

[0145] Further, the second processor comprises:

[0146] The first calculation unit is configured to calculate the voltage effective value and the actual output reactive power by using the target current data and the target voltage data.

[0147] The second calculation unit is configured to calculate the grid reactance of the SVG under test by using the voltage effective value and the actual output reactive power.

[0148] Specifically, the calculation formula of the grid reactance of the SVG under test comprises:

[0149]

[0150] In the above formula, X grid is the grid reactance of the SVG under test, V 1 is the normalized voltage effective value calculated in the maximum inductive reactive power test, V 2 is the normalized voltage effective value calculated in the maximum capacitive reactive power test, Q 1 is the normalized actual output reactive power calculated in the maximum inductive reactive power test, Q 2 is the normalized actual output reactive power calculated in the maximum capacitive reactive power test.

[0151] The third calculation unit is configured to calculate the online test working condition set by using the grid reactance of the SVG under test and the preset safe operation boundary.

[0152] The voltage effective value comprises the normalized voltage effective value calculated in the maximum inductive reactive power test and the normalized voltage effective value calculated in the maximum capacitive reactive power test; and the actual output reactive power comprises the normalized actual output reactive power calculated in the maximum inductive reactive power test and the normalized actual output reactive power calculated in the maximum capacitive reactive power test.

[0153] The preset safe operation boundary comprises the deviation of the grid connection point voltage, the action threshold of the SVG under test entering the low voltage ride through, and the action threshold of the SVG under test entering the high voltage ride through.

[0154] It should be noted that the method of calculating the voltage effective value and the actual output reactive power involved in the embodiments of the present application is well known to those skilled in the art, and therefore, the specific implementation manner is not described in detail.

[0155] Further, the third calculation unit comprises:

[0156] The first calculation module is configured to calculate an actual maximum reactive power value during the online test by using the grid reactance of the SVG to be tested and a preset safe operation boundary.

[0157] The second calculation module is configured to calculate a low-voltage fault ride-through control coefficient during the online test and a high-voltage fault ride-through control coefficient during the online test respectively by using the actual maximum reactive power value during the online test, and the low-voltage fault ride-through control coefficient during the online test and the high-voltage fault ride-through control coefficient during the online test are the online test working condition set.

[0158] Further, the first calculation module is specifically configured to:

[0159] calculate a theoretical maximum reactive power value during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary;

[0160] calculate the actual maximum reactive power value during the online test by using the theoretical maximum reactive power value during the online test;

[0161] Specifically, the calculation formula of the theoretical maximum reactive power value during the online test comprises:

[0162]

[0163] The calculation formula of the actual maximum reactive power value during the online test comprises:

[0164]

[0165] In the above formulae, Q Em is the theoretical maximum reactive power value during the online test, X grid is the grid reactance of the SVG to be tested, K B is a deviation of the grid voltage, Q m is the actual maximum reactive power value during the online test, K is a maximum reactive power overload multiple of the SVG to be tested, Q N is a rated power of the SVG to be tested.

[0166] Further, the calculation formula of the low-voltage fault ride-through control coefficient during the online test comprises:

[0167]

[0168] The calculation formula of the high-voltage fault ride-through control coefficient during the online test comprises:

[0169]

[0170] In the above formula, K L is a low-voltage fault ride-through control coefficient during online testing, U L is a voltage value after voltage drop at the grid connection point, Q m is an actual maximum allowable value of reactive power during online testing, ω 1 is an action threshold for the SVG to be tested to enter low-voltage ride-through, ω 2 is an action threshold for the SVG to be tested to enter high-voltage ride-through, K H is a high-voltage fault ride-through control coefficient during online testing, U H is a voltage value after voltage drop at the grid connection point.

[0171] Further, the first processor further comprises:

[0172] The control unit is configured to, after setting the fault ride-through control coefficient of the SVG to be tested, control the first high-voltage side acquisition end or the first low-voltage side acquisition end to acquire the actual output voltage value of the test device according to the test requirement, and send the actual output voltage value of the test device to the second processor.

[0173] It should be noted that the present application does not limit the "test requirement", which can be set by a person skilled in the art according to engineering requirements, expert experience or experimental data, etc. For example, when the fault ride-through control strategy of the SVG to be tested is based on low-voltage side voltage action, the test requirement is that the test device is synchronized with the low-voltage side voltage, and at this time the first low-voltage side acquisition end is needed to acquire the actual output voltage value of the test device. Similarly, when the fault ride-through control strategy of the SVG to be tested is based on high-voltage side voltage action, the test requirement is that the test device is synchronized with the high-voltage side voltage, and at this time the first high-voltage side acquisition end is needed to acquire the actual output voltage value of the test device.

[0174] Further, the second processor further comprises:

[0175] The fourth calculation unit is configured to, after setting the fault ride-through control coefficient of the SVG to be tested, generate the output voltage reference value of the test device at the next time based on the actual output voltage value of the test device by using a linear interpolation model established in advance.

[0176] The voltage synchronization unit is used to send the output voltage reference value of the test device at the next moment to the DA module for power amplification when the output voltage error of the test device is less than or equal to the maximum allowable error of the test device for a consecutive preset number of time moments. This results in the output test voltage of the test device being obtained, so that the DA module can send the output test voltage to the test voltage output terminal. The test voltage output terminal then connects the output test voltage to the low-voltage side voltage acquisition terminal of the SVG to synchronize the grid connection point voltage of the test device and the SVG under test.

[0177] Specifically, the calculation formula for the linear interpolation model includes:

[0178]

[0179] In the above formula, , T test To test the total time, U a ( k +1) is the test device in k The output voltage reference value at time +1 N d To match the control delay interval value of the test device, U r This represents the actual output voltage value of the testing device. e To test the output voltage error of the device, e max This represents the maximum permissible error of the testing device;

[0180] The formula for calculating the control delay interval of the matching test device includes:

[0181]

[0182] The formula for calculating the output voltage error of the testing device includes:

[0183]

[0184] The formula for calculating the maximum permissible error of the testing device includes:

[0185]

[0186] In the above formula, , T test To test the total time, T d To match the control delay of the test equipment, T s For signal output period, U a ( k-Nd +1) is the output voltage reference value at the moment t, k-N d +1) is the output voltage reference value at the moment t, U r k-N d +1) is the output voltage reference value at the moment t, k-N d +1) is the output voltage reference value at the moment t, U pccN U is the secondary voltage rated value of the SVG grid-connected point voltage, f 0 is the frequency.

[0187] Further, the second processor further comprises:

[0188] The fifth calculation unit is configured to calculate the deviation coefficient by using the output voltage actual value of the test device.

[0189] Specifically, the calculation formula of the deviation coefficient comprises:

[0190]

[0191] In the above formula, K 1 is the deviation coefficient, U r U is the output voltage actual value of the test device, U pccN U is the secondary voltage rated value of the SVG grid-connected point voltage, that is, the voltage rated value of the grid-connected point voltage after being transformed by the voltage transformer, and is generally 100 V.

[0192] The compensation unit is configured to, after the voltage synchronization is completed, determine whether to compensate the output signal amplitude of the DA module by using the current state of the preset SVG high-low on-line test signal sequence sent by the first processor, if no compensation is needed, send the current state of the SVG high-low on-line test signal sequence to the DA module, so that the DA module determines the final output voltage according to the current state, and if compensation is needed, calculate a compensation coefficient by using the deviation coefficient, and send the compensation coefficient and the current state to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0193] Further, the compensation unit is specifically configured to:

[0194] When the current state of the SVG high-low on-line test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module, and when the current state of the SVG high-low on-line test signal sequence is K u 1, compensation is needed for the output signal amplitude of the DA module.

[0195] ​Further, the DA module is also used for:

[0196] sending the final output voltage to the test voltage output end, so that the test voltage output end sends the final output voltage to the SVG to be tested, and then makes the SVG to be tested use the final output voltage to perform fault ride-through reactive power support.

[0197] Further, the SVG high-low penetration online test signal sequence is:

[0198]

[0199] In the above formula, , T test is the test total time, S k is the SVG high-low penetration online test signal sequence at the time, k K u is the drop / jump amplitude of the final output voltage compared with the secondary voltage rated value of the SVG grid connection point voltage.

[0200] Further, the calculation formula of the compensation coefficient includes:

[0201] K BC K u K 1

[0202] In the above formula, K BC is the compensation coefficient, K u is the drop / jump amplitude of the final output voltage compared with the secondary voltage rated value of the SVG grid connection point voltage, K 1 is the deviation coefficient.

[0203] Further, the calculation formula of the final output voltage includes:

[0204]

[0205] In the above formula, U O k is the final output voltage at the time, k Ua is the output voltage reference value of the test device at the time, k k is the SVG high-low penetration online test signal sequence at the time, S k k K BC ​​​​​​​​​​Compensation coefficient.

[0206] The static reactive power compensation device fault ride-through capability testing device provided by the application not only practically guarantees the safety of the SVG and the power grid during online testing, but also improves the synchronization efficiency of the test device output test voltage and the SVG grid connection point voltage, so that the port voltage of the SVG to be tested can reach the set variation range under any condition, and the compliance of the test signal and the reliability of the test result are guaranteed.

[0207] Embodiment two

[0208] The application further provides an online testing method for the static reactive power compensation device fault ride-through capability, which is suitable for the static reactive power compensation device fault ride-through capability testing device, as shown in the accompanying drawings, and includes the following steps. Figure 2

[0209] Step 1: when the first processor receives each target reactive power instruction issued by the regulation system, the first processor sends a recording wave instruction corresponding to each target reactive power instruction to the first high-voltage side collection end;

[0210] Step 2: when the first high-voltage side collection end receives the recording wave instruction, the first high-voltage side collection end collects target current data and target voltage data between the SVG to be tested and the grid connection transformer, and sends the target current data and the target voltage data to the second processor;

[0211] Step 3: the second processor determines an online testing working condition set according to the target current data and the target voltage data, so as to set the fault ride-through control coefficient of the SVG to be tested according to the online testing working condition set;

[0212] Step 4: after setting the fault ride-through control coefficient of the SVG to be tested, the second processor uses the pre-established linear interpolation model to synchronize the grid connection point voltage of the test device and the SVG to be tested;

[0213] Step 5: after the voltage synchronization is completed, the second processor determines a deviation coefficient by using a segmented amplitude coefficient compensation strategy, so as to determine a final output voltage according to the deviation coefficient, and makes the SVG to be tested support the reactive power during the fault ride-through by using the final output voltage.

[0214] Further, the method further includes: performing analog-to-digital conversion by using an AD module;

[0215] Performing power amplification on the digital signal by using a DA module.

[0216] Further, each target reactive power instruction includes a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction and an initial reactive power instruction.

[0217] ​The sequence of issuing the target reactive power commands is: the capacitive maximum reactive power command, the inductive maximum reactive power command and the initial reactive power command.

[0218] Further, the method further comprises:

[0219] The control system sends the target reactive power commands to the SVG to be tested and the first processor according to the sequence of issuing the target reactive power commands, and the time interval between the target reactive power commands is a preset time interval.

[0220] When the SVG to be tested receives the target reactive power commands, it sends the corresponding reactive power to the power grid, and the maintenance time of the reactive power is the preset time interval.

[0221] Further, step 2 comprises:

[0222] Step 22: The first high-voltage side acquisition end selects the current data and voltage data in the preset time window in the maintenance time corresponding to each target reactive power command as target current data and target voltage data, and sends the target current data and target voltage data to the second processor.

[0223] Further, step 3 comprises:

[0224] Step 31: The second processor calculates the voltage effective value and the actual output reactive power by using the target current data and the target voltage data.

[0225] Step 32: The second processor calculates the grid reactance of the SVG to be tested by using the voltage effective value and the actual output reactive power.

[0226] Step 33: The second processor calculates the online test working condition set by using the grid reactance of the SVG to be tested and the preset safe operation boundary.

[0227] The voltage effective value includes the per-unit voltage effective value calculated in the inductive maximum reactive power test and the per-unit voltage effective value calculated in the capacitive maximum reactive power test; and the actual output reactive power includes the per-unit actual output reactive power calculated in the inductive maximum reactive power test and the per-unit actual output reactive power calculated in the capacitive maximum reactive power test.

[0228] The preset safe operation boundary includes the deviation of the grid point voltage, the action threshold of the SVG to be tested entering low voltage ride through and the action threshold of the SVG to be tested entering high voltage ride through.

[0229] Further, step 33 comprises:

[0230] Step 331: Using the grid reactance of the SVG under test and the preset safe operating boundary, calculate the actual maximum allowable value of reactive power during the online test;

[0231] Step 332: Using the actual maximum allowable value of reactive power during online testing, calculate the low-voltage fault ride-through control coefficient and the high-voltage fault ride-through control coefficient during online testing, respectively. The low-voltage fault ride-through control coefficient and the high-voltage fault ride-through control coefficient during online testing constitute the online testing condition set.

[0232] Further, step 331 includes:

[0233] Step 331a: Using the grid reactance of the SVG under test and the preset safe operating boundary, calculate the theoretical maximum allowable value of reactive power during the online test;

[0234] Step 331b: Calculate the actual maximum allowable value of reactive power during the online test using the theoretical maximum allowable value of reactive power during the online test.

[0235] Furthermore, the method also includes:

[0236] After setting the fault ride-through control coefficient of the SVG under test, the first processor controls the first high-voltage side acquisition terminal or the first low-voltage side acquisition terminal to acquire the actual value of the output voltage of the test device according to the test requirements, and sends the actual value of the output voltage of the test device to the second processor.

[0237] Further, step 4 includes:

[0238] Step 41: After setting the fault ride-through control coefficient of the SVG under test, the second processor calculates and generates the reference value of the output voltage of the test device at the next moment based on the actual value of the output voltage of the test device using a pre-established linear interpolation model.

[0239] Step 42: When the output voltage error of the test device is less than or equal to the maximum permissible error of the test device for a consecutive preset number of time moments, the second processor sends the output voltage reference value of the test device at the next time moment to the DA module for power amplification to obtain the output test voltage of the test device, so that the DA module sends the output test voltage to the test voltage output terminal, and the test voltage output terminal connects the output test voltage to the low voltage side voltage acquisition terminal of the SVG to synchronize the grid connection point voltage of the test device and the SVG under test.

[0240] Further, step 5 includes:

[0241] Step 51: Using the second processor, calculate the deviation coefficient using the actual output voltage value of the test device;

[0242] Step 52: after the voltage synchronization is completed, the second processor uses the received preset SVG high-low on-line test signal sequence current state sent by the first processor to determine whether to compensate the output signal amplitude of the DA module, if no compensation is needed, the SVG high-low on-line test signal sequence current state is sent to the DA module, so that the DA module determines the final output voltage according to the current state; if compensation is needed, the compensation coefficient is calculated by using the deviation coefficient, and the compensation coefficient and the current state are sent to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0243] Further, step 52 comprises:

[0244] Step 521: when the SVG high-low on-line test signal sequence current state is 1, no compensation is needed for the output signal amplitude of the DA module; when the SVG high-low on-line test signal sequence current state is K u , compensation is needed for the output signal amplitude of the DA module.

[0245] Further, the method further comprises:

[0246] The DA module sends the final output voltage to the test voltage output end, so that the test voltage output end sends the final output voltage to the SVG to be tested, and then the SVG to be tested uses the final output voltage to perform fault ride-through reactive power support.

[0247] Further, the formula for calculating the grid reactance of the SVG to be tested comprises:

[0248]

[0249] In the above formula, X grid is the grid reactance of the SVG to be tested, V 1 is the maximum test calculated per-unit voltage effective value of inductive reactive power, V 2 is the maximum test calculated per-unit voltage effective value of capacitive reactive power, Q 1 is the maximum test calculated per-unit actual output reactive power of inductive reactive power, Q 2 is the maximum test calculated per-unit actual output reactive power of capacitive reactive power.

[0250] Further, the formula for calculating the maximum allowed value of reactive power during on-line test comprises:

[0251]

[0252] The formula for calculating the actual maximum allowed value of reactive power during on-line test comprises:

[0253]

[0254] In the above formula, Q Em This represents the theoretical maximum permissible value of reactive power during online testing. X grid The grid reactance of the SVG to be tested. K B For the deviation of the grid connection point voltage, Q m This represents the actual maximum permissible value of reactive power during online testing. K The maximum reactive power overload multiple of the SVG under test. Q N This represents the rated power of the SVG under test.

[0255] Furthermore, the formula for calculating the low-voltage fault ride-through control coefficient during online testing includes:

[0256]

[0257] The formula for calculating the high-voltage fault ride-through control factor during online testing includes:

[0258]

[0259] In the above formula, K L This refers to the low-voltage fault ride-through control factor during online testing. U L The voltage value after the voltage drop at the grid connection point. Q m This represents the actual maximum permissible value of reactive power during online testing. ω 1 represents the threshold value for the under-voltage ride-through of the SVG under test. ω 2 represents the action threshold for the SVG under test to enter high-voltage ride-through. K H This refers to the high-voltage fault ride-through control factor during online testing. U H This is the voltage value after the voltage drop at the grid connection point.

[0260] Furthermore, the calculation formula for the linear interpolation model includes:

[0261]

[0262] In the above formula, , T test To test the total time, U a ( k+1) is the output voltage reference value at the moment of k +1, N d is the interval value matching the control time delay of the test device, U r is the actual output voltage value of the test device, e is the output voltage error of the test device, e max is the maximum allowable error of the test device.

[0263] Further, the calculation formula of the interval value matching the control time delay of the test device comprises:

[0264]

[0265] The calculation formula of the output voltage error of the test device comprises:

[0266]

[0267] The calculation formula of the maximum allowable error of the test device comprises:

[0268]

[0269] In the above formula, , T test is the total test time, T d is the control time delay matching the test device, T s is the signal output period, U a k-N d +1) is the output voltage reference value at the moment of k-N d +1, U r k-N d +1) is the actual output voltage value at the moment of k-N d +1, U pccN is the secondary voltage rated value of the SVG grid-connected point voltage, f 0 is the frequency.

[0270] Further, the calculation formula of the deviation coefficient comprises:

[0271]

[0272] In the above formula, K 1 is the deviation coefficient, U ​​r the actual value of the output voltage of the testing device, U pccN the secondary voltage rating of the SVG grid-connected point voltage.

[0273] Further, the SVG high-low on-line test signal sequence is:

[0274]

[0275] In the above formula, , T test the total time of testing, S k is the SVG high-low on-line test signal sequence at time k K u the drop / rise amplitude of the final output voltage compared to the secondary voltage rating of the SVG grid-connected point voltage.

[0276] Further, the formula for calculating the compensation coefficient includes:

[0277] K BC K u K 1

[0278] In the above formula, K BC is the compensation coefficient, K u the drop / rise amplitude of the final output voltage compared to the secondary voltage rating of the SVG grid-connected point voltage, K 1 is the deviation coefficient.

[0279] Further, the formula for calculating the final output voltage includes:

[0280]

[0281] In the above formula, U O k is the final output voltage at time k Ua k is the output voltage reference value of the testing device at time k S k is the SVG high-low on-line test signal sequence at time k K BC is the compensation coefficient.

[0282] ​​​​​​​​​​The application provides an online test method for fault ride-through capability of a static var compensator, which not only ensures the safety of the online test and the operation of the SVG and the power grid, but also improves the synchronization efficiency of the test voltage output by the test device and the grid connection point voltage of the SVG, so that the test device can make the output test voltage reach the set change range under any condition of the port voltage of the SVG to be tested, and the compliance of the test signal and the reliability of the test result are ensured.

[0283] Embodiment three

[0284] An online test system for fault ride-through capability of a static var compensator, as shown in the figure, comprises a control system, a static var compensator SVG to be tested, and the static var compensator fault ride-through capability test device described above. Figure 3

[0285] The control system is connected with the test device and the SVG to be tested, and the SVG to be tested, the grid connection transformer and the power grid are connected in sequence.

[0286] The control system is configured to send each target reactive power instruction to the SVG to be tested and the first processor in the test device, respectively.

[0287] The SVG to be tested is configured to send the corresponding reactive power to the power grid when receiving each target reactive power instruction, and the maintenance time of the reactive power is a preset time interval.

[0288] The first processor in the test device is configured to send the corresponding recording instruction of each target reactive power instruction to the first high-voltage side collection end in the test device when receiving each target reactive power instruction sent by the control system.

[0289] The first high-voltage side collection end in the test device is configured to collect the target current data and the target voltage data between the SVG to be tested and the grid connection transformer when receiving the recording instruction, and send the target current data and the target voltage data to the second processor in the test device.

[0290] The second processor in the test device is configured to determine an online test working condition set by using the target current data and the target voltage data, set the fault ride-through control coefficient of the SVG to be tested according to the online test working condition set, perform synchronization of the grid connection point voltage of the test device and the SVG to be tested by using a linear interpolation model established in advance, determine a deviation coefficient by using a segmented amplitude coefficient compensation strategy, and determine a final output voltage according to the deviation coefficient, so that the SVG to be tested supports the reactive power during fault ride-through by using the final output voltage.

[0291] ​It should be noted that the high-voltage side of the grid-connected transformer is connected with the power grid, and the low-voltage side of the grid-connected transformer is connected with the SVG to be tested, so that the first high-voltage side collection end collects target current data and target voltage data between the SVG to be tested and the high-voltage side of the grid-connected transformer.

[0292] Further, the AD module in the testing device is used for analog-to-digital conversion.

[0293] The DA module in the testing device is used for power amplification of the digital signal.

[0294] Further, each target reactive power instruction includes a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction, and an initial reactive power instruction.

[0295] The delivery order of each target reactive power instruction is: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction, and the initial reactive power instruction.

[0296] Further, the regulation system is specifically used for:

[0297] According to the delivery order of each target reactive power instruction, each target reactive power instruction is sent to the SVG to be tested and the first processor respectively, and the delivery time interval between each target reactive power instruction is a preset time interval.

[0298] Further, the first high-voltage side collection end is specifically used for:

[0299] When receiving the recording instruction corresponding to each target reactive power instruction, the current data and the voltage data between the SVG to be tested and the grid-connected transformer are recorded;

[0300] The current data and the voltage data of the preset time window in the maintenance time corresponding to each target reactive power instruction are selected as target current data and target voltage data, and the target current data and the target voltage data are sent to the second processor.

[0301] Further, the second processor includes:

[0302] The first calculation unit is used for calculating the voltage effective value and the actual output reactive power by using the target current data and the target voltage data.

[0303] The second calculation unit is used for calculating the grid reactance of the SVG to be tested by using the voltage effective value and the actual output reactive power.

[0304] The third calculation unit is used for calculating the online test working condition set by using the grid reactance of the SVG to be tested and the preset safe operation boundary.

[0305] The voltage effective value includes a maximum test calculated unitary voltage effective value of inductive reactive power and a maximum test calculated unitary voltage effective value of capacitive reactive power; and the actual output reactive power includes a maximum test calculated unitary actual output reactive power of inductive reactive power and a maximum test calculated unitary actual output reactive power of capacitive reactive power.

[0306] The preset safe operation boundary includes a deviation of the grid connection point voltage, an action threshold of the to-be-tested SVG entering low voltage ride through, and an action threshold of the to-be-tested SVG entering high voltage ride through.

[0307] Further, the third calculation unit comprises:

[0308] The first calculation module is configured to calculate a maximum actual allowable value of the reactive power during the online test by using the grid reactance of the to-be-tested SVG and the preset safe operation boundary.

[0309] The second calculation module is configured to calculate a low voltage fault ride through control coefficient during the online test and a high voltage fault ride through control coefficient during the online test respectively by using the maximum actual allowable value of the reactive power during the online test, the low voltage fault ride through control coefficient during the online test and the high voltage fault ride through control coefficient during the online test being an online test working condition set.

[0310] Further, the first calculation module is specifically configured to:

[0311] The first calculation module is configured to calculate a maximum theoretical allowable value of the reactive power during the online test by using the grid reactance of the to-be-tested SVG and the preset safe operation boundary.

[0312] The first calculation module is configured to calculate the maximum actual allowable value of the reactive power during the online test by using the maximum theoretical allowable value of the reactive power during the online test.

[0313] Further, the first processor further comprises:

[0314] The control unit is configured to, after setting the fault ride through control coefficient of the to-be-tested SVG, control the first high voltage side acquisition end or the first low voltage side acquisition end to acquire an actual output voltage value of the test device according to a test requirement, and send the actual output voltage value of the test device to the second processor.

[0315] Further, the second processor further comprises:

[0316] The fourth calculation unit is configured to, after setting the fault ride through control coefficient of the to-be-tested SVG, calculate and generate an output voltage reference value of the test device at a next moment by using a linear interpolation model established in advance based on the actual output voltage value of the test device.

[0317] The voltage synchronization unit is configured to send the output voltage reference value of the test device at the next time to the DA module for power amplification when the output voltage error of the test device at the continuous preset number of time points is less than or equal to the maximum allowable error of the test device, so as to obtain the output test voltage of the test device, and send the output test voltage to the test voltage output end, and the test voltage output end connects the output test voltage to the low-voltage side voltage collection end of the SVG for voltage synchronization of the grid connection point of the test device and the SVG to be tested.

[0318] Further, the second processor further comprises:

[0319] The fifth calculation unit is configured to calculate the deviation coefficient by using the actual output voltage value of the test device.

[0320] The compensation unit is configured to, after the voltage synchronization is completed, determine whether the output signal amplitude of the DA module needs to be compensated by using the current state of the preset SVG high-low on-line test signal sequence sent by the first processor, if not, send the current state of the SVG high-low on-line test signal sequence to the DA module, so that the DA module determines the final output voltage according to the current state, and if yes, calculate the compensation coefficient by using the deviation coefficient, and send the compensation coefficient and the current state to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0321] Further, the compensation unit is specifically configured to:

[0322] When the current state of the SVG high-low on-line test signal sequence is 1, the output signal amplitude of the DA module does not need to be compensated; when the current state of the SVG high-low on-line test signal sequence is K u , the output signal amplitude of the DA module needs to be compensated.

[0323] Further, the DA module is further configured to:

[0324] send the final output voltage to the test voltage output end, so that the test voltage output end sends the final output voltage to the SVG to be tested, and then the SVG to be tested uses the final output voltage to provide reactive power support for fault ride-through.

[0325] Further, the calculation formula of the grid reactance of the SVG to be tested comprises:

[0326]

[0327] In the above formula, X grid is the grid reactance of the SVG to be tested, V 1 is the effective value of the per-unit voltage calculated by the maximum test of inductive reactive power,V 2 is the effective value of the post-standard voltage calculated by the capacitive reactive power maximum test, Q 1 is the actual output reactive power after the post-standard calculated by the inductive reactive power maximum test, Q 2 is the actual output reactive power after the post-standard calculated by the capacitive reactive power maximum test.

[0328] Further, the calculation formula of the theoretical maximum allowable value of the reactive power during the online test includes:

[0329]

[0330] The calculation formula of the actual maximum allowable value of the reactive power during the online test includes:

[0331]

[0332] In the above formula, Q Em is the theoretical maximum allowable value of the reactive power during the online test, X grid is the grid reactance of the SVG to be tested, K B is the deviation of the grid point voltage, Q m is the actual maximum allowable value of the reactive power during the online test, K is the maximum reactive power overload factor of the SVG to be tested, Q N is the rated power of the SVG to be tested.

[0333] Further, the calculation formula of the low voltage fault ride-through control coefficient during the online test includes:

[0334]

[0335] The calculation formula of the high voltage fault ride-through control coefficient during the online test includes:

[0336]

[0337] In the above formula, K L is the low voltage fault ride-through control coefficient during the online test, U L is the voltage value after the grid point voltage drops, Q m is the actual maximum allowable value of the reactive power during the online test, ω 1 is the action threshold value of the SVG to be tested entering low voltage ride-through, ω 2 is the action threshold value of the SVG to be tested entering high voltage ride-through, K HThis refers to the high-voltage fault ride-through control factor during online testing. U H This is the voltage value after the voltage drop at the grid connection point.

[0338] Furthermore, the calculation formula for the linear interpolation model includes:

[0339]

[0340] In the above formula, , T test To test the total time, U a ( k +1) is the test device in k The output voltage reference value at time +1 N d To match the control delay interval value of the test device, U r This represents the actual output voltage value of the testing device. e To test the output voltage error of the device, e max This represents the maximum permissible error of the testing device.

[0341] Furthermore, the formula for calculating the control delay interval of the matching test device includes:

[0342]

[0343] The formula for calculating the output voltage error of the testing device includes:

[0344]

[0345] The formula for calculating the maximum permissible error of the testing device includes:

[0346]

[0347] In the above formula, , T test To test the total time, T d To match the control delay of the test equipment, T s For signal output period, U a ( k-N d +1) is ( k-N d The output voltage reference value at time +1) U r ( k-Nd +1) is the output voltage of the test device, k-N d +1) is the output voltage of the test device, U pccN is the secondary voltage rating of the SVG grid-connected point voltage, f 0 is the frequency.

[0348] Further, the calculation formula of the deviation coefficient includes:

[0349]

[0350] In the above formula, K 1 is the deviation coefficient, U r is the output voltage of the test device, U pccN is the secondary voltage rating of the SVG grid-connected point voltage.

[0351] Further, the SVG high-low on-line test signal sequence is:

[0352]

[0353] In the above formula, , T test is the total time of the test, S k is the SVG high-low on-line test signal sequence at time k K u is the drop / rise amplitude of the final output voltage compared to the secondary voltage rating of the SVG grid-connected point voltage.

[0354] Further, the calculation formula of the compensation coefficient includes:

[0355] K BC K u K 1

[0356] In the above formula, K BC is the compensation coefficient, K u is the drop / rise amplitude of the final output voltage compared to the secondary voltage rating of the SVG grid-connected point voltage, K 1 is the deviation coefficient.

[0357] Further, the calculation formula of the final output voltage includes:

[0358] ​​​​

[0359] in the above formula, U O k is the final output voltage at the moment, k Ua k is the output voltage reference value of the test device at the moment, k S k is the SVG high-low pass online test signal sequence at the moment, k K BC is the compensation coefficient.

[0360] The static reactive power compensation device fault ride-through capability online test system provided by the application not only effectively guarantees the safety of the SVG and the power grid during online testing, but also improves the synchronization efficiency of the test device output test voltage and the SVG grid connection point voltage, so that the port voltage of the SVG to be tested can reach the set change range under any condition, and the compliance of the test signal and the reliability of the test result are guaranteed.

[0361] Embodiment Four

[0362] To further illustrate the static reactive power compensation device fault ride-through capability online test system described above, the application provides a specific example, as shown in Figure 3 , including the following steps:

[0363] Step 1: Build a static reactive power compensation device SVG fault ride-through capability online test system, develop a reactive power / voltage control capability test, determine the online test working condition set of the fault ride-through capability in combination with the test data and the safe operation boundary.

[0364] Further, step 1 includes the following content:

[0365] First, build the SVG fault ride-through capability online test system as shown in Figure 3 , when normally operating, the high-voltage side voltage and current collection end of the SVG to be tested are connected to the voltage transformer and current transformer of the high-voltage side of the grid-connected transformer through the electrical direct connection line (such as electrical secondary wiring) respectively; the low-voltage side voltage and current collection end of the SVG to be tested are also connected to the voltage transformer and current transformer of the low-voltage side of the grid-connected transformer through the electrical direct connection line (such as electrical secondary wiring) respectively, and can receive the reactive power / voltage adjustment instruction issued by the regulation and control system. When online testing, the test device needs to be connected, the high-voltage side voltage and current collection end of the test device are connected to the voltage transformer and current transformer of the high-voltage side of the grid-connected transformer through the electrical direct connection line respectively; the low-voltage side voltage and current collection end are also connected to the voltage transformer and current transformer of the high-voltage side of the grid-connected transformer through the electrical direct connection line respectively. ​​​​​​

[0366] Specifically, the high-voltage side voltage and current collection end of the to-be-tested SVG and the high-voltage side voltage and current collection end of the test device are connected to the first current transformer through the first current clamp meter respectively; the low-voltage side voltage and current collection end of the to-be-tested SVG and the low-voltage side voltage and current collection end of the test device are connected to the second current transformer through the second current clamp meter respectively; the high-voltage side voltage and current collection end of the to-be-tested SVG and the high-voltage side voltage and current collection end of the test device are connected to the first voltage transformer respectively; the low-voltage side voltage and current collection end of the to-be-tested SVG and the low-voltage side voltage and current collection end of the test device are connected to the second voltage transformer respectively; the to-be-tested SVG, the grid-connected transformer and the power grid are connected in turn through the electrical primary wiring, and the regulation and control system is connected with the to-be-tested SVG and the test device through the communication wiring respectively.

[0367] Then, the reactive power / voltage control capability test of the to-be-tested SVG is carried out, and the test steps are as follows:

[0368] 1) The regulation and control system issues the capacitive maximum reactive power instruction to the to-be-tested SVG; after maintaining for 2 minutes, the inductive maximum reactive power instruction is issued to the to-be-tested SVG; after maintaining for 2 minutes, the initial reactive power instruction is issued to the to-be-tested SVG; when the regulation and control system issues the control instruction to the to-be-tested SVG, the test device is synchronously forwarded to trigger the recording function of the test device.

[0369] 2) During the test, the test device records the voltage and current data of the high-voltage side of the grid-connected transformer, and selects the data of the last 30 seconds of each instruction maintaining period to calculate the voltage effective value V and the actual output reactive power Q , and the calculation formula is as follows:

[0370]

[0371]

[0372]

[0373]

[0374]

[0375]

[0376]

[0377]

[0378]

[0379] In the above formula, V reReal part of fundamental effective value of phase voltage for measuring, T Reference period of signal for measuring, t 0 is the start time of data window for calculating, t is the time, u ( t ) is instantaneous value of phase voltage for measuring, f Reference frequency of signal for measuring, V lm Imaginary part of fundamental effective value of phase voltage for measuring, V Fundamental effective value of phase voltage for measuring (i.e. voltage effective value), φ V Phase of fundamental effective value of phase voltage for measuring, I re Real part of fundamental effective value of phase current for measuring, i ( t ) is instantaneous value of phase current for measuring, I lm Imaginary part of fundamental effective value of phase current for measuring, I Fundamental effective value of phase current for measuring, φ I Phase of fundamental effective value of phase current for measuring, Q Actual output of reactive power.

[0380] 3) Calculate grid reactance of SVG to be measured X grid The calculation formula is as follows:

[0381] (1)

[0382] In the above formula, V 1 is the per-unit voltage effective value after maximum test of inductive reactive power, V 2 is the per-unit voltage effective value after maximum test of capacitive reactive power, Q 1 is the per-unit actual output of reactive power after maximum test of inductive reactive power, Q 2 is the per-unit actual output of reactive power after maximum test of capacitive reactive power.

[0383] Finally, according to the calculated grid reactance and the safe operation boundary, the online test working condition set is determined, which includes: actual maximum allowable value of reactive power during online test Q m , low voltage fault ride through control coefficient during online test K L , and high voltage fault ride through control coefficient during online test K H , and the specific steps are as follows:

[0384] 1) Referring to the constraints on grid voltage deviation in GB / T12325 "Power Quality - Supply Voltage Deviation", for SVG connected to the grid at voltage levels above 35kV, the deviation of its grid connection point voltage is... K B It should be within ±10%, taking into account the grid reactance. X grid The theoretical maximum allowable value of reactive power during online testing can be calculated. Q Em The calculation formula is as follows:

[0385] (2)

[0386] Considering the strong power grid, the result calculated according to equation (2) Q Em The reactive power may exceed the maximum reactive power overload capacity of the SVG. Therefore, the actual maximum allowable reactive power during the online test is calculated using the following formula. Q m :

[0387] (3)

[0388] In the formula, K The maximum reactive power overload multiple of the SVG under test. Q N This represents the rated power of the SVG under test.

[0389] 2) Based on the actual maximum allowable reactive power output of the SVG under test during online testing and the low-voltage fault ride-through control equation, determine the low-voltage fault ride-through control coefficients during online testing. K L The low-voltage fault ride-through control equations are as follows:

[0390] (4)

[0391] In the formula, I q and U pcc These represent the reactive current output of the SVG under test and the grid connection point voltage, respectively. Considering the reactive current output of the SVG under test during online testing... I q With actual output reactive power Q Equivalent, therefore equation (4) can be written as:

[0392] (5)

[0393] If the power grid management department requires the voltage at the grid connection point to drop to [a certain value] U LAt this time, the SVG to be tested should be able to support reliably, and the low-voltage fault ride-through control coefficient during online testing can be determined by substituting equation (5) into equation (5):

[0394] (6)

[0395] In the above equation, U L is the voltage value after the voltage drop of the grid-connected point.

[0396] 3) Similarly, the high-voltage fault ride-through control coefficient during online testing can be determined according to the actual maximum allowable value of the reactive power output by the SVG to be tested during online testing and the high-voltage fault ride-through control equation K H :

[0397] (7)

[0398] In the above equation, U H is the voltage value after the voltage drop of the grid-connected point.

[0399] Step 2: Set the fault ride-through control coefficient of the SVG to be tested to the control coefficient during low-voltage testing obtained in step 1 K L and the high-voltage fault ride-through control coefficient during online testing K H At the same time, a linear interpolation model matching the synchronization control delay is established to synchronize the test device with the voltage of the grid-connected point of the SVG to be tested, and the test voltage output end of the test device is connected to the low-voltage side voltage acquisition end of the SVG to be tested.

[0400] Further, step 2 includes the following contents:

[0401] The test device generally consists of an AD module, an FPGA processor (i.e. a second processor), a CPU processor (i.e. a first processor), and a DA module, wherein the AD module is used to collect the voltage and current signals of the high-voltage side and the low-voltage side of the grid-connected transformer; the FPGA processor is used to process the collection information of the AD module and control the output of the DA module; the CPU processor is mainly used to process information received through the network, human-computer interaction, etc.; the DA module is used to output the digital signal provided by the FPGA processor after power amplification. The output test voltage of the test device is synchronized with the voltage of the SVG grid-connected point as follows:

[0402] 1) A linear interpolation model matching the synchronization control delay of the test device is established, and the expression is as follows:

[0403] (8)

[0404] In the above equation, , T test To test the total time, U a ( k +1) is the test device in k The reference value of the output voltage at time +1; N d To match the control delay interval value of the test device, N d If it is an integer, the calculated value can be rounded down. U r This represents the actual output voltage value of the testing device. e To test the output voltage error of the device, e max The maximum permissible error of the testing device. T d To match the control delay of the test equipment, T s For signal output period, U a ( k-N d +1) is ( k-N d The output voltage reference value at time +1) U r ( k-N d +1) is ( k-N d The measured output voltage at time +1). e max The calculation formula is as follows:

[0405] (9)

[0406] In the above formula, U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage; f 0 represents the frequency, which is set to 50.

[0407] 2) The established linear interpolation model is embedded in the FPGA processor, and the output voltage reference value for the next moment is quickly calculated based on the sampled data from the AD module. U a ( k +1), which is sent to the DA module for power amplification before being output;

[0408] 3) Error between the measured output voltage and the reference output voltage of the FPGA processor based on the test device. e Determine the synchronization status of the output voltage. If the voltage error at 10 consecutive moments is less than [value missing], then [the following condition applies].e max The state of completing the output voltage synchronization is displayed on the client interface of the testing device. At this time, the output test voltage of the testing device is connected to the low-voltage side voltage collection end of the SVG.

[0409] Step 3: The CPU processor receives the preset SVG high-low penetration online test signal sequence through the communication port, and adopts a segmented amplitude coefficient compensation strategy. The processed test signal sequence is sent to the DA module through the FPGA processor, and the final output voltage is output.

[0410] Further, step 3 includes the following contents:

[0411] The SVG high-low penetration online test signal sequence is as follows: S k

[0412] (10)

[0413] In the above formula, K u is the drop / rise amplitude of the final output voltage compared to the secondary voltage rating of the SVG grid point voltage.

[0414] Considering that the port voltage of the SVG to be tested before online testing may deviate from the rated voltage value, resulting in that the test voltage directly generated according to the test signal sequence cannot reach the pre-set drop / rise amplitude, and cannot meet the test requirements. To this end, a segmented amplitude coefficient compensation strategy is adopted, and the steps are as follows:

[0415] First, the FPGA processor calculates the deviation coefficient according to the actual voltage collected by the AD K 1, and the calculation formula is as follows:

[0416] (11)

[0417] In the above formula, U r is the actual value of the output voltage of the testing device, U pccN is the secondary voltage rating of the SVG grid point voltage, that is, the voltage rating of the grid point voltage after being transformed by the voltage transformer, which is generally 100V.

[0418] Then, the FPGA processor sends K 1 to the CPU processor, and the CPU performs segmented amplitude coefficient compensation according to the received SVG high-low penetration online test signal sequence: when the sequence state is analyzed to be “1”, the DA module output signal amplitude is not intervened; when the sequence state is analyzed to be “ K u ​​When this occurs, the amplitude of the output signal of the DA module is compensated, and the compensation coefficient is... K BC = K u / K 1.

[0419] Finally, the amplitude compensation coefficient is sent to the DA module via the FPGA processor. The DA module determines the final output voltage and outputs it to the test voltage output terminal to meet the set drop / rise amplitude requirements. This allows the test voltage output terminal to send the final output voltage to the SVG under test, enabling the SVG to utilize the final output voltage for reactive power support during fault ride-through. The formula for calculating the final output voltage includes:

[0420]

[0421] In the above formula, U O ( k )for k The final output voltage at time [time]. Ua ( k ) for the test device in k The reference value of the output voltage at any given time.

[0422] This invention provides a fault ride-through capability testing device, method, and system for a static var compensator (SVC), including the selection of an online test condition set, a rapid synchronization control strategy for the testing device and system, and a segmented amplitude coefficient compensation strategy. The specific advantages of this invention are as follows:

[0423] (1) The operating condition set for online testing of SVG in this invention is formulated with consideration of the maximum reactive overload capacity of SVG and the safety boundary of grid operating voltage, which effectively ensures the safety of SVG and grid operation during online testing.

[0424] (2) The fast synchronization control strategy in this invention realizes the rapid synchronization of the test voltage output by the test device and the voltage of the SVG grid connection point within 1ms, which improves the synchronization efficiency of the two and is better than the synchronization time of the current similar devices (the synchronization time of the current similar devices is generally 10ms~60ms).

[0425] (3) The segmented amplitude coefficient compensation strategy in this invention takes into account the offset of the SVG port voltage under test, so that the test device can output the test voltage to the set change range under any condition, ensuring the compliance of the test signal and the reliability of the test results.

[0426] To further verify the effectiveness of the application, the SVG configured in a certain light storage power station in Yunnan is selected for actual measurement verification. The grid-connected point voltage of the to-be-tested SVG is 35 kV, the rated reactive power is 30 MVar, the maximum reactive power overload factor is 1.2, and the rated phase voltage of the secondary side is 57.735 V.

[0427] According to the above step 1, the reactive power / voltage control capability test of the to-be-tested SVG is first carried out, and the test waveform is as shown in Figure 4 and Figure 5 , wherein U r is the actual value of the output voltage of the test device, Q r , Q s is the reactive power control response value and the true value of the to-be-tested SVG, respectively.

[0428] Then, according to the test data, it is calculated that when the to-be-tested SVG outputs the maximum inductive reactive power 30 MVar, the grid-connected point voltage is 21.09 kV, and when the to-be-tested SVG outputs the maximum capacitive reactive power -30 MVar, the grid-connected point voltage is 21.81 kV, and thus the normalized grid impedance X grid is 0.018.

[0429] Finally, the actual maximum allowed value of the reactive power of the to-be-tested SVG during the online test can be calculated Q m , and the normalized value is 1.2. In addition, according to the requirements of the local power grid management department, when the grid-connected point voltage drops to below 0.3 or jumps to below 1.2, the to-be-tested SVG should be able to reliably support, and thus the low-voltage fault ride-through control coefficient of the to-be-tested SVG during the online test can be calculated K L is 2, and the high-voltage fault ride-through control coefficient during the online test is K H is 12, and thus the selection of the online test working condition set is completed.

[0430] According to the above step 2, a linear interpolation model matched with the control delay of the test device is established. The control delay of the device is T d is 5 ms, the signal output period is T s is 0.08 ms, and thus the matching interval can be calculated N d is 62.5, and the integral value is 63; at the same time, the rated phase voltage of the secondary side of the to-be-tested SVG can be calculated, and the error criterion is e max is 1.43. After the application of the fast synchronization strategy of the application, the synchronization effect of the output voltage of the test device is as shown in Figure 6As shown in the figure, Uain and Uaout are the measured voltage at the SVG grid connection point and the output test voltage, respectively, measured by the test device.

[0431] from Figure 6 As can be seen from the above, after adopting the fast synchronization control strategy of the present invention, when the voltage at the grid connection point of the SVG under test fluctuates, the testing device can quickly synchronize and track it, with a synchronization time of less than 1ms.

[0432] Based on step 3 above, the fault ride-through test waveform of the SVG under test after piecewise amplitude coefficient compensation is as follows: Figure 7 As shown, Figure 7 In this context, Ut_pos represents the per-unit value of the test voltage, and Iq_pos and Iqs_pos represent the actual and theoretical values ​​of the reactive current, respectively. Figure 7 As can be seen from the data, initially, because the grid connection point of the SVG under test is higher than the rated value, the output test voltage of the test device is higher than the rated value; at the time of the fault, the set voltage drop factor... K With u=0.7, the actual output voltage drops to 0.7 as can be seen from the test waveform, thus achieving segmented amplitude coefficient compensation.

[0433] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0434] Example 5

[0435] like Figure 8 As shown, the present invention also provides an electronic device, which may be a computer device, a microcontroller device, a smart mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, processor, and transceiver component are connected via a bus; the memory can be used to store executable programs, and an exemplary executable program may include instructions; the processor is used to execute the instructions stored in the memory. The memory can also be used to store data, which can be accessed and / or modified when instructions are executed.

[0436] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, etc., which are the computing core and control core of the terminal, and are suitable for implementing one or more instructions, and are suitable for loading and executing one or more instructions in the storage medium to implement a corresponding method process or a corresponding function, so as to implement the steps of the online testing method for the fault ride-through capability of the static var compensation device in the above embodiment.

[0437] Embodiment six

[0438] Based on the same inventive concept, the application further provides a readable storage medium, specifically an electronic device readable storage medium (Memory). The electronic device readable storage medium is a memory device in the electronic device, and is used to store programs and data. It can be understood that the storage medium herein can include a built-in storage medium in the electronic device, and of course can also include an expansion storage medium supported by the electronic device. The storage medium provides a storage space, and the storage space stores an operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and the instructions can be one or more execution programs (including program codes). It should be noted that the storage medium herein can be a high-speed RAM memory, or a non-volatile memory such as at least one disk memory. The processor loads and executes one or more instructions stored in the storage medium, and the steps of the online testing method for the fault ride-through capability of the static var compensation device in the above embodiment can be implemented.

[0439] Those skilled in the art should understand that the embodiments of the application can be provided as a method, a system, or a computer program product. Therefore, the application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0440] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flows and / or block diagram block or blocks. Figure 1 one or more flow or flows and / or block diagram block or blocks. Figure 1 one or more flow or flows and / or block diagram block or blocks.

[0441] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flows and / or block diagram block or blocks. Figure 1 one or more flow or flows and / or block diagram block or blocks. Figure 1 one or more flow or flows and / or block diagram block or blocks.

[0442] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flows and / or block diagram block or blocks. Figure 1 one or more flow or flows and / or block diagram block or blocks. Figure 1 one or more flow or flows and / or block diagram block or blocks.

[0443] Finally, it should be noted that the above-mentioned embodiments are merely intended to illustrate the technical solutions of the present application, rather than limit the same. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or equivalent replacements without departing from the spirit and scope of the present application, and any modifications or equivalent replacements shall be included in the protection scope of the claims of the present application.

Claims

1. A fault ride-through capability testing device for a static var compensator (SVG), wherein the testing device is connected to the SVG under test, the SVG under test is connected to a control system, the control system is connected to a grid-connected transformer, and the grid-connected transformer is connected to both the power grid and the SVG under test, characterized in that, include: First processor, second processor, and first high-voltage side acquisition terminal; The first processor is connected to the control system and the second processor respectively, and is used to send the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal when it receives each target reactive power command issued by the control system. The first high-voltage side acquisition terminal is connected between the grid-connected transformer and the power grid. When the waveform recording command is received, it is used to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer, and send the target current data and target voltage data to the second processor. The second processor is connected to the first high-voltage side acquisition terminal and is used to determine the online test condition set using the target current data and target voltage data, so as to set the fault ride-through control coefficient of the SVG under test according to the online test condition set; It is also used to synchronize the grid connection point voltage of the test device and the SVG under test using a pre-established linear interpolation model; It is also used to determine the deviation coefficient by adopting a segmented amplitude coefficient compensation strategy, so as to determine the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to provide reactive power support for fault ride-through.

2. The apparatus according to claim 1, characterized in that, Also includes: The first low-voltage side includes the acquisition terminal, AD module, DA module, and test voltage output terminal; The AD module is connected to the first high-voltage side acquisition terminal, the first low-voltage side acquisition terminal, and the second processor, respectively; the DA module is connected to the second processor and the test voltage output terminal, respectively.

3. The apparatus according to claim 2, characterized in that, The AD module is used for analog-to-digital conversion; The DA module is used to amplify the power of digital signals.

4. The apparatus according to claim 2, characterized in that, The first high-voltage side acquisition terminal is connected to the first current transformer via a first current clamp meter, and the first high-voltage side acquisition terminal is connected to the first voltage transformer; The first low-voltage side acquisition terminal is connected to the second current transformer via a second current clamp meter, and the first low-voltage side acquisition terminal is connected to the second voltage transformer; The first current transformer and the first voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the SVG under test.

5. The apparatus according to claim 1, characterized in that, The static var compensator includes: a second high-voltage side acquisition terminal and a second low-voltage side acquisition terminal; The second high-voltage side acquisition terminal is connected to the first current transformer via the first current clamp meter, and the second high-voltage side acquisition terminal is connected to the first voltage transformer; The second low-voltage side acquisition terminal is connected to the second current transformer via a second current clamp meter, and the second low-voltage side acquisition terminal is connected to the second voltage transformer; The first current transformer and the first voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the SVG under test.

6. The apparatus according to claim 1, characterized in that, The target reactive power commands include: capacitive maximum reactive power command, inductive maximum reactive power command, and initial reactive power command; The order in which the target reactive power commands are issued is as follows: capacitive maximum reactive power command, inductive maximum reactive power command, and initial reactive power command.

7. The apparatus according to claim 6, characterized in that, The control system is used to send each target reactive power instruction to the SVG under test and the first processor respectively according to the order of issuance of each target reactive power instruction, and the time interval between issuance of each target reactive power instruction is a preset time interval. The SVG under test is used to send reactive power corresponding to each target reactive power command to the power grid when it receives each target reactive power command, and the duration of sending reactive power is a preset time interval.

8. The apparatus according to claim 6, characterized in that, The first high-voltage side acquisition terminal is specifically used for: Upon receiving the waveform recording command corresponding to each target reactive power command, the current and voltage data between the SVG under test and the grid-connected transformer are recorded. The current and voltage data within a preset time window of the maintenance time corresponding to each target reactive power command are selected as the target current data and target voltage data, and the target current data and target voltage data are sent to the second processor.

9. The apparatus according to claim 1, characterized in that, The second processor includes: The first calculation unit is used to calculate the effective voltage value and the actual output reactive power using the target current data and target voltage data. The second calculation unit is used to calculate the grid reactance of the SVG under test using the effective voltage value and the actual output reactive power; The third calculation unit is used to calculate the online test condition set using the grid reactance of the SVG under test and the preset safe operating boundary; The effective voltage value includes: the effective voltage value per unit calculated by the maximum inductive reactive power test and the effective voltage value per unit calculated by the maximum capacitive reactive power test; the actual output reactive power includes: the actual output reactive power per unit calculated by the maximum inductive reactive power test and the actual output reactive power per unit calculated by the maximum capacitive reactive power test. The preset safe operating boundaries include: the deviation of the grid connection point voltage, the action threshold for the SVG under test to enter low voltage ride-through, and the action threshold for the SVG under test to enter high voltage ride-through.

10. The apparatus according to claim 9, characterized in that, The third computing unit includes: The first calculation module is used to calculate the actual maximum allowable value of reactive power during online testing by using the grid reactance of the SVG under test and the preset safe operation boundary. The second calculation module is used to calculate the low-voltage fault ride-through control coefficient and the high-voltage fault ride-through control coefficient during the online test using the actual maximum allowable value of reactive power during the online test. The low-voltage fault ride-through control coefficient and the high-voltage fault ride-through control coefficient during the online test are the online test condition set.

11. The apparatus according to claim 10, characterized in that, The first calculation module is specifically used for: Using the grid reactance of the SVG under test and the preset safe operating boundary, the theoretical maximum allowable value of reactive power during online testing is calculated; Using the theoretical maximum allowable value of reactive power during the online test, the actual maximum allowable value of reactive power during the online test is calculated.

12. The apparatus according to claim 2, characterized in that, The first processor further includes: The control unit is used to control the first high-voltage side acquisition terminal or the first low-voltage side acquisition terminal to acquire the actual value of the output voltage of the test device according to the test requirements after setting the fault ride-through control coefficient of the SVG under test, and send the actual value of the output voltage of the test device to the second processor.

13. The apparatus according to claim 12, characterized in that, The second processor further includes: The fourth calculation unit is used to calculate and generate the reference value of the output voltage of the test device at the next moment based on the actual value of the output voltage of the test device after setting the fault ride-through control coefficient of the SVG under test and using a pre-established linear interpolation model. The voltage synchronization unit is used to send the output voltage reference value of the test device at the next moment to the DA module for power amplification when the output voltage error of the test device is less than or equal to the maximum permissible error of the test device for a consecutive preset number of time moments, so as to obtain the output test voltage of the test device. The DA module then sends the output test voltage to the test voltage output terminal, and the test voltage output terminal connects the output test voltage to the low-voltage side voltage acquisition terminal of the SVG to synchronize the grid connection point voltage of the test device and the SVG under test.

14. The apparatus according to claim 13, characterized in that, The second processor further includes: The fifth calculation unit is used to calculate the deviation coefficient using the actual output voltage value of the test device; The compensation unit is used to determine, after voltage synchronization is completed, whether to compensate the output signal amplitude of the DA module by using the current state of the preset SVG high-low passthrough online test signal sequence sent by the first processor. If no compensation is needed, the current state of the SVG high-low passthrough online test signal sequence is sent to the DA module so that the DA module can determine the final output voltage based on the current state. If compensation is needed, a compensation coefficient is calculated using the deviation coefficient, and the compensation coefficient and the current state are sent to the DA module so that the DA module can determine the final output voltage based on the compensation coefficient and the current state.

15. The apparatus according to claim 14, characterized in that, The compensation unit is specifically used for: When the current state of the SVG high-low penetration online test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module; when the current state of the SVG high-low penetration online test signal sequence is... K u At this time, it is necessary to compensate for the amplitude of the output signal of the DA module.

16. The apparatus according to claim 14, characterized in that, The DA module is also used for: The final output voltage is sent to the test voltage output terminal, so that the test voltage output terminal sends the final output voltage to the SVG under test, thereby enabling the SVG under test to use the final output voltage for reactive power support during fault ride-through.

17. The apparatus according to claim 9, characterized in that, The formula for calculating the grid reactance of the SVG under test includes: In the above formula, X grid The grid reactance of the SVG to be tested. V 1 represents the per-unit effective voltage value calculated from the maximum inductive reactive power test. V 2 represents the per-unit effective voltage value calculated from the maximum capacitive reactive power test. Q 1 represents the actual per-unit output reactive power calculated from the maximum inductive reactive power test. Q 2 represents the actual per-unit output reactive power calculated from the maximum capacitive reactive power test.

18. The apparatus according to claim 11, characterized in that, The formula for calculating the theoretical maximum allowable value of reactive power during online testing includes: The formula for calculating the actual maximum allowable value of reactive power during online testing includes: In the above formula, Q Em This represents the theoretical maximum permissible value of reactive power during online testing. X grid The grid reactance of the SVG to be tested. K B For the deviation of the grid connection point voltage, Q m This represents the actual maximum permissible value of reactive power during online testing. K The maximum reactive power overload multiple of the SVG under test. Q N This represents the rated power of the SVG under test.

19. The apparatus according to claim 10, characterized in that, The formula for calculating the low-voltage fault ride-through control coefficient during the online test includes: The formula for calculating the high-voltage fault ride-through control coefficient during the online test includes: In the above formula, K L This refers to the low-voltage fault ride-through control factor during online testing. U L The voltage value after the voltage drop at the grid connection point. Q m This represents the actual maximum permissible value of reactive power during online testing. ω 1 represents the threshold value for the under-voltage ride-through of the SVG under test. ω 2 represents the action threshold for the SVG under test to enter high-voltage ride-through. K H This refers to the high-voltage fault ride-through control factor during online testing. U H This is the voltage value after the voltage drop at the grid connection point.

20. The apparatus according to claim 13, characterized in that, The calculation formula of the linear interpolation model includes: In the above formula, , T test To test the total time, U a ( k +1) is the test device in k The output voltage reference value at time +1 N d To match the control delay interval value of the test device, U r This represents the actual output voltage value of the testing device. e To test the output voltage error of the device, e max This represents the maximum permissible error of the testing device.

21. The apparatus according to claim 20, characterized in that, The formula for calculating the control delay interval of the matching test device includes: The formula for calculating the output voltage error of the testing device includes: The formula for calculating the maximum permissible error of the testing device includes: In the above formula, , T test To test the total time, T d To match the control delay of the test equipment, T s For signal output period, U a ( kN d +1) is ( kN d The output voltage reference value at time +1) U r ( kN d +1) is ( kN d Measured output voltage at time +1) U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage. f 0 represents frequency.

22. The apparatus according to claim 14, characterized in that, The formula for calculating the deviation coefficient includes: In the above formula, K 1 is the deviation coefficient. U r This represents the actual output voltage value of the testing device. U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage.

23. The apparatus according to claim 14, characterized in that, The SVG high-low penetration online test signal sequence is as follows: In the above formula, , T test To test the total time, S ( k )for k SVG high-low crossover online test signal sequence, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

24. The apparatus according to claim 14, characterized in that, The formula for calculating the compensation coefficient includes: K BC = K u / K 1 In the above formula, K BC For compensation coefficient, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point. K 1 represents the deviation coefficient.

25. The apparatus according to claim 14, characterized in that, The formula for calculating the final output voltage includes: In the above formula, U O ( k )for k The final output voltage at time [time]. Ua ( k ) for the test device in k The output voltage reference value at that moment. S ( k )for k SVG high-low crossover online test signal sequence, K BC This is the compensation coefficient.

26. An online testing method for the fault ride-through capability of a static var compensator, applicable to the fault ride-through capability testing device for a static var compensator as described in any one of claims 1-25, characterized in that, include: When the first processor receives the target reactive power commands issued by the control system, it sends the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal. When the first high-voltage side acquisition terminal receives the waveform recording command, it uses the first high-voltage side acquisition terminal to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer, and sends the target current data and target voltage data to the second processor; The second processor determines the online test condition set based on the target current data and target voltage data, and sets the fault ride-through control coefficient of the SVG under test according to the online test condition set; After setting the fault ride-through control coefficient of the SVG under test, the second processor uses a pre-established linear interpolation model to synchronize the grid connection point voltage of the test device and the SVG under test. After voltage synchronization is completed, the second processor uses a segmented amplitude coefficient compensation strategy to determine the deviation coefficient, and determines the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to provide reactive power support for fault ride-through.

27. An online testing system for the fault ride-through capability of a static var compensator, characterized in that, include: Control system, SVG under test and fault ride-through capability testing device for SVG as described in any one of claims 1-25; The control system is connected to the test device and the SVG under test respectively, and the SVG under test, the grid-connected transformer and the power grid are connected in sequence; the control system is used to send target reactive power commands to the SVG under test and the first processor in the test device respectively; The SVG under test is used to send reactive power corresponding to the target reactive power command to the power grid when it receives the target reactive power command, and the duration of sending reactive power is a preset time interval. The first processor in the testing device is used to send the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal in the testing device when it receives each target reactive power command issued by the control system. The first high-voltage side acquisition terminal in the test device is used to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer when the waveform recording command is received, and send the target current data and target voltage data to the second processor in the test device; The second processor in the testing device is used to determine an online test condition set using the target current data and target voltage data, so as to set the fault ride-through control coefficient of the SVG under test according to the online test condition set. And the grid connection point voltage of the test device and the SVG under test is synchronized using a pre-established linear interpolation model; And a segmented amplitude coefficient compensation strategy is adopted to determine the deviation coefficient, so as to determine the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to support reactive power during fault ride-through.

28. An electronic device, characterized in that, include: At least one processor and memory; The memory and processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the online test method for fault ride-through capability of the static var compensator as described in claim 26 is implemented.

29. A readable storage medium, characterized in that, It contains an execution program, which, when executed, implements the online test method for the fault ride-through capability of the static var compensator as described in claim 26.

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