Verification unit and system

Abstract

The invention provides a verification unit and system. The verification unit comprises a middle layer, a pin simulation assembly and a marking assembly. The middle layer is used for supporting the whole structure and providing an attachment platform for each component; the pin simulation assembly is arranged on the lower surface of the middle layer and is used for simulating pins after chip packaging; the marking assembly is arranged on the upper surface of the middle layer and used for simulating marking information on the packaging chip. The verification unit solves the problems that in the production process, detection equipment calibration depends on a real chip, cost is high and efficiency is low, efficient equipment function verification and calibration are achieved, chip production detection stability and accuracy are improved, and factory quality is guaranteed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor testing, and in particular to a verification unit and system. BACKGROUND

[0002] In the field of semiconductor testing, an automatic optical machine needs to run a sample confirmation machine to ensure normal function before each shift production or product line change production. The current method is to produce a set of verification units for each product, that is, to apply for production units from customers and then manually process them into verification units. Only when the test results of these verification units meet the standards can production be officially started.

[0003] However, this method has many disadvantages. First, when the product line is changed, the verification unit corresponding to the product needs to be re-run, resulting in serious waste of production capacity. For example, when changing from one product to another, at least 40 minutes of production capacity may be wasted just by running the new verification unit. Second, the verification unit is made by secondary processing based on the quantity of products, which is limited by the material and is easily damaged after multiple uses. On average, it needs to be replaced once a month, which not only consumes production unit resources but also increases labor costs. Third, the current determination of the results of running the verification unit relies on manual work, lacks systematic automatic determination and recording functions, and does not have a foolproof and subsequent tracking mechanism, making it difficult to ensure the accuracy of the determination and the traceability of the production process. Therefore, it is urgent to improve the existing verification unit technology to solve the above problems. SUMMARY

[0004] Embodiments of the present disclosure provide a verification unit and system to solve the related problems existing in the prior art technical solutions.

[0005] Based on the above problems, in a first aspect, a verification unit is provided, comprising: an intermediate layer, a pin simulation component, and a marking component

[0006] The intermediate layer is used to support the overall structure and provide an attachment platform for each component.

[0007] The pin simulation component is arranged on the lower surface of the intermediate layer and is used to simulate the pins after the chip is packaged.

[0008] The marking component is arranged on the upper surface of the intermediate layer and is used to simulate the marking information on the packaged chip.

[0009] In combination with the first aspect, in a possible implementation manner, the pin simulation component comprises:

[0010] A ball simulation component is used to simulate the ball-shaped pins of the chip after being packaged by a ball grid array through a ball-shaped alloy; and / or

[0011] An alloy sheet simulation component is used to simulate the metal contact pins of the chip after being packaged by a planar grid array through an alloy sheet.

[0012] In combination with the first aspect, in a possible implementation, the verification unit comprises a defect verification unit.

[0013] The ball simulation component is configured to reduce the size of any ball-shaped alloy in the ball simulation component in the case of simulating a ball pin defect.

[0014] The alloy sheet simulation component is configured to set a recess on any sheet-shaped alloy in the alloy sheet simulation component in the case of simulating a metal contact defect.

[0015] The marking component is configured to set a marking pattern with missing characters on the marking component in the case of simulating a character defect.

[0016] The marking component is configured to set a marking pattern with missing two-dimensional codes on the marking component in the case of simulating a two-dimensional code defect.

[0017] In combination with the first aspect, in a possible implementation, the defect verification unit further comprises a copper simulation component arranged on the lower surface of the intermediate layer and configured to simulate a substrate defect caused by damage of a substrate of the packaged chip and exposure of an internal copper layer.

[0018] In combination with the first aspect, in a possible implementation, the verification unit comprises a standard verification unit.

[0019] The standard verification unit is configured to simulate a normal packaged chip.

[0020] In combination with the first aspect, in a possible implementation, the intermediate layer is made of a material with high mechanical strength and corrosion resistance; and / or

[0021] The color of the intermediate layer is consistent with the color of the substrate of the product unit; and / or

[0022] The color and shape of the ball simulation component are consistent with the color and shape of the ball pin after the chip is packaged by a ball grid array, and the ball simulation component is made of a material with high strength, wear resistance, and good processing adaptability; and / or

[0023] The color and shape of the alloy sheet simulation component are consistent with the color and shape of the metal contact after the chip is packaged by a planar grid array, and the alloy sheet simulation component is made of a material with good processing performance and coloring performance; and / or

[0024] The marking component is made of a material conducive to marking.

[0025] In combination with the first aspect, in a possible implementation, the surface of the copper simulation component is provided with a protective coating made of a material with high hardness, strong wear resistance, and good chemical stability.

[0026] In a second aspect, a verification system is provided, comprising: the verification unit, the at least one product unit detection machine and the processor as described in the first aspect, or any possible implementation manner of the first aspect;

[0027] The product unit detection machine is configured to detect the product unit or the verification unit by using the optical machine installed thereon, and send detection data to the processor;

[0028] The processor is configured to analyze the detection data of the optical machine, determine a detection result of whether the optical machine is in normal function, and synchronize the detection result to the product unit detection machine;

[0029] The product unit detection machine is further configured to display the received detection result.

[0030] With reference to the second aspect, in a possible implementation manner, the product unit detection machine further comprises an NFC module configured to obtain information of an NFC work card, determine a verification personnel work number, and synchronize the verification personnel work number to the processor;

[0031] The processor is configured to analyze and generate report data based on the detection data of the day, the verification personnel work number, the built-in device information and the time information, and send the report data at a preset time.

[0032] With reference to the second aspect, in a possible implementation manner, the system further comprises a cloud platform;

[0033] The processor is configured to synchronize the detection result to the cloud platform;

[0034] The cloud platform is configured to receive the detection result sent by the processor and generate a log.

[0035] The beneficial effects of the embodiments of the present disclosure include:

[0036] The embodiment of the present disclosure provides a verification unit and system, which is used in the production and detection link of a semiconductor chip, assists in calibrating and verifying the function of an optical detection device, and ensures that the device accurately identifies the characteristics of chip pins, marking and the like. The middle layer supports the overall structure, provides a stable attachment platform for the pin simulation assembly and the marking assembly, ensures the installation accuracy of the assembly, and lays the foundation for accurate detection. The pin simulation assembly is arranged on the lower surface of the middle layer, simulates the pins after the chip is packaged (such as the ball shape and alloy sheet shape suitable for BGA / LGA packaging), and provides standard pin samples for the device. When the device is detected, the detection ability of the chip pins is verified by identifying the size, appearance and the like, so as to reduce the false deletion of good products or the missed detection of defective products. The marking assembly is arranged on the upper surface of the middle layer, simulates the marking information (characters, two-dimensional codes and the like) of the chip, and provides a detection object for the optical detection device. The device needs to accurately identify the marking content, definition and position, so as to verify the detection function of the device on the marking information of the chip, and ensure that the subsequent real chip marking can be effectively identified and traced.

[0037] In summary, the verification unit relies on the support of the middle layer, and the pin and marking assemblies accurately simulate the characteristics of the chip, so as to solve the problem that the calibration of the detection device depends on real chips, has high cost and low efficiency, realize efficient device function verification and calibration, improve the stability and accuracy of chip production and detection, and ensure the quality of the shipped products. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a structural schematic diagram of a verification unit according to an embodiment of the present disclosure;

[0039] Figure 2 FIG. 2 is another structural schematic diagram of a verification unit according to an embodiment of the present disclosure;

[0040] Figure 3 FIG. 3 is a schematic diagram of a ball pin defect according to an embodiment of the present disclosure;

[0041] Figure 4 FIG. 4 is a schematic diagram of an alloy sheet defect according to an embodiment of the present disclosure;

[0042] Figure 5 FIG. 5 is a schematic diagram of a character defect and a two-dimensional code defect according to an embodiment of the present disclosure;

[0043] Figure 6 FIG. 6 is a structural schematic diagram of a verification system according to an embodiment of the present disclosure;

[0044] Figure 7 FIG. 7 is a working logic diagram of a verification system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure provide a verification unit and a system, and the preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. Furthermore, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0046] The embodiments of the present disclosure provide a verification unit, as shown in the drawings, comprising: an intermediate layer 1, a pin simulation assembly 2 and a marking assembly 3. Figure 1

[0047] The intermediate layer 1 is used to support the overall structure and provide an attachment platform for each component.

[0048] The pin simulation assembly 2 is arranged on the lower surface of the intermediate layer 1 and is used to simulate the pins after the chip is packaged.

[0049] The marking assembly 3 is arranged on the upper surface of the intermediate layer 1 and is used to simulate the marking information on the packaged chip.

[0050] In the field of semiconductor testing, in order to solve the problems of capacity waste, high cost and lack of system determination existing in the traditional verification unit, a new verification unit is proposed.

[0051] The verification unit provided by the present disclosure is composed of an intermediate layer 1, a pin simulation assembly 2 and a marking assembly 3, and is suitable for the function confirmation link before each shift production or product line change production of an automatic optical machine.

[0052] The intermediate layer 1 serves as the basic structure of the verification unit and plays an important role in supporting the whole structure, and provides a stable attachment platform for the pin simulation assembly 2 and the marking assembly 3. The material thereof can be selected according to actual needs, such as high-strength and wear-resistant engineering plastics, to ensure the stability of the structure in the process of multiple tests.

[0053] The pin simulation assembly 2 is arranged on the lower surface of the intermediate layer 1 and is used to simulate the pins after the chip is packaged. In actual application, the shape, spacing and number of pins of different types of chips are different. This assembly can simulate various chip pin characteristics by designing different shapes and layouts, so that the verification unit can adapt to various product tests, and reduce the time and cost of re-producing the verification unit due to product line change.

[0054] The marking assembly 3 is located on the upper surface of the intermediate layer 1 and is used to simulate the marking information on the packaged chip. The marking information usually includes chip model, production batch, two-dimensional code and other contents. The marking assembly 3 can present these information by laser engraving or ink printing, so as to simulate the marking of the real chip and ensure the effective verification of the marking identification function of the automatic optical machine.

[0055] ​In summary, the verification unit provided by the disclosure has the characteristics of strong universality, long service life and reliable test results by modular design, organic combination of intermediate layer 1, pin simulation assembly 2 and marking assembly 3. It breaks through the limitations of traditional verification units based on quantity product processing, reduces production capacity waste and production cost, and at the same time, the components have clear division of labor, can realize comprehensive verification of the system to the machine function, has good application value and promotion prospect.

[0056] In another embodiment provided by the disclosure, the pin simulation assembly 2 comprises:

[0057] a ball simulation assembly for simulating the ball-shaped pins of a chip after BGA packaging through a ball-shaped alloy; and / or

[0058] an alloy sheet simulation assembly for simulating the metal contact pins of a chip after LGA packaging through a sheet-shaped alloy.

[0059] In the field of semiconductor testing, for the verification needs of chips of different packaging types, the pin simulation assembly 2 of the verification unit of the disclosure provides two specific implementations, namely a ball simulation assembly and an alloy sheet simulation assembly, to adapt to the test scenarios of BGA (Ball Grid Array) and LGA (Land Grid Array) packaged chips.

[0060] The ball simulation assembly realizes the simulation of the ball-shaped pins of a BGA packaged chip through a ball-shaped alloy. BGA packaging technology has the characteristics of high density and high performance, and is widely used in chips such as microprocessors and memories. In the process of semiconductor testing, automatic optical machines need to perform optical detection on the pins of BGA packaged chips, including parameters such as the shape, position and integrity of the pins. The ball simulation assembly adopts a ball-shaped alloy with similar material properties to real BGA pins, and its diameter, arrangement and height are accurately designed according to the specifications of the target chip to ensure that the optical reflection characteristics and geometric features of the BGA pins can be accurately simulated during testing. For example, for a mobile phone processor chip packaged with BGA, the ball simulation assembly can manufacture a ball-shaped alloy array with the same pin parameters as the chip through a precision casting process, which is used to verify the detection capability of the automatic optical machine for the coplanarity and solder ball diameter of the BGA pins.

[0061] The alloy sheet simulation assembly simulates the metal contact pins of the LGA packaged chip by sheet alloy. LGA packaging technology is often used for high-end chips such as notebook computer CPUs due to its good heat dissipation performance and convenient disassembly. The pins of the LGA packaged chip are in the form of planar metal contacts, and the automatic optical machine needs to detect the surface flatness and oxidation degree of these contacts. The alloy sheet simulation assembly uses sheet alloy material with high electrical conductivity, and its shape, size and surface roughness are matched with the real LGA pins. For example, for a certain type of notebook computer CPU LGA package, the alloy sheet simulation assembly can manufacture a sheet alloy array with a specific pattern and texture through precision stamping and surface treatment process, which is used to verify the detection capability of the automatic optical machine for surface defects of the LGA pins.

[0062] The two types of pin simulation assemblies 2 provided by the present disclosure adopt a modular design concept, and accurately simulate the pin characteristics of chips of different packaging types by different forms of alloy materials. In actual application, the middle layer 1 of the same verification unit can be integrated (as shown in Figure 2 ) or replaced with different pin simulation assemblies 2 according to test requirements, to realize compatible testing of chips of multiple packaging types. This design significantly improves the versatility and flexibility of the verification unit, avoids the disadvantages of traditional verification units that need to be separately manufactured for different packaging types, greatly reduces test cost and time. At the same time, the selection and processing technology of the alloy material ensure the durability and stability of the simulation assembly, reduce the waste of production capacity caused by frequent replacement of the verification unit, and improve the efficiency and reliability of semiconductor testing.

[0063] In another embodiment provided by the present disclosure, the verification unit includes a defective verification unit;

[0064] The ball simulation assembly is used to reduce the size of any spherical alloy in the ball simulation assembly in the case of simulating a spherical pin defect;

[0065] The alloy sheet simulation assembly is used to set recesses on any sheet alloy in the alloy sheet simulation assembly in the case of simulating a metal contact defect;

[0066] The marking assembly 3 is used to set a marking pattern with missing characters on the marking assembly 3 in the case of simulating a character defect;

[0067] The marking assembly 3 is used to set a marking pattern with missing two-dimensional codes on the marking assembly 3 in the case of simulating a two-dimensional code defect.

[0068] The verification unit provided by the present disclosure includes a defective verification unit, which provides a comprehensive functional verification scene for the equipment by accurately simulating various types of defective states. Based on the basic structure described above, the unit simulates various defective conditions that may occur in the real production environment through special processing.

[0069] like Figure 3 As shown, the spherical simulation component simulates defects in spherical leads by reducing the size of a specific spherical alloy. In the production of BGA packaged chips, abnormal spherical lead sizes are a common quality issue, potentially leading to poor connections between the chip and the circuit board. The defect verification unit uses precision machining processes to reduce the diameter of some spherical alloys to 80% or less of the standard value, thereby simulating lead size defects. For example, for BGA leads with a standard diameter of 0.5 mm, the defect verification unit can set the diameter of any one of the spherical alloys to 0.4 mm to simulate the presence of abnormal leads, testing the ability of automated optical inspection equipment to identify lead size deviations.

[0070] like Figure 4 As shown, the alloy sheet simulation component simulates metal contact defects by creating depressions on the surface of the alloy sheet. Surface depressions on the metal contacts of LGA packaged chips can lead to unstable electrical connections and affect chip performance. The defect verification unit uses laser etching or mechanical stamping processes to create depressions with a depth of 0.05mm to 0.1mm on the surface of the alloy sheet to simulate contact surface defects. For example, when simulating LGA contact defects of a certain CPU model, a circular depression with a diameter of 0.2mm can be created at a specific location on the alloy sheet to verify the sensitivity of the testing equipment to minute surface defects.

[0071] like Figure 5 As shown, marking component 3 generates a marking pattern with missing characters when simulating character-related defects. Missing characters in chip marking information can lead to difficulties in product traceability or misjudgment. The defect verification unit intentionally omits some characters in the marking pattern by adjusting laser engraving parameters or ink printing templates. For example, the chip model identifier, which should originally be "ABCD1234", is changed to "AB_D1234" to test the device's ability to detect character integrity.

[0072] like Figure 5 As shown, when simulating QR code defects, the marking component 3 generates a QR code pattern with missing parts. As a crucial carrier of chip information, the integrity of the QR code directly affects the accuracy of information reading. The defect verification unit simulates QR code damage by disrupting its integrity, such as deleting a corner positioning pattern or part of the data area. For example, deleting 30% of the lower right corner positioning square of a standard QR code pattern verifies the device's ability to detect QR code integrity.

[0073] The bad verification unit integrates simulation of various bad states in the same verification platform, and realizes accurate simulation of various defects through controllable physical structure adjustment. This design enables the automatic optical detection equipment to perform comprehensive function verification before production, and ensures that the detection ability of the automatic optical detection equipment for various bad conditions meets the requirements. Compared with the traditional verification unit, the unit not only can verify the detection ability of the equipment for normal products, but also can specifically test the recognition ability of the equipment for bad products, thereby significantly improving the comprehensiveness and effectiveness of the verification. Through the use of the bad verification unit, the semiconductor production enterprise can discover potential problems of the detection equipment in advance, reduce production losses caused by equipment misjudgment, improve product quality and production efficiency, and has important practical application value.

[0074] In yet another embodiment provided by the present disclosure, the bad verification unit further comprises a copper simulation component arranged on the lower surface of the intermediate layer 1 and used for simulating a substrate bad state caused by breakage of a substrate of a packaged chip to expose an internal copper layer.

[0075] In the semiconductor test process, breakage of the substrate of the packaged chip to expose the internal copper layer is a typical substrate bad state, which seriously affects the electrical performance and reliability of the chip. Therefore, in the embodiment of the present disclosure, the copper simulation component arranged on the bad verification unit is used to simulate the above-mentioned substrate bad state. The copper simulation component is arranged on the lower surface of the intermediate layer 1 and is used to accurately simulate this bad state and improve the detection and verification ability of the automatic optical machine for substrate defects.

[0076] In a possible implementation, the copper simulation component is arranged as a copper-yellow long small block and is made of copper, which more accurately simulates the state of breakage of the substrate layer to expose the internal copper layer.

[0077] The copper simulation component cooperates with the ball simulation component, the alloy sheet simulation component and the marking component 3 in the bad verification unit to build a more comprehensive bad simulation system. By simulating the bad state of breakage of the substrate to expose the copper layer, the detection precision, recognition ability and effectiveness of the detection algorithm of the automatic optical machine for substrate defects can be effectively verified. In actual production, the use of the bad verification unit containing the copper simulation component enables the automatic optical machine to fully verify its detection performance for substrate bad states before formal production, avoids the flow of bad products into the market due to the inability of the equipment to recognize such defects, reduces the quality risk and after-sales cost of the enterprise, and significantly improves the integrity and effectiveness of the semiconductor test.

[0078] In yet another embodiment provided by the present disclosure, the verification unit comprises a standard verification unit;

[0079] The standard verification unit is used for simulating a normal packaged chip.

[0080] In actual production process, the automatic optical machine needs to comprehensively verify the detection function before production. Corresponding to the bad verification unit, a standard verification unit is provided, which aims to simulate a normal packaged chip, and its function is similar to the bad verification unit, both of which are to ensure the detection accuracy and reliability of the automatic optical machine under different working conditions.

[0081] The standard verification unit is composed of an intermediate layer 1, a pin simulation component 2 and a marking component 3. Similar to the above-mentioned bad verification unit, the intermediate layer 1 provides stable support for the overall structure and provides an attachment platform for other components to ensure the stability of the structure during multiple tests. The pin simulation component 2 is customized according to the chip packaging type. For ball grid array (BGA) packaging, a precise spherical alloy simulation pin is used; for planar grid array (LGA) packaging, a flat sheet alloy simulation metal contact is used. This is similar to the idea of simulating bad conditions in the pin simulation component 2 of the bad verification unit, both of which are based on the characteristics of chip packaging and are specifically constructed, except that the standard verification unit simulates the normal state. In addition, as a general verification unit, different pin simulation components 2 can be integrated into the same verification unit during implementation.

[0082] The marking component 3 presents complete and clear marking information such as chip model, production batch, etc. and standard two-dimensional code patterns through laser engraving or high-precision ink printing, etc. This corresponds to the function of the marking component 3 in the bad verification unit, which simulates character type and two-dimensional code type bad conditions, both of which process chip marking information, except that one simulates normal and the other simulates abnormal, which serve the verification of the detection function of the automatic optical machine for chip marking information.

[0083] In terms of application scenarios, the standard verification unit, like the bad verification unit, is used before each shift production starts or when the product line is changed. Taking the smart watch chip production line as an example, when the device completes the detection of a batch of BGA packaged Bluetooth chips and is ready to switch to detecting LGA packaged master control chips, since the verification unit has been used for verification in the first batch and the verification unit integrates pins formed by two different packaging methods, it can be determined that the detection function of the detection machine for chips using BGA packaging and chips using LGA packaging is normal, so after switching, there is no need to use the verification unit for secondary verification again, saving time and cost.

[0084] The standard verification unit, through modular design and precise simulation of normal chip characteristics, complements the bad verification unit and builds a complete verification system. Both of them verify the detection function of the automatic optical machine from different angles, significantly improving the comprehensiveness and effectiveness of the detection performance verification of the device, reducing the production risk and quality problems caused by abnormal detection function of the device, and reducing the production cost of the enterprise, providing reliable protection for the quality control of semiconductor products.

[0085] In yet another embodiment of the present disclosure, the intermediate layer 1 is made of a material with high corrosion resistance and mechanical strength; and / or

[0086] The color of the intermediate layer 1 is consistent with the substrate color of the product unit; and / or

[0087] The color and shape of the ball simulation component are consistent with the color and shape of the ball-shaped pin of the chip after being packaged by the ball grid array, and the material has high strength, wear resistance and good processing adaptability; and / or

[0088] The color and shape of the alloy sheet simulation component are consistent with the color and shape of the metal contact of the chip after being packaged by the planar grid array, and the material has good processing performance and coloring property; and / or

[0089] The marking component 3 is made of a material conducive to marking.

[0090] In actual production process, the material and appearance characteristics of each component of the verification unit have a key influence on the accuracy and reliability of the test results. The present embodiment specifies the specific material and appearance design requirements of the intermediate layer 1, the ball simulation component, the alloy sheet simulation component and the marking component 3 of the verification unit.

[0091] The intermediate layer 1 is made of a material with high corrosion resistance and mechanical strength. In the semiconductor test environment, the equipment may use chemical reagents or be in a humid, high-temperature and other working conditions. The corrosion-resistant material can ensure that the intermediate layer 1 is not eroded for a long time, and the high mechanical strength can maintain the structural stability, avoiding the influence of deformation on the function of other components. When the color of the intermediate layer 1 is consistent with the substrate color of the product unit, it can provide a more realistic background reference for automatic optical machines in visual inspection. For example, titanium alloy with anodic oxidation treatment. Titanium alloy itself has high strength, low density and excellent corrosion resistance, which can provide stable support for other components. Through the anodic oxidation process, the surface can present a stable green color, accurately simulate the chip substrate color, and facilitate quick identification and positioning during detection. In addition, the oxidation film layer has high hardness, which can effectively resist friction and collision in daily detection, and has stable chemical properties and is not easy to react with the external environment, prolonging the service life of the verification unit.

[0092] The color and shape of the ball simulation component are consistent with the ball-shaped pins of the chip after BGA packaging, and the material has high strength, high wear resistance and good processing adaptability, such as tungsten-cobalt hard alloy. In the test of the BGA packaged chip, the ball-shaped pins need to withstand multiple optical detections, and the high strength and wear-resistant material can prolong the service life of the simulation component; good processing adaptability facilitates customization of shape and size according to different chip pin specifications. For example, for a BGA packaged processor chip with black-gray ball-shaped pins, the ball simulation component uses tungsten-cobalt hard alloy of the same color to accurately replicate the ball shape and size of the pins, ensuring the effectiveness of the automatic optical machine pin detection function verification. In addition, precise powder metallurgy technology can be used in the manufacturing process to accurately form balls of different sizes to simulate normal tin balls and abnormal small ball states.

[0093] The color and shape of the alloy sheet simulation component are consistent with the metal contacts of the chip after LGA packaging, and the material has good processing performance and coloring properties, such as aluminum alloy or copper alloy. During the test of the LGA packaged chip, the surface characteristics of the metal contacts directly affect the test results, and good processing performance can achieve accurate processing of the shape and size of the contacts, and coloring properties ensure that the color matches the real contacts. For example, to simulate the gold-colored metal contacts of an LGA packaged graphics card chip, the alloy sheet simulation component uses colorable aluminum alloy, which presents the same gold color through surface treatment process, and processes the same shape and spacing as the real contacts.

[0094] The marking component 3 uses a material that is conducive to marking, such as engineering plastic or metal with smooth surface and good adsorption. When simulating chip marking information, this material can ensure that the characters and patterns engraved by laser or printed by ink are clear and durable, avoiding marking blurring or falling off due to material problems, and ensuring the effective verification of the automatic optical machine's detection function of the marking information.

[0095] In summary, the verification unit is designed to improve the simulation accuracy of each component for the real packaged chip from the material properties and appearance consistency. Compared with traditional verification units, it enhances the authenticity of the test scene through targeted material selection and appearance design, effectively improves the accuracy and reliability of the automatic optical machine function verification, reduces the detection errors caused by defects in the verification unit itself, and improves the durability of the verification unit, reduces the cost of semiconductor testing, improves production efficiency and product quality.

[0096] In yet another embodiment provided by the present disclosure, the surface of the copper simulation component is provided with a protective coating, and the protective coating is a material with high hardness, strong wear resistance and good chemical stability.

[0097] In the embodiments of the present disclosure, a copper simulation component is used to simulate the substrate defect caused by the breakage of the chip package substrate, which exposes the internal copper layer. In order to ensure the stable performance and accurate simulation effect of the component in multiple tests, a protective coating is arranged on the surface of the component, and the protective coating is made of a material with high hardness, strong wear resistance and good chemical stability.

[0098] In an actual detection scenario, the defect verification unit is placed on a product tray. On the one hand, the device picks up the defect verification unit by suction, and in this process, the surface of the defect verification unit is worn. On the other hand, the friction between the defect verification unit and the product tray caused by slight shaking during transmission also causes continuous wear of the components. Under the action of multiple frictions, the copper simulation component is prone to surface damage, which affects the detection accuracy. Taking a mobile phone chip production line as an example, the device needs to detect and verify the defect verification unit multiple times a day. If the component does not take strengthening measures, repeated friction wear will cause the surface structure to fail, eventually causing the detection result of the substrate breakage defect to deviate, and affecting the verification effect of the automatic optical machine function.

[0099] The use of high-strength copper simulation components can effectively solve the above problems. Such components, with high hardness and wear resistance of the material itself, can resist friction wear during picking, placing and transmission. Taking a silicon nitride coating as an example, its hardness can reach Mohs hardness 7-8, which can greatly reduce the wear and oxidation of the copper simulation component of the defect verification unit during multiple uses, and prolong the service life of the component. The good chemical stability ensures that the protective coating is not easily chemically reacted with other substances in a complex test environment. For example, a polytetrafluoroethylene coating can resist the erosion of common chemical reagents, avoid the change of the surface morphology of the copper simulation component caused by chemical corrosion, and ensure that it can continuously and stably simulate the defect of the exposed copper layer after the breakage of the substrate.

[0100] The implementation of the protective coating can form a uniform and dense coating on the surface of the copper simulation component through a physical vapor deposition (PVD) or a chemical vapor deposition (CVD) process. The PVD process can accurately control the thickness of the coating, and is suitable for simulation components with high precision requirements; the CVD process can make the coating tightly combined with the surface of the component, and enhance the adhesion of the coating.

[0101] In the embodiments of the present disclosure, the problem of performance degradation or damage of the copper simulation assembly due to frequent use is solved by adding a special protective coating to the copper simulation assembly. Compared with the traditional simulation assembly without the protective coating, the durability and stability of the copper simulation assembly are significantly improved, ensuring that it can accurately simulate the substrate defect in a long time and high frequency semiconductor test, effectively improving the reliability of the automatic optical machine for substrate damage defect detection function verification. Reducing the cost increase and production waste caused by frequent replacement of simulation assemblies, while providing a more stable and accurate test benchmark for semiconductor product quality detection, ensuring effective control of substrate defects in the production process, and improving overall production efficiency and product quality.

[0102] Based on the same disclosure concept, the embodiments of the present disclosure also provide a verification system. Since the principle of the problem solved by the system is similar to the above-mentioned verification unit, the implementation of the verification system can refer to the implementation of the above-mentioned verification unit, and the repeated parts will not be described again.

[0103] According to the above-mentioned verification unit Figure 1 According to the above-mentioned verification unit Figure 6 According to the above-mentioned verification unit

[0104] The product unit detection machine is used to detect the product unit or the verification unit 601 by using the optical machine installed thereon, and send the detection data to the processor 603;

[0105] The processor 603 is used to analyze and process the detection data of the optical machine, determine the detection result of whether the function of the optical machine is normal, and synchronize the detection result to the product unit detection machine 602;

[0106] The product unit detection machine 602 is also used to display the received detection result.

[0107] The verification system provided by the embodiments of the present disclosure is composed of the verification unit 601, the product unit detection machine 602 and the processor 603, and is designed to build a standardized and automated detection verification process.

[0108] The verification unit 601 includes a standard verification unit and a defective verification unit, which can simulate normal packaged chips and various defect states. The standard verification unit is used to calibrate the detection function of the optical machine on normal products, and the defective verification unit is used to test the recognition ability of the machine on various defects. Taking a smart phone chip production line as an example, before production, the standard verification unit is used to detect the recognition accuracy of the optical machine on the chip pins, marking information and other conventional characteristics, and then the defective verification unit is used to test the detection ability of the machine on pin size abnormalities, missing marking characters and other defects.

[0109] The product unit detection machine 602 is equipped with an optical machine and undertakes actual detection tasks. The optical machine detects the product unit or the verification unit 601 through image acquisition and analysis technology, and transmits the acquired detection data such as image information and size parameters to the processor 603 in real time. Different types of product unit detection machines 602 can adapt to chips of different packaging forms, such as a detection machine for ball grid array (BGA) packaged chips. The lens parameters and scanning methods of the optical machine are designed specifically to achieve accurate detection.

[0110] The processor 603 is the core of the system, which receives the detection data transmitted by the detection machine, and analyzes and processes the data according to the preset detection standard and algorithm. For example, by comparing the standard parameters of the verification unit 601 with the detection data, it is judged whether the detection of the optical machine on normal chips is accurate; the detection data of the defective verification unit is analyzed to evaluate the recognition ability of the machine on various defects, so as to determine the detection result of whether the function of the optical machine is normal, and the result is synchronized to the product unit detection machine 602.

[0111] After receiving the detection result, the product unit detection machine 602 presents it visually through the display screen. The operator can intuitively obtain the functional state information of the optical machine. If the detection result shows that the machine function is normal, the production can be started; if there is an abnormality, the optical machine can be debugged or repaired in time.

[0112] The verification system provided by the disclosure combines the verification unit 601, the detection machine and the processor 603 to form an automatic and intelligent verification process. Compared with the traditional verification method relying on manual judgment, this system significantly improves the efficiency and accuracy of the detection function verification of the optical machine through standardized verification unit 601 and automatic data processing and analysis, reduces the risk of misjudgment caused by human factors. At the same time, the visualization function of the detection result of the system is convenient for production management, effectively guarantees the reliability of the optical detection link in the semiconductor production process, reduces the product defect rate caused by abnormal detection function of the equipment, and improves the overall production efficiency.

[0113] In yet another embodiment of the present disclosure, the product unit detection machine 602 further comprises an NFC module for obtaining information of the NFC badge, determining the verification personnel ID and synchronizing to the processor 603.

[0114] The processor 603 is configured to aggregate the detection data of the day, the verification personnel ID, the built-in device information and the time information to generate report data, and send the report data at a preset time.

[0115] In the embodiment of the present disclosure, the NFC module of the product unit detection machine 602 reads the information of the NFC badge through near field communication technology. In actual application of a semiconductor factory, before the verification personnel performs a detection task, the verification personnel needs to use the carried NFC badge to approach the NFC module of the detection machine. The module quickly analyzes the electronic information stored in the badge, accurately identifies the verification personnel ID, and synchronizes the information to the processor 603 in real time. For example, in a certain large chip manufacturing workshop, different shifts of verification personnel hold exclusive NFC badges. After the verification personnel of the A staff completes the identity verification using the NFC badge, the ID information is immediately transmitted to the processor 603, and the identity of the performer of this verification operation is clear.

[0116] After receiving the verification personnel ID information transmitted by the NFC module, the processor 603 integrates and analyzes the detection data sent by the detection machine on the same day, the built-in device information (such as device model, number, etc.), and the time information recorded automatically by the system. Through a preset data processing algorithm, various types of information are aggregated in a specific format to generate report data containing detection results, operators, device states and time nodes, and other key elements.

[0117] In addition, the processor 603 also has a timing task function, which can automatically send report data according to a preset time (such as before work every day, at a fixed time every week, etc.). These data can be transmitted to the factory management system database or the terminal of the designated management personnel, so that the management personnel can timely master the verification situation of the optical machine detection function and make production decisions and process optimization.

[0118] In the embodiment of the present disclosure, the NFC identity recognition technology is integrated into the verification system, and a systematic data reporting mechanism is constructed. Through the NFC module, the automatic identification and recording of the verification personnel identity are realized, the traditional manual registration mode is replaced, the information recording errors are reduced, and the verification process standardization is improved. The integration and analysis of multi-dimensional data by the processor 603 and the timing reporting function make the information of personnel operation, device state, time node and other information in the verification process form a complete data chain, which significantly enhances the traceability and management efficiency of the verification process. Compared with the traditional verification system, this scheme provides more comprehensive and accurate data support for quality control and process optimization in semiconductor production, effectively reduces the management cost, and improves the transparency and reliability of the production process.

[0119] In yet another embodiment provided by the present disclosure, the system further comprises a cloud platform;

[0120] a processor 603, configured to synchronize the detection result to the cloud platform;

[0121] the cloud platform, configured to receive the detection result sent by the processor 603 and generate a log.

[0122] In the embodiment of the present disclosure, the processor 603 serves as a data transmission node. After completing the analysis and processing of the optical machine detection data and determining the detection result, the processor 603 synchronizes the detection result to the cloud platform through a wired network or a wireless network. In a large-scale semiconductor production scenario, a product unit detection machine 602 of multiple production lines generates a large amount of detection data every day. The processor 603 uploads the data in real time after preliminary processing. For example, a chip manufacturing enterprise's production line completes hundreds of detections on standard verification units and defective verification units every hour. The processor 603 quickly transmits the detection result (such as whether the optical machine function is normal, defect identification, etc.) to the cloud platform each time to ensure that the data is timely archived.

[0123] The cloud platform undertakes the functions of data receiving, storage and log generation. Through distributed storage technology, the cloud platform can safely and stably store a large amount of detection result data, avoiding data loss due to local storage device failure. At the same time, the cloud platform analyzes and classifies the received detection result according to the preset rules, and automatically generates a log file containing information such as time stamp, device number, detection result details, etc. For example, the cloud platform classifies and stores the detection result according to dimensions such as production line, date, device type, etc., and generates corresponding logs, facilitating subsequent query and analysis.

[0124] In actual application, the detection result log stored by the cloud platform can serve the collaborative work of multiple departments. The quality control department can analyze the long-term detection performance trend of the optical machine by calling the log, and optimize the detection parameters; the research and development department can refer to the historical detection data to improve the design of the verification unit 601; and the management layer can make production scheduling and resource allocation decisions based on the detection data of the whole production line summarized by the cloud platform.

[0125] The verification system provided by the present disclosure builds a cloud-based data management architecture, breaking the limitation of traditional local storage data island. Through the data interaction between the processor 603 and the cloud platform, centralized storage and real-time sharing of the detection result are realized, significantly improving the availability and traceability of the data. Compared with the verification system without the cloud platform, this scheme not only reduces the data management cost of the enterprise, but also provides data support for the whole production process through the log generation function, helps the enterprise to realize intelligent production management, improves the efficiency and quality control level of semiconductor test verification, and provides data guarantee for continuous optimization of product quality.

[0126] Embodiment 1

[0127] For the convenience of understanding, a complete working logic of the verification system is provided as follows. Figure 7 As shown in the working flow of the verification system, when the operator performs setup (i.e., verifies the function of the optical machine on the product unit detection machine 602 by using the verification unit 601), a good verification unit and a reject verification unit are selected. All components (such as the ball simulation component, the alloy sheet simulation component, etc.) of the good verification unit are in a normal state, and are used to calibrate the optical machine. If the optical machine identifies it as a bad unit and sends it to the corresponding channel, it is determined as "machine overkill", and the equipment parameters need to be adjusted. The reject verification unit includes ball defects, pad defects, substrate defects, character defects, two-dimensional code defects, etc., and is used to test the bad recognition ability of the optical machine. If no defect is detected or all defects are not detected, it is determined as "machine underkill", and the machine needs to be debugged.

[0128] After the verification unit 601 is run, the processor 603 in the system automatically reads and analyzes the test data, combines the detection results of each component (such as the ball simulation component, the pin simulation component, the character simulation component, etc.) of the verification unit 601, and analyzes the sub-items and total results of the standard verification unit and the bad verification unit as shown in Table 1 below: when all sub-items meet the standard, the total result is determined as Pass, and the system pushes a prompt box to the operator, and the machine can be put into normal product detection. At the same time, the processor 603 synchronizes the detection results to the cloud platform to generate traceable detection logs for subsequent data query and analysis.

[0129] Table 1 Detection result table

[0130]

[0131] At 12 o'clock every day, the system collects the detection data of each machine (including the test results of the verification unit 601, the verification personnel ID associated information, etc.) according to the preset rules, automatically generates a report as shown in Table 2 below, and sends it to the supervisor in the form of an email to assist production management decision-making and realize standardized and data-based closed-loop management of the verification process.

[0132] Table 2 Report data table

[0133] Date Shift Verifier Machine Setup Result 4-Jan D Zhang San Machine A Pass 4-Jan D Zhang San Machine B Pass 4-Jan D Zhang San Machine C Pass 4-Jan D Zhang San Machine D Pass 4-Jan D Zhang San Machine E Pass 4-Jan D Zhang San Machine F Pass

[0134] The process relies on the accurate simulation of the verification unit 601 and the cooperative operation of the verification system. Through the "Good+Reject" double verification unit calibration equipment, system automatic accountability, data cloud tracking and regular reporting, a complete management system from equipment calibration to data management is built, which not only guarantees the detection accuracy of optical machines, but also provides support for production process optimization and quality traceability through data sedimentation and analysis, and strengthens the reliability and manageability of the semiconductor test link.

[0135] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments of the disclosure can be implemented by hardware, or by means of software and necessary general hardware platforms. Based on such understanding, the technical solutions of the embodiments of the disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.), and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments of the disclosure.

[0136] Those skilled in the art can understand that the drawings are only schematic of a preferred embodiment, and the modules or processes in the drawings are not necessarily required for implementing the disclosure.

[0137] Those skilled in the art can understand that the devices in the system in the embodiments can be distributed in the system according to the description of the embodiments, or can be changed and located in one or more systems different from the embodiments. The devices in the above embodiments can be combined into one device, or can be further split into multiple sub-devices.

[0138] The above sequence numbers of the embodiments of the disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0139] Obviously, those skilled in the art can make various modifications and changes to the disclosure without departing from the spirit and scope of the disclosure. Therefore, if these modifications and changes of the disclosure belong to the scope of the claims of the disclosure and their equivalent technologies, the disclosure also intends to include these modifications and changes.

Claims

1. A verification unit, characterized in that, include: Intermediate layer, pin simulation components, and marking components; The intermediate layer is used to support the overall structure and provide an attachment platform for each component; The pin simulation component is disposed on the lower surface of the intermediate layer and is used to simulate the pins of the packaged chip. The marking component is disposed on the upper surface of the intermediate layer and is used to simulate the marking information on the packaged chip.

2. The verification unit as described in claim 1, characterized in that, The pin simulation component includes: Sphere simulation components are used to simulate spherical pins of spherical alloy chips packaged via a ball grid array; and / or Alloy sheet emulation components are used to simulate metal contact pins through a planar grid array package of sheet alloy emulation chips.

3. The verification unit as described in claim 2, characterized in that, The verification unit includes a defect verification unit; The sphere simulation component is used to reduce the size of any spherical alloy in the sphere simulation component when simulating spherical pin defects. The alloy sheet simulation assembly is used to create a recess on any sheet of alloy in the alloy sheet simulation assembly when simulating a metal contact failure. The marking component is used to set a marking pattern containing missing characters on the marking component when there is a problem with the simulated character type; The marking component is used to set a marking pattern on the component to indicate the presence of a missing QR code when a simulated QR code is defective.

4. The verification unit as described in claim 3, characterized in that, The defect verification unit also includes a copper simulation component disposed on the lower surface of the intermediate layer, used to simulate substrate defects caused by substrate damage to the packaged chip, resulting in exposure of the internal copper layer.

5. The verification unit as described in claim 1, characterized in that, The verification unit includes a standard verification unit; The standard verification unit is used to simulate a normal packaged chip.

6. The verification unit as described in claim 2, characterized in that, The intermediate layer is made of a corrosion-resistant material with high mechanical strength; and / or The color of the intermediate layer is the same as the substrate color of the product unit; and / or The color and shape of the sphere simulation component are consistent with the color and shape of the spherical pins after the chip is packaged with a ball grid array, and it is made of a material with high strength, high wear resistance and good processing adaptability. and / or The color and shape of the alloy sheet simulating the component are consistent with the color and shape of the metal contacts after the chip is packaged by a planar grid array, and the material has good processing performance and colorability; and / or The marking component is made of a material that facilitates marking.

7. The verification unit as described in claim 4, characterized in that, The surface of the copper simulation component is provided with a protective coating, which is made of a material with high hardness, strong wear resistance and good chemical stability.

8. A verification system, characterized in that, Includes a verification unit as described in any one of claims 1 to 7, at least one product unit testing machine, and a processor; The product unit testing machine is used to test the product unit or the verification unit using the optical machine installed thereon, and to send the test data to the processor. The processor is used to analyze and process the detection data of the optical machine, determine the detection result of whether the optical machine is functioning normally, and synchronize the detection result to the product unit testing machine. The product unit testing machine is also used to display the received testing results.

9. The system as described in claim 8, characterized in that, The product unit testing machine also includes an NFC module for acquiring NFC employee ID information, determining the employee number of the verification personnel, and synchronizing it to the processor. The processor is used to summarize the daily detection data, verify the employee's ID number, the built-in device information and time information, analyze and generate report data, and send out the report data at a preset time.

10. The system as described in claim 8, characterized in that, The system also includes: a cloud platform; The processor is used to synchronize the detection results to the cloud platform; The cloud platform is used to receive the detection results sent by the processor and generate logs.

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