Parallel redundant storage method and electronic device

Abstract

The application discloses a parallel redundant storage method and electronic equipment, and relates to the technical field of computers, and comprises the following steps: obtaining a target volume identifier, a starting address and a data length by analyzing a data storage instruction, selecting a to-be-stored memory page number from an idle memory page based on bitmap information of a first controller, determining a first physical address of the first controller and a second physical address of a second controller mapped by the first controller according to the to-be-stored memory page number, determining a first data channel according to the first physical address, and determining a second data channel according to the second physical address, storing to-be-stored data to the first controller through the first data channel, and storing the to-be-stored data to the second controller through the second data channel. Therefore, the problem that a long response time and low storage efficiency are caused by multiple data copying during redundant backup is solved, and the storage efficiency is improved by realizing synchronous writing of the memory of the master controller and the backup controller through parallel channels.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to a parallel redundant storage method and electronic device. Background Technology

[0002] To prevent business interruption and data loss due to single point of failure, dual-controller storage architecture is widely used. In this architecture, a primary controller typically handles all I / O (Input / Output) requests, while a backup controller synchronizes the status of the primary controller in real time so that it can seamlessly take over the service in the event of a primary controller failure, thereby ensuring business continuity.

[0003] In related technologies, when the main controller receives write data, it needs to store the write data and then send it to the redundant controller after storage. After the redundant controller completes storage, it notifies the main controller, which then completes the data reception response.

[0004] However, the main controller must perform an additional network transmission operation to synchronize the data after processing the local write I / O. This not only increases write latency but also consumes internal network bandwidth, resulting in long response times and low storage efficiency. Summary of the Invention

[0005] This invention provides a parallel redundant storage method and electronic device to at least solve the problem of long response time and low storage efficiency caused by multiple data copies during redundant backup. The parallel channel of this application realizes synchronous writing of the memory of the primary and backup controllers, avoiding the overhead of secondary data transmission, thereby ensuring high reliability and significantly improving write performance.

[0006] This invention provides a parallel redundant storage method, comprising the following steps:

[0007] Determine if a data storage instruction has been received;

[0008] If the data storage instruction is received, the storage instruction is parsed to obtain the destination volume identifier, starting address and data length. The required number of memory pages is determined based on the destination volume identifier, the starting address and the data length. Based on the number of memory pages, the memory page number to be stored is selected from the free memory pages based on the bitmap information of the first controller. The bitmap information of the first controller is used to manage the cache area of ​​the first controller and the cache area of ​​the second controller.

[0009] The first physical address of the first controller and the second physical address of the second controller mapped on the first controller are determined based on the memory page number to be stored.

[0010] A first data channel is determined based on the first physical address, and a second data channel is determined based on the second physical address. The data to be stored is stored in the first controller through the first data channel, and the data to be stored is stored in the second controller through the second data channel.

[0011] The present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the parallel redundant storage method as described in the above embodiments.

[0012] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described parallel redundant storage methods.

[0013] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the above-described parallel redundant storage method steps.

[0014] This invention determines whether a data storage instruction from a server has been received. If so, it determines the memory page number to be stored based on the instruction, and then determines the first physical address of the first controller and the second physical address of the second controller mapped to the first controller based on the memory page number. A first data channel is determined based on the first physical address, and a second data channel is determined based on the second physical address. The data to be stored sent by the server is stored to the first controller via the first data channel, and then stored to the second controller via the second data channel. This solves the problem of long response times and low storage efficiency caused by multiple data copies during data redundancy backup. This application improves storage efficiency by implementing synchronous writing of the primary and backup controller memory through parallel channels. Attached Figure Description

[0015] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of redundant storage for dual controllers;

[0017] Figure 2 A flowchart of a parallel redundant storage method provided in an embodiment of the present invention;

[0018] Figure 3A schematic diagram illustrating the principle of a parallel redundant storage method provided in one embodiment of the present invention;

[0019] Figure 4 A schematic diagram of a storage system provided in one embodiment of the present invention;

[0020] Figure 5 A schematic diagram illustrating the principle of data transmission provided in one embodiment of the present invention;

[0021] Figure 6 A block diagram of a parallel redundant storage device provided in an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0024] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0025] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Before introducing the parallel redundant storage method of this application, let's first introduce the redundant storage technology.

[0027] like Figure 1As shown, the storage controller is mainly used for managing the hard drives and the data stored on them at the storage end, while also providing data access services to the server. During the data access (IO) process to the server, to ensure data security, it typically uses services from business modules such as CA (Certificate Authority), CACHE POOL, RAID (Redundant Array of Independent Disks), and multiple disks. Storage devices generally consist of two controllers: one connected to the server at the front end via technologies such as FC (Fibre Channel) and RDMA (Remote Direct Memory Access), and the other connected to the disk at the back end via technologies such as SAS (Serial Attached SCSI) and NVME (Non-Volatile Memory Express), forming a redundant system.

[0028] When an application on the server generates a write I / O request, the request is first sent to one of the controllers on the storage device, such as controller A, via a front-end card (FC). Controller A recognizes the write request and then receives the data. Figure 1 Step 1: After receiving the data, it does not immediately send a write I / O request completion response to the host. Instead, it sends the write request data to controller B via the internal network of the storage device, i.e., the external cards A and B between storage controllers A and B, as a backup redundancy. Figure 1 Step 2 in the process, and then a response indicating that the write I / O request is complete is sent to the host, such as Figure 1 Step 3 in the process ensures that if controller A fails, the host can retrieve the previously stored data from controller B. The received cached data is then asynchronously written to the backend disk later, such as... Figure 1 As shown in step 4 of the document.

[0029] As can be seen from the data flow above, data is first transmitted from the server to the cache of controller A. After controller A completes the data reception and processing, it synchronizes the data to controller B, achieving redundant backup of the data in the storage system. Controller B notifies controller A after receiving the data, and then controller A sends a data reception completion response to the server. This process involves multiple data copies, and controller B's reception process waits for controller A's reception process to complete before it can be executed, slowing down the response time to the server.

[0030] The embodiments of the present invention provide a parallel redundant storage method, and the method is described in detail in conjunction with the execution flow of the parallel redundant storage method.

[0031] Specifically, Figure 2 This is a flowchart illustrating a parallel redundant storage method provided in an embodiment of the present invention.

[0032] like Figure 2 As shown, the parallel redundant storage method includes the following steps:

[0033] In step S101, it is determined whether a data storage instruction has been received.

[0034] Among them, data storage instructions refer to commands initiated by the server to the storage system to request the writing or updating of data, and typically include information such as the destination volume identifier, the starting logical address, and the data length.

[0035] Specifically, under normal operating conditions, the first controller continuously listens to the front-end interface and detects data storage instructions from the server through hardware interrupts or polling mechanisms to confirm whether there are any new I / O requests that need to be processed.

[0036] This ensures that the controller can respond to host requests in a timely manner, which is the fundamental guarantee for achieving efficient data access and system real-time performance.

[0037] According to one embodiment of the present invention, before determining whether a data storage instruction sent by a server has been received, the method includes: determining a target page number of memory from the memory of a first controller as a cache area of ​​the first controller, and determining a target page number of memory from the memory of a second controller as a cache area of ​​the second controller, wherein the cache area of ​​the second controller is mapped to the cache area of ​​the first controller based on a preset data transmission protocol.

[0038] It should be said that, as Figure 3 As shown, the parallel redundant storage method of the present invention is applied to a storage system. The storage system is connected to a server via an external card. The storage system includes a first controller, such as controller A, and a second controller, such as controller B. Before performing parallel redundant storage, the storage system needs to be initialized.

[0039] During the initialization phase, both controllers of the storage system need to prepare two copies of memory for subsequent use in receiving data written from the server. For example... Figure 4 As shown, the process of controller A receiving data from the server is illustrated as an example (the process of controller B receiving data from the server is exactly the same and will not be described in detail).

[0040] (1) Controller A requests a block of memory with contiguous addresses from the operating system in units of pages. The size can be adjusted according to the storage platform. Here, the example is 8GB. It is used as a local data cache. The metadata management module records the usage of cached pages in the form of a bitmap. It is in use during initialization, so the bitmap is in the all-zero state.

[0041] (2) Controller B requests a block of memory with contiguous addresses from the operating system in units of pages. The size can be adjusted according to the storage platform. Here, the example is 8GB. It needs to be consistent with the amount of memory requested by controller A. As a backup cache, it needs to be mapped to controller A through the CXL (Compute Express Link Protocol).

[0042] (3) In this embodiment of the invention, the backup cache memory area (such as the physical address range 0x4000000000-0xC000000000) prepared by the controller B is marked as shareable and registered to the CXL protocol stack by the CXL controller (such as the CXL port integrated with the CPU (Central Processing Unit) or the independent CXL switch).

[0043] (4) The CXL driver of controller A node detects the shared memory of controller B node through the CXL link and requests memory mapping permission (read / write permission) from controller B node.

[0044] (5) The CXL controller of node A maps the physical address of node B to the local "virtual physical address" of node A (such as 0x34000000000-0x3C000000000) and writes it into the address translation table of node A's IOMMU (Input / Output Memory Management Unit) to ensure that peripherals (such as FC cards) can access the memory of node B through this address.

[0045] In addition, embodiments of the present invention also require initialization of external cards (such as FC cards).

[0046] (1) FC Card Selection: The FC card must support data distribution logic and multiple DMA (Direct Memory Access Channel) channels, such as... Figure 5 As shown.

[0047] (2) The memory address range (0x34000000000-0x3C000000000) mapped by the above CXL is written into the DMA address whitelist of the FC card, allowing the FC card hardware to directly access the area.

[0048] Furthermore, embodiments of the present invention also require metadata management. Both local cache and CXL mapped cache need to be strictly managed using metadata.

[0049] (1) Local cache and CXL mapped cache are memory blocks with contiguous addresses and the same size requested from the operating system at the page granularity. Cache management is at the page granularity.

[0050] (2) The local cache and the CXL mapping cache are granular and a one-to-one correspondence is established according to the physical address from smallest to largest. That is, the local cache pages 1, 5 and 7 are used, and the CXL mapping cache pages 1, 5 and 7 are used at the same time.

[0051] (3) Both requesting and releasing memory in the cache need to be done through the metadata management module.

[0052] According to one embodiment of the present invention, before receiving a storage instruction from the server, the method includes: initializing bitmap information of a first controller, updating the state of all memory pages in the first controller to an idle state, and updating the state of all memory pages in a second controller to an idle state.

[0053] The bitmap information is used to record the usage status of cached memory pages in the storage controller; for example, a bitmap.

[0054] Specifically, during system startup or initialization, the first and second controllers respectively clear the status of their locally managed cache memory and uniformly set the status of all memory pages in the first controller's bitmap to idle, preparing for subsequent memory allocation. In summary, the memory of the two controllers in this embodiment can be managed using a single mask. That is, when host data arrives and requests memory, only the memory usage of the first controller needs to be known to determine the memory usage of both controllers, reducing bitmap usage and eliminating the need to request memory from the backup controller through inter-controller interaction, ultimately improving data management efficiency.

[0055] Therefore, by performing the initialization steps, the state of all memory pages of both controllers is uniformly reset to "free," clearing any historical state remnants and ensuring that the two controllers have a completely consistent and accurate view of memory resources at startup. This consistency is the foundation for the collaborative work of the two controllers, guaranteeing the accuracy and security of subsequent memory allocation and fundamentally eliminating allocation failures or data errors caused by state chaos.

[0056] In step S102, if a data storage instruction is received, the storage instruction is parsed to obtain the destination volume identifier, starting address, and data length. The required number of memory pages is determined based on the destination volume identifier, starting address, and data length. Based on the number of memory pages, the memory page number to be stored is selected from the free memory pages according to the bitmap information of the first controller. The bitmap information of the first controller is used to manage the cache area of ​​the first controller and the cache area of ​​the second controller.

[0057] The destination volume identifier specifies the logical storage unit to which the data belongs, the starting address (usually LBA (Logical Block Addressing)) indicates the logical location of the data within the volume, and the data length refers to the amount of data in this write operation.

[0058] Specifically, upon receiving a data storage instruction, the first controller first parses the instruction to obtain the destination volume identifier, starting address, and data length. Based on the data length and the preset memory page size (e.g., 4KB (Kibibytes)), it calculates the required number of memory pages. Subsequently, it uses the bitmap information of the first controller to search for contiguous or non-contiguous free memory pages and selects pages that meet the quantity requirements to determine the memory page number to be stored in this write operation. It should be noted that the bitmap information of the first controller not only manages the first controller's own cache area but also uniformly manages the cache area of ​​the second controller, realizing a centralized view and collaborative allocation of cache resources between the two controllers.

[0059] Therefore, by parsing storage instructions to obtain the destination volume identifier, starting address, and data length, the system can accurately understand the context and resource requirements of this write operation. The data length, combined with the preset memory page size, can accurately calculate the number of memory pages required for allocation, avoiding over-allocation or under-allocation. This achieves precise allocation on demand, enabling efficient and orderly allocation of cache resources and improving system resource utilization and processing efficiency.

[0060] According to one embodiment of the present invention, after selecting the memory page number to be stored from the free memory pages based on the bitmap information of the first controller according to the number of memory pages, the method further includes: packaging the destination volume identifier, starting address, data length and the memory page to be stored into data record information; storing the data record information in the first controller, and sending the data record information to the second controller.

[0061] The data record information includes structured information on key metadata for write I / O operations, typically including the destination volume identifier, starting address, data length, and memory page number to be stored, which is used to record the logical location of the data and its mapping relationship with physical storage.

[0062] Specifically, after determining the memory page number to be stored, the first controller encapsulates the metadata of this write operation (destination volume identifier, starting address, data length) and the allocated memory page number into a data record and stores it in the local metadata area. At the same time, it sends this information to the second controller through the inter-controller communication link to ensure that the backup controller has the same data mapping relationship.

[0063] In actual execution, controller A requests two page pages of memory from the metadata management module. The metadata management module finds two free page pages through a bitmap, assuming the page numbers are 3 and 5. It records the destination volume ID (Identifier), starting address lba (Logical Block Addressing), data length, and the page numbers 3 and 5 as a message on its own end, and simultaneously sends this message to controller B for recording.

[0064] In step S103, the first physical address of the first controller and the second physical address of the second controller mapped to the first controller are determined according to the memory page number to be stored.

[0065] The memory page number to be stored refers to the memory page number allocated in the cache for this write IO data, which is used to identify the storage location of the data in the controller's memory; the first physical address is the actual address of the first controller's local DRAM corresponding to the memory page number to be stored; the second physical address is the virtual physical address formed by mapping the memory space of the second controller to the address space of the first controller through memory mapping technologies such as CXL.

[0066] Specifically, upon receiving a data storage instruction, the metadata management module of the first controller parses the destination volume, LBA, and data length in the instruction, calculates the required number of memory pages, and allocates the memory page number to be stored based on the bitmap information of the local free pages. Subsequently, the system determines the physical address of the page number on the first controller (the first physical address) and its corresponding physical address in the memory of the second controller, which has been mapped to the local address space (the second physical address), according to a preset address mapping rule. For example, when the server sends a write SCSI (SCSI Commands, Small Computer System Interface) command to the storage system, the first controller parses the storage instruction and obtains the destination volume ID, starting address LBA, and data length, such as 8KB = 2 * page.

[0067] This enables unified planning and addressing of the memory locations of the primary and backup controllers, laying the foundation for subsequent parallel writing via dual channels and ensuring the efficiency and determinism of the data redundancy process.

[0068] According to one embodiment of the present invention, determining the first physical address of the first controller and the second physical address mapped by the second controller in the first controller based on the memory page number to be stored includes: establishing a mapping address corresponding to the memory of the first controller and the second controller based on a preset data transmission protocol; determining the third physical address of the second controller, and determining the second physical address mapped by the second controller in the first controller based on the mapping address and the third physical address.

[0069] The third physical address refers to the actual hardware address of the memory to be stored in the local DRAM of the second controller.

[0070] Specifically, during the system initialization phase, the first controller establishes a mapping relationship with the memory of the second controller through a preset data transmission protocol (such as CXL.mem); after determining the page number of the memory to be stored, the system calculates its third physical address based on the physical layout of the page number in the second controller, and uses the established mapping relationship to convert the address into a second physical address that can be directly addressed on the first controller side.

[0071] This enables efficient and orderly allocation of cache resources, improving system resource utilization and processing efficiency.

[0072] In step S104, a first data channel is determined based on a first physical address, and a second data channel is determined based on a second physical address. The data to be stored is stored in the first controller through the first data channel, and in the second controller through the second data channel.

[0073] Among them, the first data channel and the second data channel refer to two independent DMA (direct memory access) channels in the front-end interface (such as FC card) that support parallel transmission, which are used to write data directly to the specified physical address.

[0074] Specifically, after determining the first physical address and the second physical address, the system assigns the first physical address to the first data channel and the second physical address to the second data channel. When the server sends data to be stored, the front-end interface works simultaneously through these two DMA channels to write the same data into the local memory of the first controller and the mapped memory of the second controller, respectively.

[0075] In actual execution, controller A configures the local cache physical addresses of page numbers 3 and 5 as memory block A to FC card DMA channel 1, and configures the CXL mapped cache physical addresses of page numbers 3 and 5 as memory block B to FC card DMA channel 2. Figure 5 As shown.

[0076] Controller A notifies the server that it can send data response. The host sends data to the storage system through the FC card. The storage-side FC card directly stores the data into the local cache of controller A via DMA channel 1. The storage-side FC card forwards the data through DMA channel 2 and CXL, and synchronously stores the data into the cache of controller B. This achieves redundant backup of data between the two storage controllers. After the data is received, controller A sends a response to the host, completing the full life cycle of server write IO.

[0077] Therefore, the present invention can store data in the memory of both the main controller and the backup controller simultaneously in a single transmission, eliminating the need for the main controller to receive data before forwarding it, thus improving storage efficiency.

[0078] In summary, the data flow of this embodiment of the invention has undergone significant modifications compared to the original flow. After the FC card of the storage system controller A receives server data, it simultaneously DMAs the data to different memory locations via dual DMA channels. One is the local memory of controller A, and the other is the memory in the physical address space of controller B mapped to its local memory via the CXL protocol. When the FC card transmits data to this part of the memory via DMA channel 2, the CXL protocol automatically forwards this part of the data to the corresponding memory in controller B. In this way, the data path is freed from the multi-step copying process of "FC card to local memory of node A to memory of node B" in the traditional scheme, and the simultaneous reception of data by controllers A and B is achieved, changing from serial to parallel processing, reducing latency, and greatly improving the storage system's performance in handling server write I / O.

[0079] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller via the first data channel and storing the data to be stored to the second controller via the second data channel, the process includes: determining a first memory page to be updated based on the memory page number to be stored and the first physical address, according to the bitmap information of the first controller; determining a second memory page to be updated based on the memory page number to be stored and the second physical address, according to the bitmap information of the first controller; and updating the state of the first memory page to be updated and / or the state of the second memory page to be updated to a used state.

[0080] Among them, the memory page to be updated refers to the memory page whose status needs to be updated in the bitmap information after the data is written. The used status indicates that the memory page has been allocated for storing data and cannot be allocated again.

[0081] Specifically, after the data is written to the memory of the first controller and the second controller through dual channels, the system looks up the bitmap information of the first controller based on the allocated memory page number to be stored and the corresponding physical address, and determines the corresponding memory page as the first memory page to be updated; at the same time, based on the synchronized metadata, the system determines the corresponding second memory page to be updated in the bitmap information of the first controller; then, the status of these two memory pages in their respective bitmaps is updated from "free" to "used".

[0082] This ensures that both controllers can simultaneously mark the memory usage status, avoiding resource conflicts and maintaining consistent memory management, which is both safe and efficient.

[0083] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the method includes: determining whether the memory usage in the first controller exceeds a preset threshold; if the memory usage in the first controller exceeds the preset threshold, then writing the dirty data in the first controller to the target storage device.

[0084] Among them, memory usage refers to the proportion of memory space occupied in the first controller cache to the total cache space; dirty data refers to temporary data that has been written to the cache but has not yet been saved to the backend disk; the preset threshold is the upper limit of memory usage ratio set by the system to trigger data write to disk.

[0085] Specifically, after the data is written to the dual-controller memory in parallel, the system continuously monitors the cache usage of the first controller. When the system detects that the memory usage reaches or exceeds the preset threshold, it indicates that the cache space is tight. The system will start a background task to write the dirty data accumulated in the first controller to the target storage device (such as SSD (Solid State Drive) or HDD (Hard Disk Drive)) in batches to release the cache space.

[0086] Therefore, the embodiments of the present invention can promptly clear old data in the cache, avoid full memory load, ensure that the system always has space to process new requests, and guarantee the stability and response speed of operation.

[0087] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the method includes: determining whether the first controller is in a preset refresh cycle; if the first controller is in a preset refresh cycle, then writing the dirty data in the first controller to the target storage device.

[0088] The preset refresh cycle is a fixed time interval set by the system to periodically check and process dirty data in the cache.

[0089] Specifically, in this embodiment of the invention, not only can the cache be written to the target storage device by setting a dirty data threshold, but the writing can also be performed at a preset period. Specifically, after the data is written to the memory of the dual controllers, the system will start a timer to poll periodically; when it is detected that the current time is within the preset refresh period, the dirty data accumulated in the first controller will be written in batches to the target storage device in the backend.

[0090] Therefore, this embodiment of the invention ensures that data does not remain in the cache for too long and regularly saves the data safely to the disk, which not only prevents data loss due to unexpected power outages, but also makes the system run more smoothly.

[0091] According to one embodiment of the present invention, after writing dirty data in the first controller to the target storage device, the method includes: generating data synchronization information and sending the data synchronization information to the second controller, so that the second controller deletes the dirty data in the second controller based on the data synchronization information.

[0092] Among them, the data synchronization information is a notification message generated by the first controller after completing the data write-to-disk process, which includes metadata such as the memory page number corresponding to the data that has been written to disk.

[0093] Specifically, after the first controller successfully writes the dirty data in the cache to the backend disk, it generates a data synchronization message and sends it to the second controller. After receiving the message, the second controller marks the corresponding dirty data in its local cache as recyclable based on the page number information and releases the occupied state of the memory page.

[0094] In actual execution, when the memory usage in the local cache of the first controller reaches a certain threshold or is executed periodically over time, dirty data (i.e., received server write IO data) in the local cache of the first controller needs to be written to the backend permanent disk, such as an SSD. After the dirty data is written to disk, the metadata management module reclaims the memory occupied by the written dirty data and updates the bitmap. The metadata management module of the first controller sends the message record of the written dirty data to the second controller, requesting the second controller to reclaim the corresponding resources. The metadata management module of controller B reclaims memory, updates the bitmap, and deletes the corresponding message record based on the received message information. Then, the first controller deletes the message information.

[0095] Therefore, the embodiments of the present invention can keep the memory states of the first controller and the second controller synchronized. As soon as the first controller is written to disk, the second controller cleans up accordingly, avoiding memory waste and making efficient use of cache resources.

[0096] According to one embodiment of the present invention, the data synchronization information includes the memory page number to be reclaimed. After the second controller deletes dirty data in the second controller based on the data synchronization information, the method further includes: determining a third memory page to be updated based on the memory page number and the bitmap information of the first controller; and updating the status of the third memory page to be updated to an idle state.

[0097] Among them, the memory page number to be reclaimed refers to the number corresponding to the data that has been written to disk in the cache; the third memory page to be updated is the specific memory page located by the second controller in the local position map according to the page number; the idle state indicates that the memory page can be reallocated and used.

[0098] Specifically, after receiving the data synchronization information containing the memory page number, the second controller looks up the local bitmap information based on the page number, locates the corresponding third memory page to be updated, and updates its status from "used" to "idle".

[0099] Therefore, the embodiments of the present invention can accurately release the memory space that is no longer needed in the second controller, ensure that cache resources are reclaimed in a timely manner, avoid waste, and enable the system to continuously and efficiently process new data.

[0100] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller via the first data channel and storing the data to be stored to the second controller via the second data channel, the method includes: determining whether the first controller has failed; if the first controller has failed, determining whether the memory usage in the second controller exceeds a preset threshold; if the memory usage in the second controller exceeds the preset threshold, writing the dirty data in the second controller to the target storage device.

[0101] The preset threshold can be set by the user, obtained through a limited number of experiments, or obtained through a limited number of computer simulations; no specific limitation is made here.

[0102] Specifically, when the system detects a failure in the first controller, the second controller immediately takes over the work. After taking over, the second controller checks the usage of its own cache. If it finds that the memory usage exceeds a preset threshold, it will proactively write the dirty data in its cache to the backend disk.

[0103] This ensures that after the primary controller fails, the backup controller can independently manage memory and data disk storage, avoiding service interruption due to full cache and guaranteeing stable system operation after a failure.

[0104] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the method includes: determining whether the first controller has failed; if the first controller has failed, determining whether the second controller is in a preset refresh cycle; if the second controller is not in a preset refresh cycle, writing the dirty data in the second controller to the target storage device.

[0105] The preset refresh cycle is a fixed time interval set by the system, used to periodically perform data write-to-disk operations.

[0106] Specifically, after the first controller fails, the second controller takes over the system operation. After taking over, the second controller will determine whether to enter the refresh cycle according to the original timing mechanism. If it is in the refresh cycle, even if the memory is not full, it will write the dirty data in its own cache to the backend storage device in batches.

[0107] This ensures that even if the primary controller fails, the backup controller can still safely save the data to the disk on time, preventing data from remaining in the cache for too long and improving the data security of the system under abnormal conditions.

[0108] According to the parallel redundant storage method proposed in this embodiment of the invention, it is determined whether a data storage instruction sent by a server has been received. If a data storage instruction is received, the memory page number to be stored is determined according to the data storage instruction, and the first physical address of the first controller and the second physical address mapped by the second controller on the first controller are determined according to the memory page number to be stored. A first data channel is determined according to the first physical address, and a second data channel is determined according to the second physical address. The data to be stored sent by the server is stored to the first controller through the first data channel, and the data to be stored is stored to the second controller through the second data channel. This solves the problem of long response time and low storage efficiency caused by multiple data copies during data redundancy backup. This application improves storage efficiency by realizing synchronous writing of the memory of the primary and backup controllers through parallel channels.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0110] Embodiments of the present invention also provide a parallel redundant storage device.

[0111] Figure 6 This is a block diagram of a parallel redundant storage device according to an embodiment of the present invention.

[0112] like Figure 6As shown, the parallel redundant storage device 10 includes: a judgment module 100, a parsing module 200, a determination module 300, and a storage module 400.

[0113] The judgment module 100 is used to determine whether a data storage instruction has been received.

[0114] The parsing module 200 is used to parse the storage instruction to obtain the destination volume identifier, starting address and data length when a data storage instruction is received, determine the required number of memory pages based on the destination volume identifier, starting address and data length, and select the memory page number to be stored from the free memory pages based on the number of memory pages and the bitmap information of the first controller. The bitmap information of the first controller is used to manage the cache area of ​​the first controller and the cache area of ​​the second controller.

[0115] The determination module 300 is used to determine the first physical address of the first controller and the second physical address of the second controller mapped to the first controller based on the memory page number to be stored.

[0116] The storage module 400 is used to determine a first data channel based on a first physical address and a second data channel based on a second physical address, to store the data to be stored to a first controller through the first data channel, and to store the data to be stored to a second controller through the second data channel.

[0117] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the storage module 400 includes: a first determining unit, a second determining unit, and an updating unit.

[0118] The first determining unit is used to determine the first memory page to be updated based on the memory page number to be stored and the first physical address, according to the bitmap information of the first controller.

[0119] The second determining unit is used to determine the second memory page to be updated based on the memory page number to be stored and the second physical address, according to the bitmap information of the first controller.

[0120] The update unit is used to update the state of the first memory page to be updated and / or the state of the second memory page to be updated to the used state.

[0121] According to an embodiment of the present invention, before determining whether a data storage instruction has been received, the determination module 100 includes a third determining unit.

[0122] The third determining unit is used to determine the memory of the target page number from the memory of the first controller as the cache area of ​​the first controller, and to determine the memory of the target page number from the memory of the second controller as the cache area of ​​the second controller, wherein the cache area of ​​the second controller is mapped to the cache area of ​​the first controller based on a preset data transmission protocol.

[0123] According to one embodiment of the present invention, after selecting the memory page number to be stored from the free memory pages based on the bitmap information of the first controller according to the memory page number, the parsing module 200 further includes: a packing unit and a sending unit.

[0124] The packaging unit is used to package the destination volume identifier, starting address, data length, and memory pages to be stored into data record information.

[0125] The sending unit is used to store data recording information in the first controller and send the data recording information to the second controller.

[0126] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the storage module 400 includes: a first judgment unit and a first writing unit.

[0127] The first judgment unit determines whether the memory usage in the first controller exceeds a preset threshold.

[0128] The first write unit is used to write dirty data from the first controller to the target storage device when the memory usage in the first controller exceeds a preset threshold.

[0129] According to one embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the storage module 400 includes: a second judgment unit and a second writing unit.

[0130] The second judgment unit is used to determine whether the first controller is in a preset refresh cycle.

[0131] The second write unit is used to write dirty data from the first controller to the target storage device when the first controller is in a preset refresh cycle.

[0132] According to one embodiment of the present invention, after writing dirty data in the first controller to the target storage device, the method includes: a generation subunit.

[0133] The deletion subunit is used to generate data synchronization information and send the data synchronization information to the second controller, so that the second controller deletes dirty data in the second controller based on the data synchronization information.

[0134] According to one embodiment of the present invention, the data synchronization information includes the memory page number to be reclaimed. After the second controller deletes dirty data in the second controller based on the data synchronization information, the deletion subunit further includes: determining the subunit and updating the subunit.

[0135] The "determine sub-component" is used to determine the third memory page to be updated based on the memory page number and the bitmap information of the first controller.

[0136] The update sub-component is used to update the state of the third memory page to be updated to an idle state.

[0137] According to an embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the storage module 400 includes: a third judgment unit, a fourth judgment unit and a third writing unit.

[0138] The third judgment unit is used to determine whether the first controller has malfunctioned.

[0139] The fourth judgment unit is used to determine whether the memory usage in the second controller exceeds a preset threshold in the event of a failure of the first controller.

[0140] The third write unit is used to write dirty data from the second controller to the target storage device when the memory usage in the second controller exceeds a preset threshold.

[0141] According to an embodiment of the present invention, after storing the data to be stored sent by the server to the first controller through the first data channel and storing the data to be stored to the second controller through the second data channel, the storage module 400 includes: a fifth judgment unit, a sixth judgment unit and a fourth writing unit.

[0142] The fifth judgment unit is used to determine whether the first controller has malfunctioned.

[0143] The sixth judgment unit is used to determine whether the second controller is in a preset refresh cycle in the event of a failure of the first controller.

[0144] The fourth write unit is used to write dirty data in the second controller to the target storage device if the second controller is in a preset refresh cycle.

[0145] According to one embodiment of the present invention, the determining module 300 includes: an establishment unit and a mapping unit.

[0146] The establishment unit is used to establish the mapping address between the memory of the first controller and the memory of the second controller based on a preset data transmission protocol.

[0147] The mapping unit is used to determine the third physical address of the second controller, and based on the mapping address, determine the second physical address mapped by the second controller to the first controller.

[0148] According to one embodiment of the present invention, before receiving a storage instruction from the server, the determination module 100 includes an initialization unit.

[0149] The initialization unit is used to initialize the bitmap information of the first controller, update the state of all memory pages in the first controller to the free state, and update the state of all memory pages in the second controller to the free state.

[0150] In summary, the descriptions of the features in the embodiments corresponding to the parallel redundant storage device can be found in the relevant descriptions of the embodiments corresponding to the parallel redundant storage method, and will not be repeated here.

[0151] Embodiments of the present invention also provide an electronic device, which may include:

[0152] The memory 701, the processor 702, and the computer program stored on the memory 701 and executable on the processor 702.

[0153] When the processor 702 executes the program, it implements the parallel redundant storage method provided in the above embodiments.

[0154] Furthermore, electronic devices also include:

[0155] Communication interface 703 is used for communication between memory 701 and processor 702.

[0156] The memory 701 is used to store computer programs that can run on the processor 702.

[0157] The memory 701 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0158] If the memory 701, processor 702, and communication interface 703 are implemented independently, then the communication interface 703, memory 701, and processor 702 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized into address buses, data buses, control buses, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0159] Optionally, in a specific implementation, if the memory 701, processor 702, and communication interface 703 are integrated on a single chip, then the memory 701, processor 702, and communication interface 703 can communicate with each other through an internal interface.

[0160] The processor 702 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0161] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the parallel redundant storage method at runtime.

[0162] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0163] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the parallel redundant storage method.

[0164] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0165] The parallel redundant storage method provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A parallel redundant storage method, characterized in that, Includes the following steps: Determine if a data storage instruction has been received; If the data storage instruction is received, the storage instruction is parsed to obtain the destination volume identifier, starting address and data length. The required number of memory pages is determined based on the destination volume identifier, the starting address and the data length. Based on the number of memory pages, the memory page number to be stored is selected from the free memory pages based on the bitmap information of the first controller. The bitmap information of the first controller is used to manage the cache area of ​​the first controller and the cache area of ​​the second controller. The first physical address of the first controller and the second physical address of the second controller mapped on the first controller are determined based on the memory page number to be stored. A first data channel is determined based on the first physical address, and a second data channel is determined based on the second physical address. The data to be stored is stored in the first controller through the first data channel, and the data to be stored is stored in the second controller through the second data channel. Before determining whether the data storage instruction has been received, the process includes: determining a target number of pages in the memory of the first controller as a cache area of ​​the first controller, and determining a target number of pages in the memory of the second controller as a cache area of ​​the second controller, wherein the cache area of ​​the second controller is mapped to the cache area of ​​the first controller based on a preset data transmission protocol. The step of determining the first physical address of the first controller and the second physical address of the second controller mapped on the first controller based on the memory page number to be stored includes: establishing a mapping address between the memory of the first controller and the memory of the second controller based on a preset data transmission protocol; determining the third physical address of the second controller, and determining the second physical address of the second controller mapped on the first controller based on the mapping address and the third physical address.

2. The method according to claim 1, characterized in that, After storing the data to be stored in the first controller via the first data channel and then storing the data to be stored in the second controller via the second data channel, the process includes: Based on the memory page number to be stored and the first physical address, the first memory page to be updated is determined according to the bitmap information of the first controller; Based on the memory page number to be stored and the second physical address, the second memory page to be updated is determined according to the bitmap information of the first controller; Update the state of the first memory page to be updated and / or the state of the second memory page to be updated to the used state.

3. The method according to claim 1, characterized in that, After selecting the memory page number to be stored from the free memory pages based on the bitmap information of the first controller according to the number of memory pages, the method further includes: The destination volume identifier, the starting address, the data length, and the memory page to be stored are packaged into data record information; The data recording information is stored in the first controller and then sent to the second controller.

4. The method according to claim 1, characterized in that, After storing the data to be stored to the first controller via the first data channel and storing the data to be stored to the second controller via the second data channel, the process includes: Determine whether the memory usage in the first controller exceeds a preset threshold; If the memory usage in the first controller exceeds the preset threshold, the dirty data in the first controller is written to the target storage device, and it is determined whether the first controller is in a preset refresh cycle. If the first controller is in the preset refresh cycle, then the dirty data in the first controller is written to the target storage device.

5. The method according to claim 4, characterized in that, After writing the dirty data from the first controller to the target storage device, the process includes: Data synchronization information is generated and sent to the second controller, so that the second controller deletes dirty data in the second controller based on the data synchronization information.

6. The method according to claim 5, characterized in that, The data synchronization information includes the memory page number to be reclaimed. After the second controller deletes dirty data in the second controller based on the data synchronization information, it also includes: Based on the memory page number, the third memory page to be updated is determined according to the bitmap information of the first controller; Update the status of the third memory page to be updated to idle.

7. The method according to claim 1, characterized in that, After storing the data to be stored to the first controller via the first data channel and storing the data to be stored to the second controller via the second data channel, the process includes: Determine whether the first controller has malfunctioned; If the first controller malfunctions, it is determined whether the memory usage in the second controller exceeds a preset threshold, and / or whether the second controller is in a preset refresh cycle. If the memory usage in the second controller exceeds the preset threshold, and / or the second controller is in the preset refresh cycle, then dirty data in the second controller is written to the target storage device.

8. The method according to claim 1, characterized in that, Before receiving storage instructions from the server, the process includes: Initialize the bitmap information of the first controller, update the state of all memory pages in the first controller to the idle state, and update the state of all memory pages in the second controller to the idle state.

9. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the parallel redundant storage method as described in any one of claims 1-8.

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