Load value prediction method and apparatus, electronic device, and computer program product

Abstract

The application provides a load value prediction method and device, electronic equipment and computer program product, wherein the method first accesses a load value prediction cache according to a program counter value of a target load instruction in an instruction distribution stage to read a plurality of prediction items corresponding to the target load instruction; then compares the program counter value of the target load instruction with each prediction item in the plurality of prediction items; then obtains a predicted load value corresponding to the target load instruction from the hit prediction item in the case of a hit prediction item comparison; further obtains a prediction verification result by performing a virtual address comparison and a write-after-read dependency detection on the target load instruction through a memory access unit; and finally determines the predicted load value as a target load value corresponding to the target load instruction in the case of a successful verification prediction. The load to use delay is effectively reduced, and the memory access unit pressure is reduced.

Description

Technical Field

[0001] This application belongs to the field of processor technology, and in particular relates to a load value prediction method, apparatus, electronic device and computer program product. Background Technology

[0002] In modern high-performance processor design, out-of-order execution technology is commonly used to improve instruction-level parallelism. Among these, the load instruction, as a critical operation for fetching data from memory, directly impacts the overall processor performance. Load-to-use latency refers to the minimum number of clock cycles required from the issuance of a load instruction to the time its data is used by subsequent instructions; this latency is one of the main bottlenecks limiting processor performance improvement. To reduce this latency, existing technologies have introduced load value prediction mechanisms, aiming to provide predicted values ​​for load instructions in advance for use by subsequent instructions.

[0003] In related technologies, processors with load value prediction capabilities can provide predicted values ​​through a prediction cache during the instruction dispatch stage to reduce load-to-use latency. However, they still have significant drawbacks: after prediction, they still need to access the data cache to obtain the actual data and compare it with the predicted value to verify the prediction's correctness. This verification process cannot reduce the number of accesses to the data cache, resulting in the memory access unit's pressure not being effectively alleviated, thus limiting further improvements in instruction execution efficiency. Summary of the Invention

[0004] This application provides a load value prediction method, apparatus, electronic device, and computer program product, which can reduce the loading-to-use delay while effectively reducing the access pressure on the data cache.

[0005] A first aspect of this application provides a load value prediction method applied to a processor. The processor includes a load value prediction cache and a memory access unit. The method includes: during the instruction dispatch phase, accessing the load value prediction cache based on the program counter (PC) value of a target load instruction to read a set of multiple prediction items corresponding to the target load instruction; comparing the program counter value of the target load instruction with each prediction item in the set of multiple prediction items; if the prediction item match is successful, obtaining the predicted load value corresponding to the target load instruction from the matched prediction items, wherein the predicted load value is used to provide to the data dependency instruction corresponding to the target load instruction, and the data dependency instruction is executed based on the predicted load value; performing virtual address (VA) comparison and read-after-write (RAW) dependency detection on the target load instruction through the memory access unit to obtain a prediction verification result; if the prediction verification result is successful, determining the predicted load value as the target load value corresponding to the target load instruction.

[0006] In this application's technical solution, by retrieving the predicted load value from the load value prediction cache in advance during the instruction dispatch phase and providing it to data-dependent instructions, the loading-to-use latency is effectively reduced. Furthermore, by using the predicted value directly as the final result after verifying a successful prediction, there is no need to access the data cache again, thus avoiding access to the data cache and reducing memory access pressure.

[0007] Optionally, in one possible implementation of the first aspect, comparing the program counter value of the target loading instruction with each of a set of multiple prediction items includes: performing a hash operation on the program counter value of the target loading instruction to obtain a hashed program counter value (Hpc) corresponding to the target loading instruction; and comparing the hashed program counter value corresponding to the target loading instruction with the hashed program counter values ​​of the set of multiple prediction items. Thus, by performing a hash operation on the program counter value and then comparing it, the number of bits and power consumption of the hardware comparator are reduced, optimizing hardware costs while ensuring prediction accuracy.

[0008] Optionally, in another possible implementation of the first aspect, the above-mentioned virtual address comparison and post-write read dependency detection of the target loading instruction to obtain the prediction verification result includes: performing virtual address comparison and post-write read dependency detection on the target loading instruction; if no post-write read dependency is detected, the prediction item match is achieved, and the virtual address matches, the prediction verification result is determined to be successful; if no post-write read dependency is detected and the prediction item match is unsuccessful, or if no post-write read dependency is detected, the prediction item match is achieved, and the virtual address does not match, or if a post-write read dependency is detected and the prediction item match is achieved, or if a post-write read dependency is detected and the prediction item match is unsuccessful, the prediction verification result is determined to be unsuccessful. Therefore, by comprehensively considering the three conditions of post-write read dependency detection, prediction item match status, and virtual address matching to determine the prediction verification result, a complete prediction verification logic is established to ensure the security and accuracy of prediction usage.

[0009] Optionally, in another possible implementation of the first aspect, the processor further includes a data cache, and the method further includes: retrieving the target load value corresponding to the target load instruction from the data cache when no write-after-read dependency is detected and the prediction match fails; re-executing the target load instruction and marking the target load instruction as unpredictable when no write-after-read dependency is detected, the prediction match succeeds, and the virtual address does not match, wherein the unpredictable mark is used to instruct the processor to retrieve the target load value corresponding to the target load instruction from the data cache when the target load instruction is received; re-executing the target load instruction and marking the target load instruction as unpredictable when a write-after-read dependency is detected and the prediction match succeeds; and retrieving the target load value corresponding to the target load instruction from the data cache when a write-after-read dependency is detected and the prediction match fails. Thus, by adopting different processing strategies of accessing the data cache or rolling back and re-executing for different prediction failure situations, execution efficiency is maximized while ensuring program correctness.

[0010] Optionally, in another possible implementation of the first aspect, the method further includes: if the prediction item match fails, adding a prediction item corresponding to the loading instruction to the load value prediction cache and initializing the confidence level of the prediction item; if the prediction verification result is a successful verification, after determining the predicted load value as the target load value corresponding to the target load instruction, the method further includes: increasing the confidence level of the prediction item; if the prediction verification result is a failed verification, decreasing the confidence level of the prediction item; if the prediction verification result is a successful verification, determining the predicted load value as the target load value corresponding to the target load instruction includes: when the prediction verification result is a successful verification and the confidence level of the prediction item corresponding to the target load instruction is greater than or equal to a preset confidence threshold, determining the predicted load value as the target load value corresponding to the target load instruction. Thus, by dynamically managing the usage conditions of prediction items through a confidence level mechanism, the prediction value is used only when the confidence level meets the threshold, thereby improving prediction accuracy and avoiding the negative impact of low-quality predictions on pipeline performance.

[0011] Optionally, in another possible implementation of the first aspect, before the above-mentioned method obtains the prediction verification result by performing virtual address comparison and write-after-read dependency detection on the target load instruction through the memory access unit, the method further includes: when the target store instruction writes a stored data value to the load value prediction cache, comparing the target virtual address to be accessed by the target load instruction with the target virtual address to be accessed by the target store instruction, and comparing the data size of the target load instruction with the data size of the target store instruction; if the target virtual address to be accessed by the target load instruction is the same as the target virtual address to be accessed by the target store instruction, and the data size of the target load instruction matches the data size of the target store instruction, the stored data value of the target store instruction is determined as the target load value corresponding to the target load instruction. Thus, by performing address and size comparison and implementing data bypass when the target store instruction updates the prediction cache, the store-load conflict is resolved, and pipeline rollback caused by prediction failure is avoided.

[0012] Optionally, in another possible implementation of the first aspect, each prediction item in the aforementioned load value prediction cache includes a valid bit, a hash program counter value, a virtual address, a tag, a data size, a confidence level, and a value, where the tag is the result of hashing the physical address (PA). If the prediction verification result indicates successful prediction, after determining the predicted load value as the target load value corresponding to the target load instruction, the method further includes updating the virtual address, tag, data size, confidence level, and value to the corresponding prediction item. Thus, by updating the prediction item with the verified actual data after execution, the timeliness and accuracy of the prediction cache data are maintained, providing a reliable foundation for subsequent predictions.

[0013] A second aspect of this application provides a load value prediction apparatus applied to a processor, the processor including a load value prediction cache and a memory access unit, the apparatus comprising:

[0014] The cache access module is used during the instruction dispatch phase to access the load value prediction cache based on the program counter value of the target load instruction, so as to read a set of multiple prediction items corresponding to the target load instruction.

[0015] The comparison module is used to compare the program counter value of the target load instruction with each of a set of multiple predictions.

[0016] The value acquisition module is used to obtain the predicted loading value corresponding to the target loading instruction from the matched predicted items when the predicted item comparison is successful. The predicted loading value is used to provide the data dependency instruction corresponding to the target loading instruction, and the data dependency instruction is executed based on the predicted loading value.

[0017] The prediction and verification module is used to perform virtual address comparison and write-read dependency detection on the target load instruction through the memory access unit to obtain the prediction and verification results.

[0018] The load value determination module is used to determine the predicted load value as the target load value corresponding to the target load instruction when the prediction verification result is successful.

[0019] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the load value prediction method of the first aspect described above.

[0020] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the load value prediction method of the first aspect described above.

[0021] The fifth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the load value prediction method of the first aspect described above.

[0022] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a load value prediction architecture provided in an embodiment of this application;

[0025] Figure 2 This is a flowchart illustrating a load value prediction method provided in an embodiment of this application;

[0026] Figure 3 This is a flowchart illustrating another load value prediction method provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the structure of a load value prediction device provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0030] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0031] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0032] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0033] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0035] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0036] In related technologies, processors with load value prediction capabilities can provide predicted values ​​through a prediction cache during the instruction dispatch stage to reduce load-to-use latency. However, they still have significant drawbacks: after prediction, they still need to access the data cache to obtain the actual data and compare it with the predicted value to verify the prediction's correctness. This verification process cannot reduce the number of accesses to the data cache, resulting in the memory access unit's pressure not being effectively alleviated, thus limiting further improvements in instruction execution efficiency.

[0037] In view of this, embodiments of this application provide a load value prediction method, apparatus, electronic device, and computer program product. First, during the instruction distribution phase, a load value prediction cache is accessed based on the program counter value of the target load instruction to read a set of multiple prediction items corresponding to the target load instruction. Then, the program counter value of the target load instruction is compared with each prediction item in the set of multiple prediction items. Next, if the prediction item match is successful, the predicted load value corresponding to the target load instruction is obtained from the matched prediction items. This predicted load value is used to provide data-dependent instructions corresponding to the target load instruction, and the data-dependent instructions execute based on the predicted load value. Further, through a memory access unit, virtual address comparison and write-after-read dependency detection are performed on the target load instruction to obtain a prediction verification result. Finally, if the prediction verification result indicates successful prediction, the predicted load value is determined as the target load value corresponding to the target load instruction. Therefore, by obtaining the predicted load value from the load value prediction cache in advance during the instruction distribution phase and providing it to data-dependent instructions, the load-to-use latency is effectively reduced. Furthermore, by using the predicted value directly as the final result after successful prediction verification without accessing the data cache again, access to the data cache is avoided, reducing the pressure on the memory access unit.

[0038] To illustrate the technical solution of this application, specific embodiments are described below.

[0039] Figure 1 A schematic diagram of a load value prediction architecture provided by an embodiment of this application is shown. The load value prediction method provided by this embodiment is applicable to out-of-order processors. Figure 1 The processor shown comprises two main parts: a load value prediction cache during the instruction dispatch stage and related verification logic in the memory access unit. For ease of explanation, this application uses a RISC-V (Reduced Instruction Set Computer V) implementation with both virtual and physical addresses of 48 bits as an example.

[0040] The addresses specified in the program are virtual addresses, which need to be translated to obtain the actual physical addresses. Physical addresses are the actual memory addresses.

[0041] The following section provides a detailed explanation of the above-mentioned load value prediction architecture, with specific steps involved.

[0042] In the above Figure 1 Based on the load value prediction architecture shown, Figure 2 A flowchart illustrating a load value prediction method provided in an embodiment of this application is shown. Figure 2 As shown, the loaded value prediction method may include the following steps:

[0043] Step 201: During the instruction dispatch phase, the load value prediction cache is accessed based on the program counter value of the target load instruction to read a set of multiple prediction items corresponding to the target load instruction.

[0044] It's important to note that the instruction dispatch phase primarily involves sending instructions to the issue queues corresponding to each execution unit, awaiting execution. Instruction issuance (Issue) is the process of sending instructions from the issue queue to the execution unit for execution. Load instructions are used to retrieve values ​​from specified addresses in memory.

[0045] In this embodiment, the load value prediction cache is a multi-way storage structure, the size and number of ways of which are determined by the specific implementation. Assuming 64 groups of load value prediction caches, each with 4 ways, are used, there are a total of 64*4=256 prediction items. The required index is 6 bits, and each time a group of 4 prediction items is read (an example of a group of multiple prediction items).

[0046] In one embodiment, each prediction in the loaded value prediction cache includes a valid bit (Vld), a hash program counter value (Hpc), a virtual address, a tag, a size, a confidence level (Conf), and a value.

[0047] The Valid bit is used to identify whether a prediction item contains valid data. The Valid bit is set to Valid when the load instruction that caused the newly allocated prediction item completes execution and fills its data back into the prediction item. The Valid bit is also cleared synchronously when the corresponding cache line in the data cache is marked as invalid. The Value field provides the predicted load data for subsequent load instructions. This field is written into the corresponding prediction item after the load instruction that caused the newly allocated prediction item completes execution and may be updated during subsequent load or store instructions. The store instruction stores the value obtained from the load instruction at a specified address in memory at the specified address. Other contents of the prediction item will be described in the following embodiments.

[0048] Step 202: Compare the program counter value of the target load instruction with each of a set of multiple predictions.

[0049] During the instruction dispatch phase, the processor uses the low-order bits of the program counter value of the loaded instruction as an index to access the load value prediction cache. For example, when using bits 2 to 7 (PC[7:2]) of the program counter value as an index, it reads a set of four predictions from the cache for comparison and selects the matching prediction.

[0050] In one embodiment, the program counter value of the target load instruction is hashed to obtain the hash program counter value Hpc corresponding to the target load instruction; the hash program counter value corresponding to the target load instruction is then compared with the hash program counter values ​​in a set of multiple prediction items. Therefore, by hashing the program counter values ​​and then comparing them, the number of bits and power consumption of the hardware comparator are reduced, optimizing hardware costs while ensuring prediction accuracy.

[0051] Here, Hpc is the result of hashing the program counter value corresponding to the load instruction. The specific implementation of this hash operation can be determined according to design requirements. For example, it can be generated by performing a bitwise XOR operation on different fields of the program counter value. Specifically, the four fields from bits 47 to 38, bits 37 to 28, bits 27 to 18, and bits 17 to 8 of the program counter value are XORed to obtain a 10-bit wide hash program counter value (Hpc[9:0]). Although the method of approximating the match using the hash program counter value will lead to a certain degree of decrease in the hit rate, it can effectively reduce the hardware area and power consumption by significantly reducing the number of bits of the hardware comparator.

[0052] Step 203: If the prediction item match is successful, obtain the predicted load value corresponding to the target load instruction from the matched prediction items. The predicted load value is used to provide data dependency instructions corresponding to the target load instruction, and the data dependency instructions are executed based on the predicted load value.

[0053] In this embodiment, when the comparison result is a match, the predicted loading value is obtained from the matched predicted item. This predicted value is directly transmitted to the data dependency instructions of the target loading instruction, enabling these instructions to continue executing subsequent operations based on the predicted value, thus achieving instruction-level parallel processing.

[0054] Step 204: Through the memory access unit, perform virtual address comparison and write-after-read dependency detection on the target load instruction to obtain the prediction verification result.

[0055] RAW (Read After Write) dependency refers to a situation where a load instruction precedes a store instruction for the same address.

[0056] In one embodiment, virtual address comparison and post-write read dependency detection can be performed on the target load instructions. If no post-write read dependency is detected, the prediction term match is achieved, and the virtual address matches, the prediction verification result is determined to be successful. If no post-write read dependency is detected and the prediction term match is missed, or if no post-write read dependency is detected, the prediction term match is achieved, and the virtual address does not match, or if a post-write read dependency is detected and the prediction term match is achieved, or if a post-write read dependency is detected and the prediction term match is missed, the prediction verification result is determined to be unsuccessful. Therefore, by comprehensively considering the three conditions of post-write read dependency detection, prediction term match status, and virtual address matching to determine the prediction verification result, a complete prediction verification logic is established, ensuring the security and accuracy of prediction usage.

[0057] It should be noted that while subsequent load instructions directly retrieve data from the load value prediction cache, they are still sent to the memory access unit through the normal pipeline path. This instruction carries prediction information (including HpcHit indicating whether a hit occurred, the VA read from the load value prediction cache, etc.) for verification. The memory access unit itself performs RAW detection (a necessary step in all out-of-order processor designs, used to detect if there are any pending memory instructions for the same address preceding the load instruction; if so, it waits for the corresponding memory instruction to complete). This solution makes the following judgment based on this detection mechanism: if no RAW is detected (i.e., no pending memory instructions for the same address preceding the load instruction), and HpcHit is 1, and matches the VA calculated by the address calculation unit in the memory access unit, then the load value prediction is successful, and the data cache is no longer accessed.

[0058] In one embodiment, if no post-write read dependency is detected and the prediction match fails, the target load value corresponding to the target load instruction is retrieved from the data cache. If no post-write read dependency is detected, the prediction match succeeds, and the virtual address does not match, the target load instruction is re-executed, and a non-prediction flag is set for the target load instruction. This non-prediction flag instructs the processor to retrieve the target load value corresponding to the target load instruction from the data cache upon receiving the target load instruction. Similarly, if a post-write read dependency is detected and the prediction match succeeds, the target load instruction is re-executed, and a non-prediction flag is set for the target load instruction. Finally, if a post-write read dependency is detected and the prediction match fails, the target load value corresponding to the target load instruction is retrieved from the data cache. Therefore, by employing different handling strategies—accessing the data cache or rolling back and re-execution—for different prediction failure scenarios, execution efficiency is maximized while ensuring program correctness.

[0059] It should be noted that if no RAW is detected and HpcHit is 0, the data cache is accessed normally to retrieve data without triggering an internal exception or rollback. If no RAW is detected and HpcHit is 1, but the VA does not match, an internal exception is triggered and a rollback is executed. Subsequent instructions are re-executed from the beginning of that load instruction, and the load instruction is marked as NoPred so that when it is re-executed, it does not retrieve data from the load value prediction cache but instead retrieves data from the data cache through the normal path. If RAW is detected and HpcHit is 1, an internal exception is triggered and a rollback is executed. Subsequent instructions are re-executed from the beginning of that load instruction, and the load instruction is marked as NoPred. If RAW is detected but HpcHit is 0, the data cache is accessed normally to retrieve data without triggering an internal exception or rollback.

[0060] In one embodiment, before performing virtual address comparison and write-after-read dependency detection on the target load instruction to obtain the prediction verification result, when the target store instruction writes stored data values ​​to the load value prediction cache, the target virtual address to be accessed by the target load instruction can be compared with the target virtual address to be accessed by the target store instruction, and the data size of the target load instruction can be compared with the data size of the target store instruction. If the target virtual address to be accessed by the target load instruction is the same as the target virtual address to be accessed by the target store instruction, and the data size of the target load instruction matches the data size of the target store instruction, the stored data value of the target store instruction is determined as the target load value corresponding to the target load instruction. Therefore, by performing address and size comparison and implementing data bypass when the target store instruction updates the prediction cache, the store-load conflict is resolved, and pipeline rollback caused by prediction failure is avoided.

[0061] The virtual address (VA) is the memory access address of the load instruction, calculated by the address calculation logic in the memory access unit. After the load instruction that causes the allocation of a new load value prediction cache entry is executed, this virtual address is filled into the corresponding load value prediction cache entry. If the virtual address does not match during the memory access unit comparison, the value in the load value prediction cache is considered invalid. The data size (Size) indicates the size of the data accessed by the load instruction, and is filled into the corresponding load value prediction cache entry after the load instruction that causes the allocation of a new load value prediction cache entry is executed. Size is used to determine whether subsequent load instructions are within the address coverage of this prediction entry; only load instructions within the coverage can use the prediction value in this entry. Taking the RISC-V architecture as an example, the data size of load / store instructions includes four types: byte, halfword (2 bytes), word (4 bytes), and double word (8 bytes). Therefore, the data size field can be implemented using 2-bit binary encoding, where 2'b00, 2'b01, 2'b10, and 2'b11 correspond to byte, halfword, word, and double word, respectively.

[0062] In this embodiment, for some special RAW cases, the following processing mechanisms can be used to improve execution efficiency. First scenario: When a program instruction accessing the same address has been executed and updated to the load value prediction cache, the data retrieved from the load value prediction cache is the latest data. Second scenario: When a program instruction accessing the same address has been executed and is updating the load value prediction cache, and a subsequent load instruction is reading data from the load value prediction cache, the virtual address and data size of the item to be read are compared with the virtual address and data size updated in the storage instruction. If a match is found, the stored value is directly output as the load value through a bypass method. Third scenario: When a program instruction accessing the same address is about to complete and is being written to the data cache in the memory access unit in the next clock cycle, it is simultaneously sent to the write port of the load value prediction cache. At this time, a subsequent load instruction is reading data from the same address from the load value prediction cache, causing the load instruction to be unable to obtain new data in the current cycle. To address this issue, in the next cycle—the cycle in which the load value prediction cache outputs data (containing virtual addresses), which is also the cycle in which storage instruction information arrives at the load value prediction cache write port—the system compares the read virtual address and data size with the virtual address and data size in the storage completion information sent from the memory access unit. If they match, the stored value replaces the value read from the load value prediction cache. It should be noted that the specific processing cycle described here may vary depending on the implementation, but the processing logic remains similar.

[0063] Step 205: If the prediction verification result is successful, the predicted loading value is determined as the target loading value corresponding to the target loading instruction.

[0064] In this embodiment, when the prediction verification result indicates successful verification, the predicted load value is determined as the final result of the target load instruction. At this time, the processor directly uses the predicted value as valid data and suppresses the initiation of actual access operations to the data cache.

[0065] In one embodiment, if a prediction item match fails, a new prediction item corresponding to the load instruction is added to the load value prediction cache, and the confidence level of the prediction item is initialized. If the prediction verification result indicates a successful prediction, the predicted load value is determined as the target load value corresponding to the target load instruction, and the confidence level of the prediction item is increased. If the prediction verification result indicates a failed prediction, the confidence level of the prediction item is decreased. If the prediction verification result indicates a successful prediction, and the confidence level of the prediction item corresponding to the target load instruction is greater than or equal to a preset confidence threshold, the predicted load value is determined as the target load value corresponding to the target load instruction. Therefore, the use conditions of prediction items are dynamically managed through a confidence level mechanism, using the prediction value only when the confidence level meets the threshold, thereby improving prediction accuracy and avoiding the negative impact of low-quality predictions on pipeline performance.

[0066] For example, the confidence field (Conf) is represented using a 2-bit width. Whenever a load or store instruction accesses a new address, the system allocates a new prediction in the load value prediction cache, initially setting the confidence to 0. When the prediction is confirmed as a hit in the memory access unit, its confidence increases by 1, stopping at a maximum value of 2'b11. When a prediction hits in the early matching phase but fails to hit in the final verification of the memory access unit, the confidence decreases by 1, stopping at 0. Only when the same prediction accumulates two consecutive hits (i.e., a confidence greater than or equal to 2'b10) will its data value be used as a prediction value. When the confidence is below 2'b10, the system only updates the confidence and does not use the value from that prediction for prediction.

[0067] In one embodiment, after step 205, the virtual address, label, data size, confidence level, and value can be updated to the corresponding prediction item. Thus, by updating the prediction item with the verified actual data after execution, the timeliness and accuracy of the prediction cache data are maintained, providing a reliable foundation for subsequent predictions.

[0068] Regarding the replacement strategy for the loaded value prediction cache, the system checks the confidence scores of the four prediction items within the same group and selects the item with the lowest confidence score and the smallest path number for replacement. For example, when the confidence scores of path 0 and path 1 are both 0, the prediction item corresponding to path 0 will be replaced first.

[0069] During the execution of a load instruction, whether the instruction allocates a new item in the value prediction cache or hits an existing prediction item, the corresponding index and path information are recorded. The index, composed of a specific field of the program counter value, is used to select the target group in the value prediction cache; the path information is used to determine the specific location within the group. After the load instruction is completed, the system updates the corresponding virtual address, label, data size, confidence level, and data value to the specified prediction item based on the recorded index and path information.

[0070] The tag field is the result of hashing the physical address. Specifically, it involves performing a hash calculation on bits 47 to 12 of the physical address. For example, bits 47-36, 35-24, and 23-12 of the physical address can be XORed to generate a 12-bit tag value. This tag value is filled into the corresponding prediction item after the load instruction that causes the newly allocated prediction item is executed. Its main function is to synchronize the invalidation of the corresponding item in the load value prediction cache by comparing the tag value when the corresponding cache line in the data cache is marked as invalid, thereby maintaining data consistency.

[0071] The value field is written into the corresponding prediction item after the load instruction that causes the new prediction item to be assigned is executed. This field may be updated during the subsequent execution of load instructions or storage instructions.

[0072] The load value prediction method disclosed in the above embodiments of this application firstly accesses the load value prediction cache based on the program counter value of the target load instruction during the instruction dispatch stage to read a set of multiple prediction items corresponding to the target load instruction; then, the program counter value of the target load instruction is compared with each prediction item in the set of multiple prediction items; next, if the prediction item comparison is successful, the predicted load value corresponding to the target load instruction is obtained from the matched prediction items, wherein the predicted load value is used to provide to the data dependency instruction corresponding to the target load instruction, and the data dependency instruction is executed based on the predicted load value; further, the memory access unit performs virtual address comparison and write-after-read dependency detection on the target load instruction to obtain the prediction verification result; finally, if the prediction verification result is successful, the predicted load value is determined as the target load value corresponding to the target load instruction. Therefore, by obtaining the predicted load value from the load value prediction cache in advance during the instruction dispatch stage and providing it to the data dependency instruction, the load-to-use latency is effectively reduced. In addition, by directly using the predicted value as the final result after successful prediction verification, it is not necessary to access the data cache again, thereby avoiding access to the data cache and reducing the pressure on the memory access unit.

[0073] In this embodiment, the load-value prediction cache has Content-Addressable Memory (CAM) functionality, meaning it can locate the memory structure of the target address by matching the stored content. For a storage instruction that needs to update the load-value prediction cache, it carries virtual address information. The system determines the specific cache entry to be written by comparing this virtual address with the virtual addresses of existing entries in the cache. It is important to note that since CAM requires significant hardware implementation costs, the number of entries in the load-value prediction cache should be controlled during actual design. Too many cache entries can lead to problems such as degraded timing performance, increased chip area, and increased power consumption.

[0074] To facilitate understanding of the above embodiments, the following is in conjunction with... Figure 3 This paper introduces a detailed method for predicting load values. Figure 3 As shown, during the instruction dispatch phase, the processor first accesses the load value prediction cache. At this point, it reads multiple fields from the cache entries, including key information such as the valid bit, virtual address, confidence level, and predicted value.

[0075] The core judgment phase consists of three levels: First, a prediction item comparison and confidence check are performed. Only when the prediction item match is found and the confidence level is greater than or equal to 2, the process proceeds to the next judgment level. If neither condition is met, the process directly jumps to the data cache access path. The second judgment level performs virtual address matching verification, comparing the virtual address in the prediction item with the actually calculated virtual address. If the match fails, an exception handling mechanism is triggered; if the match is successful, the process proceeds to the third level of dependency checking. The third level checks for any incomplete related storage instructions, i.e., checks for write-after-read dependencies. If incomplete storage instructions exist, the exception handling process is also triggered.

[0076] The exception handling mechanism is activated when a virtual address mismatch or an incomplete memory instruction exists. The processor reports an internal exception and performs a pipeline rollback. After the rollback, the load instruction is re-executed, this time forcing data retrieval from the data cache and skipping the prediction mechanism. In the successful prediction path, the predicted load value is considered a valid result after passing all three check levels. This value is directly written to the physical register to complete the load operation, while the system simultaneously updates the label, confidence level, and predicted value fields in the prediction cache. The data cache access path serves as a backup execution channel, activated when prediction fails or confidence is insufficient. This path retrieves the target data from the data cache through regular memory access operations and completes the subsequent register write operations. The entire process balances prediction performance and execution accuracy through a multi-level verification mechanism, maintaining architectural consistency while shifting the load forward. The exception handling mechanism ensures reliable recovery from prediction errors, while confidence management provides adaptive prediction strategy adjustment capabilities.

[0077] See Figure 4 The diagram shows a structural schematic of a load value prediction device provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0078] The load value prediction device may specifically include the following modules:

[0079] The cache access module 401 is used during the instruction dispatch phase to access the load value prediction cache based on the program counter value of the target load instruction, so as to read a set of multiple prediction items corresponding to the target load instruction.

[0080] The comparison module 402 is used to compare the program counter value of the target load instruction with each of a set of multiple predictions.

[0081] The value acquisition module 403 is used to obtain the predicted loading value corresponding to the target loading instruction from the predicted item when the prediction item matching is successful. The predicted loading value is used to provide the data dependency instruction corresponding to the target loading instruction, and the data dependency instruction is executed based on the predicted loading value.

[0082] The prediction and verification module 404 is used to perform virtual address comparison and write-read dependency detection on the target load instruction through the memory access unit to obtain the prediction and verification results.

[0083] The load value determination module 405 is used to determine the predicted load value as the target load value corresponding to the target load instruction when the prediction verification result is that the prediction is successful.

[0084] The load value prediction apparatus disclosed in the above embodiments of this application first accesses the load value prediction cache based on the program counter value of the target load instruction during the instruction distribution stage to read a set of multiple prediction items corresponding to the target load instruction; then, it compares the program counter value of the target load instruction with each prediction item in the set of multiple prediction items; next, if the prediction item match is successful, it obtains the predicted load value corresponding to the target load instruction from the matched prediction items, wherein the predicted load value is used to provide to the data dependency instruction corresponding to the target load instruction, and the data dependency instruction executes based on the predicted load value; further, through the memory access unit, it performs virtual address comparison and write-after-read dependency detection on the target load instruction to obtain the prediction verification result; finally, if the prediction verification result is that the prediction is successful, the predicted load value is determined as the target load value corresponding to the target load instruction. Therefore, by obtaining the predicted load value from the load value prediction cache in advance during the instruction distribution stage and providing it to the data dependency instruction, the loading-to-use latency is effectively reduced. In addition, by directly using the predicted value as the final result after verifying a successful prediction, it is not necessary to access the data cache again, thus avoiding access to the data cache and reducing the pressure on the memory access unit.

[0085] Furthermore, in one possible implementation of this application embodiment, the comparison module 402 may specifically include the following units:

[0086] The first calculation unit is used to perform a hash operation on the program counter value of the target loading instruction to obtain the hash program counter value corresponding to the target loading instruction.

[0087] The first comparison unit is used to compare the hash program counter value corresponding to the target loading instruction with the hash program counter values ​​in a set of multiple prediction items.

[0088] Therefore, by performing a hash operation on the program counter value and then comparing it, the number of bits and power consumption of the hardware comparator can be reduced, thus optimizing hardware costs while ensuring prediction accuracy.

[0089] Furthermore, in another possible implementation of this application embodiment, the prediction verification module 404 may specifically include the following units:

[0090] The first detection unit is used to perform virtual address comparison and write-after-read dependency detection on the target loading instructions.

[0091] The first determining unit is used to determine that the prediction verification result is successful if no write-after-read dependency is detected, the prediction term match is found, and the virtual address is matched.

[0092] The second determining unit is used to determine the prediction verification result as prediction verification failure when no post-write dependency is detected and the prediction term match is missed, or when no post-write dependency is detected, the prediction term match is missed and the virtual address does not match, or when a post-write dependency is detected and the prediction term match is missed, or when a post-write dependency is detected and the prediction term match is missed.

[0093] Therefore, by comprehensively considering three conditions—write-after-read dependency detection, prediction item hit status, and virtual address matching—the prediction verification result is determined, thereby establishing a complete prediction verification logic to ensure the security and accuracy of prediction usage.

[0094] Furthermore, in another possible implementation of this application embodiment, the processor further includes a data cache, and the second determining unit is specifically used to: obtain the target load value corresponding to the target load instruction from the data cache when no write-after-read dependency is detected and the prediction term match is missed; re-execute the target load instruction and mark the target load instruction as not predictable when no write-after-read dependency is detected, the prediction term match is hit, and the virtual address does not match, wherein the not predictable flag is used to instruct the processor to obtain the target load value corresponding to the target load instruction from the data cache when the target load instruction is received; re-execute the target load instruction and mark the target load instruction as not predictable when a write-after-read dependency is detected and the prediction term match is hit; and obtain the target load value corresponding to the target load instruction from the data cache when a write-after-read dependency is detected and the prediction term match is missed. Thus, by adopting a processing strategy of accessing the data cache or rolling back and re-executing for different prediction failure situations, execution efficiency is maximized while ensuring program correctness.

[0095] Furthermore, in another possible implementation of this application embodiment, the above-mentioned load value prediction device may further include the following modules:

[0096] The first processing module is used to add a prediction item corresponding to the loading instruction to the loading value prediction cache and initialize the confidence level of the prediction item when the prediction item comparison fails.

[0097] The second processing module is used to increase the confidence level of the prediction item after determining the predicted loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is successful.

[0098] The third processing module is used to reduce the confidence level of the predicted item when the prediction verification result is that the prediction has failed.

[0099] The aforementioned loading value determination module 405 is specifically used to: determine the predicted loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is that the prediction was successful and the confidence level of the prediction item corresponding to the target loading instruction is greater than or equal to the preset confidence threshold.

[0100] Therefore, by dynamically managing the usage conditions of prediction items through a confidence level mechanism, prediction values ​​are only used when the confidence level meets the standard, thereby improving prediction accuracy and avoiding the negative impact of low-quality predictions on pipeline performance.

[0101] Furthermore, in another possible implementation of this application embodiment, the above-mentioned load value prediction device may further include the following modules:

[0102] The first comparison module is used to compare the target virtual address to be accessed by the target load instruction with the target virtual address to be accessed by the target storage instruction, and to compare the data size of the target load instruction with the data size of the target storage instruction, when the target storage instruction writes the stored data value into the load value prediction cache.

[0103] The first determining module is used to determine the stored data value of the target storage instruction as the target load value corresponding to the target loading instruction when the target virtual address to be accessed by the target loading instruction is the same as the target virtual address to be accessed by the target storage instruction, and the data size of the target loading instruction matches the data size of the target storage instruction.

[0104] Therefore, by comparing addresses and sizes and implementing data bypass when updating the prediction cache with the target storage instruction, the store-load conflict is resolved, and pipeline rollback caused by prediction failure is avoided.

[0105] Furthermore, in another possible implementation of this application embodiment, each prediction item in the above-mentioned load value prediction cache includes a valid bit, a hash program counter value, a virtual address, a tag, a data size, a confidence level, and a value, wherein the tag is the result of hashing the physical address. The above-mentioned load value prediction device may further include the following modules:

[0106] The update module is used to update the virtual address, label, data size, confidence level, and value to the corresponding prediction item.

[0107] Therefore, by updating the prediction items with the verified actual data after execution, the timeliness and accuracy of the prediction cache data are maintained, providing a reliable foundation for subsequent predictions.

[0108] The load value prediction device provided in this application embodiment can be applied in the foregoing method embodiment. For details, please refer to the description of the above method embodiment, which will not be repeated here.

[0109] Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 5 As shown, the electronic device 500 of this embodiment includes: at least one processor 510 ( Figure 5 The diagram shows only one processor, a memory 520, and a computer program 521 stored in the memory 520 and executable on the at least one processor 510. When the processor 510 executes the computer program 521, it implements the steps in the above-described load value prediction method embodiment.

[0110] The electronic device 500 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. This electronic device may include, but is not limited to, a processor 510 and a memory 520. Those skilled in the art will understand that... Figure 5 This is merely an example of electronic device 500 and does not constitute a limitation on electronic device 500. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0111] The processor 510 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0112] In some embodiments, the memory 520 may be an internal storage unit of the electronic device 500, such as a hard disk or memory of the electronic device 500. In other embodiments, the memory 520 may be an external storage device of the electronic device 500, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 500. Furthermore, the memory 520 may include both internal and external storage units of the electronic device 500. The memory 520 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 520 can also be used to temporarily store data that has been output or will be output.

[0113] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0115] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0116] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0118] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0119] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0120] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the various method embodiments described above.

[0121] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for predicting loading values, characterized in that, Applied to a processor, the processor including a load value prediction cache and a memory access unit, the method includes: During the instruction dispatch phase, the load value prediction cache is accessed according to the program counter value of the target load instruction to read a set of multiple prediction items corresponding to the target load instruction; each prediction item in the load value prediction cache includes a valid bit, a hash program counter value, a virtual address, a tag, a data size, a confidence level, and a value, wherein the tag is the result of hashing the physical address; The program counter value of the target loading instruction is compared with each of the prediction items in the set of multiple prediction items; If the prediction item match is successful, the predicted loading value corresponding to the target loading instruction is obtained from the matched prediction item. The predicted loading value is used to provide to the data dependency instruction corresponding to the target loading instruction, and the data dependency instruction is executed based on the predicted loading value. If the prediction item match fails, a new prediction item corresponding to the loading instruction is added to the loading value prediction cache, and the confidence level corresponding to the prediction item is initialized. When the target storage instruction writes a stored data value into the load value prediction cache, the target virtual address to be accessed by the target load instruction is compared with the target virtual address to be accessed by the target storage instruction, and the data size of the target load instruction is compared with the data size of the target storage instruction. If the target virtual address to be accessed by the target loading instruction is the same as the target virtual address to be accessed by the target storage instruction, and the data size of the target loading instruction matches the data size of the target storage instruction, then the storage data value of the target storage instruction is determined as the target loading value corresponding to the target loading instruction. The memory access unit performs virtual address comparison and write-after-read dependency detection on the target load instruction to obtain the prediction verification result. If the prediction verification result indicates that the prediction was successful, the predicted loading value is determined as the target loading value corresponding to the target loading instruction; the confidence level corresponding to the prediction item is increased. If the prediction verification result is that the prediction fails, the confidence level corresponding to the prediction item is reduced. The step of determining the predicted loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is a successful prediction includes: when the prediction verification result is a successful prediction and the confidence level of the prediction item corresponding to the target loading instruction is greater than or equal to a preset confidence threshold, the predicted loading value is determined as the target loading value corresponding to the target loading instruction.

2. The method according to claim 1, characterized in that, The step of comparing the program counter value of the target loading instruction with each of the multiple prediction terms in the set includes: Perform a hash operation on the program counter value of the target loading instruction to obtain the hash program counter value corresponding to the target loading instruction; The hash program counter value corresponding to the target loading instruction is compared with the hash program counter values ​​in the set of multiple prediction items.

3. The method according to claim 1, characterized in that, The virtual address comparison and write-after-read dependency detection of the target loading instruction to obtain the prediction verification result includes: The target loading instruction is subjected to virtual address comparison and write-after-read dependency detection; If no write-after-read dependency is detected, the prediction term match is found, and the virtual address is matched, the prediction verification result is determined to be a successful prediction verification. If no write-after-read dependency is detected and the prediction term match is missed, or if no write-after-read dependency is detected, the prediction term match is missed, and the virtual address does not match, or if a write-after-read dependency is detected and the prediction term match is missed, or if a write-after-read dependency is detected and the prediction term match is missed, the prediction verification result is determined to be a prediction verification failure.

4. The method according to claim 3, characterized in that, The processor further includes a data cache, and the method further includes: If no write-after-read dependency is detected and the prediction item match is not hit, the target load value corresponding to the target load instruction is obtained from the data cache; If no write-after-read dependency is detected, the prediction term match is hit, and the virtual address does not match, the target load instruction is re-executed, and the target load instruction is marked with a non-prediction flag. The non-prediction flag is used to instruct the processor to obtain the target load value corresponding to the target load instruction from the data cache when the target load instruction is received. If a write-after-read dependency is detected and the prediction match is successful, the target loading instruction is re-executed, and the target loading instruction is marked as not predictable. If a write-after-read dependency is detected and the prediction item match is not hit, the target load value corresponding to the target load instruction is obtained from the data cache.

5. The method according to any one of claims 1-4, characterized in that, After determining the predicted loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is successful, the method further includes: The virtual address, the label, the data size, the confidence level, and the value are updated in the corresponding prediction item.

6. A load value prediction device, characterized in that, Applied to a processor, the processor including a load value prediction cache and a memory access unit, the means comprising: The cache access module is used during the instruction distribution phase to access the load value prediction cache based on the program counter value of the target load instruction, so as to read a set of multiple prediction items corresponding to the target load instruction; each prediction item in the load value prediction cache includes a valid bit, a hash program counter value, a virtual address, a tag, a data size, a confidence level, and a value, wherein the tag is the result of hashing the physical address; The comparison module is used to compare the program counter value of the target loading instruction with each of the multiple prediction items in the set of prediction items; The value acquisition module is used to obtain the predicted loading value corresponding to the target loading instruction from the predicted item when the prediction item match is successful, wherein the predicted loading value is used to provide to the data dependency instruction corresponding to the target loading instruction, and the data dependency instruction is executed based on the predicted loading value; The first processing module is used to add a prediction item corresponding to the loading instruction to the loading value prediction cache and initialize the confidence level corresponding to the prediction item when the prediction item comparison fails. The first comparison module is used to compare the target virtual address to be accessed by the target loading instruction with the target virtual address to be accessed by the target storage instruction, and to compare the data size of the target loading instruction with the data size of the target storage instruction, when the target storage instruction writes the storage data value into the load value prediction cache. The first determining module is used to determine the stored data value of the target storage instruction as the target loading value corresponding to the target loading instruction when the target virtual address to be accessed by the target loading instruction is the same as the target virtual address to be accessed by the target storage instruction, and the data size of the target loading instruction matches the data size of the target storage instruction. The prediction and verification module is used to perform virtual address comparison and write-after-read dependency detection on the target load instruction through the memory access unit to obtain the prediction and verification result; The loading value determination module is used to determine the predicted loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is that the prediction is successful. The second processing module is used to increase the confidence level of the prediction item after determining the prediction loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is that the prediction is successful. The third processing module is used to reduce the confidence level of the prediction item when the prediction verification result is that the prediction has failed. The loading value determination module is further configured to determine the predicted loading value as the target loading value corresponding to the target loading instruction when the prediction verification result is that the prediction is successful and the confidence level of the prediction item corresponding to the target loading instruction is greater than or equal to a preset confidence threshold.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 5.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1 to 5.

Images