Jailhouse interrupt controller matching method, device, server and media

Abstract

This invention discloses a Jailhouse interrupt controller matching method, apparatus, server, and medium, belonging to the field of interrupt technology. It includes: obtaining the physical address of the GICR and generating a GICR physical address list; traversing the GICR physical address list and recording the first GICR physical address; calculating the difference between adjacent first and second GICR physical addresses; determining whether the physical addresses of the first and second GICRs are in a contiguous address space; if not, recording the second GICR physical address and generating a GICR base address array; reading the GICR base address array and mapping it to a GICR virtual base address array; and matching the GICR with the CPU. This enables correct matching of the GICR and CPU, achieving accurate interrupt routing.

Description

Technical Field

[0001] This invention relates to the field of interrupt technology, and in particular to a Jailhouse interrupt controller matching method, apparatus, server, and medium. Background Technology

[0002] With the widespread adoption of ARM architecture in the server field, the demand for efficient virtualization technology is becoming increasingly prominent. The lightweight partitioning management program (Jailhouse) directly divides hardware resources to create multiple independent cells, providing near-native performance within each partition, making it particularly suitable for scenarios with high requirements for real-time performance and performance isolation.

[0003] In the ARM architecture, the GICv3 / v4 interrupt controller significantly improves multi-core scalability by separating the CPU interface logic from the global interrupt dispatcher (GICDistributor, GICD) to a per-CPU independent interrupt redistributor (GICRDestributor, GICR). Jailhouse's original design was for embedded platforms, which have a limited number of GICRs, a simple memory mapping layout, and can be accessed uniformly using static or linear offset methods.

[0004] However, in large-scale multi-core servers, processors often adopt a multi-chip (DIE) architecture, which makes the GICRs distributed in multiple discrete address segments. The existing Jailhouse cannot effectively identify and access all GICRs, resulting in the inability to match GICRs to the correct CPU and the inability to accurately route interrupts to the target CPU, which severely limits its applicability in complex hardware topologies. Summary of the Invention

[0005] This invention provides a Jailhouse interrupt controller matching method, apparatus, server, and medium to solve the technical problems of matching errors and inaccurate interrupt routing caused by Jailhouse's inability to recognize discretely distributed GICR registers in the prior art.

[0006] In a first aspect, embodiments of the present invention provide a Jailhouse interrupt controller matching method, comprising:

[0007] At the OS kernel level, obtain the GICR physical address and generate a list of GICR physical addresses;

[0008] Traverse the list of GICR physical addresses and record the first GICR physical address;

[0009] Starting from the first GICR physical address, calculate the difference between adjacent first GICR physical addresses and second GICR physical addresses;

[0010] Based on the difference, determine whether the physical addresses of the first GICR and the second GICR are in contiguous address spaces;

[0011] When the address space is not contiguous, record the physical address of the second GICR and generate a GICR base address array based on the physical address of the first GICR and the physical address of the second GICR.

[0012] In the hypervisor virtual layer, the GICR base address array is read and mapped to a GICR virtual base address array;

[0013] The GICR and CPU are matched based on the GICR virtual base address array.

[0014] Secondly, embodiments of the present invention also provide a Jailhouse interrupt controller matching device, comprising:

[0015] The acquisition and generation module is used at the OS kernel layer to obtain the GICR physical address and generate a list of GICR physical addresses;

[0016] The recording module is used to traverse the GICR physical address list and record the first GICR physical address;

[0017] The difference calculation module is used to calculate the difference between adjacent first GICR physical addresses and second GICR physical addresses, starting from the first GICR physical address.

[0018] The judgment module is used to determine whether the physical addresses of the first GICR and the second GICR are in contiguous address spaces based on the difference.

[0019] The array generation module is used to record the physical address of the second GICR when the address space is not contiguous, and to generate a GICR base address array based on the first GICR physical address and the second GICR physical address.

[0020] The mapping module is used to read the GICR base address array in the hypervisor virtual layer and map the GICR base address array to a GICR virtual base address array;

[0021] The matching module is used to match the GICR and the CPU according to the GICR virtual base address array.

[0022] Thirdly, embodiments of the present invention also provide a server, comprising:

[0023] One or more processors;

[0024] Storage device for storing one or more programs;

[0025] When the one or more programs are executed by the one or more processors, the one or more processors implement the Jailhouse interrupt controller matching method as provided in the above embodiments.

[0026] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the Jailhouse interrupt controller matching method as provided in the above embodiments.

[0027] The Jailhouse interrupt controller matching method, apparatus, server, and medium provided in this invention, at the OS kernel layer, obtain the GICR physical address and generate a GICR physical address list; traverse the GICR physical address list and record the first GICR physical address; starting from the first GICR physical address, calculate the difference between adjacent first and second GICR physical addresses; determine whether the physical addresses of the first and second GICRs are in contiguous address spaces based on the difference; if they are not in contiguous address spaces, record the second GICR physical address and generate a GICR base address array based on the first and second GICR physical addresses; at the hypervisor virtual layer, read the GICR base address array and map it to a GICR virtual base address array; match the GICR and CPU based on the GICR virtual base address array. The OS kernel layer detects and constructs the GICR physical base address array, accurately locating the physical address of the GICR in different contiguous address spaces. Subsequently, address mapping and CPU matching are completed in the virtual layer, ensuring the correct establishment of the mapping relationship between the interrupt controller and the CPU core. This enables accurate and reliable interrupt routing under complex hardware topologies, significantly improving system compatibility and stability. Attached Figure Description

[0028] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0029] Figure 1 This is a flowchart of the Jailhouse interrupt controller matching method provided in Embodiment 1 of the present invention;

[0030] Figure 2 This is a flowchart illustrating the matching process between the GICR and the CPU in the Jailhouse interrupt controller matching method provided in Embodiment 1 of the present invention.

[0031] Figure 3This is a flowchart of the Jailhouse interrupt controller matching method provided in Embodiment 2 of the present invention;

[0032] Figure 4 This is a flowchart of the Jailhouse interrupt controller matching method provided in Embodiment 3 of the present invention;

[0033] Figure 5 This is a structural diagram of the Jailhouse interrupt controller matching device provided in Embodiment 4 of the present invention;

[0034] Figure 6 This is a structural diagram of the server provided in Embodiment 5 of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0036] Example 1

[0037] Figure 1 This is a flowchart of the Jailhouse interrupt controller matching method provided in Embodiment 1 of the present invention. This embodiment can be applied to the matching of GICRs with discrete address distributions and CPUs in a multi-DIE environment, and specifically includes the following steps:

[0038] Step 110: At the OS kernel level, obtain the GICR physical address and generate a GICR physical address list.

[0039] The OS kernel layer is the lowest-level core component in the hypervisor that directly interacts with the physical hardware, and it forms the foundation of the entire virtualization system. Running at the CPU's core privilege level, such as EL1 in the ARM architecture, the OS kernel layer has direct control over the physical hardware, handling all hardware-related core operations, and providing secure and efficient hardware access interfaces for upper-layer virtualization functions.

[0040] For example, in a multi-DIE system architecture, the Global Interrupt Controller's (GICR) is not physically centralized but distributed across each DIE in the system. For the ARM architecture, at the OS kernel level, the physical addresses of the GICRs are obtained through the Device Tree. This process can be viewed as parsing hardware topology description information. By traversing the Device Tree nodes, the GIC master node with the GIC version identifier can be found, such as arm,gic-v3. Then, by parsing the corresponding GICR entry in the node's reg attribute, all GICR physical addresses and their lengths for each DIE can be extracted, and a list of GICR physical addresses is generated.

[0041] Step 120: Traverse the GICR physical address list and record the first GICR physical address.

[0042] The list is an ordered set containing the physical address of each GICR obtained in step 110. After the OS kernel layer completes the construction of the GICR physical address list, iterates through the list and records the physical address of the first GICR. The physical address of the first GICR serves as a reference point for the entire GICR address space, providing crucial access information for subsequent processes and forming the starting point for all subsequent GICR register allocations.

[0043] Step 130: Starting from the first GICR physical address, calculate the difference between adjacent first GICR physical addresses and second GICR physical addresses.

[0044] In this embodiment, the first GICR physical address and the second GICR physical address refer to two adjacent addresses arranged sequentially in the list. For example, when traversing to the GICR physical address with index i, the first GICR physical address is the GICR physical address with index i, and the second GICR physical address is the GICR physical address with index i+1.

[0045] After the first GICR physical address in the record list, starting from the first physical address, the address offset between two adjacent GICR units is calculated by address arithmetic operations, that is, by subtracting the first address from the second address.

[0046] Step 140: Determine whether the physical addresses of the first GICR and the second GICR are in contiguous address spaces based on the difference.

[0047] In complex system architectures with multiple DIEs, the system's GICR physical address space is typically not a single contiguous region. Each DIE has its own independent set of GICR regions, which are isolated from each other in the global physical address mapping, thus forming multiple non-contiguous address space segments. Therefore, determining whether an address space is contiguous based on the difference is a crucial step for correctly matching the GICR to the CPU.

[0048] For example, in the GICv3 architecture, all GICRs are arranged at equal intervals in the physical address space, and each GICR consists of two main frames: a GICR_CTLR frame (64KB) and a GICR_SGI frame (64KB). Therefore, a GICR frame is 128KB, and the fixed interval between all GICRs is 128KB. If the calculated difference between adjacent addresses is exactly 128KB, it indicates that the physical addresses of the first and second GICRs belong to the same contiguous block. Conversely, if the difference is greater than 128KB, it indicates that an address space gap has been encountered, and the current first and second GICRs belong to two different non-contiguous regions, usually corresponding to different DIE regions.

[0049] For example, in a dual-DIE system, suppose the two GICR addresses of DIE-0 are 0x0800_0000 and 0x0802_0000, respectively, with a difference of 0x20000, indicating that they are contiguous. Subsequently, when traversing to the first GICR of DIE-1, its address is 0x1000_0000. At this point, using the last GICR address of DIE-0, 0x0802_0000, as the physical address of the first GICR, and 0x1000_0000 as the physical address of the second GICR, the calculated difference is greater than 0x20000, indicating that they are not contiguous, i.e., they are not in the same contiguous memory space.

[0050] Step 150: When the address space is not contiguous, record the physical address of the second GICR and generate a GICR base address array based on the physical address of the first GICR and the physical address of the second GICR.

[0051] In a multi-DIE system architecture, the global GICR address space typically consists of multiple independent, non-contiguous physical address regions. When non-contiguousness is identified through address differences, a single starting address is insufficient to describe the entire hardware layout. Therefore, when traversing to the first and second GICR physical addresses mentioned in step 130, and determining from the differences that the first and second GICR physical addresses are not contiguous address spaces, the second GICR physical address is recorded. This is significant because it provides the starting point for a new, independent contiguous address region. Subsequently, a GICR base address array is generated based on the first GICR physical address and all second GICR physical addresses determined to be in non-contiguous address spaces.

[0052] The GICR base address array records the starting base address of each contiguous GICR address region in the system. Therefore, the OS kernel layer can correctly manage and access all GICR units distributed across multiple discontinuous physical spaces through this dual addressing model of region base address and kernel offset within the region.

[0053] Step 160: In the hypervisor virtual layer, read the GICR base address array and map the GICR base address array to a GICR virtual base address array.

[0054] The Hypervisor virtualization layer operates at the highest privilege level, EL2, in the ARM architecture. This layer is specifically designed at the hardware level for system virtualization and can work in conjunction with the operating system kernel running at a lower privilege level, EL1.

[0055] For example, the hypervisor virtual layer reads the GICR base address array pre-obtained by the kernel layer. Subsequently, the virtual layer maps each GICR physical base address to the hypervisor's virtual address space by configuring the page tables in the EL2 stage, thereby generating a corresponding GICR virtual base address array. After mapping, the hypervisor can directly access and manage these interrupt controller registers through virtual addresses without directly manipulating physical addresses.

[0056] Step 170: Match the GICR and the CPU according to the GICR virtual base address array.

[0057] In a multi-DIE system, a unified virtual view is created for all GICR units that are physically distributed across each DIE by constructing a GICR virtual base address array, and the matching between GICR and CPU is achieved based on the virtual base address array.

[0058] Figure 2This is a flowchart illustrating the matching process between the GICR and CPU in the Jailhouse interrupt controller matching method described in Embodiment 1 of the present invention. Figure 2 The matching of GICR and CPU may include the following steps:

[0059] Step 210: Read the CPU's MPDIR register to obtain the CPU affinity flag.

[0060] In the ARM multi-die processor architecture, MPIDR is a critical system register that uniquely identifies the location of each CPU within the hardware topology. The affinity identifier can be viewed as the hardware address of the CPU core; it typically consists of multiple levels of numbers (e.g., Aff0, Aff1, Aff2, Aff3) that collectively indicate the CPU's specific location within the chip, cluster, and further within the cluster.

[0061] For example, on a dual-DIE server, each DIE contains a 4-core cluster. When the system boots up, the executable code reads the CPU's MPIDR register. The affinity identifiers of the four cores on DIE-0 are 0x0000_0000, 0x0000_0001, 0x0000_0100, and 0x0000_0101, while the four cores on DIE-1 correspond to 0x0001_0000, 0x0001_0001, 0x0001_0100, and 0x0001_0101. By parsing these identifiers, the hypervisor can clearly identify that these are two independent DIEs, each containing a 4-core cluster. This allows it to allocate appropriate CPU resources to the GICR, ensuring that interrupts are handled by the CPU core with the highest affinity.

[0062] Step 220: Traverse the GICR virtual base address array to obtain the current GICR virtual base address and the next GICR virtual base address.

[0063] In this embodiment, the current GICR virtual base address refers to the GICR virtual base address currently pointed to by the iterator during the traversal process, representing the current target being processed by the program. The next GICR virtual base address refers to the GICR virtual base address following the GICR virtual base address currently pointed to by the iterator during the traversal process.

[0064] Step 230: Obtain the first GICR affinity identifier, the second GICR affinity identifier, and the third GICR affinity identifier through the GICR register.

[0065] In the GICv3 architecture, the GICR affinity identifier is a key attribute that uniquely identifies the physical location of the GICR within the system interrupt controller topology. This identifier corresponds to the CPU core's MPIDR affinity identifier, together describing its coordinates within the multi-level hierarchy. By reading the affinity information in the GICR register, the affinity of each GICR for different CPUs can be precisely determined.

[0066] For example, complete topology information can be read from the TYPER register of the GICR. The TYPER register divides the affinity identifier into multiple fields, commonly Aff3, Aff2, and Aff1. Using these three identifiers, the complete address of the GICR in the hardware topology can be obtained.

[0067] In this embodiment, the first GICR affinity identifier is the GICR affinity identifier corresponding to the current GICR virtual base address. The second GICR affinity identifier is the GICR affinity identifier corresponding to the same contiguous address space as the current GICR virtual base address. The third GICR affinity identifier is the GICR affinity identifier corresponding to the next GICR virtual base address.

[0068] Step 240: Compare the CPU affinity identifier with the first GICR affinity identifier. If the CPU affinity identifier is equal to the first GICR affinity identifier, match the GICR and the CPU.

[0069] Step 250: When the CPU affinity identifier is not equal to the first GICR affinity identifier, compare the CPU affinity identifier and the second GICR affinity identifier; when the CPU affinity identifier and the second GICR affinity identifier are equal, match the GICR and the CPU.

[0070] Step 260: When the CPU affinity identifier and the second GICR affinity identifier are not equal, compare the CPU affinity identifier and the third GICR affinity identifier; when the CPU affinity identifier and the third GICR affinity identifier are equal, match the GICR and the CPU.

[0071] In this embodiment, optionally, the matching process between the GICR and the CPU adopts a hierarchical determination mechanism, consisting of three levels of progressive comparison. The first level compares whether the CPU affinity identifier matches the first GICR affinity identifier; if they match, the matching is complete. Otherwise, it proceeds to the second level of the matching process. The second level further compares whether the CPU affinity identifier matches the second GICR affinity identifier; if they match, the matching is successful. Otherwise, it continues to the third level of the matching process. The third level compares whether the CPU affinity identifier matches the third GICR affinity identifier; if they match, the matching is complete.

[0072] This embodiment obtains the GICR physical address at the OS kernel layer and generates a GICR physical address list; it iterates through the GICR physical address list and records the first GICR physical address; starting from the first GICR physical address, it calculates the difference between adjacent first and second GICR physical addresses; based on the difference, it determines whether the physical addresses of the first and second GICRs are in contiguous address spaces; if not, it records the second GICR physical address and generates a GICR base address array based on the first and second GICR physical addresses; at the hypervisor virtual layer, it reads the GICR base address array and maps it to a GICR virtual base address array; based on the GICR virtual base address array, it matches the GICR with the CPU. The OS kernel layer detects and constructs the GICR physical base address array, accurately locating the physical address of the GICR in different contiguous address spaces. Address mapping is then completed at the virtual layer, and each GICR is associated with the corresponding CPU based on the affinity identifier. This ensures that the CPU that is correctly matched with the GICR can obtain the highest working efficiency, thereby achieving accurate and reliable routing of interrupts under complex hardware topologies and significantly improving system compatibility and stability.

[0073] Example 2

[0074] Figure 3 This is a flowchart of the Jailhouse interrupt controller matching method provided in Embodiment 2 of the present invention. This embodiment is based on the above embodiment and optimized. Before the step of reading the GICR base address array in the hypervisor virtual layer and mapping the GICR base address array to a GICR virtual base address array, the method further includes: adding a shared memory segment in the hypervisor and storing the GICR base address array in the shared memory segment; specifically, the step of reading the GICR base address array in the hypervisor virtual layer is optimized to: reading the GICR base address array from the shared memory segment in the hypervisor virtual layer.

[0075] See Figure 3 The Jailhouse interrupt controller matching method includes:

[0076] Step 310: At the OS kernel layer, obtain the GICR physical address and generate a GICR physical address list.

[0077] Step 320: Traverse the GICR physical address list and record the first GICR physical address.

[0078] Step 330: Starting from the first GICR physical address, calculate the difference between the adjacent first GICR physical address and the second GICR physical address.

[0079] Step 340: Determine whether the physical addresses of the first GICR and the second GICR are in contiguous address spaces based on the difference.

[0080] Step 350: When the address space is not contiguous, record the physical address of the second GICR and generate a GICR base address array based on the physical address of the first GICR and the physical address of the second GICR.

[0081] Step 360: In the hypervisor, add a shared memory segment and store the GICR base address array into the shared memory segment.

[0082] For example, firstly, by modifying the Hypervisor's internal scripts, a shared memory segment named .ext is defined, with its size set to a standard memory page, such as 4KB on an ARM architecture. This shared memory segment is statically stored within the Hypervisor's memory space. Subsequently, the GICR base address array is stored in the shared memory segment.

[0083] Step 370: In the hypervisor virtual layer, read the GICR base address array from the shared memory segment and map the GICR base address array to a GICR virtual base address array.

[0084] For example, during the operation of the Hypervisor virtual layer (EL2), the GICR base address array, pre-built and stored in the kernel layer (EL1), is read by accessing global variables in the shared memory segment. This process enables the secure transfer of GIC data information from EL1 to EL2, providing the virtual machine with an independent and complete GIC virtual view.

[0085] Step 380: Match the GICR and the CPU according to the GICR virtual base address array.

[0086] This embodiment obtains the GICR physical address at the OS kernel layer and generates a GICR physical address list; it iterates through the GICR physical address list and records the first GICR physical address; starting from the first GICR physical address, it calculates the difference between adjacent first and second GICR physical addresses; based on the difference, it determines whether the physical addresses of the first and second GICRs are contiguous address spaces; if not, it records the second GICR physical address and generates a GICR base address array based on the first and second GICR physical addresses; in the hypervisor, a shared memory segment is added, and the GICR base address array is stored in the shared memory segment; in the hypervisor virtual layer, the GICR base address array is read from the shared memory segment and mapped to a GICR virtual base address array; based on the GICR virtual base address array, the GICR and CPU are matched. Using the above method, with the shared memory segment as a bridge, the transfer of GIC data information between the EL1 kernel layer and the EL2 virtual layer is realized. It can not only complete the mapping and conversion of GICR addresses in the virtualization environment, but also assist in the correct matching between GICR and CPU.

[0087] Example 3

[0088] Figure 4 This is a flowchart of the Jailhouse interrupt controller matching method provided in Embodiment 3 of the present invention. This embodiment is an optimization based on Embodiment 1. Before the step of reading the GICR base address array in the hypervisor virtual layer and mapping the GICR base address array to a GICR virtual base address array, the method further includes: obtaining the GICD physical address in the OS kernel layer; obtaining the user-configured GICR physical address and the user-configured GICD physical address; determining whether the physical address in the GICR base address array is consistent with the user-configured GICR physical address; determining whether the GICD physical address is consistent with the user-configured GICD physical address; when the physical address in the GICR base address array is consistent with the user-configured GICR physical address, and the GICD physical address is consistent with the user-configured GICD physical address, the GICR base address array is retained.

[0089] See Figure 4 The Jailhouse interrupt controller matching method includes:

[0090] Step 410: At the OS kernel layer, obtain the GICR physical address and generate a GICR physical address list.

[0091] Step 420: Traverse the GICR physical address list and record the first GICR physical address.

[0092] Step 430: Starting from the first GICR physical address, calculate the difference between the adjacent first GICR physical address and the second GICR physical address.

[0093] Step 440: Determine whether the physical addresses of the first GICR and the second GICR are in contiguous address spaces based on the difference.

[0094] Step 450: When the address space is not contiguous, record the physical address of the second GICR and generate a GICR base address array based on the physical address of the first GICR and the physical address of the second GICR.

[0095] Step 460: At the OS kernel layer, obtain the GICD physical address; obtain the user-configured GICR physical address and the user-configured GICD physical address; determine whether the physical address in the GICR base address array is consistent with the user-configured GICR physical address; determine whether the GICD physical address is consistent with the user-configured GICD physical address; if the physical address in the GICR base address array is consistent with the user-configured GICR physical address, and the GICD physical address is consistent with the user-configured GICD physical address, retain the GICR base address array.

[0096] For example, during jailhouse initialization, the driver traverses the device tree to find the node with the string "arm,gic-v3". Within this node, the "reg" attribute defines the physical address and size of the GICD register block. The OS kernel can directly read and record this physical address by calling the standard device tree resolution interface.

[0097] In this embodiment, the user-configured GICR physical address and GICD physical address refer to address values ​​predefined by the system administrator in a configuration file on the host machine. In the hypervisor, the configuration file details the system's hardware resource layout. Users need to manually specify the physical base addresses of GICD and GICR in the configuration file according to the actual hardware configuration. Subsequently, Jailhouse reads the configuration file upon startup and performs GIC-related initialization tasks based on the information contained therein.

[0098] The GICD address read from the device tree and the GICR base address array generated in step 450 are compared with the expected information manually configured by the user. Only when they match perfectly can the accuracy of the user configuration file be verified, and the Hypervisor will then retain the generated GICR base address array for subsequent operations.

[0099] Step 470: In the hypervisor virtual layer, read the GICR base address array and map the GICR base address array to a GICR virtual base address array.

[0100] Step 480: Match the GICR and the CPU according to the GICR virtual base address array.

[0101] This embodiment optimizes the process before the step of reading the GICR base address array and mapping it to a GICR virtual base address array in the hypervisor virtual layer. Specifically, it optimizes the process as follows: at the OS kernel layer, it obtains the GICD physical address; obtains the user-configured GICR physical address and the user-configured GICD physical address; determines whether the physical address in the GICR base address array matches the user-configured GICR physical address; determines whether the GICD physical address matches the user-configured GICD physical address; if both the physical address in the GICR base address array and the user-configured GICR physical address match, and the GICD physical address matches the user-configured GICD physical address, the GICR base address array is retained. Using this method, it ensures that the GIC information constructed by the hypervisor is completely consistent with the user configuration, laying the foundation for accurate matching of GICR and CPU, and providing a guarantee for correct interrupt routing.

[0102] Example 4

[0103] Figure 5 This is a schematic diagram of the Jailhouse interrupt controller matching device provided in Embodiment 4 of the present invention, as shown below. Figure 5 As shown, the device includes:

[0104] The generation module 510 is used to obtain the GICR physical address and generate a list of GICR physical addresses at the OS kernel layer.

[0105] Recording module 520 is used to traverse the GICR physical address list and record the first GICR physical address;

[0106] The difference calculation module 530 is used to calculate the difference between adjacent first GICR physical addresses and second GICR physical addresses, starting from the first GICR physical address.

[0107] The judgment module 540 is used to determine whether the physical address of the first GICR and the physical address of the second GICR are in a contiguous address space based on the difference.

[0108] The array generation module 550 is used to record the physical address of the second GICR when the address space is not contiguous, and to generate a GICR base address array based on the first GICR physical address and the second GICR physical address.

[0109] The mapping module 560 is used to read the GICR base address array in the hypervisor virtual layer and map the GICR base address array to a GICR virtual base address array;

[0110] The matching module 570 is used to match the GICR and the CPU according to the GICR virtual base address array.

[0111] The Jailhouse interrupt controller matching device provided in this embodiment obtains the GICR physical address at the OS kernel layer and generates a GICR physical address list; it traverses the GICR physical address list and records the first GICR physical address; starting from the first GICR physical address, it calculates the difference between adjacent first and second GICR physical addresses; it determines whether the physical addresses of the first and second GICRs are in contiguous address spaces based on the difference; if they are not in contiguous address spaces, it records the second GICR physical address and generates a GICR base address array based on the first and second GICR physical addresses; at the hypervisor virtual layer, it reads the GICR base address array and maps it to a GICR virtual base address array; and it matches the GICR and the CPU based on the GICR virtual base address array. The OS kernel layer detects and constructs the GICR physical base address array, accurately locating the physical address of the GICR in different contiguous address spaces. Subsequently, address mapping and CPU matching are completed in the virtual layer, ensuring the correct establishment of the mapping relationship between the interrupt controller and the CPU core. This enables accurate and reliable interrupt routing under complex hardware topologies, significantly improving system compatibility and stability.

[0112] Based on the above embodiments, the determination module includes:

[0113] The difference determination unit is used to determine if the difference is greater than GICRFrame, and the physical addresses of the first GICR and the second GICR are non-contiguous address spaces.

[0114] Based on the above embodiments, the matching module includes:

[0115] The CPU affinity flag acquisition unit is used to read the CPU's MPDIR register and obtain the CPU affinity flag.

[0116] An array traversal unit is used to traverse the GICR virtual base address array and obtain the current GICR virtual base address and the next GICR virtual base address;

[0117] The GICR affinity identifier acquisition unit is used to acquire the first GICR affinity identifier, the second GICR affinity identifier, and the third GICR affinity identifier through the GICR register;

[0118] A first-level comparison unit is used to compare the CPU affinity identifier with the first GICR affinity identifier, and when the CPU affinity identifier is equal to the first GICR affinity identifier, the GICR and CPU are matched;

[0119] A secondary comparison unit is used to compare the CPU affinity identifier and the second GICR affinity identifier when the CPU affinity identifier is not equal to the first GICR affinity identifier, and to match the GICR and the CPU when the CPU affinity identifier and the second GICR affinity identifier are equal.

[0120] A three-level comparison unit is used to compare the CPU affinity identifier and the third GICR affinity identifier when the CPU affinity identifier and the second GICR affinity identifier are not equal, and to match the GICR and the CPU when the CPU affinity identifier and the third GICR affinity identifier are equal.

[0121] Based on the above embodiments, the acquisition and generation module includes:

[0122] The physical address acquisition unit is used to obtain the GICR physical address by resolving the device tree.

[0123] Based on the above embodiments, the mapping module includes:

[0124] A memory segment read unit is used to read the GICR base address array from the shared memory segment in the hypervisor virtual layer.

[0125] Based on the above embodiments, the device further includes:

[0126] Add a module to add a shared memory segment in the hypervisor and store the GICR base address array into the shared memory segment;

[0127] The configuration information confirmation module is used to obtain the GICD physical address at the OS kernel layer; to obtain the user-configured GICR physical address and the user-configured GICD physical address; to determine whether the physical address in the GICR base address array is consistent with the user-configured GICR physical address; to determine whether the GICD physical address is consistent with the user-configured GICD physical address; and to retain the GICR base address array when the physical address in the GICR base address array is consistent with the user-configured GICR physical address and the GICD physical address is consistent with the user-configured GICD physical address.

[0128] The Jailhouse interrupt controller matching device provided in this embodiment of the invention can execute the Jailhouse interrupt controller matching method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0129] Example 5

[0130] Figure 6 This is a schematic diagram of the structure of a server provided in Embodiment 5 of the present invention. Figure 6 A block diagram is shown of an exemplary server 12 suitable for implementing embodiments of the present invention. Figure 6 The server 12 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0131] like Figure 6 As shown, server 12 is presented in the form of a general-purpose computing server. The components of server 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0132] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0133] Server 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by server 12, including volatile and non-volatile media, removable and non-removable media.

[0134] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache 32. Server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (… Figure 6 Not shown; usually referred to as a "hard drive"). Although Figure 6 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0135] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.

[0136] Server 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing server, display 24, etc.), and with one or more servers that enable users to interact with server 12, and / or with any server (e.g., network card, modem, etc.) that enables server 12 to communicate with one or more other computing servers. This communication can be performed via input / output (I / O) interface 22. Furthermore, server 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with other modules of server 12 via bus 18. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with server 12, including but not limited to: microcode, server drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0137] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the Jailhouse interrupt controller matching method provided in the embodiments of the present invention.

[0138] Example 6

[0139] Embodiment 6 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the Jailhouse interrupt controller matching method as described in any of the above embodiments.

[0140] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0141] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0142] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0143] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0144] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A Jailhouse Interrupt Controller matching method, characterized in that, The method comprises the following steps: In the OS kernel layer, GICR physical addresses are obtained, and a GICR physical address list is generated; The first GICR physical address is recorded by traversing the GICR physical address list; The difference between the first GICR physical address and the second GICR physical address is calculated; It is judged whether the first GICR physical address and the second GICR physical address are continuous address spaces according to the difference; When the address spaces are not continuous, the second GICR physical address is recorded, and a GICR base address array is generated according to the first GICR physical address and the second GICR physical address; In the hypervisor virtual layer, the GICR base address array is read, and the GICR base address array is mapped into a GICR virtual base address array; The GICR and the CPU are matched according to the GICR virtual base address array; The matching of the GICR and the CPU according to the GICR virtual base address array comprises the following steps: The CPU affinity identifier is obtained by reading the MPDIR register of the CPU; The current GICR virtual base address and the next GICR virtual base address are obtained by traversing the GICR virtual base address array; The first GICR affinity identifier, the second GICR affinity identifier and the third GICR affinity identifier are obtained through the register of the GICR; The first GICR affinity identifier is the GICR affinity identifier corresponding to the current GICR virtual base address; the second GICR affinity identifier is the GICR affinity identifier corresponding to the same continuous address space as the current GICR virtual base address; and the third GICR affinity identifier is the GICR affinity identifier corresponding to the next GICR virtual base address; When the CPU affinity identifier is equal to the first GICR affinity identifier, the GICR and the CPU are matched; When the CPU affinity identifier is not equal to the first GICR affinity identifier, the CPU affinity identifier and the second GICR affinity identifier are compared, and when the CPU affinity identifier is equal to the second GICR affinity identifier, the GICR and the CPU are matched; When the CPU affinity identifier is not equal to the second GICR affinity identifier, the CPU affinity identifier and the third GICR affinity identifier are compared, and when the CPU affinity identifier is equal to the third GICR affinity identifier, the GICR and the CPU are matched.

2. The method of claim 1, wherein, The judgment of whether the first GICR physical address and the second GICR physical address are continuous address spaces according to the difference comprises the following steps: If the difference is greater than GICRFrame, the first GICR physical address and the second GICR physical address are non-continuous address spaces.

3. The method of claim 1, wherein, The obtaining of the GICR physical address in the OS kernel layer comprises the following steps: The GICR physical address is obtained by parsing the device tree.

4. The method of claim 1, wherein, Before the step of reading the GICR base address array at the hypervisor virtual layer and mapping the GICR base address array as a GICR virtual base address array, the method further comprises: In the hypervisor, adding a shared memory segment and storing the GICR base address array in the shared memory segment.

5. The method of claim 4, wherein, The step of reading the GICR base address array at the hypervisor virtual layer comprises: Reading the GICR base address array from the shared memory segment at the hypervisor virtual layer.

6. The method of claim 1, wherein, Before the step of reading the GICR base address array at the hypervisor virtual layer and mapping the GICR base address array as a GICR virtual base address array, the method further comprises: Obtaining a GICD physical address at an OS kernel layer; Obtaining a user-configured GICR physical address and a user-configured GICD physical address; Determining whether the physical address in the GICR base address array is consistent with the user-configured GICR physical address; Determining whether the GICD physical address is consistent with the user-configured GICD physical address; When the physical address in the GICR base address array is consistent with the user-configured GICR physical address and the GICD physical address is consistent with the user-configured GICD physical address, reserving the GICR base address array.

7. A Jailhouse Interrupt Controller matching apparatus, characterized in that, Comprise: An obtaining module, configured to obtain a GICR physical address at an OS kernel layer and generate a GICR physical address list; A recording module, configured to traverse the GICR physical address list and record a first GICR physical address; A difference calculation module, configured to calculate a difference between a first GICR physical address and a second GICR physical address adjacent to the first GICR physical address, starting from the first GICR physical address; A judging module, configured to determine whether the first GICR physical address and the second GICR physical address are continuous address spaces according to the difference; An array generating module, configured to record the second GICR physical address and generate a GICR base address array according to the first GICR physical address and the second GICR physical address when the first GICR physical address and the second GICR physical address are not continuous address spaces; A mapping module, configured to read the GICR base address array at a hypervisor virtual layer and map the GICR base address array as a GICR virtual base address array; A matching module, configured to match a GICR and a CPU according to the GICR virtual base address array; The matching module comprises: A CPU affinity identifier obtaining unit, configured to read an MPDIR register of the CPU and obtain a CPU affinity identifier; An array traversing unit, configured to traverse the GICR virtual base address array and obtain a current GICR virtual base address and a next GICR virtual base address; A GICR affinity identifier obtaining unit, configured to obtain a first GICR affinity identifier, a second GICR affinity identifier and a third GICR affinity identifier through a register of the GICR; a first comparison unit configured to compare the CPU affinity tag with the first GICR affinity tag, and match the GICR and the CPU when the CPU affinity tag is equal to the first GICR affinity tag; a second comparison unit configured to compare the CPU affinity tag with the second GICR affinity tag when the CPU affinity tag is not equal to the first GICR affinity tag, and match the GICR and the CPU when the CPU affinity tag is equal to the second GICR affinity tag; a third comparison unit configured to compare the CPU affinity tag with the third GICR affinity tag when the CPU affinity tag is not equal to the second GICR affinity tag, and match the GICR and the CPU when the CPU affinity tag is equal to the third GICR affinity tag.

8. A server, characterized by The server comprises: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the Jailhouse interrupt controller matching method as claimed in any one of claims 1-6.

9. A storage medium containing computer-executable instructions for performing the Jailhouse interrupt controller matching method as claimed in any one of claims 1-6 when executed by a computer processor.

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