Interactive scheduler with dynamic jump of priority

Abstract

The invention relates to an interactive scheduler with dynamic priority hopping. Comprising a time slice management module, a kernel context maintenance and switching module, a priority management module, a task preemption module, a task insertion module, a task deletion module, a task selection module, a task state conversion module, a monitoring CPU load module, a task allocation module, a skip list operation module, a queue state synchronization module and a context integrity module. A skip list and multi-queue design is adopted, the scheduling logic is simplified, the task switching overhead is reduced, the data structure operation performance (O (log n) complexity) is improved, complex calculation is avoided directly according to priority scheduling, and the real-time task response capability is enhanced; and the user experience of the desktop and the interactive task is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of schedulers, in particular to an interactive scheduler with dynamic priority hopping. BACKGROUND

[0002] In the field of current operating system schedulers, the CFS (Completely Fair Scheduler) scheduler of the Linux kernel is a widely adopted fair scheduling algorithm. CFS manages all runnable tasks through a red-black tree data structure and decides the execution order of tasks based on their virtual runtime (vruntime), aiming to achieve fair allocation of CPU time and high throughput. The CFS scheduler performs well in servers and compute-intensive tasks, fully utilizing the performance of multi-core processors and ensuring relatively fair CPU time for each task.

[0003] However, the CFS scheduler has obvious shortcomings in handling interactive tasks (such as desktop applications, games, audio and video processing, etc.). First, due to the high scheduling delay of CFS, interactive tasks may experience noticeable lag when responding to user input, affecting user experience. Second, the scheduling logic of CFS is relatively complex, involving the calculation of virtual runtime and the management of red-black trees, resulting in high task switching overhead and further increasing scheduling delay. In addition, CFS has weak support for real-time tasks, with high response delay for high-priority tasks, making it difficult to meet the requirements of application scenarios with high real-time requirements. Finally, the implementation of CFS is complex, increasing the overhead and maintenance difficulty of the scheduler, which is not conducive to application in resource-constrained embedded systems.

[0004] Therefore, we propose an interactive scheduler with dynamic priority hopping, which improves interactive performance by prioritizing interactive tasks and reducing scheduling delay. SUMMARY

[0005] The present application aims to overcome the shortcomings of the prior art and adapt to real needs, providing an interactive scheduler with dynamic priority hopping to solve the technical problems of current CFS scheduling delay being too high, interactive tasks may experience noticeable lag when responding to user input, affecting user experience. Second, the scheduling logic of CFS is relatively complex, involving the calculation of virtual runtime and the management of red-black trees, resulting in high task switching overhead and further increasing scheduling delay. In addition, CFS has weak support for real-time tasks, with high response delay for high-priority tasks, making it difficult to meet the requirements of application scenarios with high real-time requirements. Finally, the implementation of CFS is complex, increasing the overhead and maintenance difficulty of the scheduler, which is not conducive to application in resource-constrained embedded systems.

[0006] To achieve the objectives of this invention, the technical solution adopted is as follows: An interactive scheduler based on a skip list structure is designed, comprising a time slice management module, a kernel context maintenance and switching module, a priority management module, a task preemption module, a task insertion module, a task deletion module, a task selection module, a task state transition module, a CPU load monitoring module, a task allocation module, a skip list operation module, a queue state synchronization module, a context integrity module, a wake-up processing module, a load calculation module, a threshold judgment module, a migration evaluation module, and an interrupt optimization module.

[0007] The time slice management module is used to implement time slice initialization, dynamic adjustment, exhaustion check and compensation mechanism, and includes a time slice initialization submodule, a time slice dynamic adjustment submodule, a time slice exhaustion check submodule and a time slice compensation mechanism submodule.

[0008] The kernel context maintenance and switching module is used to save and restore the task register state and perform processor core switching. It includes a task switching submodule, a run queue management submodule, a task status tracking submodule, and a scheduling decision submodule.

[0009] The priority management module is used to implement real-time priority mapping, dynamic adjustment and inheritance mechanism, and includes a real-time priority mapping submodule, a dynamic priority adjustment submodule, a priority inheritance mechanism submodule and a priority compensation strategy submodule.

[0010] The task preemption module is used to trigger preemption logic, including a preemption trigger check submodule and a preemption execution submodule;

[0011] The task insertion module is used to insert new tasks into the skip list queue according to priority, and includes a CPU affinity selection submodule, a skip list insertion operation submodule, and a queue status update submodule.

[0012] The task deletion module is used to remove tasks from the queue and release resources, and includes a skip list deletion operation submodule and a resource release management submodule.

[0013] The task selection module is used to select the optimal task from the skip list queue, and includes a candidate task selection submodule, a real-time task priority processing submodule, and a queue status query submodule.

[0014] The task state transition module is used to manage the task state machine and its validity verification, and includes a state validity check submodule, a context saving and recovery submodule, and a state flag update submodule.

[0015] The CPU load monitoring module is used to periodically sample the load of each CPU queue and trigger a load balancing operation. It includes a load calculation submodule and a trigger threshold judgment submodule.

[0016] The task allocation module is used to perform cross-CPU task migration, and includes a target CPU evaluation submodule and a migration execution submodule.

[0017] The skip list operation module supports dynamic level adjustment and bidirectional pointer maintenance, ensuring O(log n) time complexity for insertion and O(1) for deletion;

[0018] The queue status synchronization module updates the number of tasks, average priority, and NUMA node load of the running queue through atomic operations.

[0019] The context integrity module integrates state validity checks and memory barrier mechanisms to prevent illegal state transitions;

[0020] The wake-up processing module is used to manage the transition of tasks from the blocked state to the ready state, and selects the target CPU queue in combination with NUMA affinity;

[0021] The load calculation module calculates CPU utilization in real time based on the exponential moving average algorithm.

[0022] The threshold judgment module monitors the queue length and triggers a balancing operation based on CPU load.

[0023] The migration evaluation module selects the optimal migration target CPU using a topology cost model.

[0024] The interrupt optimization module implements a lightweight preemption flag during clock interrupts, delaying the full context switch to a safe point.

[0025] Preferably, the skip list operation module supports dynamic hierarchical expansion. When the queue length is ≥1000 tasks, it automatically expands to 8 levels. Short queues adopt a low-level structure to reduce maintenance overhead.

[0026] Preferably, the compensation mechanism of the time slice management module compensates interactive tasks according to the formula: remaining time slice + = used time slice × 0.5, with the upper limit being the original time slice length.

[0027] Preferably, the task allocation module adopts lock-free load balancing, uses trylock instead of blocking lock, and skips the current CPU queue processing when failure occurs.

[0028] Preferably, the inheritance mechanism of the priority management module temporarily elevates the priority of a low-priority task to the level of a high-priority task when a real-time task is blocked.

[0029] Preferably, the wake-up processing module forces the task to run on the CPU specified by the affinity mask, and triggers migration to a legitimate CPU or refuses scheduling if the violation occurs.

[0030] Preferably, the interrupt optimization module only marks the need_resched flag in the clock interrupt, and the actual switching is delayed until the kernel preemptible point is executed;

[0031] The kernel interface module exposes scheduling parameters through / proc / sys / kernel, including real-time task time slice baseline values, interactive priority promotion strategies, and isolated CPU masks.

[0032] Preferably, the task state transition module integrates hunger detection, and low-priority tasks are temporarily promoted to the original value +10 after waiting for more than 200ms;

[0033] The task preemption module can preempt real-time tasks unconditionally, while ordinary tasks must simultaneously meet the conditions of time slice exhaustion and deadline priority.

[0034] Preferably, the context integrity module prohibits direct conversion from RUNNING to EXIT, and requires a transition through the BLOCKED state;

[0035] The queue state synchronization module ensures multi-core access consistency through the RCU mechanism and holds a spinlock on the running queue during updates.

[0036] Preferably, the threshold judgment module triggers load balancing when the queue length is >100 or the CPU utilization is >80%.

[0037] The migration assessment module prioritizes NUMA local nodes and CPUs with a load difference >15% as migration targets, and avoids lock contention through atomic variable checks.

[0038] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0039] 1. This invention uses a skip list data structure and a multi-queue design, which simplifies the scheduling logic and reduces the overhead of task switching. The insertion, deletion, and search operations of the skip list are O(log n) on average, which is better than the red-black tree operations of CFS. Moreover, the scheduler directly uses the task priority for scheduling, avoiding the complex virtual runtime calculations in CFS. In addition, the scheduler has better support for real-time tasks and can respond to high-priority tasks faster, meeting the needs of application scenarios with high real-time requirements. At the same time, the scheduler is specifically optimized for desktop and interactive tasks, which can better adapt to these workloads and improve the user experience. Attached Figure Description

[0040] Figure 1 This is the input / output data flow diagram of the present invention;

[0041] Figure 2 This is a schematic diagram of the functional modules of the present invention;

[0042] Figure 3 This is a schematic diagram of the integrated architecture of the present invention;

[0043] Figure 4 This is a diagram showing the composition of the time slice management module submodules of the present invention;

[0044] Figure 5 This is a diagram showing the composition of the kernel context maintenance and switching module submodules of the present invention;

[0045] Figure 6 This is a diagram showing the composition of the priority management module submodule of the present invention;

[0046] Figure 7 This is a diagram showing the composition of the task preemption module submodule of the present invention;

[0047] Figure 8 This is a diagram showing the composition of the insertion task module submodules of the present invention;

[0048] Figure 9 This is a diagram showing the composition of the task deletion module submodules of the present invention;

[0049] Figure 10 This is a diagram showing the composition of the task selection module submodules of the present invention;

[0050] Figure 11 This is a diagram showing the composition of the task state transition module submodule of the present invention;

[0051] Figure 12 This is a diagram showing the composition of the CPU load monitoring module submodule of the present invention;

[0052] Figure 13 This is a diagram showing the composition of the task allocation module submodule of the present invention. Detailed Implementation

[0053] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0054] An interactive scheduler with dynamic priority skipping, see [link to scheduler]. Figures 1 to 13 It includes a time slice management module, a kernel context maintenance and switching module, a priority management module, a task preemption module, a task insertion module, a task deletion module, a task selection module, a task state transition module, a CPU load monitoring module, a task allocation module, a skip list operation module, a queue state synchronization module, a context integrity module, a wake-up handling module, a load calculation module, a threshold judgment module, a migration evaluation module, and an interrupt optimization module;

[0055] The time slice management module is used to implement time slice initialization, dynamic adjustment, exhaustion check and compensation mechanism, and includes a time slice initialization submodule, a time slice dynamic adjustment submodule, a time slice exhaustion check submodule and a time slice compensation mechanism submodule.

[0056] The kernel context maintenance and switching module is used to save and restore the state of task registers and perform processor core switching. It includes a task switching submodule, a run queue management submodule, a task status tracking submodule, and a scheduling decision submodule.

[0057] The priority management module is used to implement real-time priority mapping, dynamic adjustment and inheritance mechanisms, and includes a real-time priority mapping submodule, a dynamic priority adjustment submodule, a priority inheritance mechanism submodule and a priority compensation strategy submodule.

[0058] The task preemption module is used to trigger preemption logic, and includes a preemption trigger check submodule and a preemption execution submodule;

[0059] The task insertion module is used to insert new tasks into the skip list queue according to priority. It includes a CPU affinity selection submodule, a skip list insertion operation submodule, and a queue status update submodule.

[0060] The task deletion module is used to remove tasks from the queue and release resources, and includes a skip list deletion operation submodule and a resource release management submodule.

[0061] The task selection module is used to select the optimal task from the skip list queue, and includes a candidate task selection submodule, a real-time task priority processing submodule, and a queue status query submodule.

[0062] The task state transition module is used to manage the task state machine and its validity verification. It includes a state validity check submodule, a context saving and recovery submodule, and a state flag update submodule.

[0063] The CPU load monitoring module is used to periodically sample the load of each CPU queue and trigger balancing operations. It includes a load calculation submodule and a trigger threshold judgment submodule.

[0064] The task scheduling module is used to perform cross-CPU task migration, and includes a target CPU evaluation submodule and a migration execution submodule.

[0065] The skip list operation module supports dynamic level adjustment and bidirectional pointer maintenance, ensuring O(log n) time complexity for insertion and O(1) time complexity for deletion;

[0066] The queue status synchronization module updates the number of tasks, average priority, and NUMA node load in the running queue through atomic operations;

[0067] The context integrity module integrates state validity checks and memory barrier mechanisms to prevent illegal state transitions;

[0068] The wake-up processing module manages the transition of tasks from the blocked state to the ready state, and selects the target CPU queue based on NUMA affinity;

[0069] The load calculation module calculates CPU utilization in real time based on the exponential moving average algorithm;

[0070] The threshold judgment module monitors queue length and CPU load to trigger balancing operations;

[0071] The migration evaluation module selects the optimal migration target CPU using a topology cost model;

[0072] The interrupt optimization module implements a lightweight preemption flag in clock interrupts, delaying the full context switch to a safe point.

[0073] Specifically, the skip list operation module supports dynamic hierarchical expansion. When the queue length is ≥1000 tasks, it automatically expands to 8 levels. Short queues adopt a low-level structure to reduce maintenance overhead.

[0074] More specifically, the compensation mechanism of the time slice management module compensates interactive tasks according to the formula: Remaining time slice + = Used time slice × 0.5, with the upper limit being the original time slice length.

[0075] Furthermore, the task allocation module adopts lock-free load balancing, using trylock instead of blocking lock, and skipping the current CPU queue processing when failure occurs.

[0076] Furthermore, the priority management module's inheritance mechanism temporarily elevates the priority of low-priority tasks to the level of high-priority tasks when real-time tasks are blocked.

[0077] It is worth noting that the wake-up processing module forces tasks to run on the CPU specified by the affinity mask, and if this is violated, it will trigger a migration to a legitimate CPU or refuse scheduling.

[0078] It is worth noting that the interrupt optimization module only marks the need_resched flag in the clock interrupt, and the actual switching is delayed until the kernel preemptible point is executed;

[0079] The kernel interface module exposes scheduling parameters through / proc / sys / kernel, including real-time task time slice baselines, interactive priority promotion policies, and isolated CPU masks.

[0080] It is worth mentioning that the task state transition module integrates hunger detection, which temporarily raises the priority of low-priority tasks to the original value +10 after waiting for more than 200ms.

[0081] The task preemption module can preempt real-time tasks unconditionally, while ordinary tasks must simultaneously meet the conditions of time slice exhaustion and deadline priority.

[0082] It is worth noting that the context integrity module prohibits direct conversion from RUNNING to EXIT, and requires a transition through the BLOCKED state;

[0083] The queue status synchronization module ensures multi-core access consistency through the RCU mechanism, holding a spin lock on the running queue during updates. It's worth emphasizing that the threshold judgment module triggers load balancing when the queue length > 100 or CPU utilization > 80%.

[0084] The migration assessment module prioritizes NUMA local nodes and CPUs with a load difference >15% as migration targets, and avoids lock contention through atomic variable checks.

[0085] Example 1

[0086] Time slice management module

[0087] Background: In operating systems, time-slice management is crucial for schedulers to ensure fair task scheduling and system responsiveness. For interactive tasks, appropriate time-slice allocation can significantly improve the user experience.

[0088] Objective: To demonstrate how the time slice management module dynamically adjusts the time slice length based on task type and system load, and to handle time slice exhaustion and compensation mechanisms.

[0089] Specific implementation:

[0090] S1, Time slice initialization

[0091] When a task is first scheduled, the time slice management module initializes the time slice length based on the task type (real-time task or normal task). Real-time tasks typically receive shorter time slices to ensure rapid response.

[0092] S2, Dynamic Adjustment

[0093] When the system load is high, the module will shorten the time slice of ordinary tasks so that more tasks can get a chance to execute; when the system load is low, the time slice will be extended appropriately to reduce context switching overhead.

[0094] S3, Exhaustion Check

[0095] The module continuously tracks the remaining time slice of a task, and when the time slice is exhausted, it triggers the scheduler to reselect a task for execution.

[0096] S4. Compensation Mechanism

[0097] For tasks that are blocked due to waiting for I / O events, the module compensates for a certain time slice when it resumes execution to make up for the execution time loss caused by the blockage.

[0098] The details are shown in the table below:

[0099]

[0100] Example 2

[0101] Priority Management Module

[0102] Background: Priority management is the core of the scheduler's task scheduling strategy. It determines the order of tasks in the scheduling queue, which is especially important for real-time and interactive tasks.

[0103] Objective: To demonstrate how the priority management module implements real-time priority mapping, dynamic adjustment, and inheritance mechanisms.

[0104] Specific implementation:

[0105] S1, Real-time Priority Mapping

[0106] The module maps the priority set by the user for real-time tasks to kernel scheduling weights, ensuring that real-time tasks can unconditionally preempt ordinary tasks.

[0107] S2, Dynamic Adjustment

[0108] The module dynamically adjusts task priorities based on system load and task behavior (such as historical execution time and waiting time). For example, for interactive tasks, if the waiting time is long, the module will increase its priority so that it can be executed faster.

[0109] S3, Priority Inheritance

[0110] When a high-priority task is blocked while waiting for resources, the module will temporarily increase the priority of the low-priority task that holds the resource to prevent priority inversion.

[0111] The details are shown in the table below:

[0112]

[0113] Example 3

[0114] Task preemption module

[0115] Background: Task preemption is the key mechanism for the scheduler to achieve unconditional preemption of real-time tasks and priority scheduling of ordinary tasks. It ensures that high-priority tasks can obtain CPU resources in a timely manner.

[0116] Objective: To demonstrate how the task preemption module triggers the preemption logic, ensuring that high-priority tasks obtain CPU resources in a timely manner.

[0117] Specific implementation:

[0118] S1, Preemption Trigger Check

[0119] The module continuously monitors the task queue and immediately triggers preemption logic when a high-priority task is detected to be ready.

[0120] S2, Preemptive Execution

[0121] This module is responsible for context switching, saving the currently executing task and loading the context of a high-priority task to allocate CPU resources. It also handles cross-core scheduling requests, ensuring that high-priority tasks can execute on the appropriate CPU.

[0122] The details are shown in the table below:

[0123]

[0124] Example 4

[0125] Load balancing module

[0126] Background: Load balancing is an important mechanism for schedulers to optimize task distribution across multi-core processors and improve overall system performance. It ensures a relatively balanced load across CPU cores, preventing some cores from being overloaded while others remain idle.

[0127] Objective: To demonstrate how the load balancing module monitors the load of each CPU queue and optimizes task distribution through a lock-free migration mechanism.

[0128] Specific implementation:

[0129] S1, Load Sampling

[0130] The module periodically collects load information for each CPU core, including queue length and CPU utilization.

[0131] S2, Migration Decision

[0132] Based on the load information, the module decides whether to migrate tasks from one CPU core to another. For example, when the load on a CPU core is too high, the module will choose to migrate some tasks to CPU cores with lower load.

[0133] S3, Lock-free migration

[0134] To ensure the efficiency and safety of the migration process, the module adopts a lock-free migration mechanism to avoid performance degradation caused by lock contention during the migration process.

[0135] As shown in the table below:

[0136]

[0137] Example 5

[0138] Skip list operation module

[0139] Background: Skip lists are an efficient data structure suitable for implementing fast query and maintenance of task queues. In schedulers, skip lists are used to manage task queues, supporting fast task insertion, deletion, and query operations.

[0140] Objective: To demonstrate how the skip list operation module supports dynamic hierarchical adjustment and bidirectional pointer maintenance, ensuring efficient insertion and deletion of tasks.

[0141] Specific implementation:

[0142] S1, Skip list insertion

[0143] When a new task is created, the skip list operation module inserts it into the appropriate position in the skip list according to the task's priority. To maintain the balance and efficiency of the skip list, the module dynamically adjusts the skip list's hierarchy based on the queue length.

[0144] S2, Skip list deletion

[0145] When a task is completed or blocked, the module needs to remove it from the skip list. To ensure the efficiency of the deletion operation, the module uses a two-way pointer maintenance mechanism, which can quickly locate the task node to be deleted and update the pointers of its predecessor and successor nodes.

[0146] S3, Dynamic Hierarchy Adjustment

[0147] The skip list hierarchy may change as tasks are inserted and deleted. The module dynamically adjusts the skip list hierarchy based on the current queue length and task priority distribution to maintain the skip list's efficiency.

[0148]

[0149] Example 6

[0150] Kernel context maintenance and switching module

[0151] Background: Kernel context maintenance and switching is the underlying support for the scheduler to implement task scheduling. It is responsible for saving and restoring the execution environment of tasks, ensuring that tasks can continue to execute on the correct CPU core.

[0152] Objective: To demonstrate how the kernel context maintenance and switching module saves and restores task register states and performs processor core switching.

[0153] Specific implementation:

[0154] S1, Context Preservation

[0155] When a task is preempted or voluntarily relinquishes the CPU, the module is responsible for saving the task's register state, stack pointer, and other critical information so that the task can return to the correct state when it resumes execution.

[0156] S2, Context Recovery

[0157] When a task is selected for execution by the scheduler, the module is responsible for loading the previously saved context information, restoring the task to its state before it was preempted, and continuing execution.

[0158] S3, processor core switching

[0159] In systems that support multi-core processors, the module is also responsible for handling the migration of tasks between different CPU cores, ensuring that tasks can be executed on the appropriate CPU core.

[0160] The details are shown in the table below:

[0161]

[0162] Example 7

[0163] Task state transition module

[0164] Background: Tasks undergo various state transitions during their lifecycle, such as ready, running, blocked, and terminated. The task state transition module manages these state transitions to ensure the legitimacy and consistency of tasks.

[0165] Objective: To demonstrate how the task state transition module manages the task state machine and performs validity checks.

[0166] Specific implementation:

[0167] S1, State Machine Management

[0168] The module defines the state machine of the task, specifying the conditions and paths for transitions between different states. For example, a task can only transition from the ready state to the running state, and cannot directly transition from the ready state to the terminated state.

[0169] S2, Legality Verification

[0170] When a task undergoes a state transition, the module validates the transition request to ensure that the transition conforms to the state machine definition. For example, if a task attempts to transition directly from the running state to the terminated state, the module will reject the request and may log an error.

[0171] The details are shown in the table below:

[0172]

[0173] Example 8

[0174] CPU load monitoring module

[0175] Background: Monitoring CPU load is the basis for the scheduler to perform load balancing and task scheduling. By monitoring the load of each CPU core in real time, the scheduler can make more reasonable scheduling decisions.

[0176] Objective: To demonstrate how the CPU load monitoring module periodically samples the load of each CPU queue and triggers load balancing operations.

[0177] Specific implementation:

[0178] S1, Load Sampling

[0179] The module periodically collects load information for each CPU core, including queue length, CPU utilization, and task waiting time.

[0180] S2, Load Analysis

[0181] The module analyzes the collected load information and calculates the load balance of each CPU core.

[0182] S3, Trigger Equalization

[0183] When an imbalance in CPU load is detected, the module will trigger a load balancing operation to migrate tasks from overloaded CPU cores to less loaded CPU cores.

[0184] The specific attributes are shown in the table below:

[0185]

[0186] The specific steps are as follows:

[0187]

[0188] Example 9

[0189] Task allocation module

[0190] Background: Task allocation is an important means for schedulers to optimize task distribution and improve overall system performance. Through proper task allocation, the load on each CPU core can be relatively balanced, avoiding resource waste.

[0191] Objective: To demonstrate how the task scheduling module performs cross-CPU task migration.

[0192] Specific implementation:

[0193] S1, Migration Decision

[0194] Based on the load information provided by the CPU load monitoring module, the module decides whether it is necessary to migrate a task from one CPU core to another.

[0195] S2, Migration Execution

[0196] The module is responsible for performing task migration operations, including removing tasks from the queue of the source CPU core and inserting them into the queue of the target CPU core.

[0197] S3, Migration Optimization

[0198] To improve migration efficiency, the module will employ optimization techniques such as lock-free data structures and batch migration to reduce performance overhead during the migration process.

[0199] The details are shown in the table below:

[0200]

[0201] Example 10

[0202] Queue status synchronization module

[0203] Background: In multi-core processor systems, the task queue states of each CPU core need to be kept synchronized to ensure that the scheduler can make correct scheduling decisions. The queue state synchronization module is responsible for maintaining the consistency of the task queue states of each CPU core.

[0204] Objective: To demonstrate how the queue status synchronization module updates the number of tasks, average priority, and NUMA node load in the running queue through atomic operations.

[0205] Specific implementation:

[0206] S1, Atomic Operations

[0207] The module uses atomic operations to update information such as the number of tasks in the run queue, average priority, and NUMA node load, ensuring the accuracy and consistency of this information in a concurrent environment.

[0208] S2, Synchronization Mechanism

[0209] The module also defines a synchronization mechanism to ensure that the task queue status of each CPU core can be synchronized in a timely manner when tasks are inserted, deleted, or migrated.

[0210] The specific attributes are shown in the table below:

[0211]

[0212] The specific steps are as follows:

[0213]

[0214]

[0215] Example 11

[0216] Wake-up processing module

[0217] Background: Wake-up processing is a crucial mechanism for the scheduler to respond to external events (such as I / O completion, semaphore release, etc.). When a task is blocked, the wake-up processing module is responsible for transitioning the task from a blocked state to a ready state and inserting it into the run queue.

[0218] Objective: To demonstrate how the wake-up handling module manages the transition of a task from a blocked state to a ready state.

[0219] Specific implementation:

[0220] S1, Event Detection

[0221] The module continuously monitors the occurrence of external events, such as I / O completion and semaphore release.

[0222] S2, Task Awakening

[0223] When a task-related event is detected, the module is responsible for transitioning the task from a blocked state to a ready state and calculating the task's priority and waiting time.

[0224] S3, Insert into the run queue

[0225] The module inserts tasks into appropriate run queues based on their priority and waiting time, so that the scheduler can select the task for execution as soon as possible.

[0226] The attributes are as follows:

[0227]

[0228]

[0229] The module operations are as follows:

[0230]

[0231] Example 12

[0232] Load calculation module

[0233] Background: Load calculation is one of the bases for the scheduler to perform load balancing and task scheduling. By calculating the CPU load in real time, the scheduler can more accurately understand the system's operating status and make more reasonable scheduling decisions.

[0234] Objective: To demonstrate how the load calculation module calculates CPU utilization in real time based on the exponential moving average algorithm.

[0235] Specific implementation:

[0236] S1, Data Acquisition

[0237] The module periodically collects CPU utilization data, including the time percentages in user mode, kernel mode, and idle mode.

[0238] S2, Algorithm Calculation

[0239] The module uses an exponential moving average algorithm to smooth the collected CPU utilization data, resulting in more stable load metrics.

[0240] S3, Result Output

[0241] The module outputs the calculated CPU load metrics to other modules of the scheduler (such as the load balancing module, task allocation module, etc.) so that they can make corresponding scheduling decisions based on the load situation.

[0242] The attributes are as follows:

[0243]

[0244] The operation is as follows:

[0245]

[0246] Example 13

[0247] Threshold determination module

[0248] Background: Threshold determination is a key condition for the scheduler to trigger operations such as load balancing and priority compensation. By setting reasonable thresholds, the scheduler can take appropriate measures in a timely manner when the system load reaches a certain level, ensuring system stability and performance.

[0249] Objective: To demonstrate how the threshold judgment module monitors queue length and triggers CPU load balancing operations.

[0250] Specific implementation:

[0251] S1, Threshold Setting

[0252] The module sets reasonable queue lengths and CPU load thresholds based on the actual situation of the system and the requirements of the scheduling strategy.

[0253] S2, Real-time Monitoring

[0254] The module continuously monitors the task queue length and load of each CPU core.

[0255] S3, Trigger Operation

[0256] When the queue length exceeds the set threshold or the CPU load reaches a certain level, the module will trigger corresponding operations (such as load balancing, priority compensation, etc.) to ensure the stability and performance of the system.

[0257] The attributes are as follows:

[0258]

[0259] The operation is as follows:

[0260]

[0261]

[0262] Example 14

[0263] Migration assessment module

[0264] Background: Selecting the appropriate target CPU core for migration is crucial during task allocation. The migration evaluation module is responsible for assessing the migration cost of each CPU core and selecting the optimal migration target.

[0265] Objective: To demonstrate how the migration assessment module selects the optimal migration target CPU using a topology cost model.

[0266] Specific implementation:

[0267] S1, Cost Model

[0268] The module defines a topology cost model that takes into account factors such as physical distance between CPU cores, cache sharing, and memory access latency.

[0269] S2, Cost Calculation

[0270] During task migration, the module calculates the cost of migrating tasks to each CPU core based on the topology cost model.

[0271] S3, Target Selection

[0272] The module selects the lowest-cost CPU core as the migration target to ensure the execution efficiency and performance of the task after migration.

[0273] The attributes are as follows:

[0274]

[0275]

[0276] The operation is as follows:

[0277]

[0278] Example 15

[0279] Scheduler core processing flow

[0280] Core processing flow:

[0281] S1, Task Creation

[0282] (1) User process initiated

[0283] User processes create new tasks through system calls fork() or exec().

[0284] (2) Kernel initialization

[0285] The kernel allocates a task_struct structure for the new task, which records key information such as task ID, priority, and time slice, and marks the task status as NEW, indicating that the task has been created but is not yet ready.

[0286] (3) Resource allocation

[0287] The kernel allocates necessary resources such as memory space and file descriptors for the new task.

[0288] (4) State transition

[0289] After resource allocation is complete, the task status changes from NEW to READY, indicating that the task is ready for scheduling. The task is then inserted into the run queue of its corresponding priority, waiting for the scheduler to select it for execution.

[0290] S2, Task Scheduling

[0291] (1) Scheduler selects tasks

[0292] The scheduler traverses the run queue and selects the next task to execute based on task priority (by quickly looking up the highest priority task using a skip list data structure). The scheduler is optimized for real-time tasks (SCHED_FIFO / SCHED_RR), allowing real-time tasks to unconditionally preempt currently executing regular tasks.

[0293] (2) Context switching

[0294] The scheduler performs a context switch, saves the context (register values, stack pointer, etc.) of the current task (if it exists), loads the context of the newly selected task, and hands over CPU control to the new task.

[0295] (3) Task execution

[0296] A new task begins execution, its state changes to RUNNING, and it occupies a CPU time slice.

[0297] S3, Time Slice Management

[0298] (1) Time slice calculation

[0299] The time slice length for a normal task is dynamically calculated by sched_latency_ns and the run queue length nr_running (e.g., time_slice = sched_latency_ns / nr_running), aiming to balance task switching overhead and system throughput.

[0300] (2) Time slice expires

[0301] During task execution, the time slice gradually runs out. When the time slice expires, the scheduler changes the task status from RUNNING back to READY, and the task is reinserted into the run queue, waiting for the next scheduling.

[0302] S4, Blocking and Wake-up

[0303] (1) Active blocking

[0304] If a task needs to wait for events such as I / O operation completion or semaphore acquisition during execution, it will actively call the blocking operation, enter the BLOCKED state, and be removed from the run queue to release CPU resources.

[0305] (2) Interrupt wake-up

[0306] When the event a task is waiting for occurs (such as the completion of an I / O operation), the hardware generates an interrupt. In the interrupt handler, the kernel wakes the task from the BLOCKED state, re-inserts it into the run queue, and transitions its state back to READY, waiting for the scheduler to select it for execution.

[0307] S5, Termination Processing

[0308] (1) Mission terminated

[0309] A task can end its lifecycle either through normal termination (execution of all instructions) or forced termination (receiving a kill signal). The task status changes from RUNNING or BLOCKED to EXIT.

[0310] (2) Resource recycling

[0311] The kernel reclaims memory space, file descriptors, and other resources used by the task.

[0312] (3) Subprocess recycling

[0313] If a task has child processes, the parent process needs to reclaim the child processes' resources through the wait() system call to avoid resource leaks.

[0314] As shown in the table below:

[0315] State name Description New (NEW) Task just created (e.g. fork() call), not yet initialized, not schedulable Ready (READY) Task initialized, waiting in run queue for scheduler to pick for execution Running (RUNNING) Task executing on CPU, holding time slice or real-time priority resources Blocked (BLOCKED) Task voluntarily gave up CPU while waiting for resources (e.g. I / O, lock) or events (e.g. signal) Exit (EXIT) Task finished (normal exit or terminated), waiting for kernel to reclaim resources

[0316] In addition, all components designed in this invention are general standard parts or components known to those skilled in the art. Their structures and principles can be learned by those skilled in the art through technical manuals or conventional experimental methods. They can be fully implemented by those skilled in the art, so there is no need to elaborate. The content protected by this invention does not involve improvements to the internal structure and methods.

[0317] The embodiments disclosed in this invention are preferred embodiments, but are not limited thereto. Those skilled in the art can easily understand the spirit of this invention based on the above embodiments and make different extensions and variations, but as long as they do not depart from the spirit of this invention, they are all within the protection scope of this invention.

Claims

1. An interactive scheduler based on a skip list structure, characterized in that, It includes modules for time slice management, kernel context maintenance and switching, priority management, task preemption, task insertion, task deletion, task selection, task state transition, CPU load monitoring, task allocation, skip list operation, queue state synchronization, context integrity, wake-up handling, load calculation, threshold judgment, migration evaluation, and interrupt optimization. The time slice management module is used to implement time slice initialization, dynamic adjustment, exhaustion check and compensation mechanism, and includes a time slice initialization submodule, a time slice dynamic adjustment submodule, a time slice exhaustion check submodule and a time slice compensation mechanism submodule. The kernel context maintenance and switching module is used to save and restore the task register state and perform processor core switching. It includes a task switching submodule, a run queue management submodule, a task status tracking submodule, and a scheduling decision submodule. The priority management module is used to implement real-time priority mapping, dynamic adjustment and inheritance mechanism, and includes a real-time priority mapping submodule, a dynamic priority adjustment submodule, a priority inheritance mechanism submodule and a priority compensation strategy submodule. The task preemption module is used to trigger preemption logic, including a preemption trigger check submodule and a preemption execution submodule; The task insertion module is used to insert new tasks into the skip list queue according to priority, and includes a CPU affinity selection submodule, a skip list insertion operation submodule, and a queue status update submodule. The task deletion module is used to remove tasks from the queue and release resources, and includes a skip list deletion operation submodule and a resource release management submodule. The task selection module is used to select the optimal task from the skip list queue, and includes a candidate task selection submodule, a real-time task priority processing submodule, and a queue status query submodule. The task state transition module is used to manage the task state machine and its validity verification, and includes a state validity check submodule, a context saving and recovery submodule, and a state flag update submodule. The CPU load monitoring module is used to periodically sample the load of each CPU queue and trigger a load balancing operation. It includes a load calculation submodule and a trigger threshold judgment submodule. The task allocation module is used to perform cross-CPU task migration, and includes a target CPU evaluation submodule and a migration execution submodule. The skip list operation module supports dynamic level adjustment and bidirectional pointer maintenance, ensuring O(log n) time complexity for insertion and O(1) for deletion; The queue status synchronization module updates the number of tasks, average priority, and NUMA node load of the running queue through atomic operations. The context integrity module integrates state validity checks and memory barrier mechanisms to prevent illegal state transitions; The wake-up processing module is used to manage the transition of tasks from the blocked state to the ready state, and selects the target CPU queue in combination with NUMA affinity; The load calculation module calculates CPU utilization in real time based on the exponential moving average algorithm. The threshold judgment module monitors the queue length and triggers a balancing operation based on CPU load. The migration evaluation module selects the optimal migration target CPU using a topology cost model. The interrupt optimization module implements a lightweight preemption flag during clock interrupts, delaying the full context switch to a safe point.

2. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The skip list operation module supports dynamic hierarchical expansion. When the queue length is ≥1000 tasks, it automatically expands to 8 levels. Short queues adopt a low-level structure to reduce maintenance overhead.

3. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The compensation mechanism of the time slice management module compensates interactive tasks according to the formula: Remaining time slice + = Used time slice × 0.5, with the upper limit being the original time slice length.

4. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The task allocation module adopts lock-free load balancing, using trylock instead of blocking lock, and skips the current CPU queue processing when failure occurs.

5. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The inheritance mechanism of the priority management module temporarily elevates the priority of a low-priority task to the level of a high-priority task when a real-time task is blocked.

6. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The wake-up processing module forces tasks to run on the CPU specified by the affinity mask, and if this is violated, it triggers migration to a legitimate CPU or refuses scheduling.

7. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The interrupt optimization module only marks the need_resched flag in the clock interrupt, and the actual switching is delayed until the kernel preemptible point is executed; The kernel interface module exposes scheduling parameters through / proc / sys / kernel, including real-time task time slice baseline values, interactive priority promotion strategies, and isolated CPU masks.

8. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The task state transition module integrates hunger detection, and low-priority tasks are temporarily promoted to the original value +10 after waiting for more than 200ms. The task preemption module can preempt real-time tasks unconditionally, while ordinary tasks must simultaneously meet the conditions of time slice exhaustion and deadline priority.

9. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The context integrity module prohibits direct conversion from RUNNING to EXIT; a transition through the BLOCKED state is required. The queue state synchronization module ensures multi-core access consistency through the RCU mechanism and holds a spinlock on the running queue during updates.

10. The interactive scheduler based on a skip list structure as described in claim 1, characterized in that, The threshold judgment module triggers load balancing when the queue length is greater than 100 or the CPU utilization is greater than 80%. The migration assessment module prioritizes NUMA local nodes and CPUs with a load difference >15% as migration targets, and avoids lock contention through atomic variable checks.

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