Method and device for reducing cache consumption

Abstract

The invention provides a method and device for reducing cache consumption, and the method comprises the steps: receiving a registration request from an application program, and enabling the registration request to be used for indicating a buffer region with a specific size; searching a cache pool in an input / output memory management unit IOMMU according to the specific size, and determining whether the cache pool has an IOMMU buffer area matched with the buffer area; and when the buffer pool has the first IOMMU buffer matched with the buffer, returning the first IOMMU buffer to the application program. The method and the device for reducing the cache consumption can achieve the purpose of reducing the consumed time and the computing power of the system.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory access processing techniques. In particular, the present disclosure relates to a method and apparatus for reducing cache consumption. BACKGROUND

[0002] In a smart phone, a direct memory access (DMA) engine often needs to use a large amount of contiguous memory regions. The DMA engine cannot use the memory management unit (MMU) of the CPU and can only access contiguous physical blocks in the physical memory. However, it is difficult for the system to allocate a large amount of contiguous physical blocks in the physical memory. For example, when the system allocates a 60MB physical block in the physical memory, the system can need to sort a large amount of physical memory in the physical memory, thereby causing additional system burden.

[0003] In order to solve these problems, an input / output memory management unit (IOMMU) is designed. The IOMMU maps contiguous input / output virtual addresses (IOVAs) of virtual blocks to non-contiguous physical addresses (PAs) of physical blocks and records the mapping relationship in an IOMMU page table. The DMA engine checks the IOMMU page table through the IOMMU and accesses the physical memory according to the IOVA.

[0004] However, the mapping relationship between the PA and the IOVA needs to be established before each use or release of the buffer. For example, in the worst case, a 16MB buffer will be composed of 4096 non-contiguous 4KB physical blocks. The time and computing power of the system for establishing the mapping relationship will increase by about ten times.

[0005] Therefore, a method and apparatus for reducing cache consumption are needed to cache the mapping relationship between the PA and the IOVA and reduce the time and computing power consumed by the system. SUMMARY

[0006] The following disclosure is merely exemplary in nature and is in no way intended to limit the scope of the application. The disclosure is intended only to illustrate aspects, embodiments, and features of the application. Other aspects, embodiments, and features will become apparent from a review of the following description, the claims, and the appended drawings. That is, the following disclosure is provided by way of example only and is not intended to limit the scope of the claimed subject matter in any way. Indeed, it is intended that the subject matter claimed be determined by the claims and equivalents thereof and further, that the scope of the claims include all technical equivalents. Thus, the following disclosure is not intended to limit the claimed subject matter in any way.

[0007] Therefore, the main purpose of the present disclosure is to provide a method and apparatus for reducing cache consumption to reduce the time and computing power consumed by the system.

[0008] In an embodiment, a method for reducing cache consumption is provided. An input / output memory management unit (IOMMU) of a device can implement the method. The method includes receiving a registration request from an application, wherein the registration request is used to indicate a buffer with a specific size; searching a cache pool in the input / output memory management unit (IOMMU) according to the specific size, and determining whether the cache pool has an IOMMU buffer matching the buffer; and returning a first IOMMU buffer to the application when the cache pool has the first IOMMU buffer matching the buffer.

[0009] In an embodiment, in the cache pool, the first IOMMU buffer has a mapping relationship between a physical address and an input / output virtual address (IOVA), and the application accesses the first IOMMU buffer via the IOMMU according to the mapping relationship.

[0010] In an embodiment, the method further includes: when the cache pool does not have an IOMMU buffer matching the buffer, obtaining a physical block from a physical memory according to the specific size, wherein each physical block has a physical address (PA); mapping non-contiguous PAs corresponding to the physical block to contiguous input / output virtual addresses (IOVAs) in an IOVA buffer pool; and providing the physical block for the application to access according to the contiguous IOVAs.

[0011] In an embodiment, the method further includes: receiving a release request, wherein the release request is used to indicate that the IOMMU releases a second IOMMU buffer; obtaining a score indicator of the second IOMMU buffer; determining whether the score indicator of the second IOMMU buffer is greater than a threshold value; and caching the second IOMMU buffer in the cache pool when the score indicator of the second IOMMU buffer is greater than the threshold value.

[0012] In an embodiment, the method further includes: releasing the second IOMMU buffer when the score indicator of the second IOMMU buffer is not greater than the threshold value.

[0013] In an embodiment, the score indicator of the second IOMMU buffer is related to a size of the second IOMMU buffer and a usage in a period of time.

[0014] In an embodiment, the method further includes: obtaining a best cache block quantity of the first IOMMU buffer; determining whether a current cache block quantity of the first IOMMU buffer exceeds the best cache block quantity of the first IOMMU buffer; and caching the first IOMMU buffer in the cache pool when the current cache block quantity of the first IOMMU buffer does not exceed the best cache block quantity of the first IOMMU buffer.

[0015] In an embodiment, the method further comprises: releasing the first IOMMU buffer when the current number of cache blocks of the first IOMMU buffer exceeds the optimal number of cache blocks of the first IOMMU buffer.

[0016] In an embodiment, the optimal number of cache blocks of the first IOMMU buffer is greater than a maximum number of transient remaining blocks, and the maximum number of transient remaining blocks is equal to a number of cache blocks used by the application program minus a number of cache blocks released by the IOMMU.

[0017] In an embodiment, the method further comprises: receiving a recycling notification, wherein the recycling notification is used to indicate that the IOMMU releases a predetermined number of IOMMU buffers in the cache pool; obtaining a score indicator of each IOMMU buffer; and releasing the IOMMU buffers in ascending order of the score indicators until the number of released IOMMU buffers reaches the predetermined number.

[0018] In an embodiment, the method further comprises: training a model to determine whether each IOMMU buffer in the cache pool needs to be cached or released, wherein the model is based on a convolutional neural network model.

[0019] In an embodiment, an apparatus for reducing cache consumption is provided. The apparatus includes a memory; and an input / output memory management unit (IOMMU) communicatively connected to the memory. The IOMMU contains circuitry to perform the following steps: receiving a registration request from an application program, wherein the registration request is used to indicate a buffer having a specific size; searching a cache pool in the IOMMU according to the specific size, and determining whether the cache pool has an IOMMU buffer matching the buffer; and returning the first IOMMU buffer to the application program when the cache pool has the first IOMMU buffer matching the buffer. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are included to provide a further understanding of the content of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the principles of the present application. It is understood that the drawings are not necessarily to scale. Certain components are shown exaggerated in size or in proportion to other components for the purpose of simplicity and clarity.

[0021] Figure 1 is a block diagram depicting an example computing device for implementing demand paging techniques in I / O devices of the present application.

[0022] Figure 2 is a schematic diagram depicting an example IOMMU page table in an IOMMU and system memory.

[0023] Figure 3 This is a flowchart describing a method for reducing cache consumption according to an embodiment of the present invention.

[0024] Figure 4 This is a flowchart describing a method for releasing the IOMMU buffer according to an embodiment of the present invention.

[0025] Figure 5 This is a flowchart describing a method for releasing the IOMMU buffer according to an embodiment of the present invention.

[0026] Figure 6 This is a flowchart describing a method for reclaiming the IOMMU buffer according to an embodiment of the present invention.

[0027] Figures 7A-7E This is a flowchart illustrating a portion of the IOMMU allocation and merging of IOMMU buffers according to an embodiment of the present invention.

[0028] Figure 8 This is a schematic diagram illustrating the mapping relationship between PA and IOVA according to an embodiment of the present invention. Detailed Implementation

[0029] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements by differences in name, but rather by differences in function. The term "comprising" as used throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" herein includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0030] The following description is for illustrating the general principles of the invention and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.

[0031] The following description is intended to enable those skilled in the art to make and use the invention, and is provided in the context of the patent application and its claims. Various modifications to the embodiments and general principles and features described herein will be apparent to those skilled in the art. Therefore, the invention is not intended to be limited to the embodiments shown, but is accorded the widest scope consistent with the principles and features described herein.

[0032] Figure 1This is a block diagram of an exemplary computing device 100 that can be used to implement the techniques of the present invention for demand paging in I / O devices. The computing device 100 may include, for example, a personal computer, desktop computer, laptop computer, tablet computer, computer workstation, video game platform or console, mobile phone (e.g., cellular or satellite phone), landline phone, internet phone, smartphone, handheld device (such as a portable video game device or personal digital assistant (PDA)), personal music player, video player, display device, television, set-top box, server, intermediate network device, mainframe computer, any mobile device, or any other type of device that processes and / or displays graphical data.

[0033] like Figure 1 As shown in the example, computing device 100 may include a user input interface 104, a central processing unit (CPU) 106, one or more memory controllers 108, system memory 110, a display interface 116, a display 118, and buses 120 and 122. In some cases, Figure 1 All hardware elements shown can be on-chip, for example, in a System-on-Chip (SoC) design. User input interface 104, CPU 106, memory controller 108, and display interface 116 can communicate using bus 20. Memory controller 108 and system memory 110 can also communicate using bus 122. Buses 120 and 122 can be any of various bus architectures, such as third-generation buses (e.g., HyperTransport bus or InfiniBand bus), second-generation buses (e.g., Advanced Graphics Port bus, Peripheral Component Interconnect (PCI) Express bus, or Advanced Scalable Interface (AXI) bus), or other types of buses or device interconnects. It should be noted that... Figure 1 The specific configurations of the bus and communication interfaces between different components shown are merely exemplary, and the techniques of this invention can be implemented using computing devices with other configurations having the same or different components.

[0034] CPU 106 may include a general-purpose or special-purpose processor that controls the operation of computing device 100. A user can provide input to computing device 100 to cause CPU 106 to execute one or more software applications. Software applications executing on CPU 106 may include, for example, an operating system, word processor applications, email applications, spreadsheet applications, media player applications, video game applications, graphical user interface applications, or other programs. A user can provide input to computing device 100 through one or more input devices (not shown), such as a keyboard, mouse, microphone, touchpad, touchscreen, or other input devices connected to computing device 100 via user input interface 104.

[0035] Software applications executing on CPU 106 can include one or more graphics rendering instructions that instruct CPU 106 to render graphics data to display 118. In some examples, the software instructions can conform to a graphics application programming interface (API), such as the Open Graphics Library (OpenGL®) API, the Open Graphics Library Embedded Systems (OpenGL ES) API, the Open Computing Language (OpenCL®) API, the Direct3D API, the X3D API, the RenderMan API, the WebGL API, or any other public or proprietary standard graphics API.

[0036] Memory controller 108 facilitates the transfer of data to and from system memory 110. For example, memory controller 108 can receive memory read and write commands and service such commands with respect to system memory 110 in order to provide memory services to components in computing device 100. Memory controller 108 is communicatively coupled to system memory 110 by memory bus 122. Although memory controller 108 is shown in FIG. 1 as a separate processing module from CPU 106 and system memory 110, in other examples, some or all of the functionality of memory controller 108 can be implemented on CPU 106 and / or system memory 110. Figure 1

[0037] Memory controller 108 can also include one or more memory management units (MMUs), including an input / output memory management unit (IOMMU) for controlling I / O device access (e.g., GPU) to system memory 110. The I / O memory management unit can implement a virtual memory system. The virtual memory space can be divided into a plurality of virtual blocks. The virtual blocks can be contiguous, but the physical blocks in system memory 110 corresponding to the virtual blocks can not be contiguous in system memory 110. A block can be considered the smallest unit that an MMU can manage.

[0038] Figure 2 is a diagram depicting an example IOMMU page table 210 in system memory 110. An IOMMU is generally used to map virtual addresses to physical addresses. IOMMU page table 210 includes four virtual blocks with virtual addresses (IOVA 1-5). It should be understood that IOMMU page table 210 is a virtual construct and is shown in FIG. 2 for ease of understanding. An IOMMU can manage a physical memory space by dynamically allocating and deallocating blocks of physical memory. Figure 2

[0039] In​​​​Figure 2 In particular embodiments, system memory 110 can include physical addresses (PA1-PAm). IOMMU can map contiguous virtual addresses IOVA1-3 in IOMMU page table 210 to non-contiguous physical addresses PA4, PA2, and PA6, respectively.

[0040] System memory 110 can store program modules and / or instructions for execution by CPU 106, and / or data for use by programs executing on CPU 106. For example, system memory 110 can store a window manager application that CPU 106 uses to present a graphical user interface (GUI) on display 118. In addition, system memory 110 can store user applications and application surface data related to the applications. System memory 110 can also store information used and / or generated by other components of computing device 100. System memory 110 can include one or more volatile or non-volatile memories or storage components, such as, for example, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, a magnetic data media or an optical storage media.

[0041] Display interface 116 can configure display 118 to display images represented by rendered image data. In some examples, display interface 116 can include a digital-to-analog converter (DAC) configured to convert digital values to analog signals that display 118 can use. In other examples, display interface 116 can pass digital values directly to display 118 for processing. Display 118 can include a monitor, a television, a projection device, a liquid crystal display (LCD), a plasma display panel, a light-emitting diode (LED) array such as an organic LED (OLED) display, a cathode ray tube (CRT) display, electronic paper, a surface-conduction electron-emitter display (SED), a laser television display, a nanocrystal display, or other type of display unit. Display 118 can be integrated within computing device 100. For example, display 118 can be a screen of a mobile phone. Alternatively, display 118 can be a separate device connected to computing device 100 through a wired or wireless communication link. For example, display 118 can be a computer monitor or a flat-panel display connected to a personal computer through an electrical cable or a wireless link.

[0042] Figure 3 is a flowchart 300 describing a method of reducing cache consumption according to an embodiment of the present invention. In this embodiment, the method is implemented by Figure 1 the IOMMU of computing device 100.

[0043] In step S305, the IOMMU of the computing device receives a registration request from the application, where the registration request is used to indicate a buffer with a specific size.

[0044] In step S310, the IOMMU searches the cache pool in the IOMMU according to the specific size, and determines whether the cache pool has an IOMMU buffer matching the buffer. In one embodiment, when the size of the IOMMU buffer is greater than or equal to the specific size of the buffer, the IOMMU can determine that the IOMMU buffer matches the buffer.

[0045] In response to the cache pool having a first IOMMU buffer matching the buffer (YES in step S310), in step S315, the IOMMU returns the first IOMMU buffer to the application, where the first IOMMU buffer has a mapping relationship between a physical address (PA) and an I / O virtual address (IOVA) in the cache pool, and the application accesses the first IOMMU buffer through the IOMMU according to the mapping relationship.

[0046] Returning to step S310, in response to the cache pool not having an IOMMU buffer matching the buffer (NO in step S310), in step S320, the IOMMU obtains a physical block from the physical memory according to the specific size, where each physical block has a physical address (PA).

[0047] Next, in step S325, the IOMMU maps the non-contiguous PAs corresponding to the physical block to contiguous IOVAs in the IOVA cache pool.

[0048] In step S330, the IOMMU provides the physical block for the application to access according to the contiguous IOVAs.

[0049] Specifically, each IOMMU buffer in the cache pool has its own mapping relationship. When the IOMMU finds an IOMMU buffer matching the buffer, the IOMMU can directly reuse the IOMMU buffer with the mapping relationship. When the IOMMU cannot find an IOMMU buffer matching the buffer in the cache pool, the IOMMU needs to register a new IOMMU buffer and establish a mapping relationship between the PA and the IOVA of the new IOMMU buffer.

[0050] Figure 4 FIG. 4 is a flowchart 400 illustrating a method of releasing an IOMMU buffer according to an embodiment of the present application. In this embodiment, the method is implemented by an IOMMU of a computing device 100. Figure 1

[0051] ​In step S405, the IOMMU of the computing device receives a release request, where the release request is used to instruct the IOMMU to release the second IOMMU buffer.

[0052] Then, in step S410, the IOMMU obtains a score indicator of the second IOMMU buffer, where the score indicator of the second IOMMU buffer is related to a size of the cache buffer and a usage of the second IOMMU buffer in a period of time.

[0053] Next, in step S415, the IOMMU determines whether the score indicator of the second IOMMU buffer is greater than a threshold value.

[0054] In response to the score indicator of the second IOMMU buffer being greater than the threshold value (YES in step S415), in step S420, the IOMMU caches the second IOMMU buffer into the cache pool.

[0055] Back to step S415, in response to the score indicator of the second IOMMU buffer not being greater than the threshold value (NO in step S425), the IOMMU releases the second IOMMU buffer and a mapping relationship between the PA and the IOVA of the second IOMMU buffer.

[0056] For example, when a user uses an application on a computing device, the IOMMU can calculate score indicators of IOMMU buffers used by the application in a period of time. Assuming that the IOMMU buffers used by the application have sizes of 932 KB, 868 KB, 5124 KB, and 4 KB, in a period of 3 minutes, the usage of the 932 KB buffer is 513 KB, the usage of the 868 KB buffer is 347 KB, the usage of the 5124 KB buffer is 352 KB, and the usage of the 4 KB buffer is 391 KB. The score indicators of the 932 KB, 868 KB, 5124 KB, and 4 KB buffers can be represented as follows:

[0057] The score indicator of the 932 KB buffer = 932 * 0.5 + 513 * 0.5 = 722.5

[0058] The score indicator of the 868 KB buffer = 868 * 0.5 + 347 * 0.5 = 607.5

[0059] The score indicator of the 5124 KB buffer = 5124 * 0.5 + 352 * 0.5 = 2378

[0060] The score indicator of the 4 KB buffer = 4 * 0.5 + 391 * 0.5 = 197.5

[0061] wherein 0.5 is the ratio of the buffer size to the usage. The IOMMU can decide whether to cache the IOMMU buffer according to a preset threshold or a dynamic threshold. In this example, the threshold is set to 700, thus the IOMMU caches the 5124KB buffer and the 932KB buffer into the cache pool, and does not release the mapping relationship corresponding to the 5124KB buffer and the 932KB buffer. It should be noted that although the example of 0.5 as the ratio of the buffer size to the usage is taken, the present application should not be limited thereto.

[0062] Figure 5 FIG. 5 is a flowchart 500 illustrating a method of releasing an IOMMU buffer according to an embodiment of the present application. In this embodiment, the method is implemented by the IOMMU of the computing device 100 in FIG. 1. Figure 1

[0063] In step S505, the IOMMU obtains the optimal cache block quantity of the IOMMU buffer, wherein the optimal cache block quantity of the IOMMU buffer is greater than the maximum quantity of the transient remaining blocks, and the maximum quantity of the transient remaining blocks is equal to the cache block quantity used by the application program minus the cache block quantity released by the IOMMU.

[0064] In step S510, the IOMMU determines whether the current cache block quantity of the IOMMU buffer exceeds the optimal cache block quantity of the IOMMU buffer.

[0065] When the current cache block quantity of the IOMMU buffer does not exceed the optimal cache block quantity of the IOMMU buffer (NO in step S510), in step S515, the IOMMU caches the IOMMU buffer into the cache pool.

[0066] Returning to step S510, when the current cache block quantity of the IOMMU buffer exceeds the optimal cache block quantity of the IOMMU buffer (YES in step S510), in step S520, the IOMMU releases the IOMMU buffer. In one embodiment, the IOMMU only releases the cache block quantity exceeding the optimal cache block quantity.

[0067] It should be noted that the flowchart 500 can be triggered when the IOMMU receives the registration request or the release request. For example, the flowchart 500 can be triggered after step S305 in FIG. 3 and step S405 in FIG. 4. Although the IOMMU only determines whether to release or cache one IOMMU buffer in Figure 3 Figure 4 It should be noted that the flowchart 500 can be triggered when the IOMMU receives the registration request or the release request. For example, the flowchart 500 can be triggered after step S305 in FIG. 3 and step S405 in FIG. 4. Although the IOMMU only determines whether to release or cache one IOMMU buffer in Figure 5

[0068] ​​​In another embodiment, the IOMMU can periodically update the score indicator, the optimal cache block number, and the maximum number of transient remaining blocks for each IOMMU buffer in the cache pool to periodically decide whether to release or cache each IOMMU cache buffer.

[0069] In some embodiments, the IOMMU can train a model to find the most suitable size of IOMMU buffer. Since the application uses the IOMMU buffer in a specific scenario, there are obvious rules for the size of the buffer and the transient remaining blocks of the buffer. The IOMMU can train a recognition model to identify the characteristics of the buffer corresponding to the application in various common scenarios, where the characteristics are formed into a feature database. The recognition model can determine which size of buffer is cached into the cache pool according to the feature database. Finally, the IOMMU feeds back the usage rate of the buffer to the recognition model to improve the accuracy of the prediction. In another embodiment, the recognition model is based on a convolutional neural network (CNN) model.

[0070] Figure 6 A flowchart 600 describing a method of recycling IOMMU buffers according to an embodiment of the present application is described. In this embodiment, the method is implemented by the IOMMU of the computing device 100 in Figure 1

[0071] In step S605, the IOMMU receives a recycling notification, where the recycling notification is used to instruct the IOMMU to release a predetermined number of IOMMU buffers in the cache pool.

[0072] Then, in step S610, the IOMMU obtains the score indicator of each IOMMU buffer.

[0073] In step S615, the IOMMU releases the IOMMU buffers in ascending order of the score indicators until the number of released IOMMU buffers reaches the predetermined number.

[0074] As an example, assume that the recycling notification received by the IOMMU instructs the IOMMU to release three IOMMU buffers in the cache pool. The IOMMU calculates and obtains the score indicators of all IOMMU buffers in the cache pool. The IOMMU releases the three IOMMU buffers in ascending order according to the smallest score indicators.

[0075] ​In another embodiment, a user using a computing device can pre-register a large size IOMMU buffer, which can be cached by IOMMU into a cache pool. When an application needs to use a buffer, IOMMU allocates a portion of the IOMMU buffer as the buffer and returns a portion of the IOMMU buffer to the application. After the application uses the portion of the IOMMU buffer, IOMMU merges the portion of the IOMMU buffer back into the large size IOMMU buffer.

[0076] Figures 7A-7E is a flow chart showing IOMMU allocating and merging portions of IOMMU buffer according to an embodiment of the present application.

[0077] In Figure 7A , a user can pre-register an IOMMU buffer with IOMMU, where the IOMMU buffer includes 4096 virtual blocks with virtual addresses (IOVA 1~4096) in IOMMU page table 710, physical memory 720 includes m physical blocks with physical addresses (PA 1~m), and the IOMMU buffer has a mapping relationship between PA and IOVA. For example, IOVA 1 maps to PA 4, IOVA 2 maps to PA 2, IOVA 3 maps to PA 6, and so on.

[0078] In Figure 7B , the virtual blocks with IOVA 1~2 are allocated to an application. In Figure 7C , the virtual block with IOVA 3 is allocated to the application.

[0079] In Figure 7D , the virtual blocks with IOVA 1~2 are returned by the application. In Figure 7E , the virtual block with IOVA 3 is returned by the application.

[0080] Figures 7A-7E The process in is applicable to buffer types with high low latency requirements. When such buffers are placed in the cache pool of IOMMU, IOMMU can set such buffers as the highest scoring indicators to prevent such buffers from being recycled.

[0081] In addition, an input / output memory management unit (IOMMU) can train a model to pre-register IOMMU buffers required by different applications according to a feature database containing the applications and their corresponding features, where the model is based on a convolutional neural network (CNN) model. After a specific application and its features are input to the model, the model calculates an IOMMU buffer size suitable for the specific application and its features. In some embodiments, the features can include a buffer size required by the application and a number of remaining blocks contained in the buffer. The IOMMU can update the training parameters of the model according to the buffer usage results.

[0082] Figure 8 is a schematic diagram showing the mapping relationship between a physical address (PA) and an input / output virtual address (IOVA) according to an embodiment of the present application. The mapping relationship between the physical address and the input / output virtual address can be stored in a cache pool 800.

[0083] For fast searching, the IOMMU can be sorted according to the size of the IOMMU buffer. In an embodiment, the cache pool 800 has a structure of a red-black tree.

[0084] As described above, the method and device for reducing cache consumption in the present application establish a cache pool in the IOMMU for storing the mapping relationship between the physical address and the input / output virtual address of each IOMMU buffer. In this way of storing the mapping relationship, when the application indicates to register the buffer, the IOMMU does not need to perform the actions of applying for the physical address, allocating the input / output virtual address, and establishing the mapping relationship between the physical address and the input / output virtual address; when the application indicates to release the buffer, the IOMMU does not need to perform the actions of releasing the physical address, the input / output virtual address, and the mapping relationship between the physical address and the input / output virtual address. Therefore, the method and device for reducing cache consumption in the present application can achieve the purpose of reducing the time and computing power consumed by the system.

[0085] Any specific order or hierarchy of steps in the processes disclosed herein are meant to be examples. Those of ordinary skill in the art will realize and understand that any specific order or hierarchy of steps can be modified to fall within the scope of the present disclosure. The accompanying method claims present various steps in the example order for purposes of illustration and description. The various steps can be rearranged in their sequence.

[0086] The use of the terms "first", "second", "third", etc. to modify an element in the claims are used merely as labels for the sake of identification and do not imply any priority, order of use, or precedence over one another, or the order of execution of steps in a method.

[0087] While the present disclosure has been disclosed in terms of embodiments thereof, it will be apparent to those skilled in the art that various modifications and improvements can be made to the disclosed embodiments without departing from the scope of the present disclosure.

Claims

1. A method for reducing cache consumption, wherein the method is implemented by a device, comprising: Receive a registration request from the application, where, This registration request is used to indicate a buffer of a specific size; Based on this specific size, search the input / output memory management unit (IOMMU) for a cache pool and determine whether the cache pool has an IOMMU buffer that matches the buffer; and When the cache pool has a first IOMMU buffer that matches the buffer, return the first IOMMU buffer to the application.

2. The method for reducing cache consumption as described in claim 1, characterized in that, In this cache pool, the first IOMMU buffer has a mapping relationship between physical addresses and input / output virtual addresses (IOVAs), and the application accesses the first IOMMU buffer via the IOMMU according to the mapping relationship.

3. The method for reducing cache consumption as described in claim 1, characterized in that, Further includes: When there is no matching IOMMU buffer in the cache pool, physical blocks of that specific size are retrieved from physical memory, where each physical block has a physical address PA. Map the non-contiguous PAs corresponding to the physical block to contiguous IOVAs in the IOVA buffer pool; and Based on the continuous IOVA, the physical block is provided for the application to access.

4. The method for reducing cache consumption as described in claim 1, characterized in that, Further includes: Receive a release request, wherein the release request is used to instruct the IOMMU to release the second IOMMU buffer; Obtain the scoring metrics for the second IOMMU buffer; Determine whether the scoring metric for the second IOMMU buffer is greater than the threshold; and When the score metric of the second IOMMU buffer exceeds the threshold, the second IOMMU buffer is cached in the cache pool.

5. The method for reducing cache consumption as described in claim 4, characterized in that, Further includes: The second IOMMU buffer is released when the score metric in the second IOMMU buffer is not greater than the threshold.

6. The method for reducing cache consumption as described in claim 4, characterized in that, The rating metric for the second IOMMU buffer is related to the size of the second IOMMU buffer and its usage over a period of time.

7. The method for reducing cache consumption as described in claim 1, characterized in that, Further includes: Obtain the optimal number of cache blocks for this first IOMMU buffer; Determine whether the current number of cached blocks in the first IOMMU buffer exceeds the optimal number of cached blocks in the first IOMMU buffer; and When the current number of cached blocks in the first IOMMU buffer does not exceed the optimal number of cached blocks in the first IOMMU buffer, the first IOMMU buffer is cached in the cache pool.

8. The method for reducing cache consumption as described in claim 7, characterized in that, Further includes: The first IOMMU buffer is released when the current number of cached blocks in the first IOMMU buffer exceeds the optimal number of cached blocks in the first IOMMU buffer.

9. The method for reducing cache consumption as described in claim 7, characterized in that, The optimal number of cached blocks in the first IOMMU buffer is greater than the maximum number of transient remaining blocks, and the maximum number of transient remaining blocks is equal to the number of cached blocks used by the application minus the number of cached blocks released by the IOMMU.

10. The method for reducing cache consumption as described in claim 1, characterized in that, Further includes: Receive a recycling notification, wherein the recycling notification is used to instruct the IOMMU to release a predetermined number of IOMMU buffers in the cache pool; Obtain the score metrics for each IOMMU buffer; and The IOMMU buffers are released in ascending order of the scoring metrics until the predetermined number of IOMMU buffers has been released.

11. The method for reducing cache consumption as described in claim 1, characterized in that, Further includes: The model is trained to determine whether each IOMMU buffer in the cache pool needs to be cached or freed. This model is based on a convolutional neural network.

12. An apparatus for reducing cache consumption, comprising: Memory; and The input / output memory management unit (IOMMU) is communicatively connected to the memory, and the IOMMU contains circuitry to perform the following steps: Receive a registration request from the application, where, This registration request is used to indicate a buffer of a specific size; Based on this specific size, search the cache pool within the IOMMU and determine if the cache pool has an IOMMU buffer that matches the buffer; and When the cache pool has a first IOMMU buffer that matches the buffer, return the first IOMMU buffer to the application.

13. The apparatus for reducing cache consumption as described in claim 12, characterized in that, In this cache pool, the first IOMMU buffer has a mapping relationship between physical addresses and input / output virtual addresses (IOVAs), and the application accesses the first IOMMU buffer via the IOMMU according to the mapping relationship.

14. The apparatus for reducing cache consumption as described in claim 12, characterized in that, The circuit further performs the following steps: When there is no matching IOMMU buffer in the cache pool, physical blocks of that specific size are retrieved from physical memory, where each physical block has a physical address PA. Map the non-contiguous PAs corresponding to the physical block to contiguous IOVAs in the IOVA buffer pool; and Based on the continuous IOVA, the physical block is provided for the application to access.

15. The apparatus for reducing cache consumption as described in claim 12, characterized in that, The circuit further performs the following steps: Receive a release request, wherein the release request is used to instruct the IOMMU to release the second IOMMU buffer; Obtain the scoring metrics for the second IOMMU buffer; Determine whether the scoring metric for the second IOMMU buffer is greater than the threshold; and When the score metric of the second IOMMU buffer exceeds the threshold, the second IOMMU buffer is cached in the cache pool.

16. The apparatus for reducing cache consumption as described in claim 15, characterized in that, The circuit further performs the following operations: The second IOMMU buffer is released when the score metric in the second IOMMU buffer is not greater than the threshold.

17. The apparatus for reducing cache consumption as described in claim 15, characterized in that, The rating metric for the second IOMMU buffer is related to the size of the second IOMMU buffer and its usage over a period of time.

18. The apparatus for reducing cache consumption as described in claim 12, characterized in that, The circuit further performs the following operations: Obtain the optimal number of cache blocks for this first IOMMU buffer; Determine whether the current number of cached blocks in the first IOMMU buffer exceeds the optimal number of cached blocks in the first IOMMU buffer; and When the current number of cached blocks in the first IOMMU buffer does not exceed the optimal number of cached blocks in the first IOMMU buffer, the first IOMMU buffer is cached in the cache pool.

19. The apparatus for reducing cache consumption as described in claim 18, characterized in that, The circuit further performs the following operations: The first IOMMU buffer is released when the current number of cached blocks in the first IOMMU buffer exceeds the optimal number of cached blocks in the first IOMMU buffer.

20. The apparatus for reducing cache consumption as described in claim 18, characterized in that, The optimal number of cached blocks in the first IOMMU buffer is greater than the maximum number of transient remaining blocks, and the maximum number of transient remaining blocks is equal to the number of cached blocks used by the application minus the number of cached blocks released by the IOMMU.

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