FPGA-based multi-channel DMA implementation method

Abstract

The application relates to the technical field of big data transmission interaction, and specifically discloses a multi-channel DMA implementation method based on FPGA, unnecessary data carrying and CPU intervention are eliminated by integrating a hardware acceleration unit on a data transmission path, an intelligent scheduler ensures low-delay response of a high-priority channel, the weighted fair queue algorithm is used to guarantee fair bandwidth distribution of all channels, the total throughput is maximized, multiple completed interruptions are combined into one, the interruption response and processing burden of the CPU are greatly reduced, software interaction is simplified, CPU resources are released to process other important tasks, a single high-performance transmission engine is used to serve multiple channels, compared with a scheme in which an independent engine is instantiated for each channel, valuable FPGA logic resources are saved, high-performance and low-delay data transmission is realized, data processing delay is greatly reduced, and the flexibility, scalability and maintainability of the system are enhanced.

Description

Technical Field

[0001] This invention relates to the field of big data transmission and interaction technology, and in particular to a multi-channel DMA implementation method based on FPGA. Background Technology

[0002] Currently, storage capacity and data volume have increased dramatically in the big data field, placing more stringent demands on storage device capacity and read / write speeds. FPGA, as a programmable array with multiple embedded soft cores, is increasingly widely used in high-speed signal applications. Data transfer between FPGA and computer typically uses DMA (Direct Memory Access) to accelerate data transfer and reduce CPU load. The DMA controller can move data from one address space (computer) to another address space (FPGA) without CPU intervention, thus saving CPU resources. However, existing DMA technologies implement one-to-one transfers, resulting in low resource utilization and high requirements for logic resources and hardware costs when transmitting multiple data streams.

[0003] In existing technologies, it is ensured that the PS and PL will not operate on the same BUFF simultaneously during data transmission, enabling multi-channel DMA, multi-address, and highly flexible data transmission. To reduce the occupancy of logic resources during DMA data transmission, only a single DMA channel needs to be time-division multiplexed during multi-channel data transmission, reducing logic development time costs and hardware selection costs.

[0004] However, in existing technologies, DMA only performs a single transfer with one descriptor during data transmission, resulting in processing delays during data transmission, which affects the flexibility of system use and reduces the scalability of the system. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel DMA implementation method based on FPGA, which aims to solve the technical problem that in the prior art, only one descriptor performs a single transmission during the data transmission process, resulting in processing delays in the DMA during data transmission, affecting the flexibility of system use, and reducing the scalability of the system.

[0006] To achieve the above objectives, the present invention employs a multi-channel DMA implementation method based on FPGA, comprising the following steps:

[0007] The design incorporates a reconfigurable descriptor structure, adding opcode, configuration register, and status register fields to the traditional descriptor, enabling the DMA controller to identify and execute simple computational tasks during data transfer.

[0008] Build a centralized transmission engine with an integrated intelligent scheduler;

[0009] Integrate hardware acceleration units on the data path of the DMA engine;

[0010] The doorbell register provides an automatic descriptor chain management mechanism and interrupt aggregation function, automatically updating the status and writing it back to the descriptor after the transmission is completed;

[0011] The register configuration bus enables dynamic reconfiguration and performance monitoring, allowing the CPU to adjust channel parameters and scheduling strategies during runtime.

[0012] The design features a reconfigurable descriptor structure, adding opcode, configuration register, and status register fields to the traditional descriptor. This enables the DMA controller to identify and execute simple computational tasks during data transfer, including the following steps:

[0013] Define a pool of descriptor lists in memory. Each descriptor is a fixed-length data structure containing standard fields such as source address, destination address, transmission length, and pointer to the next descriptor.

[0014] Extend the descriptor structure, add an opcode field, and perform hardware-accelerated operations such as specified CRC calculation, byte order exchange, and data encryption;

[0015] Add a configuration register field to provide initial values ​​and key index parameters for the operation specified by the opcode;

[0016] Add a status register field so that the execution result or error status can be automatically written by the DMA hardware after the transfer is completed;

[0017] The software is responsible for creating and initializing the descriptor list in memory and writing the first address of the list into the corresponding channel register of the DMA controller.

[0018] The intelligent scheduler employs a dynamic arbitration algorithm that combines priority and weighted fair queues to allocate bandwidth to multiple data transmission channels and schedule them to a unified hardware transmission engine.

[0019] The centralized transmission engine for building an integrated intelligent scheduler includes the following steps:

[0020] In the FPGA's BRAM, an independent context buffer area is allocated for each channel;

[0021] Instantiate an AXI4 master controller, a centralized data transmission engine that serves all channels;

[0022] Design an intelligent scheduler to check the readiness status of all enabled channels and filter out candidate channels with data to be processed.

[0023] Configure priority and weight parameters for each channel and initialize its credit counter;

[0024] During scheduler arbitration, the highest priority ready channel is selected first.

[0025] The selected channel loads its context into the centralized transmission engine to perform data transmission, and deducts the channel's credit based on the amount of data transmitted.

[0026] Credit is replenished to all channels according to a weighted ratio when credit is low for a fixed period or when credit is low across all channels.

[0027] In this process, the opcode in the descriptor is triggered in the hardware acceleration unit, and the data is encrypted, verified, and format converted simultaneously during transmission.

[0028] The integration of hardware acceleration units on the data path of the DMA engine includes the following steps:

[0029] The hardware acceleration unit can be inserted as a bypassable module into the write or read data path of the DMA controller.

[0030] The hardware acceleration unit is designed as a pipeline structure and adopts a unified AXI4-Stream interface to seamlessly integrate with high-speed data streams;

[0031] The multiplexer is controlled by the opcode decoding result to dynamically select whether the data path is DC transmission or flows through a specified hardware acceleration unit.

[0032] During data transmission, the source data is first sent to the hardware acceleration unit selected by the opcode for processing, and the processing result is then written to the target address.

[0033] When the transmission task is completed, the results generated by the hardware acceleration unit are automatically written back to the status register field of the current descriptor.

[0034] The automatic management mechanism and interrupt aggregation function of the descriptor chain using the doorbell register automatically updates the status and writes it back to the descriptor after the transmission is completed, including the following steps:

[0035] Implement a state machine inside the DMA controller. The state machine automatically manages the acquisition, processing, state write-back, and loading of the next descriptor.

[0036] Set a completion counter and an interrupt threshold register, and increment the counter by one for each complete descriptor transfer;

[0037] When the value of the completion counter reaches the preset interrupt threshold, the DMA controller sends an interrupt to the CPU to achieve interrupt aggregation.

[0038] Interrupt service routines can process multiple completed tasks in batches by reading the value of the completion counter, significantly reducing interrupt overhead.

[0039] The doorbell register mechanism is designed so that after the software prepares the descriptor list, it only needs to write the channel number to the register to activate DMA transfer.

[0040] The register configuration bus performs dynamic reconfiguration and performance monitoring, allowing the CPU to adjust the parameters of each channel and the scheduling strategy during runtime, including the following steps:

[0041] Design a mapped register file for the DMA controller using the AXI4-Lite interface, including global control, channel-specific, and performance monitoring registers;

[0042] During runtime, the software can dynamically modify the priority, weight, and interrupt threshold of each channel by reading and writing registers, thereby enabling system behavior reconfiguration.

[0043] Integrate a performance monitoring counter for each channel to record its transmitted bytes and number of completion descriptors in real time.

[0044] The software periodically polls the performance monitoring counters to analyze system bandwidth bottlenecks and traffic status of each channel.

[0045] Based on the performance analysis results, the software dynamically adjusts the scheduling parameters, enabling the DMA system to continuously optimize itself and adapt to changing data flow characteristics.

[0046] Specifically, a security identifier field or digital signature field is added to the reconfigurable descriptor structure to store the integrity check code or digital signature of the descriptor. A lightweight security verification module is integrated inside the DMA controller. After the DMA scheduler acquires and loads a descriptor, it first calls the security verification module to perform integrity verification on the key fields of the descriptor according to a preset key or algorithm. If the verification is successful, the normal transmission and processing tasks continue to be executed. If the verification fails, the execution of the descriptor is terminated, a security error code is written to its status register, and an error exception interrupt is initiated to the CPU.

[0047] Specifically, the clock domain of the DMA controller is clearly defined. Its register configuration bus interface typically shares a low-frequency clock domain with the CPU, while the core data transfer engine runs in an independent high-frequency clock domain to pursue high performance. Synchronization circuits are designed on critical paths across clock domains. For control signals from the low-frequency domain to the high-frequency domain, a two-stage register synchronizer is used for synchronization. For status signals from the high-frequency domain to the low-frequency domain, a synchronization mechanism is used for safe transmission. Each channel of the DMA controller adds an independent idle state detection circuit and a clock gating unit. When a channel has no pending descriptors for several consecutive scheduling cycles, its context buffer and related logic clock signals are automatically turned off, putting it into a low-power state. When the channel is activated again by the doorbell register or receives a new descriptor, the scheduler reopens the corresponding clock gating unit to restore normal operation.

[0048] This invention discloses a multi-channel DMA implementation method based on FPGA. The reconfigurable descriptor structure links multiple descriptors to form a dynamically configurable task list. By integrating a hardware acceleration unit on the data transmission path—a dedicated hardware computing circuit integrated into the data path—specific computing tasks are directly completed on the data movement path. This avoids data being moved back and forth between memory and the CPU core, significantly improving energy efficiency and reducing latency. It eliminates unnecessary data movement and CPU intervention, drastically reducing data processing latency. An intelligent scheduler ensures low-latency response for high-priority channels, while a weighted fair queue algorithm guarantees fair bandwidth allocation for all channels, maximizing total throughput. Multiple completion interrupts are merged into one, greatly reducing CPU interrupt response and processing burden. The software only needs to submit the task chain once and implement a "ringing" operation; subsequent work is automatically completed by DMA, simplifying software interaction and freeing up resources. The CPU resources are freed up to handle other important tasks. By modifying the opcodes in the descriptor, the DMA can be commanded to execute new data processing tasks without changing the hardware circuit. It can adapt to new application protocols or data formats. The CPU can dynamically adjust the parameters of each channel at runtime, enabling the system to self-optimize online and flexibly adapt to changing workloads. It uses a single high-performance transmission engine to serve multiple channels, saving valuable FPGA logic resources compared to the solution of instantiating an independent engine for each channel. The computational tasks are handled by dedicated hardware units, which are more energy efficient than software processing, helping to reduce the total power consumption of the system. It achieves high-performance, low-latency data transmission. Furthermore, through the co-design of hardware and software, it provides a highly flexible, efficient, and easy-to-manage DMA architecture, realizing transfer-as-process, significantly reducing system latency and total power consumption, eliminating unnecessary data movement and intermediate storage, greatly reducing data processing latency, and enhancing the system's flexibility, scalability, and maintainability. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart of the steps of a multi-channel DMA implementation method based on FPGA according to the present invention. Detailed Implementation

[0051] Please see Figure 1 This invention provides a multi-channel DMA implementation method based on FPGA, comprising the following steps:

[0052] S1: Design a reconfigurable descriptor structure, adding opcode, configuration register and status register fields to the traditional descriptor, so that the DMA controller can identify and execute simple calculation tasks during data transfer;

[0053] S2: A centralized transmission engine that integrates an intelligent scheduler;

[0054] S3: Integrates hardware acceleration units on the data path of the DMA engine;

[0055] S4: The doorbell register performs automatic management of the descriptor chain and interrupt aggregation, automatically updating the status and writing it back to the descriptor after the transmission is completed;

[0056] S5: The register configuration bus performs dynamic reconfiguration and performance monitoring, allowing the CPU to adjust the parameters of each channel and the scheduling strategy at runtime.

[0057] In this embodiment, the reconfigurable descriptor structure links multiple descriptors to form a dynamically configurable task list. By integrating hardware acceleration units on the data transmission path—dedicated hardware computing circuits integrated into the data path—specific computing tasks are completed directly on the data movement path. This avoids data being moved back and forth between memory and CPU cores, greatly improving energy efficiency and reducing latency. It eliminates unnecessary data movement and CPU intervention, significantly reducing data processing latency. The intelligent scheduler ensures low-latency response for high-priority channels, while a weighted fair queue algorithm guarantees fair bandwidth allocation across all channels, maximizing total throughput. Multiple completion interrupts are merged into one, greatly reducing CPU interrupt response and processing burden. The software only needs to submit the task chain once and implement the "ringing" mechanism. The DMA handles all subsequent tasks automatically, simplifying software interaction and freeing up CPU resources for other important tasks. New data processing tasks can be commanded to the DMA by modifying the opcodes in the descriptor without changing the hardware circuitry. It can adapt to new application protocols or data formats. The CPU can dynamically adjust the parameters of each channel during runtime, enabling the system to self-optimize online and flexibly adapt to changing workloads. Using a single high-performance transmission engine to serve multiple channels saves valuable FPGA logic resources compared to instantiating an independent engine for each channel. Dedicated hardware units handle computational tasks, resulting in higher energy efficiency than software processing, helping to reduce overall system power consumption. It achieves high-performance, low-latency data transmission and, through hardware and software co-design, provides a highly flexible, efficient, and easily manageable DMA architecture.

[0058] Furthermore, the design allows for the reconfiguration of the descriptor structure, adding opcode, configuration register, and status register fields to the traditional descriptor. This enables the DMA controller to identify and execute simple computational tasks during data transfer, including the following steps:

[0059] Define a pool of descriptor lists in memory. Each descriptor is a fixed-length data structure containing standard fields such as source address, destination address, transmission length, and pointer to the next descriptor.

[0060] Extend the descriptor structure, add an opcode field, and perform hardware-accelerated operations such as specified CRC calculation, byte order exchange, and data encryption;

[0061] Add a configuration register field to provide initial values ​​and key index parameters for the operation specified by the opcode;

[0062] Add a status register field so that the execution result or error status can be automatically written by the DMA hardware after the transfer is completed;

[0063] The software is responsible for creating and initializing the descriptor list in memory and writing the first address of the list into the corresponding channel register of the DMA controller.

[0064] In this embodiment, it is determined whether the task can be efficiently implemented by a dedicated, pipelined hardware acceleration unit. After integration into the DMA data path, its overall throughput is close to that of pure data transfer. By adding an opcode field, the DMA controller can directly execute the specified hardware acceleration operation while transferring data, eliminating the extra step of "first transferring to CPU memory and then processing by the CPU" in the traditional solution. This greatly reduces data processing latency, improves overall throughput, and significantly reduces the CPU burden and software overhead. It offloads simple and repetitive task calculations from the CPU to the DMA hardware, freeing the CPU from heavy low-level data processing and improving the utilization efficiency of CPU resources. This reconfigurable descriptor structure is a key bridge connecting software intent and hardware capabilities, upgrading DMA from a simple data transfer channel to an intelligent, programmable data preprocessing engine, bringing comprehensive advantages of high performance, low overhead, high flexibility, and high reliability to the core system.

[0065] Furthermore, the intelligent scheduler employs a dynamic arbitration algorithm that combines priority and weighted fair queues to allocate bandwidth to multiple data transmission channels and schedule them to a unified hardware transmission engine.

[0066] In this implementation, high-priority channels can obtain immediate response and extremely low transmission latency, ensuring strict performance guarantees for data streams with stringent real-time requirements. The weighted fair queue mechanism ensures that all low-priority channels can also obtain a preset bandwidth share according to their weight ratio, thus guaranteeing the fairness of the system.

[0067] Furthermore, the centralized transmission engine for constructing an integrated intelligent scheduler includes the following steps:

[0068] In the FPGA's BRAM, an independent context buffer area is allocated for each channel;

[0069] Instantiate an AXI4 master controller, a centralized data transmission engine that serves all channels;

[0070] Design an intelligent scheduler to check the readiness status of all enabled channels and filter out candidate channels with data to be processed.

[0071] Configure priority and weight parameters for each channel and initialize its credit counter;

[0072] During scheduler arbitration, the highest priority ready channel is selected first.

[0073] The selected channel loads its context into the centralized transmission engine to perform data transmission, and deducts the channel's credit based on the amount of data transmitted.

[0074] Credit is replenished to all channels according to a weighted ratio when credit is low for a fixed period or when credit is low across all channels.

[0075] In this embodiment, a single, wide-bit-width centralized AXI master controller is used instead of multiple independent DMA engines, which greatly saves the valuable logic resources of the FPGA. An independent context cache is configured for each channel in the BRAM, which enables fast saving and restoration of hardware state during channel switching with almost no overhead, ensuring scheduling efficiency. The wide-bit-width high-performance AXI master controller can maximize the use of memory bandwidth and give full play to the performance advantages of the centralized engine, providing a solid foundation for high-throughput data transmission.

[0076] Furthermore, the opcodes in the descriptor are triggered in the hardware acceleration unit, and the data undergoes near-data computation, including encryption, verification, and format conversion, simultaneously during transmission.

[0077] In this implementation, the data is computed synchronously as it flows from source to destination, eliminating the multi-step operation of "first transmitting to memory, then being read and processed by the CPU, and finally being written back to memory" in the traditional architecture. This fundamentally reduces the end-to-end latency of data processing and achieves synchronous optimization of latency, bandwidth, and power consumption.

[0078] Furthermore, integrating the hardware acceleration unit on the data path of the DMA engine includes the following steps:

[0079] The hardware acceleration unit can be inserted as a bypassable module into the write or read data path of the DMA controller.

[0080] The hardware acceleration unit is designed as a pipeline structure and adopts a unified AXI4-Stream interface to seamlessly integrate with high-speed data streams;

[0081] The multiplexer is controlled by the opcode decoding result to dynamically select whether the data path is DC transmission or flows through a specified hardware acceleration unit.

[0082] During data transmission, the source data is first sent to the hardware acceleration unit selected by the opcode for processing, and the processing result is then written to the target address.

[0083] When the transmission task is completed, the results generated by the hardware acceleration unit are automatically written back to the status register field of the current descriptor.

[0084] In this embodiment, the hardware acceleration unit is directly inserted into the data path as a bypassable module. Through pipelined design and a standard stream interface, it is tightly integrated with the DMA engine, enabling data processing and data transmission to occur synchronously within the same clock cycle. The computational latency is perfectly hidden within the transmission time, achieving real-time processing with almost zero overhead. The pipelined hardware acceleration unit can process data once per clock cycle, matching the data throughput capability of the high-speed DMA engine. This avoids the hardware acceleration unit becoming a performance bottleneck and ensures high overall system throughput. It not only successfully endows the DMA channel with computing power but also achieves flexible, efficient, and reliable data processing without sacrificing any transmission performance through ingenious hardware integration.

[0085] Furthermore, the automatic management mechanism and interrupt aggregation function for the descriptor chain automatically update the status and write it back to the descriptor after transmission is completed, reducing software overhead through the doorbell register mechanism, including the following steps:

[0086] Implement a state machine inside the DMA controller. The state machine automatically manages the acquisition, processing, state write-back, and loading of the next descriptor.

[0087] Set a completion counter and an interrupt threshold register, and increment the counter by one for each complete descriptor transfer;

[0088] When the value of the completion counter reaches the preset interrupt threshold, the DMA controller sends an interrupt to the CPU to achieve interrupt aggregation.

[0089] Interrupt service routines can process multiple completed tasks in batches by reading the value of the completion counter, significantly reducing interrupt overhead.

[0090] The doorbell register mechanism is designed so that after the software prepares the descriptor list, it only needs to write the channel number to the register to activate DMA transfer.

[0091] In this implementation, the interrupt aggregation mechanism reduces the original N interrupts required to generate N descriptors to just one interrupt. This significantly reduces the number of context switches, interrupt responses, and interrupt service routines executed by the CPU, freeing it from frequent low-level interrupt handling and allowing it to focus on core business logic. This significantly improves overall system performance. The hardware state machine automatically completes the acquisition, execution, state write-back, and linked list traversal of descriptors, ensuring continuous, efficient, and error-free execution of the entire transmission task chain. By setting interrupt thresholds, the software can precisely control the frequency of interrupt generation, thus flexibly balancing "low latency" and "low overhead," greatly improving the system's efficiency, reliability, and maintainability.

[0092] Furthermore, the dynamic reconfiguration and performance monitoring via the register configuration bus, which allows the CPU to adjust the parameters of each channel and the scheduling strategy at runtime, includes the following steps:

[0093] Design a mapped register file for the DMA controller using the AXI4-Lite interface, including global control, channel-specific, and performance monitoring registers;

[0094] During runtime, the software can dynamically modify the priority, weight, and interrupt threshold of each channel by reading and writing registers, thereby enabling system behavior reconfiguration.

[0095] Integrate a performance monitoring counter for each channel to record its transmitted bytes and number of completion descriptors in real time.

[0096] The software periodically polls the performance monitoring counters to analyze system bandwidth bottlenecks and traffic status of each channel.

[0097] Based on the performance analysis results, the software dynamically adjusts the scheduling parameters, enabling the DMA system to continuously optimize itself and adapt to changing data flow characteristics.

[0098] In this implementation, the software can dynamically adjust key parameters such as priority, weight, and interrupt threshold during system operation, enabling the DMA controller to seamlessly adapt to different working modes or changing data flow characteristics without resetting or restarting. This greatly improves the system's flexibility and adaptability. The integrated performance monitoring counter provides the software with accurate and real-time data on the flow and working status of each channel, transforming the DMA controller from a fixed-function hardware module into an observable, controllable, and optimizable intelligent platform. This provides runtime flexibility and a solid data foundation and hardware support for continuous performance optimization and efficient operation and maintenance of the system.

[0099] Furthermore, a security identifier field or digital signature field is added to the reconfigurable descriptor structure to store the integrity check code or digital signature of the descriptor. A lightweight security verification module is integrated inside the DMA controller. After the DMA scheduler acquires and loads a descriptor, it first calls the security verification module to perform integrity verification on the key fields of the descriptor according to a preset key or algorithm. If the verification is successful, the normal transmission and processing tasks continue to be executed. If the verification fails, the execution of the descriptor is terminated, a security error code is written to its status register, and an error exception interrupt is initiated to the CPU.

[0100] In this implementation, malware is prevented from launching DMA attacks by tampering with the descriptor list. Any unauthorized or tampered descriptors are intercepted before execution, thus transforming the DMA controller from a potential security vulnerability into a trusted security component. The verification process is completed in parallel by the hardware module within the DMA controller, introducing almost no additional latency. This is a high-performance, low-overhead security solution that perfectly meets the dual requirements of performance and security in high-speed data transmission scenarios. It enables the DMA controller to have self-protection and authentication capabilities, improves system security, prevents DMA attacks, and meets the requirements of high-security applications.

[0101] Furthermore, the clock domain of the DMA controller is clearly defined. Its register configuration bus interface typically shares a low-frequency clock domain with the CPU, while the core data transfer engine runs in an independent high-frequency clock domain to pursue high performance. Synchronization circuits are designed on critical paths across clock domains. For control signals from the low-frequency domain to the high-frequency domain, a two-stage register synchronizer is used for synchronization. For status signals from the high-frequency domain to the low-frequency domain, a synchronization mechanism is used for safe transmission. Each channel of the DMA controller adds an independent idle state detection circuit and a clock gating unit. When a channel has no pending descriptors for several consecutive scheduling cycles, its context buffer and related logic clock signals are automatically turned off, putting it into a low-power state. When the channel is activated again by the doorbell register or receives a new descriptor, the scheduler reopens the corresponding clock gating unit to restore normal operation.

[0102] In this implementation, by clearly defining the clock domain, low-speed operations such as register configuration and high-speed operations such as core data transmission are each assigned their own responsibilities, avoiding compromises based on a single clock frequency. An independent idle detection and clock gating unit is added to each channel, achieving fine-grained power management. When a channel is idle, its clock network can be automatically shut down, and dynamic power consumption is reduced to zero. The entry and exit from low-power states are completed automatically and quickly by hardware. The channel can be instantly woken up by events such as activation by the doorbell register or the arrival of a new descriptor, and resume full-speed operation. This wake-up process has extremely low latency and is predictable, which will not affect the real-time performance of the system, ensuring the stability of the system under high-speed operation and significantly optimizing power consumption.

[0103] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A method for implementing multi-channel DMA based on FPGA, characterized in that, Includes the following steps: The design incorporates a reconfigurable descriptor structure, adding opcode, configuration register, and status register fields to the traditional descriptor, enabling the DMA controller to identify and execute simple computational tasks during data transfer. Build a centralized transmission engine with an integrated intelligent scheduler; Hardware acceleration units are integrated into the data path of the DMA engine. The opcode in the descriptor is triggered in the hardware acceleration unit. During data transmission, encryption, verification, and format conversion are performed synchronously. The hardware acceleration unit is inserted into the write or read data path of the DMA controller as a bypassable module. The hardware acceleration unit is designed as a pipeline structure and adopts a unified AXI4-Stream interface to match the seamless integration of high-speed data streams. A multiplexer is used to dynamically select whether the data path is direct transmission or flows through a specified hardware acceleration unit, controlled by the opcode decoding result. During data transmission, the source data is first sent to the hardware acceleration unit selected by the opcode for processing, and the processing result is then written to the target address. At the end of the transmission task, the result generated by the hardware acceleration unit is automatically written back to the status register field of the current descriptor. An automatic descriptor chain management mechanism and interrupt aggregation function are implemented using a doorbell register. After the transfer is completed, the status is automatically updated and written back to the descriptor. A state machine is implemented inside the DMA controller. The state machine automatically manages the acquisition, processing, status writing back, and loading of the next descriptor. A completion counter and an interrupt threshold register are set. The counter is incremented by one for each completed descriptor transfer. When the value of the completion counter reaches the preset interrupt threshold, the DMA controller sends an interrupt to the CPU to realize interrupt aggregation. The interrupt service routine reads the value of the completion counter to process multiple completed tasks in batches, which greatly reduces interrupt overhead. The doorbell register mechanism is designed so that after the software prepares the descriptor chain list, it only needs to write the channel number to the register to activate the DMA transfer. The register configuration bus enables dynamic reconfiguration and performance monitoring, allowing the CPU to adjust channel parameters and scheduling strategies at runtime. A mapped register file is designed for the DMA controller via the AXI4-Lite interface, containing global control, channel-specific, and performance monitoring registers. At runtime, the software can dynamically modify the priority, weight, and interrupt threshold of each channel by reading and writing registers, thereby achieving system behavior reconfiguration. A performance monitoring counter is integrated into each channel to record its transmitted bytes and completion descriptor count in real time. The software periodically polls the performance monitoring counter to analyze system bandwidth bottlenecks and the traffic status of each channel. Based on the performance analysis results, the software dynamically adjusts the scheduling parameters, enabling the DMA system to continuously self-optimize and adapt to changing data flow characteristics.

2. The FPGA-based multi-channel DMA implementation method as described in claim 1, wherein the design allows for a reconfigurable descriptor structure, adding opcode, configuration register, and status register fields to the traditional descriptor, enabling the DMA controller to identify and execute simple computational tasks during data transmission, characterized in that... Includes the following steps: Define a pool of descriptor lists in memory. Each descriptor is a fixed-length data structure containing standard fields such as source address, destination address, transmission length, and pointer to the next descriptor. Extend the descriptor structure, add an opcode field, and perform hardware-accelerated operations such as specified CRC calculation, byte order exchange, and data encryption; Add a configuration register field to provide initial values ​​and key index parameters for the operation specified by the opcode; Add a status register field so that the execution result or error status can be automatically written by the DMA hardware after the transfer is completed; The software is responsible for creating and initializing the descriptor list in memory and writing the first address of the list into the corresponding channel register of the DMA controller.

3. The FPGA-based multi-channel DMA implementation method as described in claim 1, wherein the centralized transmission engine that integrates an intelligent scheduler is characterized in that, The intelligent scheduler uses a dynamic arbitration algorithm that combines priority and weighted fair queues to allocate bandwidth to multiple data transmission channels and schedule them to a unified hardware transmission engine.

4. The FPGA-based multi-channel DMA implementation method as described in claim 1, wherein the centralized transmission engine integrating an intelligent scheduler is characterized in that, Includes the following steps: In the FPGA's BRAM, an independent context buffer area is allocated for each channel; Instantiate an AXI4 master controller, a centralized data transmission engine that serves all channels; Design an intelligent scheduler to check the readiness status of all enabled channels and filter out candidate channels with data to be processed. Configure priority and weight parameters for each channel and initialize its credit counter; During scheduler arbitration, the highest priority ready channel is selected first. The selected channel loads its context into the centralized transmission engine to perform data transmission, and deducts the channel's credit based on the amount of data transmitted. Credit is replenished to all channels according to a weighted ratio when credit is low for a fixed period or when credit is low across all channels.

5. The FPGA-based multi-channel DMA implementation method as described in claim 1, characterized in that, It also includes the following steps: A security identifier field or digital signature field is added to the reconfigurable descriptor structure to store the integrity check code or digital signature of the descriptor. A lightweight security verification module is integrated inside the DMA controller. After the DMA scheduler acquires and loads a descriptor, it first calls the security verification module to perform integrity verification on the key fields of the descriptor according to a preset key or algorithm. If the verification is successful, the normal transmission and processing tasks continue to be executed. If the verification fails, the execution of the descriptor is terminated, a security error code is written to its status register, and an error exception interrupt is initiated to the CPU.

6. The FPGA-based multi-channel DMA implementation method as described in claim 1, characterized in that, It also includes the following steps: The clock domain of the DMA controller is clearly defined. Its register configuration bus interface usually shares a low-frequency clock domain with the CPU, while the core data transfer engine runs in an independent high-frequency clock domain to pursue high performance. Synchronization circuits are designed on the critical path across clock domains. For control signals from the low-frequency domain to the high-frequency domain, a two-stage register synchronizer is used for synchronization. For status signals from the high-frequency domain to the low-frequency domain, a synchronization mechanism is used for safe transmission. Each channel of the DMA controller adds an independent idle state detection circuit and a clock gating unit. When a channel has no pending descriptors for several consecutive scheduling cycles, its context buffer and related logic clock signals are automatically turned off, putting it into a low-power state. When the channel is activated again by the doorbell register or receives a new descriptor, the scheduler reopens the corresponding clock gating unit to restore normal operation.

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