Address configuration method, server and storage medium

Abstract

The invention relates to the technical field of servers, and discloses an address configuration method, a server and a storage medium, the method is applied to the server comprising a mainboard and a backboard, and the method comprises the following steps: the backboard determines whether the mainboard is a target mainboard; if yes, determining whether the mainboard comprises a multi-protocol channel expander or not; if the multi-protocol channel extender is not included, the backboard configures an address for the I2C equipment according to a first configuration mode, and if the multi-protocol channel extender is included, the backboard configures an address for the I2C equipment according to a second configuration mode; the mainboard determines whether the backboard is a target backboard or not, and if yes, whether the mainboard comprises a multi-protocol channel expander or not is determined; if the multi-protocol channel expander is not included, the mainboard configures an address for the VPP of the CPU according to a first configuration mode; and if the multi-protocol channel expander is included, the mainboard configures an address for the VPP according to a second configuration mode. The address configuration efficiency is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of server, in particular to an address configuration method, a server and a storage medium. BACKGROUND

[0002] In recent years, with the rapid development of cloud computing, big data and Internet of Things industries, the demand for data storage of servers has increased dramatically. In order to improve the data storage capacity of the server, a solid state drive (SSD) based on a non-volatile memory express (NVMe) protocol can be used to store data.

[0003] The server includes a mainboard and a backboard, the backboard includes a complex programmable logic device (CPLD), the CPLD includes an inter-integrated circuit (I2C) device, and the NVMe SSD is installed on the backboard and connected with the I2C device in the CPLD. The mainboard includes a central processing unit (CPU), and a virtual pin port (VPP) of the CPU is connected with the I2C device in the CPLD. In order to enable the CPU to manage the NVMe SSD through the VPP, for example, to perform a lighting operation on the NVMe SSD, the addresses of the VPP and the I2C device need to be configured respectively, and only when the addresses of the two match, the CPU can manage the NVMe SSD through the VPP. How to improve the address configuration efficiency of the VPP and the address configuration efficiency of the I2C device is a problem to be solved. SUMMARY

[0004] In view of the above problems, embodiments of the present application provide an address configuration method, a server and a storage medium, which are used to solve the problem that the VPP and the I2C cannot be configured with addresses quickly in the prior art.

[0005] According to an aspect of the embodiments of the present application, a method for address configuration is provided, which is applied to a server including a mainboard and a backboard, the mainboard including a central processing unit (CPU), and the backboard including a complex programmable logic device (CPLD), devices in the CPLD including I2C devices, the method including: in response to the server being connected to a working power supply, the backboard determining whether the mainboard is a target mainboard, and the mainboard determining whether the backboard is a target backboard; if the backboard determines that the mainboard is the target mainboard, the backboard determining whether the mainboard includes a multi-protocol channel extender; if the backboard determines that the mainboard does not include the multi-protocol channel extender, the backboard configuring addresses for the I2C devices according to a preset first configuration mode, and storing the configured addresses in a first register in the backboard; if the backboard determines that the mainboard includes the multi-protocol channel extender, the backboard configuring addresses for the I2C devices according to a preset second configuration mode, and storing the configured addresses in the first register; if the mainboard determines that the backboard is the target backboard, the mainboard determining whether the mainboard includes the multi-protocol channel extender; if the mainboard determines that the mainboard does not include the multi-protocol channel extender, the mainboard configuring addresses for virtual pin ports (VPPs) of the CPU according to the first configuration mode, and storing the configured addresses in a second register in the mainboard, wherein the VPPs of the CPU are connected to the I2C devices, and the addresses stored in the second register match the addresses stored in the first register, so that the CPU can manage external devices connected to the CPLD through the I2C devices; if the mainboard determines that the mainboard includes the multi-protocol channel extender, the mainboard configuring addresses for the VPPs of the CPU according to the second configuration mode, and storing the configured addresses in the second register.

[0006] In an optional mode, the target mainboard includes a platform control extender (PCH), a first general input / output pin of the PCH being connected to a first pull-up resistor, the first general input / output pin being connected to a second general input / output pin of a CPLD in the target backboard; the backboard determining whether the mainboard is the target mainboard includes: the backboard determining whether a level of the second general input / output pin is a high level; if the level of the second general input / output pin is the high level, the backboard determining that the mainboard is the target mainboard.

[0007] In one alternative embodiment, the third general purpose input / output pin of the CPLD in the target backplane is connected to a second pull-up resistor, and the third general purpose input / output pin is connected to the fourth general purpose input / output pin of the PCH in the target motherboard; the motherboard determines whether the backplane is the target backplane by: the motherboard determining whether the level of the fourth general purpose input / output pin is high; if the level of the fourth general purpose input / output pin is high, then the motherboard determines that the backplane is the target backplane.

[0008] In one alternative approach, when the motherboard includes the multi-protocol channel extender, the PCH in the motherboard is connected to the multi-protocol channel extender, and the address of the multi-protocol channel extender is one of a plurality of addresses; the motherboard determines whether it includes the multi-protocol channel extender by: the PCH in the motherboard sending a first command to each of the plurality of addresses; if the PCH receives a first response signal from a device at a certain address in response to receiving the first command, then it is determined that the motherboard includes the multi-protocol channel extender.

[0009] In one alternative embodiment, the motherboard includes a PCH, and before the motherboard determines whether the motherboard includes the multi-protocol channel extender, the method further includes: in response to the server being powered on, the motherboard sets the level of a fifth general-purpose input / output pin of the PCH to a first level; after the motherboard determines whether the motherboard includes the multi-protocol channel extender, the method further includes: if the motherboard determines that the motherboard includes the multi-protocol channel extender, then setting the level of the fifth general-purpose input / output pin to a second level; a sixth general-purpose input / output pin of the CPLD in the backplane is connected to the fifth general-purpose input / output pin; the backplane determining whether the motherboard includes the multi-protocol channel extender includes: the backplane determining whether the level of the sixth general-purpose input / output pin is the second level; if the level of the sixth general-purpose input / output pin is the second level, then the backplane determines that the motherboard includes the multi-protocol channel extender.

[0010] In one optional manner, the motherboard configures an address for the CPU's Virtual Pin Port (VPP) according to the first configuration method, including: the CPU sending a second command to the CPLD via the CPU's VPP to scan the I2C devices in the CPLD connected to the CPU's VPP, wherein the second command includes a first scan address; if the CPU receives a second response signal returned by the I2C device configured with the first scan address, the CPU configures the address of the CPU's VPP to the first scan address according to the first configuration method, updates the first scan address, and proceeds to the step of the CPU sending the second command to the CPLD via the CPU's VPP; if the CPU does not receive the second response signal, the scan ends.

[0011] In one optional embodiment, when the motherboard includes the multi-protocol channel extender, the CPU includes multiple sets of virtual pin ports (VPPs) corresponding to the multiple channels. The motherboard configures addresses for the CPU's VPPs according to the second configuration method, including: the CPU selecting an unselected channel from the multiple channels; the CPU sending a third command to the CPLD through a target VPP in the set of VPPs corresponding to the selected channel, to scan the I2C devices connected to the target VPP in the CPLD, wherein the target VPP is one of the VPPs in that set of VPPs that has not sent the third command to the CPLD. The third command includes a second scan address. If the CPU receives a third response signal returned by the I2C device configured with the second scan address, the CPU configures the address of the target virtual pin port VPP of the channel to the second scan address according to the second configuration method, updates the second scan address, and proceeds to the step of the CPU sending a third command to the CPLD through one of the target virtual pin ports VPPs of the CPU in the group of virtual pin ports VPPs corresponding to the selected channel. If the CPU does not receive the third response signal, it determines whether all of the multiple channels have been selected. If there are still channels that have not been selected, the CPU proceeds to the step of selecting one unselected channel from the multiple channels.

[0012] According to another aspect of the embodiments of this application, a server is provided, including a motherboard and a backplane, the motherboard including a CPU, the backplane including a CPLD, and the server being used to execute the address configuration method described above.

[0013] In one alternative embodiment, the motherboard includes a PCH, a first general purpose input / output pin of the PCH connected to a first pull-up resistor, the first general purpose input / output pin being connected to a second general purpose input / output pin of the CPLD; a third general purpose input / output pin of the CPLD connected to a second pull-up resistor, the third general purpose input / output pin being connected to a fourth general purpose input / output pin of the PCH; and a fifth general purpose input / output pin of the PCH being connected to a sixth general purpose input / output pin of the CPLD.

[0014] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the address configuration method as described above.

[0015] In this embodiment of the application, the motherboard and the backplane can be configured with addresses for VPP and I2C devices independently, thereby improving address configuration efficiency. Since the motherboard and the backplane are configured with addresses in the same way, the addresses configured by the two are matched, so that the motherboard can control the hard drive connected to the backplane through VPP.

[0016] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0017] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1 A schematic diagram of the server structure provided in an embodiment of this application is shown;

[0019] Figure 2 A flowchart illustrating the address configuration method provided in an embodiment of this application is shown;

[0020] Figure 3 It shows Figure 2 A flowchart illustrating the sub-step of step 111. Detailed Implementation

[0021] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein.

[0022] After the CPU's Basic Input Output System (BIOS) and the backplane CPLD are respectively written with the VPP address and I2C device address, the CPU can control external devices (such as hard drives) connected to the backplane via the virtual I2C link. Typically, the backplane engineer configures the I2C device address, and the motherboard engineer configures the VPP address. The I2C device address range is 0x40 to 0x4E, meaning the backplane engineer can configure the I2C device address to any even-numbered address within this range. After the backplane engineer configures the I2C device address, the motherboard engineer needs to obtain the configured address from the backplane engineer, configure the VPP address corresponding to the I2C device, and then solidify it to the CPU via BIOS encoding. However, this address configuration method requires communication between the motherboard engineer and the backplane engineer, and if a different backplane model is replaced, the VPP address needs to be refreshed to match the new I2C device address. This address configuration method may pose version management risks. Other address configuration methods, such as indirectly obtaining the address of the I2C device on the backplane through the Baseboard Management Controller (BMC) and reporting it to the motherboard BIOS, have problems such as complex communication protocols and uncontrollable states of the backplane during software communication.

[0023] To control more hard drives, motherboards may incorporate an IO MUX chip. This IO MUX chip, such as the PCA9544, is a multi-protocol channel expander. It expands a single HP_I2C bus into multiple HP_I2C buses. Internally, the IO MUX chip uses several channels to expand one HP_I2C bus into several HP_I2C buses, and each expanded HP_I2C bus can then control multiple hard drives. After expanding one HP_I2C bus into multiple HP_I2C buses, the corresponding VPPs (Virtual Private Servers) also need to be configured with addresses.

[0024] Configuring addresses without requiring communication between motherboard and backplane engineers will improve address configuration efficiency. However, when configuring addresses separately for VPP and I2C devices, the addresses configured for the VPP and I2C devices must match so that the motherboard can control the NVMe SSD connected to the backplane.

[0025] Based on this, to improve address configuration efficiency, this application proposes an address configuration method. The backplane determines whether the motherboard is the target motherboard. If so, it determines whether the motherboard includes an IO MUX. If the motherboard does not include an IO MUX, the backplane configures the I2C device address according to a preset first configuration method; if the motherboard includes an IO MUX, the backplane configures the I2C device address according to a preset second configuration method. Simultaneously, the motherboard determines whether the backplane is the target backplane. If so, it determines whether the motherboard includes an IO MUX. If the motherboard does not include an IO MUX, the motherboard configures the VPP address according to a preset first configuration method; if the motherboard includes an IO MUX, the motherboard configures the VPP address according to a preset second configuration method. Through this method, the motherboard and backplane can independently configure addresses for the VPP and I2C devices respectively, and the configured addresses match, enabling the motherboard to control the NVMe SSD connected to the backplane via VPP.

[0026] Figure 1 A schematic diagram of the server structure provided in an embodiment of this application is shown. Figure 1As shown, the server includes a motherboard and a backplane. The motherboard includes a CPU, a Platform Controller Hub (PCH), an I / O MUX, and multi-channel I / O (MCIO) slots conforming to the SFF-8654 protocol specification. The backplane includes MCIO slots conforming to the SFF-8654 protocol specification and a CPLD. The CPLD has an I2C link consisting of multiple I2C devices (i.e., I / O Expander devices). The MCIO slots on the motherboard and the backplane are connected via MCIO cables, which carry I2C and general-purpose input / output (GPIO) sideband signals. The MCIO slots on the backplane are connected to the multiple I2C devices in the CPLD. The PCH is connected to the CPU and controlled by the BIOS within the CPU. The CPU and PCH communicate via a Direct Media Interface (DMI) bus. The System Management Bus (SMBUS) module in the PCH (not shown in the figure) is connected to the IO MUX on the motherboard via an SMBUS link. The three GPIO pins of the PCH (GPIO[0], GPIO[1], and GPIO[2]) are connected to the three pins of the CPLD on the backplane via MCIO cables. The CPU is connected to the CPLD via the HP_I2C channel, and the IO MUX is connected between the CPU and the CPLD as a multi-protocol channel extender. If some server motherboards do not include an IO MUX, the CPU is directly connected to the CPLD via the HP_I2C channel. Figure 1 This example only illustrates the case of four external hard drives (e.g., NVMe SSDs) connected to the backplane, and does not limit the number of external hard drives connected to the backplane. In the server provided in this embodiment, the motherboard and backplane jointly execute the address configuration method provided in this application.

[0027] The CPU virtualizes high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) resources as HP_I2C. To achieve this virtualization mapping, a series of registers are configured on the CPU to store the VPP address. The CPLD contains multiple I2C devices for managing the backplane hard drive, each with its own I2C device address. The CPLD also has a series of registers to store these I2C device addresses. Only when the addresses in the CPU's registers and the CPLD's registers are configured correctly according to the mapping relationship can the VPP function properly.

[0028] Each I2C device in a CPLD can control more than one hard drive. Knowing the I2C address of each I2C device allows control of all the hard drives connected to it. The address of each I2C device in the CPLD is stored in a register within the CPLD. Hard drives in different slots are controlled by different I2C devices, and the addresses of these different I2C devices are stored in different registers within the CPLD. The backplane has multiple MCIO slots for connecting MCIO cables to multiple MCIO slots on the motherboard. Each MCIO slot connects to a different I2C device. Multiple PCIe controllers exist within the CPU, and these controllers are virtualized as VPPs. The VPPs connect to the I2C devices in the CPLD and communicate by sending I2C protocol commands to the CPLD. Each VPP has a register within the CPU to store its address, which is the address of the I2C device connected to that VPP. This is how the CPU successfully virtualizes PCIe into a VPP. The VPPs connected to each MCIO slot on the motherboard are also different. In hardware, each VPP is connected to its corresponding MCIO slot on the motherboard. The motherboard's MCIO slot connects to its corresponding MCIO slot on the backplane, and the backplane's MCIO slot connects to its corresponding I2C device. This establishes a hardware connection between the VPP and the I2C device. For VPPs and I2C devices with a hardware connection, the address value in the VPP's CPU register and the address value in the I2C device's CPLD register can be set to the same address value in software. This allows the CPU to successfully establish the HP_I2C path to control the corresponding hard drive.

[0029] It is worth noting that for VPP and I2C devices that are connected in hardware, the address values ​​in the CPU register of the VPP and the CPLD register of the I2C device can be set to address values ​​with a unique mapping relationship in software, so that the CPU can successfully open the HP_I2C path to control the corresponding hard drive.

[0030] Figure 2 A flowchart illustrating the address configuration method provided in an embodiment of this application is shown. This method can be applied to... Figure 1 The server shown. (As shown) Figure 2 As shown, the method includes the following steps:

[0031] Step 101: The backplane determines whether the motherboard is the target motherboard. If not, proceed to step 102; if yes, proceed to step 109.

[0032] In this context, the target motherboard and target backplane refer to the motherboard and backplane configured to execute the address configuration method provided in this application after the server is powered on. For a server, only when the motherboard and backplane in the server are respectively the target motherboard and target backplane can both the motherboard and backplane configure addresses for the VPP and I2C devices according to the preset first configuration method or second configuration method, so as to achieve the purpose of matching the configured VPP address with the I2C address, so that the CPU in the motherboard can manage the hard drive connected to the CPLD through VPP. If the backplane can perform this step, it means that the backplane is the target backplane. Therefore, the backplane determines which method to configure the I2C device address by judging whether the motherboard is the target motherboard. Only when the motherboard and backplane are respectively the target motherboard and target backplane will the corresponding series of registers in the CPU in the target motherboard and the CPLD in the target backplane be filled with address values ​​by default according to the preset first configuration method or second configuration method. Since the address values ​​are filled in the registers of the CPU and CPLD, the CPU can scan the I2C devices on the CPLD through VPP.

[0033] In this embodiment, the first general-purpose input / output pin (i.e., GPIO[0] of PCH) in the target motherboard is connected to a first pull-up resistor to make the level of GPIO[0] of PCH in the target motherboard high, and GPIO[0] of PCH in the target motherboard is connected to the second general-purpose input / output pin (i.e., GPIO[0] of CPLD) in the target backplane. Therefore, in this step, the backplane can determine whether the motherboard is the target motherboard by determining whether the level of GPIO[0] of CPLD is high. If the level of GPIO[0] of CPLD is high, the motherboard is determined to be the target motherboard; otherwise, it is not the target motherboard.

[0034] Step 102: Configure the address for the I2C device on the backplane using the general configuration method.

[0035] If the backplane determines that the motherboard is not the target motherboard, it means that the motherboard has not been configured to execute the address configuration method provided in this application after the server is connected to power, and the motherboard has not pre-stored the first and second configuration methods. Therefore, even if the backplane configures the address for the I2C device according to the first or second configuration method, because the motherboard cannot configure the address for the VPP according to the first or second configuration method, a mismatch may occur between the address configured by the backplane for I2C and the address configured by the motherboard for VPP, resulting in the motherboard being unable to control the hard drive connected to the backplane through VPP. Therefore, in this step, the backplane configures the address for the I2C device according to a general configuration method. The general configuration method can be determined as needed; for example, the general configuration method can be a traditional address configuration method.

[0036] Step 103: The motherboard determines whether the backplane is the target backplane. If not, proceed to step 104; if yes, proceed to step 105.

[0037] This step is similar to step 101. In this embodiment, the third general-purpose input / output pin (i.e., the GPIO[1] of the CPLD in the target backplane) is connected to the second pull-up resistor so that the level of the GPIO[1] of the CPLD in the target backplane is high, and the GPIO[1] of the CPLD in the target backplane is connected to the fourth general-purpose input / output pin (i.e., the GPIO[1] of the PCH in the target motherboard. Therefore, in this step, the motherboard can determine whether the backplane is the target backplane by determining whether the level of the GPIO[1] of the PCH is high. If the level of the GPIO[1] of the PCH is high, then the backplane is determined to be the target backplane.

[0038] Step 104: Configure the VPP address for the motherboard using the general configuration method.

[0039] Steps 103 to 104 are similar to steps 101 to 102. Therefore, the principles and implementation methods of steps 103 to 104 can be referred to steps 103 to 104, and will not be repeated here.

[0040] Step 105: The motherboard determines whether it includes a multi-protocol channel extender. If yes, proceed to step 106; otherwise, proceed to step 107.

[0041] The address of the IO MUX is somewhere between 0xE0 and 0xEF. Therefore, the motherboard can determine whether it includes an IO MUX by checking if there are devices at these addresses. (Reference) Figure 1 Since the PCH and IO MUX are connected via an SMBUS link, the PCH, as the SMBUS master device, can send SMBUS commands (i.e., the first command) to control the SMBUS slave device (i.e., the IO MUX chip). Therefore, the PCH can send SMBUS commands one by one in the address range from 0xE0 to 0xEF. If an SMBUS slave device exists at a certain address, the SMBUS slave device will return an acknowledgment signal after receiving the corresponding SMBUS read command. The PCH can determine the existence of the IO MUX by receiving the acknowledgment signal.

[0042] Since the I / O MUX is located on the motherboard, the backplane cannot directly send SMBUS commands to the I / O MUX to determine whether the motherboard includes an I / O MUX. Because GPIO levels only have two states—low and high—one level can be used to indicate that the motherboard does not have an I / O MUX, and the other level can be used to indicate that the motherboard does have an I / O MUX.

[0043] In this embodiment of the application, in order for the backplane to determine whether the motherboard includes an IO MUX, the GPIO of the PCH is connected to the GPIO of the CPLD, and the motherboard sets the level state of the GPIO of the PCH so that the CPLD can determine whether the motherboard includes an IO MUX based on the level state of the GPIO. For example, if the fifth general-purpose input / output pin of the PCH (i.e., the GPIO[2] of the PCH) is connected to the sixth general-purpose input / output pin of the CPLD (i.e., the GPIO[2] of the CPLD), then the motherboard sets the level state of the GPIO[2] of the PCH so that the CPLD can determine whether the motherboard includes an IO MUX based on the level state of the GPIO[2] of the CPLD.

[0044] In this embodiment, the first level of GPIO[2] indicates that the motherboard does not include an IO MUX, and the second level of GPIO[2] indicates that the motherboard includes an IO MUX. The first level can be either high or low. If the first level is high, the second level is low; if the first level is low, the second level is high.

[0045] After the service is connected to the operating power supply, before the motherboard determines whether the motherboard includes an IO MUX, in order to avoid being affected by the historical level of GPIO[2], the motherboard can first set the level of GPIO[2] of PCH to the first level, that is, the motherboard does not include an IO MUX by default. After the motherboard determines that the motherboard includes an IO MUX, the motherboard then sets the level of GPIO[2] of PCH to the second level. After the motherboard determines that the motherboard does not include an IO MUX, the motherboard does not need to reset the level of GPIO[2] of PCH.

[0046] Therefore, prior to step 105, in this embodiment of the application, the address configuration method further includes: in response to the server being connected to the operating power supply, the motherboard sets the level of GPIO[2] of PCH to the first level.

[0047] Step 106: The motherboard sets the level of the fifth general purpose input / output pin to the second level.

[0048] In this step, after the motherboard executes step 105 and determines that the motherboard includes an IO MUX, the motherboard sets the level of the GPIO[2] of the PCH to the second level.

[0049] Step 107: The backplane determines whether the level of the sixth general purpose input / output pin is the second level. If not, proceed to step 108; if yes, proceed to step 110.

[0050] In this step, the CPLD determines whether the level of CPLD's GPIO[2] is the second level to determine whether the motherboard includes an IO MUX. If the CPLD determines that the level of CPLD's GPIO[2] is not the second level, then the CPLD determines that the motherboard does not include an IO MUX and proceeds to step 108. If the CPLD determines that the level of CPLD's GPIO[2] is the second level, then the CPLD determines that the motherboard includes an IO MUX and proceeds to step 110.

[0051] It is worth noting that, in order for the backplane to accurately determine whether the motherboard includes an IO MUX based on the level of the GPIO[2] of the CPLD, in this embodiment, if the backplane needs to execute step 107 after executing step 101, then the backplane executes step 107 only after a preset time interval. The preset time is longer than or equal to the time required for the motherboard to execute steps 105 to 106, thereby avoiding the situation where the backplane has already determined whether the motherboard includes an IO MUX based on the level of the GPIO[2] of the CPLD before completing step 106. This will prevent the backplane from determining that the motherboard does not include an IO MUX, thus ensuring that the determination result of the backplane is consistent with the actual situation.

[0052] Step 108: The backplane configures the address of the I2C device according to the preset first configuration method and stores the configured address in the first register.

[0053] If both the motherboard and backplane determine that they do not include an I / O MUX, then both the motherboard and backplane configure addresses for the VPP and I2C devices respectively according to the preset first configuration method. As mentioned earlier, the address range for I2C devices is 0x40 to 0x4E. In this step, the address of the I2C device can be set to any even address within the range of 0x40 to 0x4E, as long as all I2C device addresses are distinct. For example, for multiple I2C devices in a CPLD, the addresses can be configured sequentially according to an arithmetic progression starting from a certain address, or a geometric progression starting from a certain address.

[0054] The CPLD includes multiple first registers, with one first register corresponding to each I2C device. Each first register stores the address of its corresponding I2C device. Therefore, in this step, after the backplane configures the addresses of each I2C device according to the first configuration method, the address of each I2C device is stored in the first register corresponding to that I2C device. For example, if the CPLD has six I2C devices, namely E1, E2, E3, E4, E5, and E6, then in this step, the addresses of E1 to E6 can be set to 0x40, 0x42, 0x44, 0x46, 0x48, and 0x4a respectively. The address 0x40 of E1 is stored in the first register CpldReg1 corresponding to E1, and the address 0x42 of E2 is stored in the first register CpldReg2 corresponding to E2. The process for E3 to E6 is similar to that for E1 and E2, and will not be described in detail here.

[0055] Step 109: The motherboard configures the address for VPP according to the first configuration method and stores the configured address in the second register.

[0056] This step is similar to step 108, so the specific implementation method of this step can be referred to step 108.

[0057] It is understandable that if the number of VPPs included in the motherboard exceeds the number of I2C devices included in the CPLD, there may be some idle VPPs (i.e., VPPs not connected to I2C devices in the hardware circuitry). Assigning addresses to these idle VPPs could lead to resource waste. Therefore, to avoid this situation, in this step, preferably, the motherboard assigns VPP addresses according to steps a1 to a2 as follows.

[0058] Step a1: The CPU sends a second command to the CPLD via the VPP to scan the I2C devices in the CPLD that are connected to the VPP.

[0059] In step 106, after the backplane configures the addresses for all I2C devices, the CPU sends a second command to the CPLD via the VPP. The second command includes the first scan address. If the CPLD configures the address of a certain I2C device as the first scan address, the I2C device with the address of the first scan address will return an acknowledgment signal after receiving the second command.

[0060] Step a2: If the CPU receives a second acknowledgement signal from the I2C device configured as the first scan address, the CPU configures the VPP's address as the first scan address according to the first configuration method, updates the first scan address, and proceeds to step a1. If the CPU does not receive an acknowledgement signal, the process ends.

[0061] In this example, the CPU contains 6 Virtual Private Servers (VPPs), and the CPLD contains 6 I2C devices. The 6 VPPs and 6 I2C devices are connected sequentially, one-to-one. The first configuration method uses an arithmetic progression starting at address 0x40. When the CPU executes step a1 for the first time, it sends a first second command to the CPLD through the first VPP. This first second command includes a first first scan address (0x40). After receiving the acknowledgment signal from the I2C device at address 0x40, the CPU configures the address of the first VPP to 0x40 and stores 0x40 in the second register corresponding to that first VPP. When the CPU executes step a1 for the second time, it sends a second second command to the CPLD through the second VPP. This second second command includes a second first scan address (0x42). After receiving the acknowledgment signal from the I2C device at address 0x42, the CPU configures the address of the second VPP to 0x42 and stores 0x42 in the second register corresponding to that second VPP. The way the CPU configures addresses for the other four VPPs is similar to the way it configures addresses for the first VPP, so it will not be described again here.

[0062] If the CPU includes 6 VPPs and the CPLD includes 4 I2C devices, and the first 4 VPPs and 4 I2C devices are connected sequentially, then when the CPU executes step a1 for the 5th time, since the CPU does not receive an acknowledgment signal from the I2C device with address 0x48, it can be determined that there are no I2C devices configured with addresses 0x48 or greater in the CPLD. At this time, the CPU stops executing step a1, ends the process, and no longer configures addresses for the 5th and 6th VPPs.

[0063] Since the CPU does not know what type of backplane is connected to the server, it cannot know how many I2C devices exist or how many VPP addresses need to be configured. Therefore, the CPU scans for the existence of I2C devices while configuring VPP addresses according to preset configuration rules, thereby avoiding configuring addresses for idle VPPs.

[0064] Step 110: The backplane configures the address of the I2C device according to the preset second configuration method and stores the configured address in the first register.

[0065] As mentioned earlier, if the motherboard includes an I / O MUX, then one HP_I2C bus on the motherboard can be expanded into multiple HP_I2C buses. These expanded HP_I2C buses are used to control multiple hard drives. In other words, the CPU includes multiple VPPs corresponding to multiple channels, with one channel corresponding to one VPP, and one VPP containing multiple VPPs. Therefore, when an I2C device on the backplane connects to a VPP on the motherboard, it may be connected to a specific VPP corresponding to a specific channel.

[0066] The CPLD can determine which I2C device in the current backplane is connected to a VPP under different channels based on hardware design and industry standards. For I2C devices connected to different VPPs within the same channel, different addresses need to be configured for each I2C device. However, for I2C devices connected to VPPs in different channels, due to channel differences, the same address can be configured for each I2C device. Therefore, in this step, the backplane can configure addresses for the I2C devices according to the second configuration method. Specifically, when configuring addresses for the I2C devices, the backplane can configure addresses for each group of I2C devices separately. Each group of I2C devices refers to I2C devices connected to a VPP of one channel. When configuring addresses for each group of I2C devices, refer to step 108 and configure addresses for each I2C device in each group according to the first configuration method.

[0067] For example, the CPU includes two sets of VPPs corresponding to two channels. IO MUX channel 1 corresponds to 4 VPPs, which are connected to the 1st to 4th I2C devices in the CPLD. IO MUX channel 2 corresponds to 2 VPPs, which are connected to the 5th to 6th I2C devices in the CPLD. Therefore, the 1st to 4th I2C devices in the CPLD constitute the first group of I2C devices, and the 5th to 6th I2C devices constitute the second group of I2C devices. Thus, in this step, the backplane can refer to step 106 and configure the addresses of each I2C device in each group of I2C devices according to the first configuration method. For example, the backplane can configure the addresses of the 1st to 4th I2C devices as 0x40, 0x42, 0x44, and 0x46 respectively, and the addresses of the 5th to 6th I2C devices as 0x40 and 0x42 respectively.

[0068] Similar to step 108, after configuring the address for the I2C device on the backplane, it is also necessary to store the address of each I2C device in the first register corresponding to that I2C device.

[0069] Step 111: The motherboard configures the address for VPP according to the second configuration method and stores the configured address in the second register.

[0070] This step is similar to step 109. When configuring addresses for VPPs, the motherboard can configure addresses for each VPP in each group of VPPs according to the first configuration method.

[0071] If there are idle VPPs in the VPP corresponding to a certain channel on the motherboard, configuring addresses for these idle VPPs may result in wasted resources. Therefore, to avoid the above situation, in this step, preferably, the motherboard configures VPP addresses according to the following steps.

[0072] Figure 3 It shows Figure 2 A flowchart illustrating the sub-steps of step 111. (See attached flowchart.) Figure 3 As shown in the embodiment of this application, step 111 includes the following steps:

[0073] Step 1111: The CPU selects an unselected channel from multiple channels.

[0074] Step 1112: The CPU sends a third command to the CPLD through a target VPP in a group of VPPs corresponding to the selected channel, in order to scan the I2C devices in the CPLD connected to the target VPP.

[0075] The target VPP is the VPP in this group that has not sent a third command to the CPLD, and the third command includes the second scan address.

[0076] Step 1113: The CPU determines whether it has received a third acknowledgment signal from the I2C device configured as the second scan address. If yes, proceed to step 1114; otherwise, proceed to step 1115.

[0077] Step 1114: The CPU configures the address of the target VPP of the channel to the second scan address according to the second configuration method, updates the second scan address, and then proceeds to step 1112.

[0078] Steps 1112 to 1114 are similar to steps a1 to a2 mentioned above. Therefore, the principles and implementation methods of steps 1112 to 1114 can be referred to steps a1 to a2 mentioned above, and will not be repeated here.

[0079] Step 1115: The CPU determines whether all channels have been selected. If yes, the process ends; otherwise, proceed to step 1111.

[0080] Since the addresses of each I2C device connected to a group of VPPs corresponding to a channel are even-numbered addresses within the range of 0x40 to 0x4E, to determine the total number of I2C devices connected to a group of VPPs, a third command should be sent to the CPLD one by one through the VPP of that channel. Furthermore, the second scan address included in the third command sent to the CPLD by different VPPs corresponding to the same channel should be different. This process continues until the CPU receives no acknowledgment signal from the I2C device, at which point it switches to the next VPP corresponding to the channel to send the third command. In other words, all IO Expander devices under each channel should be scanned. Only after scanning all devices under all channels can the number of VPPs that need to be configured with addresses be determined to ensure that the CPU can properly control all hard disk devices on the backplane.

[0081] For example, the CPU includes two sets of VPPs corresponding to two channels. When the CPU executes step 1111 for the first time, it selects IO MUIX channel 1. When it executes step 1112 for the first time, it sends a third command to the CPLD through the first VPP of IO MUIX channel 1. At this time, the second scan address included in the third command is 0x40. If an acknowledgment signal is received from the I2C device, in step 1114, the CPU configures the address of the first VPP of IO MUIX channel 1 to 0x40, updates the second scan address to 0x42, and returns to step 1112 to send a third command to the CPLD through the second VPP of IO MUIX channel 1. At this time, the second scan address included in the third command is 0x42. If no acknowledgment signal is received from the I2C device, it returns to step 1115. In step 1115, it is determined that multiple channels have not been selected, so it returns to step 1111 to select IO MUIX channel 1. In step 1112, the CPU sends a third command to the CPLD via the first VPP of IOMUIX channel 2. The second scan address included in the third command is 0x40. If an acknowledgment signal is received from the I2C device, in step 1114, the CPU configures the address of the first VPP of IOMUIX channel 2 to 0x40, updates the second scan address to 0x42, and returns to step 1112 to send a third command to the CPLD via the second VPP of IOMUIX channel 2. The second scan address included in the third command is 0x42, and so on.

[0082] In this embodiment of the application, the motherboard and the backplane can be configured with addresses for VPP and I2C devices independently, thereby improving address configuration efficiency. Since the motherboard and the backplane are configured with addresses in the same way, the addresses configured by the two are matched, so that the motherboard can control the hard drive connected to the backplane through VPP.

[0083] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described address configuration method embodiment.

[0084] This application provides a computer program that can be executed by a processor to implement the above-described address configuration method embodiment.

[0085] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described address configuration method embodiment.

[0086] In the several embodiments provided in this application, any function, if implemented as a software functional module / unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the technical solution of this application can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or other electronic device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, the embodiments of this application are not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application.

[0088] It should be noted that the above embodiments are illustrative of this application and not restrictive, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In claims enumerating several means, several units or modules of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

[0089] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An address configuration method applied to a server including a motherboard and a backplane, the motherboard including a central processing unit (CPU), the backplane including a complex programmable logic device (CPLD), and devices in the CPLD including I2C devices, characterized in that, The method includes: In response to the server being connected to a power source, the backplane determines whether the motherboard is the target motherboard, and the motherboard determines whether the backplane is the target backplane; If the backplane determines that the motherboard is the target motherboard, then the backplane determines whether the motherboard includes a multi-protocol channel extender; If the backplane determines that the motherboard does not include the multi-protocol channel extender, then the backplane configures the address for the I2C device according to a preset first configuration method and stores the configured address in the first register in the backplane; If the backplane determines that the motherboard includes the multi-protocol channel extender, the backplane configures the address for the I2C device according to the preset second configuration method and stores the configured address in the first register; If the motherboard determines that the backplane is the target backplane, then the motherboard determines whether the motherboard includes the multi-protocol channel extender; If the motherboard determines that it does not include the multi-protocol channel extender, the motherboard configures an address for the CPU's virtual pin port (VPP) according to the first configuration method and stores the configured address in a second register in the motherboard. The CPU's virtual pin port (VPP) is connected to the I2C device, and the address stored in the second register matches the address stored in the first register, so that the CPU can manage external devices connected to the CPLD through the I2C device. If the motherboard determines that it includes the multi-protocol channel extender, the motherboard configures the address of the virtual pin port (VPP) of the CPU according to the second configuration method and stores the configured address in the second register.

2. The method according to claim 1, characterized in that, The target motherboard includes a platform controller expander (PCH), the first general-purpose input / output pin of the PCH is connected to a first pull-up resistor, and the first general-purpose input / output pin is connected to the second general-purpose input / output pin of the CPLD in the target backplane. The backplane determines whether the motherboard is the target motherboard, including: The backplane determines whether the level of the second general-purpose input / output pin is high. If the level of the second general-purpose input / output pin is high, the backplane determines that the motherboard is the target motherboard.

3. The method according to claim 1, characterized in that, The third general purpose input / output pin of the CPLD in the target backplane is connected to the second pull-up resistor, and the third general purpose input / output pin is connected to the fourth general purpose input / output pin of the PCH in the target motherboard. The motherboard determines whether the backplane is the target backplane, including: The motherboard determines whether the level of the fourth general-purpose input / output pin is high. If the level of the fourth general-purpose input / output pin is high, the motherboard determines that the backplane is the target backplane.

4. The method according to claim 1, characterized in that, When the motherboard includes the multi-protocol channel extender, the PCH in the motherboard is connected to the multi-protocol channel extender, and the address of the multi-protocol channel extender is one of multiple addresses; The motherboard determines whether it includes the multi-protocol channel extender, including: The PCH in the motherboard sends a first command to each of the plurality of addresses one by one; If the PCH receives a first response signal from a device at a certain address in response to receiving the first command, then it is determined that the motherboard includes the multi-protocol channel extender.

5. The method according to claim 1, characterized in that, The motherboard includes a PCH, and before the motherboard determines whether the multi-protocol channel extender is included in the motherboard, the method further includes: In response to the server being powered on, the motherboard sets the level of the fifth general purpose input / output pin of the PCH to the first level; After the motherboard determines whether it includes the multi-protocol channel extender, the method further includes: If the motherboard determines that it includes the multi-protocol channel extender, then the level of the fifth general-purpose input / output pin is set to the second level; The sixth general-purpose input / output pin of the CPLD in the backplane is connected to the fifth general-purpose input / output pin. The backplane determines whether the motherboard includes the multi-protocol channel extender, including: The backplane determines whether the level of the sixth general-purpose input / output pin is the second level; If the level of the sixth general-purpose input / output pin is the second level, then the backplane determines that the motherboard includes the multi-protocol channel extender.

6. The method according to claim 1, characterized in that, The motherboard configures the address of the CPU's virtual pin port (VPP) according to the first configuration method, including: The CPU sends a second command to the CPLD through the CPU's virtual pin port (VPP) to scan the I2C devices in the CPLD that are connected to the CPU's virtual pin port (VPP). The second command includes a first scan address. If the CPU receives a second response signal from the I2C device configured with the first scan address, the CPU configures the address of its virtual pin port (VPP) to the first scan address according to the first configuration method, updates the first scan address, and proceeds to the step of the CPU sending a second command to the CPLD through the CPU's virtual pin port (VPP). If the CPU does not receive the second response signal, the scan ends.

7. The method according to claim 1, characterized in that, When the motherboard includes the multi-protocol channel extender, the CPU includes multiple sets of virtual pin ports (VPPs) corresponding to multiple channels. The motherboard configures addresses for the CPU's VPPs according to the second configuration method, including: The CPU selects an unselected channel from the plurality of channels; The CPU sends a third command to the CPLD through a target virtual pin port VPP in a group of virtual pin ports VPPs corresponding to the selected channel, in order to scan the I2C device in the CPLD connected to the target virtual pin port VPP. The target virtual pin port VPP is a virtual pin port VPP in the group of virtual pin ports VPPs of the CPU that has not sent the third command to the CPLD. The third command includes a second scan address. If the CPU receives a third response signal returned by the I2C device configured as the second scan address, the CPU configures the address of the target virtual pin port VPP of the channel as the second scan address according to the second configuration method, updates the second scan address, and then proceeds to the step of the CPU sending a third command to the CPLD through one of the target virtual pin ports VPPs of the CPU in the group of virtual pin ports VPPs corresponding to the selected channel. If the CPU does not receive the third response signal, it determines whether all of the multiple channels have been selected. If there are still channels that have not been selected among the multiple channels, then the process proceeds to the step where the CPU selects an unselected channel from among the multiple channels.

8. A server comprising a motherboard and a backplane, the motherboard including a CPU, and the backplane including a CPLD, characterized in that, The server is used to execute the address configuration method according to any one of claims 1 to 7.

9. The server according to claim 8, characterized in that, The motherboard includes a PCH, the first general-purpose input / output pin of the PCH is connected to a first pull-up resistor, and the first general-purpose input / output pin is connected to the second general-purpose input / output pin of the CPLD. The third general purpose input / output pin of the CPLD is connected to the second pull-up resistor, and the third general purpose input / output pin is connected to the fourth general purpose input / output pin of the PCH. The fifth general purpose input / output pin of the PCH is connected to the sixth general purpose input / output pin of the CPLD.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the address configuration method according to any one of claims 1 to 7.

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