Bus link layer, on-chip bus, and chip

Abstract

The application provides a bus link layer, an on-chip bus and a chip, relates to the chip design and manufacturing technical field, and comprises an upstream virtual channel distributor used for determining an upstream virtual channel based on credit values of respective virtual channels, an upstream virtual channel memory used for receiving target data sent by an upstream module and storing the target data into a storage space corresponding to the upstream virtual channel, a downstream virtual channel distributor used for determining a downstream virtual channel based on credit values of respective virtual channels, and a downstream virtual channel memory used for storing the target data into a storage space corresponding to the downstream virtual channel and sending the target data to a downstream module. The device provided by the application makes the upstream and downstream modules no longer need to integrate and manage a huge storage array, so that the overall layout and wiring of the chip is more flexible, the timing convergence is also easier, and the design complexity and physical implementation difficulty of the chip are significantly reduced.

Description

Technical Field

[0001] This application relates to the field of chip design and manufacturing technology, and in particular to a bus link layer, on-chip bus, and chip. Background Technology

[0002] High-performance computing is achieved through a high-speed interconnect bus link layer between various modules within the chip. To meet performance, timing, and latency requirements, the bus link layer typically uses Virtual Channel (VC) technology to avoid deadlock and head-of-line blocking, thereby improving bus throughput.

[0003] In the architecture of related technologies, storage units used for caching data are typically integrated into upstream modules that send data or downstream modules that receive data. As chip size increases, the physical distance between modules grows, or the number of data types that need to be supported increases, the capacity of these storage units becomes extremely large. Placing these large storage units in functionally complex upstream and downstream modules results in a huge storage area that severely impacts module layout and routing, increases the difficulty of chip implementation, and makes timing convergence very challenging.

[0004] Therefore, improving the transmission performance of the on-chip bus and reducing the implementation difficulty of the chip have become urgent technical problems to be solved in the industry. Summary of the Invention

[0005] This application provides a bus link layer, an on-chip bus, and a chip to solve the technical problem of how to improve the transmission performance of the on-chip bus and reduce the implementation difficulty of the chip.

[0006] This application provides a bus link layer for transmitting target data between upstream and downstream modules, including:

[0007] An upstream virtual channel allocator, connected to the upstream module, is used to determine the upstream virtual channel corresponding to the target data based on the credit value of each virtual channel in the upstream virtual channel memory.

[0008] An upstream virtual channel memory, connected to the upstream module and the upstream virtual channel allocator, is used to receive target data sent by the upstream module and to store the target data in the storage space corresponding to the upstream virtual channel;

[0009] A downstream virtual channel allocator, connected to the upstream virtual channel memory, is used to determine the downstream virtual channel corresponding to the target data based on the credit value of each virtual channel in the downstream virtual channel memory.

[0010] A downstream virtual channel memory, connected to the upstream virtual channel memory, the downstream virtual channel allocator, and the downstream module, is used to store the target data in the storage space corresponding to the downstream virtual channel and to send the target data to the downstream module.

[0011] The credit value of the virtual channel is used to represent the number of available data buffer units in the virtual channel.

[0012] In some embodiments, the upstream virtual channel memory is further used for:

[0013] When sending the target data of the upstream virtual channel to the downstream virtual channel memory, the data transmission information of the upstream virtual channel is sent to the upstream module;

[0014] The upstream module is configured to: send the target data to the upstream virtual channel in the upstream virtual channel memory and decrease the credit value of the upstream virtual channel; and increase the credit value of the upstream virtual channel based on the received data transmission information of the upstream virtual channel.

[0015] In some embodiments, it also includes:

[0016] An upstream data credit counter, connected to the upstream virtual channel memory and the downstream virtual channel memory, is used to decrease the credit value of the downstream virtual channel when the target data is stored in the downstream virtual channel; and to increase the credit value of the downstream virtual channel when the target data stored in the downstream virtual channel is sent to the downstream module.

[0017] In some embodiments, it also includes:

[0018] A downstream data credit counter, connected to the downstream virtual channel memory and the downstream module, is used to reduce the credit value of the downstream module when the downstream module receives the target data.

[0019] In some embodiments, it also includes:

[0020] An upstream data allocator, connected to the upstream module, the upstream virtual channel memory, and the upstream virtual channel allocator, is used to determine the storage space corresponding to the upstream virtual channel in the upstream virtual channel memory based on the storage space address of the upstream virtual channel sent by the upstream virtual channel allocator, and to send the target data to the storage space corresponding to the upstream virtual channel.

[0021] An upstream multiplexer, connected to the upstream virtual channel memory and the downstream virtual channel memory, is used to arbitrate the target data stored in each virtual channel of the upstream virtual channel memory and send the selected target data to the downstream virtual channel memory.

[0022] In some embodiments, it also includes:

[0023] A downstream data distributor, connected to the upstream virtual channel memory, the downstream virtual channel memory, and the downstream virtual channel distributor, is used to determine the storage space corresponding to the downstream virtual channel in the downstream virtual channel memory based on the storage space address of the downstream virtual channel sent by the downstream virtual channel distributor, and to send the target data to the storage space corresponding to the downstream virtual channel.

[0024] A downstream multiplexer, connected to the downstream virtual channel memory and the downstream module, is used to arbitrate the target data stored in each virtual channel of the downstream virtual channel memory and send the selected target data to the downstream module.

[0025] In some embodiments, it also includes:

[0026] A data register, connected to the upstream virtual channel memory and the downstream virtual channel memory, is used to time the transmission of the target data between the upstream virtual channel memory and the downstream virtual channel memory.

[0027] In some embodiments, it also includes:

[0028] A signal register, connected to the downstream virtual channel memory and the upstream data credit counter, is used to record the data transmission information sent by the downstream virtual channel memory to the upstream data credit counter.

[0029] This application provides an on-chip bus, including the bus link layer described above.

[0030] This application provides a chip including the aforementioned on-chip bus.

[0031] The bus link layer, on-chip bus, and chip provided in this application decouple the massive cache and flow control logic originally belonging to upstream and downstream modules by constructing an independent bus link layer containing two levels of virtual channel memory and corresponding allocators. The upstream virtual channel memory classifies and stores data sent by the upstream module through virtual channels, improving packet header effect and avoiding bus deadlock. The upstream and downstream virtual channel allocators use credit values ​​as a flow control mechanism to ensure orderly and reliable data transmission between the two levels of memory within the bus link layer, improving the transmission performance of the on-chip bus. The downstream virtual channel memory can cache data sent to the downstream module through virtual channels. This eliminates the need for upstream and downstream modules to integrate and manage huge memory arrays, making the overall chip layout and routing more flexible, timing convergence easier, and significantly reducing the design complexity and physical implementation difficulty of the chip. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a virtual channel in related technologies.

[0035] Figure 2 This is one of the structural diagrams of the bus link layer provided in this application.

[0036] Figure 3 This is a schematic diagram of the internal data transmission of the chip provided in this application.

[0037] Figure 4 This is the second schematic diagram of the bus link layer provided in this application.

[0038] Figure 5 This is the third schematic diagram of the bus link layer provided in this application.

[0039] Figure 6 This is the fourth schematic diagram of the bus link layer provided in this application.

[0040] Figure 7 This is the fifth schematic diagram of the bus link layer provided in this application.

[0041] Figure 8This is the sixth schematic diagram of the bus link layer provided in this application.

[0042] Figure 9 This is the seventh schematic diagram of the bus link layer provided in this application.

[0043] Figure 10 This is a schematic diagram of the on-chip bus provided in this application.

[0044] Figure 11 This is a schematic diagram of the chip structure provided in this application. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0046] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps, units, or modules is not necessarily limited to those explicitly listed, but may include other steps, units, or modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0047] In order to improve data throughput and reduce data transmission latency when performing high-performance computing on chips, virtual channels are usually added in various modules inside the chip. This design can avoid bus deadlock problems, solve head-of-line blocking, and improve bus throughput.

[0048] Figure 1 This is a schematic diagram of the structure of a virtual channel in related technologies, such as... Figure 1As shown, the implementation of a virtual channel includes a virtual channel allocator (VC Allocator), a switch allocator (Switch Allocator), a route calculator (RouteComputation), input buffers, and a crossbar switch. Multiple input buffers need to be configured to handle data from different sources. Multiple virtual channels are configured within each input buffer.

[0049] In this architecture, input buffers for caching data are typically integrated within the upstream module sending data or the downstream module receiving data. As chip size increases, the physical distance between modules grows, or the number of data types to be supported increases, the capacity of these storage units becomes extremely large. Placing these large storage units within complex upstream and downstream modules results in a huge storage area that severely impacts module layout and routing, making timing convergence very difficult (data signal transmission speed cannot meet the preset clock frequency requirements).

[0050] In order to address the shortcomings of related technologies, Figure 2 This is one of the structural diagrams of the bus link layer provided in this application, such as... Figure 2 As shown, the bus link layer 200 is used to transmit target data between the upstream module 100 and the downstream module 300, including:

[0051] The upstream virtual channel allocator 210, connected to the upstream module 100, is used to determine the upstream virtual channel corresponding to the target data based on the credit value of each virtual channel in the upstream virtual channel memory.

[0052] The upstream virtual channel memory 220 is connected to the upstream module 100 and the upstream virtual channel allocator 210, and is used to receive target data sent by the upstream module and store the target data in the storage space corresponding to the upstream virtual channel.

[0053] The downstream virtual channel allocator 230 is connected to the upstream virtual channel memory 220 and is used to determine the downstream virtual channel corresponding to the target data based on the credit value of each virtual channel in the downstream virtual channel memory.

[0054] The downstream virtual channel memory 240 is connected to the upstream virtual channel memory 220, the downstream virtual channel allocator 230 and the downstream module 300, and is used to store target data in the storage space corresponding to the downstream virtual channel and to send target data to the downstream module.

[0055] The credit value of a virtual channel is used to represent the number of data buffer units available in the virtual channel.

[0056] Specifically, Figure 3 This is a schematic diagram of the internal data transmission of the chip provided in this application, as shown below. Figure 3 As shown, the various modules within the chip transmit data via an on-chip bus. These modules include storage modules, computing modules, and other functional modules. Each module connects to a node on the on-chip bus, and data transmission is handled by the bus link layer between the nodes.

[0057] An upstream module refers to the source module for data transmission, while a downstream module refers to the destination module. Different functional modules within a chip require extensive data exchange. For example, a computation module, acting as an upstream module, may need to send processed data to downstream modules such as a storage module. The transmitted data, referred to as target data in this application, can be any form of digital information, such as computation instructions, pixel data, network data packets, or any other data that needs to be transmitted across modules.

[0058] In this embodiment, the bus link layer, as an independent and modular functional entity, is positioned between the upstream and downstream modules, separating the storage function and related control logic in the data transmission link from the upstream and downstream modules. The bus link layer includes an upstream virtual channel allocator, an upstream virtual channel memory, a downstream virtual channel allocator, and a downstream virtual channel memory.

[0059] The upstream virtual channel memory is connected to the upstream module and serves as the first-level buffer for target data entering the bus link layer from the upstream module, storing the target data. The upstream virtual channel memory is internally divided into multiple virtual channels. A virtual channel is a logical channel that allows multiple independent data streams to share the same physical link. Each virtual channel has its own independent storage space. Physically, the storage space can be implemented using static random access memory or any other suitable on-chip storage technology. The capacity of the upstream virtual channel memory can be configured according to specific application scenarios (such as bandwidth requirements, latency sensitivity, etc.), for example, based on the number of virtual channels required by the upstream module to send target data, the data bit width, and the data buffer size corresponding to each virtual channel. When the upstream module needs to send target data, it first sends the data to the upstream virtual channel memory.

[0060] The virtual channels within the upstream virtual channel memory can form a one-dimensional or multi-dimensional storage space for storing data from different sources or of different types. In a specific embodiment, these virtual channels can constitute... OK Two-dimensional storage space of columns, M is a natural number.

[0061] The upstream virtual channel allocator dynamically selects and allocates a suitable virtual channel (i.e., the upstream virtual channel) for the target data about to enter the upstream virtual channel memory. The allocation is based on the credit value of each virtual channel in the upstream virtual channel memory. In this embodiment, the credit value quantitatively represents the number of currently available data buffer units in a virtual channel. A data buffer unit is used to temporarily store a data unit (the size of the data unit can be set as needed, such as bits or bytes). For example, if a virtual channel's data buffer size is 16 data buffer units (the maximum credit value is 16), and 5 data buffer units have been used (5 data units are stored), then the number of available data buffer units is 11, and the corresponding credit value is 11. A credit value of 0 indicates that the virtual channel is full and cannot receive new data. Therefore, by monitoring the credit values ​​of each virtual channel in the upstream virtual channel memory, the upstream virtual channel allocator ensures that target data is only allocated to virtual channels with available space, thereby avoiding data overflow and loss.

[0062] In one specific embodiment, the upstream virtual channel allocator can parse the data source and data type of the target data sent by the upstream module, determine the upstream virtual channel where the target data needs to be stored based on the credit value of each virtual channel, and output the storage space address of the upstream virtual channel.

[0063] Similarly, the downstream portion of the bus link layer also contains corresponding components. The downstream virtual channel memory is connected to the upstream virtual channel memory and the downstream module, serving as a second-level buffer before target data leaves the bus link layer and enters the downstream module. Internally, it is also divided into multiple virtual channels with independent storage spaces. The downstream virtual channel memory receives target data forwarded from the upstream virtual channel memory and sends it to the downstream module. The capacity of the downstream virtual channel memory can be configured according to specific application scenarios (such as bandwidth requirements, latency sensitivity, etc.), for example, determined by the number of virtual channels required for the downstream module to receive target data, the data bit width, and the data buffer size corresponding to each virtual channel.

[0064] The virtual channels within the downstream virtual channel memory can form one-dimensional or multi-dimensional storage space for storing data from different sources or of different types. In a specific embodiment, these virtual channels can constitute... OK Two-dimensional storage space of columns, P is a natural number.

[0065] The downstream virtual channel allocator manages data transfer from the upstream virtual channel memory to the downstream virtual channel memory. When a virtual channel in the upstream virtual channel memory has target data ready for forwarding, the downstream virtual channel allocator selects and allocates a virtual channel with sufficient space (this virtual channel is the downstream virtual channel) based on the credit value of each virtual channel in the downstream virtual channel memory. This process also uses the credit value as a flow control mechanism to ensure orderly and reliable data transmission between the two levels of memory within the bus link layer.

[0066] The bus link layer provided in this application decouples the massive cache and flow control logic originally belonging to upstream and downstream modules by constructing an independent bus link layer containing two levels of virtual channel memory and corresponding allocators. The upstream virtual channel memory classifies and stores data sent by the upstream module through virtual channels, improving packet header effect and avoiding bus deadlock. The upstream and downstream virtual channel allocators use credit values ​​as a flow control mechanism to ensure orderly and reliable data transmission between the two levels of memory within the bus link layer, improving the transmission performance of the on-chip bus. The downstream virtual channel memory can cache data sent to the downstream module through virtual channels. This eliminates the need for upstream and downstream modules to integrate and manage huge memory arrays, making the overall chip layout and routing more flexible, timing convergence easier, and significantly reducing the design complexity and physical implementation difficulty of the chip.

[0067] In some embodiments, the upstream virtual channel memory is also used for:

[0068] When sending the target data of the upstream virtual channel to the downstream virtual channel memory, send the data transmission information of the upstream virtual channel to the upstream module;

[0069] The upstream module is configured to: send target data to the upstream virtual channel in the upstream virtual channel memory and decrease the credit value of the upstream virtual channel; and increase the credit value of the upstream virtual channel based on the data transmission information received from the upstream virtual channel.

[0070] Specifically, when target data stored in an upstream virtual channel in the upstream virtual channel memory is successfully sent to the downstream virtual channel memory, it means that one or more data buffer units of the upstream virtual channel's storage space are released. In this case, the upstream virtual channel memory generates and sends a data transmission message for the upstream virtual channel to the upstream module.

[0071] The data transmission message is used to notify the upstream module that previously occupied data buffer units are now available. In one specific embodiment, the data transmission message can be a data packet containing the number of data buffer units that have been released.

[0072] Correspondingly, the upstream module is configured to coordinate the credit mechanism. Internally, the upstream module maintains a local credit value for each upstream virtual channel it might use. The initial value of this credit value is equal to the maximum number of data cache units in the corresponding virtual channel.

[0073] The upstream module sends target data to the upstream virtual channel in the upstream virtual channel memory and decrements the credit value of the upstream virtual channel. The decrease in credit value is proportional to the number of data buffer units required to receive the target data. For example, when the upstream module needs to send one unit of target data to a virtual channel in the upstream virtual channel memory, the upstream module first checks whether the credit value corresponding to that virtual channel is greater than zero. If it is greater than zero, the upstream module sends the target data and simultaneously decrements the credit value by one. This operation can be understood as "consuming" one credit. If the credit value is zero, the upstream module pauses sending data to that virtual channel and waits for the credit to be returned.

[0074] When the upstream module receives data transmission information from the upstream virtual channel memory, it increments the corresponding virtual channel's credit value based on the information's content. The increase in credit value is proportional to the number of data buffer units that need to be released to transmit the target data. For example, if the data transmission information determines that a virtual channel needs to release one data buffer unit, the credit value of that virtual channel is incremented by one. This operation can be understood as "returning" one credit unit.

[0075] The bus link layer provided in this application embodiment ensures that the data transmission rate of the upstream module matches the receiving and forwarding capabilities of the bus link layer, thereby effectively preventing buffer overflow and data loss caused by excessively fast data injection, guaranteeing high data transmission throughput, and realizing full utilization of bus bandwidth.

[0076] In some embodiments, it also includes:

[0077] An upstream data credit counter, connected to both the upstream and downstream virtual channel storage, is used to decrease the credit value of the downstream virtual channel when target data is stored in the downstream virtual channel, and to increase the credit value of the downstream virtual channel when target data stored in the downstream virtual channel is sent to the downstream module.

[0078] Specifically, Figure 4 This is the second schematic diagram of the bus link layer provided in this application, as shown below. Figure 4 As shown, the upstream data credit counter 250 is connected to the upstream virtual channel memory 220 and the downstream virtual channel memory 240.

[0079] It should be noted that this counter is named the upstream data credit counter because its main function is to provide credit information about the available space in the downstream part (i.e., the downstream virtual channel memory) to the upstream part of the bus link layer (i.e., the upstream virtual channel memory and its forwarding logic). In physical implementation, this counter can be an independent hardware module containing a set of counter units, each corresponding to a virtual channel in the downstream virtual channel memory, used to independently track the credit value of that virtual channel.

[0080] When target data is successfully forwarded from the upstream virtual channel memory and received by the downstream virtual channel memory and stored in a downstream virtual channel, the upstream data credit counter decrements the credit value of that downstream virtual channel. This process is typically triggered by a control signal associated with a write operation to the downstream virtual channel memory. For example, whenever a data cell is written to a virtual channel in the downstream virtual channel memory, a valid write signal notifies the upstream data credit counter to decrement the credit value corresponding to that virtual channel by one. This operation accurately reflects that a data buffer cell in the downstream virtual channel is occupied, and the available space is reduced.

[0081] Once the target data stored in the downstream virtual channel memory is successfully sent to the downstream module, the data buffer unit occupied by that data is released. At this time, the upstream data credit counter increments the credit value of the corresponding downstream virtual channel. This operation is typically triggered by a control signal (which could be a data transmission message) associated with a read operation from the downstream virtual channel memory. For example, whenever a data unit is read from a virtual channel in the downstream virtual channel memory and sent to the downstream module, the downstream virtual channel memory sends a data transmission message to notify the upstream data credit counter to increment the credit value corresponding to that virtual channel, indicating that a data buffer unit has become available again.

[0082] The bus link layer provided in this application manages the data flow between the two-level memory through an upstream data credit counter. This enables the data forwarding behavior of the upstream virtual channel memory to accurately match the receiving capability of the downstream virtual channel memory, thereby ensuring that the data transmitted within the bus link layer will not be lost due to instantaneous rate mismatch. This greatly enhances the reliability of data transmission and achieves full-bandwidth data transmission.

[0083] In some embodiments, it also includes:

[0084] The downstream data credit counter, connected to the downstream virtual channel memory and the downstream module, is used to reduce the credit value of the downstream module when the downstream module receives the target data.

[0085] Specifically, Figure 5 This is the third schematic diagram of the bus link layer structure provided in this application, as shown below. Figure 5 As shown, the downstream data credit counter 260 is connected to the downstream virtual channel memory 240 and the downstream module 300.

[0086] The downstream data credit counter manages the data flow from the downstream virtual channel memory at the bus link layer to the final destination downstream module. The downstream data credit counter controls the data transmission behavior of the downstream virtual channel memory by tracking the available space in the downstream module's input buffer.

[0087] It is important to understand that reducing the credit value of the downstream module in this embodiment refers to reducing the credit value maintained internally by the downstream data credit counter, which corresponds to the receiving buffer capacity of the downstream module. Physically, this downstream data credit counter can be located within the bus link layer as part of its egress control logic. The downstream module can also have a virtual channel memory containing multiple virtual channels for storing target data. Correspondingly, the credit value managed by the downstream data credit counter is the credit value of each virtual channel in the downstream module.

[0088] When data in the downstream virtual channel memory is selected by arbitration and prepared to be sent to the downstream module, its transmission logic first checks the corresponding credit value in the downstream data credit counter. Data will only be sent if the credit value is greater than zero. Once the downstream module confirms receipt of the target data (i.e., the data has successfully crossed the interface), the downstream data credit counter will decrement the credit value. This operation indicates that the input buffer unit of the downstream module has been occupied.

[0089] After processing the data in its input buffer, the downstream module releases the corresponding data buffer. Then, it sends a credit return signal (which could be data processing information) to the bus link layer. Upon receiving this credit return signal, the downstream data credit counter increments its internal credit value accordingly. In this way, the credit value dynamically and accurately reflects the real-time receiving capability of the downstream module.

[0090] The bus link layer provided in this application embodiment manages the output of target data from the bus link layer to the downstream module by setting a downstream data credit counter. This ensures that the data transmission rate of the bus link layer is strictly limited by the actual receiving and processing capabilities of the downstream module, thereby effectively avoiding data loss due to data congestion at the bus exit and guaranteeing the reliability and efficiency of the entire on-chip network data transmission.

[0091] In some embodiments, it also includes:

[0092] The upstream data allocator, connected to the upstream module, the upstream virtual channel memory, and the upstream virtual channel allocator, is used to determine the storage space corresponding to the upstream virtual channel in the upstream virtual channel memory based on the storage space address of the upstream virtual channel sent by the upstream virtual channel allocator, and send the target data to the storage space corresponding to the upstream virtual channel.

[0093] The upstream multiplexer, connected to the upstream and downstream virtual channel memories, is used to arbitrate the target data stored in each virtual channel of the upstream virtual channel memory and send the selected target data to the downstream virtual channel memory.

[0094] Specifically, Figure 6 This is the fourth schematic diagram of the bus link layer structure provided in this application, as shown below. Figure 6 As shown, the bus link layer also includes an upstream data distributor 221 and an upstream multiplexer 222.

[0095] The upstream data distributor can be implemented using a data selector. The upstream data distributor connects to the upstream module, the upstream virtual channel memory, and the upstream virtual channel distributor.

[0096] When an upstream module has target data to send, the upstream virtual channel allocator selects an available upstream virtual channel based on a credit value. Simultaneously, the upstream virtual channel allocator generates a corresponding memory address and sends this address to the upstream data allocator. This memory address can be a write pointer to a specific memory location, a chip select signal to enable a specific memory bank, or any control signal that uniquely identifies the physical memory location corresponding to the selected virtual channel. Upon receiving this address, the upstream data allocator establishes a path from the upstream module to the upstream virtual channel's memory, ensuring that subsequently arriving target data can be accurately written into the allocated virtual channel.

[0097] An upstream multiplexer can be implemented using an arbitration logic unit and a multiplexer. The upstream multiplexer is connected to both the upstream and downstream virtual channel memories.

[0098] The upstream virtual channel memory may contain target data to be forwarded in multiple virtual channels. At this point, these virtual channels will send requests to the upstream multiplexer. The upstream multiplexer then selects the target data of one virtual channel from all requests for transmission, based on a preset arbitration strategy (e.g., round-robin arbitration, fixed-priority arbitration, etc.).

[0099] The bus link layer provided in this application embodiment ensures the orderliness and accuracy of data writing by the upstream data allocator, while the upstream multiplexer enables fair and efficient scheduling of data reading, enhancing the orderliness of data processing within the bus link layer and providing a solid foundation for achieving high-performance on-chip data transmission.

[0100] In some embodiments, it also includes:

[0101] The downstream data distributor, connected to the downstream module, the downstream virtual channel memory, and the downstream virtual channel distributor, is used to determine the storage space corresponding to the downstream virtual channel in the downstream virtual channel memory based on the storage space address of the downstream virtual channel sent by the downstream virtual channel distributor, and send the target data to the storage space corresponding to the downstream virtual channel.

[0102] The downstream multi-channel arbitrator is connected to the downstream virtual channel memory and the downstream module. It is used to arbitrate the target data stored in each virtual channel of the downstream virtual channel memory and send the selected target data to the downstream module.

[0103] Specifically, Figure 7 This is the fifth schematic diagram of the bus link layer structure provided in this application, as shown below. Figure 7 As shown, the bus link layer also includes a downstream data distributor 241 and a downstream multiplexer 242.

[0104] The downstream data distributor can be implemented using a data selector. The downstream data distributor connects to the upstream virtual channel memory, the downstream virtual channel memory, and the downstream virtual channel distributor.

[0105] The downstream data distributor connects to the downstream virtual channel distributor and the write port of the downstream virtual channel memory. Its data input receives output data from the upstream multiplexer (in the case where the upstream multiplexer is set up behind the upstream virtual channel memory). When upstream data needs to be forwarded, the downstream virtual channel distributor first selects an available downstream virtual channel based on the credit value of each virtual channel in the downstream virtual channel memory and generates a corresponding storage space address. This address is then sent to the downstream data distributor. The downstream data distributor then uses this address to accurately send the received target data to the corresponding storage space in the downstream virtual channel memory. This process ensures the correct flow of data between the two levels of memory within the bus link layer.

[0106] The downstream multiplexer can be implemented using an arbitration logic unit and a multiplexer. The downstream multiplexer is connected to the read ports of all virtual channels in the downstream virtual channel memory and the input ports of the downstream module. The downstream virtual channel memory may contain multiple virtual channels with target data ready for transmission. These virtual channels simultaneously send transmission requests to the downstream multiplexer. The downstream multiplexer selects one virtual channel's target data from all requests for transmission based on a preset arbitration strategy (e.g., round-robin arbitration, fixed-priority arbitration, etc.).

[0107] The bus link layer provided in this application embodiment ensures the orderly transmission of data from upstream to downstream of the link layer by the downstream data distributor, while the downstream multiplexer enables the orderly transmission of data to the final destination module. This enhances the orderliness of data processing within the bus link layer and provides a solid foundation for achieving high-performance on-chip data transmission.

[0108] In some embodiments, it also includes:

[0109] The data register, connected to the upstream and downstream virtual channel memories, is used to time the transfer of target data between the upstream and downstream virtual channel memories.

[0110] Specifically, Figure 8 This is the sixth schematic diagram of the bus link layer structure provided in this application, as shown below. Figure 8 As shown, the bus link layer also includes one or more data registers 270.

[0111] Within the bus link layer, the entire data path from the read port of the upstream virtual channel memory, through the upstream multiplexer, to the write port of the downstream virtual channel memory inherently contains a certain combinational logic delay.

[0112] This application embodiment inserts at least one data register on the data transmission path between the upstream and downstream virtual channel memories. This register can be positioned between the upstream and downstream virtual channel memories, for example, after the output of the upstream multiplexer, in the middle of a long physical connection, or before the input of the downstream data distributor. Its function is to divide a complete, excessively long data path into two or more shorter path segments. For example, after the target data is sent from the upstream virtual channel memory, it only needs to reach this data register within one clock cycle; in the next clock cycle, the data is then sent from this register and finally reaches the downstream virtual channel memory.

[0113] The number of data registers can be determined based on the actual physical wiring length and timing requirements. If the physical distance is very long, multiple data registers can be inserted in series along the data path to divide the ultra-long path into multiple short path segments that can transmit stably within a single clock cycle. The number of data registers, i.e., the number of pipeline stages (steps), can be used as a configurable parameter of the bus link layer.

[0114] The bus link layer provided in this application embodiment has at least one data register, which reduces the difficulty of timing convergence and enables the bus link layer to operate stably at higher clock frequencies.

[0115] In some embodiments, it also includes:

[0116] The signal register, connected to the downstream virtual channel memory and the upstream data credit counter, is used to record the data transmission information sent from the downstream virtual channel memory to the upstream data credit counter.

[0117] Specifically, Figure 9 This is the seventh schematic diagram of the bus link layer structure provided in this application, as shown below. Figure 9 As shown, the bus link layer also includes one or more signal registers 280.

[0118] When target data in the downstream virtual channel memory is sent to the downstream module, a data transmission message (used for credit return) is generated. This message needs to be sent to the upstream data credit counter to update its credit value. Physically, the signal path from the downstream virtual channel memory back to the upstream data credit counter can span a considerable physical distance. Similar to the data path, this long signal path also faces the challenge of timing convergence.

[0119] In this embodiment, at least one signal register is inserted on the signal path between the downstream virtual channel memory and the upstream data credit counter. This signal register performs timing processing on this control path. This operation divides a long combinational logic path into two or more shorter segments, ensuring that the delay of each segment is within the clock cycle allowable range. One or more signal registers can be flexibly inserted depending on the actual physical wiring distance.

[0120] The bus link layer provided in this application embodiment has at least one signal register, which solves the timing problem of the reverse control path and ensures that the entire bus link layer can work stably and reliably as a whole under high-speed clock, regardless of its physical size.

[0121] Figure 10 This is a schematic diagram of the on-chip bus structure provided in this application, such as... Figure 10 As shown, the on-chip bus 1000 includes the bus link layer 200 in the above embodiments.

[0122] Specifically, the on-chip bus is used to connect multiple heterogeneous or homogeneous functional modules within the chip. Any two nodes on the on-chip bus that need to communicate directly (such as between two adjacent routers, or between a router and its connected terminal functional modules) can be connected through the bus link layer.

[0123] The on-chip bus provided in this application inherits all the technical advantages brought by the bus link layer, which significantly reduces the physical implementation difficulty of the entire on-chip bus and makes timing convergence easier.

[0124] Figure 11 This is a schematic diagram of the chip structure provided in this application, as shown below. Figure 11 As shown, chip 1100 includes the on-chip bus 1000 in the above embodiments.

[0125] Specifically, the chip can be an artificial intelligence chip, which can be a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a domain-specific architecture (DSA), etc.

[0126] The chip provided in this application inherits all the technical advantages brought by the on-chip bus, which significantly reduces the physical implementation difficulty of the entire chip, makes timing convergence easier, and greatly simplifies the design of each functional module connected to the bus.

[0127] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A bus link layer, characterized in that, Used for transmitting target data between upstream and downstream modules, including: An upstream virtual channel allocator, connected to the upstream module, is used to determine the upstream virtual channel corresponding to the target data based on the credit value of each virtual channel in the upstream virtual channel memory. An upstream virtual channel memory, connected to the upstream module and the upstream virtual channel allocator, is used to receive target data sent by the upstream module and to store the target data in the storage space corresponding to the upstream virtual channel; A downstream virtual channel allocator, connected to the upstream virtual channel memory, is used to determine the downstream virtual channel corresponding to the target data based on the credit value of each virtual channel in the downstream virtual channel memory. A downstream virtual channel memory, connected to the upstream virtual channel memory, the downstream virtual channel allocator, and the downstream module, is used to store the target data in the storage space corresponding to the downstream virtual channel and to send the target data to the downstream module. The credit value of the virtual channel is used to represent the number of available data buffer units in the virtual channel.

2. The bus link layer according to claim 1, characterized in that, The upstream virtual channel memory is also used for: When sending the target data of the upstream virtual channel to the downstream virtual channel memory, the data transmission information of the upstream virtual channel is sent to the upstream module; The upstream module is configured to: send the target data to the upstream virtual channel in the upstream virtual channel memory and decrease the credit value of the upstream virtual channel; and increase the credit value of the upstream virtual channel based on the received data transmission information of the upstream virtual channel.

3. The bus link layer according to claim 1, characterized in that, Also includes: An upstream data credit counter, connected to the upstream virtual channel memory and the downstream virtual channel memory, is used to decrease the credit value of the downstream virtual channel when the target data is stored in the downstream virtual channel; and to increase the credit value of the downstream virtual channel when the target data stored in the downstream virtual channel is sent to the downstream module.

4. The bus link layer according to claim 1, characterized in that, Also includes: A downstream data credit counter, connected to the downstream virtual channel memory and the downstream module, is used to reduce the credit value of the downstream module when the downstream module receives the target data.

5. The bus link layer according to any one of claims 1 to 4, characterized in that, Also includes: An upstream data allocator, connected to the upstream module, the upstream virtual channel memory, and the upstream virtual channel allocator, is used to determine the storage space corresponding to the upstream virtual channel in the upstream virtual channel memory based on the storage space address of the upstream virtual channel sent by the upstream virtual channel allocator, and to send the target data to the storage space corresponding to the upstream virtual channel. An upstream multiplexer, connected to the upstream virtual channel memory and the downstream virtual channel memory, is used to arbitrate the target data stored in each virtual channel of the upstream virtual channel memory and send the selected target data to the downstream virtual channel memory.

6. The bus link layer according to any one of claims 1 to 4, characterized in that, Also includes: A downstream data distributor, connected to the upstream virtual channel memory, the downstream virtual channel memory, and the downstream virtual channel distributor, is used to determine the storage space corresponding to the downstream virtual channel in the downstream virtual channel memory based on the storage space address of the downstream virtual channel sent by the downstream virtual channel distributor, and to send the target data to the storage space corresponding to the downstream virtual channel. A downstream multiplexer, connected to the downstream virtual channel memory and the downstream module, is used to arbitrate the target data stored in each virtual channel of the downstream virtual channel memory and send the selected target data to the downstream module.

7. The bus link layer according to any one of claims 1 to 4, characterized in that, Also includes: A data register, connected to the upstream virtual channel memory and the downstream virtual channel memory, is used to time the transmission of the target data between the upstream virtual channel memory and the downstream virtual channel memory.

8. The bus link layer according to claim 3, characterized in that, Also includes: A signal register, connected to the downstream virtual channel memory and the upstream data credit counter, is used to record the data transmission information sent by the downstream virtual channel memory to the upstream data credit counter.

9. An on-chip bus, characterized in that, Includes the bus link layer as described in any one of claims 1 to 8.

10. A chip, characterized in that, Includes the on-chip bus as described in claim 9.

Images