A method for logically diagnosing a hidden defect, an electronic device, and a storage medium

Abstract

The present application relates to the technical field of electronic design automation design, in particular to a logic diagnosis method for latent defects, an electronic device and a storage medium, which obtains a latent defect file, the latent defect file including one or more failure bits; splits the latent defect file into N independent failure-like vectors according to the failure bits, each failure-like vector including only one failure bit; performs path backtracking and simulation on the N failure-like vectors to obtain a candidate defect list for explaining each failure-like vector; obtains a minimum set of candidate defects that can explain all failure-like vectors with the least number according to the candidate defect lists of the N failure-like vectors; performs fault simulation through the vector according to the minimum set, and calculates the score of each candidate defect in the minimum set according to the fault simulation result and the candidate defect list of each failure-like vector to generate a final diagnosis report, thereby solving the technical problem that latent defects cannot be effectively diagnosed at present.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation design, in particular to a logic diagnosis method for hidden defects, an electronic device and a storage medium. BACKGROUND

[0002] Manufacturing defects of integrated circuits increasingly present complex and non-ideal characteristics, resulting in some defects only showing a small amount of failure response in production testing, which is referred to as failure caused by hidden defects. Traditional logic diagnosis methods rely on failure vectors (failing patterns) captured by automatic test equipment (ATE) as input, adopt a single-location-at-a-time (SLAT) strategy, evaluate the explanatory ability of each potential defect location to the observed failure behavior through fault simulation, and output the suspect location with the highest matching degree as the diagnosis result. This method has good positioning accuracy when facing scenarios with sufficient failure data and defect behavior conforming to standard fault models.

[0003] However, for failures caused by hidden defects, the electrical behavior often exhibits non-perfect behavior, i.e., the defect is affected by multiple factors, resulting in it being triggered only under a small number of test vectors in functional or scan testing. In actual testing, only one or a few failure vectors can be captured, and the number of failure bits corresponding in the failure vectors is very small. These limited failure responses cannot be completely covered by any single, deterministic fault model. Therefore, the traditional logic diagnosis mechanism based on failure vector matching cannot converge to the accurate physical location, and the diagnosis capability is completely disabled, severely restricting the efficiency and accuracy of defect root cause analysis. Therefore, there is an urgent need for a logic diagnosis method that can diagnose hidden defects. SUMMARY

[0004] To solve the above technical problems, the technical solution adopted by the present application is as follows: a logic diagnosis method for hidden defects, the method comprising the following steps:

[0005] S100, obtaining a hidden defect file, the hidden defect file including one or more failure bits.

[0006] S200, splitting the hidden defect file into N independent failure-like vectors according to the failure bits, each failure-like vector including only one failure bit, and N being greater than or equal to 1.

[0007] S300, performing path tracing and simulation on the N class failure vectors to obtain a candidate defect list for explaining each class failure vector, the candidate defect list including M candidate defects, where M is greater than or equal to 0.

[0008] S400, obtaining a minimum set of candidate defects that explain the N class failure vectors in the minimum number according to the candidate defect list of the N class failure vectors.

[0009] S500, performing fault simulation by vector according to the minimum set, and calculating a score of each candidate defect in the minimum set according to the fault simulation result and the candidate defect list of each class failure vector to generate a final diagnosis report.

[0010] In addition, the present application also provides a non-transitory computer readable storage medium, the storage medium stores at least one instruction or at least one program, the at least one instruction or the at least one program is loaded and executed by the processor to realize the above method.

[0011] In addition, the present application also provides an electronic device, comprising a processor and the above non-transitory computer readable storage medium.

[0012] The present application has at least the following beneficial effects:

[0013] The embodiment of the present application provides a logic diagnosis method for hidden defects, an electronic device and a storage medium, which obtains a hidden defect file, splits each failure bit in the hidden defect file into an independent class failure vector, obtains a candidate defect list according to the class failure vector, and then obtains a diagnosis report based on the candidate defect list and the vector, which splits limited failure data into class failure vectors with the finest granularity, converts a complex multi-bit failure problem into multiple simple unit failure problems, and uses a traditional fault model to comprehensively search for defects for each simple unit failure problem, finally obtains a diagnosis report, realizes the conversion of the diagnosis problem of hidden defects into multiple simple problems that can be processed by the traditional fault model, and uses mature technology to realize efficient diagnosis, and solves the technical problem that hidden defects cannot be diagnosed at present. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 A flow chart of a logic diagnosis method for hidden defects is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be apparently and completely described in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by a person skilled in the art without any creative work belong to the protection scope of the present application.

[0017] Unless otherwise defined, all the technical and scientific terms used in the embodiments of the present application have the same meanings as commonly understood by a person skilled in the art.

[0018] Please refer to Figure 1 which shows a logical diagnosis method for a hidden defect, and the method comprises the following steps:

[0019] S100, obtaining a hidden defect file, wherein the hidden defect file comprises one or more failure bits.

[0020] Wherein, the test pattern is a combination of a group of input signals, which is used to be applied to the input end of a chip or circuit to detect whether its function is normal.

[0021] It should be noted that according to the result of the functional test, the corresponding test pattern can be divided into a failing pattern and a passing pattern.

[0022] Wherein, the failing pattern is a test pattern in which the actual output of the circuit is inconsistent with the expected output in the test. The failing pattern indicates that the circuit has a fault behavior under this input, which is the basis for diagnosis.

[0023] Wherein, the passing pattern is a test pattern in which the actual output of the circuit is consistent with the expected output in the test.

[0024] Wherein, the failure bit is a bit in the failing pattern in which the actual output is inconsistent with the expected output.

[0025] It should be noted that multiple test patterns are needed as input signals when testing the function of a chip. If the functional test fails, it may correspond to one or more failing patterns, and each failing pattern may have one or more failure bits.

[0026] Wherein, the hidden defect file only comprises the failure bits of the failing pattern.

[0027] In an embodiment, S100 further comprises:

[0028] S110, acquire test response data of the chip to be tested, identify and count the number of failure vectors.

[0029] It should be noted that after acquiring the test response data of the chip to be tested, the number of failure vectors therein is counted first. Since the hidden defects are activated only under a very small number of test vectors in the test, the number of captured failure vectors is very small.

[0030] S120, input all the failure vectors into a first diagnosis algorithm for logical diagnosis, and if no result is generated, perform S130.

[0031] S130, compare the number of failure vectors with a preset threshold value, and when the number of failures is less than the preset threshold value, determine that the current failure behavior is difficult to be completely explained by an existing fault model, and store the failure bits in the failure vectors into the hidden defect file.

[0032] It should be noted that in order to more accurately identify the hidden defects, the embodiment of the present application sets a preset threshold value to determine whether the current failure vector belongs to the response scenario of the hidden defect. When the number of failure vectors is less than the preset threshold value, it is determined that it is not sufficient to support the diagnosis model under the single-point defect assumption, that is, it is difficult to be completely explained by any single and certain fault model.

[0033] The first diagnosis algorithm is a defect diagnosis algorithm. In one embodiment, the first diagnosis algorithm is a single-location-at-a-time (SLAT) algorithm, and other types of diagnosis algorithms also fall within the protection scope of the present application.

[0034] The preset threshold value is a value preset by a user. In one embodiment, the preset threshold value is 3, 4 or 5, and other values of the preset threshold value also fall within the protection scope of the present application. The preset threshold value can be dynamically adjusted according to actual conditions.

[0035] In one embodiment, in S120, if all the failure vectors are input into the first diagnosis algorithm for logical diagnosis, and if a diagnosis result is generated, S200 does not need to be performed. It is indicated that the existing first diagnosis algorithm can be completely explained by the existing fault model.

[0036] In one embodiment, in S120, if all the failure vectors are input into the first diagnosis algorithm for logical diagnosis, if no result is generated, and the number of failure vectors is greater than a preset threshold, S200 does not need to be performed. It should be noted that the failure vectors meeting the condition may not be caused by physical defects, but are caused by test flow abnormalities. For example, improper chip version (change) management causes the test vectors to be mismatched with the circuit design. Or, there is a timing violation, poor contact, or power disturbance in the test vector load and response unload process, causing data shift errors (shift terror), etc. Such problems usually need to be prioritized to check the stability of the test environment and process, rather than to locate physical defects.

[0037] S200, the hidden defect file is split into N independent failure vectors according to the failure bits, each failure vector includes only one failure bit, and N is greater than or equal to 1.

[0038] Among them, the hidden defect file includes all the failure bits, and each failure bit is split out as an independent failure vector when splitting.

[0039] As an example, when the hidden defect file includes N failure bits {a1a2a3…a N}, the N failure bits are split into N failure vectors {a1}, {a2}, {a3}, …, {a N}. It should be noted that there may be two or more failure bits in the hidden defect file that belong to different bit positions of the same failure vector.

[0040] S300, path tracing and simulation are performed on the N failure vectors to obtain a candidate defect list for explaining each failure vector, and the candidate defect list includes M candidate defects, where M is greater than or equal to 0.

[0041] Among them, the candidate defect (suspect) is a possible defect position and its fault model in the chip circuit, which is used to explain the observed failure vector, and to locate the real defect through diagnosis scoring. Among them, the defect position in the chip circuit refers to the specific element or node in the circuit, which is the physical space position where the defect may occur. The fault model (Fault Model) is used to describe the defect type and behavior that may occur at the current defect position, which can reuse traditional fault models, without the need for additional development, shortening the development cycle and improving the development efficiency.

[0042] It should be noted that path tracing can identify the potential impact area of each failure bit in the circuit.

[0043] As an example, for the first class failure vector, it corresponds to the first candidate defect list; for the second class failure vector, it corresponds to the second candidate defect list; and so on, each class failure vector corresponds to a candidate defect list. It should be noted that there may be a situation that the candidate defect list is empty, at this time M = 0, that is, no candidate defect is found that can reproduce the current class failure vector.

[0044] In an embodiment, S300 further comprises:

[0045] S310, starting from each class failure vector, the suspicious circuit node list is obtained by tracing back its logic propagation path along the connection relationship in the circuit netlist.

[0046] It should be noted that the potential circuit nodes affecting the failure bits can be determined by tracing back its logic propagation path, and then the suspicious circuit node list is obtained.

[0047] S320, for each suspicious circuit node, a fault model is injected, and fault simulation is performed with all class failure vectors as input to obtain the candidate defect list of each class failure vector.

[0048] It should be noted that in the process of fault simulation, by comparing the simulation output with the expected response, candidate defects that can reproduce each class failure vector are identified. Each candidate defect in the candidate defect list can individually explain the class failure vector it belongs to.

[0049] S400, according to the candidate defect list of the N class failure vectors, the minimum set of candidate defects that explain all class failure vectors with the least number of candidate defects is obtained.

[0050] Among them, all candidate defects in the minimum set can completely explain all class failure vectors, and the number of candidate defects required is the least.

[0051] It should be noted that in chip testing, a real defect may cause multiple failure vectors. However, due to the complexity of defect behavior, a single defect may not be able to completely explain all observed failure responses. That is, when there are multiple defects acting on the chip at the same time, a single candidate defect (suspect) cannot cover all failure vectors. Therefore, multiple candidate defects are needed to jointly explain.

[0052] As an example, ideally, when there are three class failure vectors: a first class failure vector, a second class failure vector and a third class failure vector; wherein a first candidate defect, a second candidate defect and a third candidate defect can independently explain the first class failure vector; the first candidate defect, the third candidate defect and a seventh candidate defect can independently explain the second class failure vector; the third candidate defect, a fifth candidate defect and a ninth candidate defect can independently explain the third class failure vector. Wherein the third candidate defect can simultaneously explain the first class failure vector, the second class failure vector and the third class failure vector, then the minimum set only includes the third candidate defect. As another example, non-ideally, when there are three class failure vectors: a first class failure vector, a second class failure vector and a third class failure vector; wherein a second candidate defect and a third candidate defect can independently explain the first class failure vector; the first candidate defect and the third candidate defect can independently explain the second class failure vector; a ninth candidate defect can independently explain the third class failure vector. At this time, there is no candidate defect that can simultaneously explain the three class failure vectors, so joint explanation is needed through candidate defect combination, at this time the minimum set includes the third candidate defect and the ninth candidate defect, the first and second class failure vectors are explained through the third candidate defect, and the third class failure vector is explained through the ninth candidate defect, so that the minimum set covers all failure vectors through joint explanation.

[0053] In an embodiment, the algorithm for obtaining the minimum set in S400 is a Min-Cover algorithm. Other algorithms capable of obtaining the minimum set also fall within the protection scope of the present application.

[0054] S500, according to the minimum set and through a vector, fault simulation is performed, and according to the fault simulation result and the candidate defect list of each class failure vector, a score of each candidate defect in the minimum set is calculated, and a final diagnosis report is generated.

[0055] In an embodiment, S500 further includes a fault simulation step:

[0056] S510, in the logical diagnosis process, all candidate defects in the minimum set are injected into a netlist to construct a joint fault simulation model; and the joint fault simulation model is simulated through a vector, if the simulation fails, the joint fault simulation model corresponding to the candidate defect is a false positive model of test pass and simulation failure, and the candidate defect of the false positive model obtained is taken as the fault simulation result.

[0057] It should be noted that, in the fault simulation of the candidate defects in the minimum set according to the vector, the simulation result shows that an error is output (Simulation Fail), but in actual chip testing, the test vector is not observed to have an error (Tester Pass), that is, a contradictory situation of test pass but simulation failure occurs. Therefore, the credibility of the candidate defects corresponding to the false positive model needs to be further reduced.

[0058] In an implementation, S500 further includes a candidate defect scoring step for each candidate defect in the minimum set:

[0059] S520, for each candidate defect in the minimum set, according to the candidate defect list, the number of similar failure vectors that can be explained by each candidate defect in the minimum set and the fault simulation result, the score of each candidate defect in the minimum set is calculated, and a diagnosis report is obtained; wherein the number of similar failure vectors that can be explained by the current candidate defect is positively correlated with the score, and the fault simulation result is negatively correlated with the score, that is, the more similar failure vectors that can be explained by the current candidate defect, the less the fault simulation result, and the higher the score of the candidate defect. Ideally, a certain candidate defect can explain all similar failure vectors, and the number of fault simulation results is 0, that is, the contradictory situation of test pass but simulation failure is 0, and the score of the candidate defect is full marks. It should be noted that the fault simulation result obtained in S510 is applicable to S520.

[0060] In summary, the embodiment of the present application provides a logical diagnosis method for hidden defects, which obtains a hidden defect file, splits each failure bit in the hidden defect file into an independent similar failure vector, performs simulation according to the similar failure vector to obtain a candidate defect list, and then obtains a diagnosis report based on the candidate defect list and the vector, thereby solving the technical problem that hidden defects cannot be diagnosed at present.

[0061] The embodiment of the present application further provides a non-transitory computer readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a method in the method embodiment, and the at least one instruction or the at least one program is loaded and executed by the processor to realize the method provided by the above-mentioned embodiment.

[0062] The embodiment of the present application further provides an electronic device, which includes a processor and the aforementioned non-transitory computer readable storage medium.

[0063] Embodiments of the present application also provide a computer program product comprising program code for causing an electronic device to perform the steps of the methods according to various exemplary embodiments of the present application described above in the specification when said program product is run on the electronic device.

[0064] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

[0065] Although some specific embodiments of the present application have been described in detail by way of example, it should be understood that the above examples are only for illustration and are not intended to limit the scope of the present application. Those skilled in the art should understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A logical diagnostic method for concealed defects, characterized in that, The method includes the following steps: S100, Obtain a hidden defect file, wherein the hidden defect file includes one or more failure bits; S200, the hidden defect file is split into N independent class failure vectors according to the failure bits, each class failure vector includes only one failure bit, and N is greater than or equal to 1; S300, perform path tracing and simulation on N types of failure vectors to obtain a list of candidate defects for explaining each type of failure vector. The list of candidate defects includes M candidate defects, where M is greater than or equal to 0. S400: Based on the candidate defect list of N class failure vectors, obtain the minimum set of candidate defects that can explain the N class failure vectors with the minimum number of defects. S500, perform fault simulation based on the minimum set and through vectors, and calculate the score of each candidate defect in the minimum set based on the fault simulation results and the candidate defect list of each type of failure vector, and generate a final diagnostic report.

2. The method according to claim 1, characterized in that, The S500 also includes: S510, During the logic diagnosis process, the fault models corresponding to all candidate defects in the minimum set are simultaneously injected into the netlist to construct a joint fault simulation model. The joint fault simulation model is then simulated using the vector. If the simulation fails, the joint fault simulation model corresponding to the candidate defect is a false alarm model that passes the test but fails the simulation. S520, for each candidate defect in the minimum set, the score of each candidate defect in the minimum set is calculated by combining the candidate defect list of each type of failure vector and the false alarm model, and a diagnostic report is obtained.

3. The method according to claim 1, characterized in that, The S100 also includes: S110: Acquire the test response data of the chip under test, identify and count the number of failure vectors; S120: Input all failure vectors into the first diagnostic algorithm for logical diagnosis. If no result is generated, then execute S130. S130, compare the number of failure vectors with a preset threshold. When the number of failures is less than the preset threshold, determine that the current failure behavior is difficult to be fully explained by the existing fault model, and store the failure bits in the failure vectors into the hidden defect file.

4. The method according to claim 1, characterized in that, In S120, if all failure vectors are input into the first diagnostic algorithm for logical diagnosis, and no result is generated, and the number of failure vectors is greater than the preset threshold, then S200 does not need to be executed.

5. The method according to claim 1, characterized in that, The S300 also includes: S310, Starting from each type of failure vector, trace the logical propagation path backward along the connection relationship in the circuit netlist to obtain a list of suspicious circuit nodes; S320, inject a fault model into each suspicious circuit node, perform fault simulation using all types of failure vectors as input, and obtain the candidate defect list for each type of failure vector.

6. The method according to claim 1, characterized in that, S500 also includes a fault simulation step: S510, During the logic diagnosis process, the fault models corresponding to all candidate defects in the minimum set are simultaneously injected into the netlist to construct a joint fault simulation model; The joint fault simulation model is then simulated using the vector. If the simulation fails, the joint fault simulation model corresponding to the candidate defect is a false alarm model that passes the test but fails the simulation. The candidate defect of the obtained false alarm model is taken as the fault simulation result.

7. The method according to claim 1, characterized in that, S500 also includes a scoring step for each candidate defect in the minimum set: S520, for each candidate defect in the minimum set, obtain the number of class failure vectors that each candidate defect in the minimum set can explain and the fault simulation results according to the candidate defect list, calculate the score of each candidate defect in the minimum set, and obtain a diagnostic report; wherein, the number of class failure vectors that the current candidate defect can explain is positively correlated with the score, and the fault simulation results are negatively correlated with the score.

8. The method according to claim 1, characterized in that, The algorithm for obtaining the minimum set in S400 is the minimum set covering algorithm.

9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.

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