A uvm-based atomic-level computing chip verification method

Abstract

The application relates to the field of function verification of digital integrated circuits and discloses an atomic-level computing chip verification method based on UVM. First, a UVM simulation verification platform containing various core components is built; then a software program is used to generate test excitation with physical meaning, containing information such as configuration, functional, pseudo-potential, orbital file and the like; subsequently, the test excitation is input into the built UVM verification platform and a software reference model respectively; the UVM verification platform applies the test excitation to a design under test and outputs a calculation result; the reference model also correspondingly generates a reference result; finally, the output of the design under test is compared with the output of the reference model, and the correctness of the function of the atomic-level computing chip is verified through visual auxiliary analysis and quantitative error analysis. Through the excitation generation based on physical constraints and the effective error evaluation method, the application can solve the function verification difficulty of the atomic-level computing chip.

Description

Technical Field

[0001] This invention relates to the field of functional verification of digital integrated circuits, and specifically to an atomic-level computing chip verification method based on UVM. Background Technology

[0002] Atomic-level computing is a key tool for exploring the microscopic world of matter, with wide applications in physics, chemistry, materials science, and biomedicine. It primarily relies on two core methods: molecular dynamics (MD) to simulate the motion of atoms under classical mechanics, and density functional theory (DFT) to precisely calculate electronic structure based on the first principles of quantum mechanics. These methods can reveal atomic-scale phenomena that are difficult to capture experimentally, enabling the analysis of dynamic processes within the microscopic structural domains of matter.

[0003] Currently, atomic-level computing primarily relies on Central Processing Units (CPUs) and Graphics Processing Units (GPUs) employing the von Neumann architecture. However, the separation of memory and computation units in this architecture leads to frequent data transfers, creating significant "memory walls" and "power walls" that severely restrict further improvements in computational efficiency. To overcome this limitation, Application Specific Integrated Circuit (ASIC) chips, which do not adhere to the von Neumann architecture, have become a key direction for performance enhancement. However, the complexity of atomic-level computing results in highly complex ASIC designs, which cannot be modified after tape-out and require reliable functional verification during the design phase.

[0004] Universal Verification Methodology (UVM) is a chip verification methodology based on SystemVerilog (SV). Its core mechanisms include constrained random stimulus generation, coverage-driven verification, and component reusability. UVM provides a set of predefined standardized libraries and verification architecture frameworks, further enhancing the flexibility of the verification platform. However, traditional UVM verification methods have two major limitations in atomic-level computing chip verification: first, randomly generated stimuli lack physical meaning and cannot reflect the true needs of atomic-level computing scenarios; second, atomic-level computing is a regression-type task, and the bit-level precise comparison methods in traditional UVM verification platforms cannot adapt to the inherent numerical biases of atomic-level computing. Summary of the Invention

[0005] To verify the functional correctness of atomic-level computing chips, this invention provides a UVM-based verification method for atomic-level computing chips. This method solves the functional verification challenge of atomic-level computing chips through physically constrained stimulus generation and effective error evaluation methods. The invention includes the following steps:

[0006] Step S1: Build a UVM simulation verification platform for atomic-level computation. Its core components include:

[0007] 1) DUT (Design Under Test): The design to be verified.

[0008] 2) Reference model: The reference model is used to provide an ideal DUT model. Its input is the same as the DUT, and its output is used to compare with the output of the DUT.

[0009] 3) Sequencer: A sequence generator used to manage and schedule test stimuli.

[0010] 4) Sequence: A sequence used to generate test stimuli.

[0011] 5) Monitor: A monitor used to monitor the output of the DUT.

[0012] 6) Driver: The driver converts the stimulus sent by the sequence into a signal that the DUT can recognize.

[0013] 7) Agent: A proxy used to encapsulate various components.

[0014] 8) Scoreboard: The scoreboard compares the output of the DUT with the output of the reference model to verify the correctness of the function.

[0015] Step S2: Generate physically meaningful test stimuli, including information such as configuration, functional, pseudopotential, orbital file, whether +U is applied, whether an electric field is applied, and whether spin is considered.

[0016] Step S3: Run the above verification platform using Synopsys VCS / Verdi tools. Use Synopsys VCS as the simulation tool and Verdi as the waveform debugging tool. During the simulation, the platform's internal Sequence and Driver work together to convert physical data into timing signals to drive the DUT for calculations, while the chip's output is captured by the Monitor.

[0017] Step S4: Build a software reference model using a programming language such as C++ and generate reference results. This model reads test stimuli consistent with those input to the DUT and outputs the corresponding calculation results as reference data.

[0018] Step S5: Use scripts such as Matlab to compare and analyze the calculation results of the DUT and the reference model. Evaluation metrics include visualization-assisted analysis and quantitative error analysis. Visual analysis involves plotting a scatter plot with the reference model output on the horizontal axis and the DUT results on the vertical axis to compare the consistency of the two results. Quantitative error analysis includes calculating the root mean square error (RMSE) and the maximum absolute error (MAE). RMSE measures the overall deviation of output values ​​such as energy, force, system virial, and charge density. Let the test sample size be n, and the DUT calculation results be {y1, y2, ..., y...}. n The calculation results of the reference model are as follows: The formula for calculating RMSE is:

[0019]

[0020] MAE is used to capture local outliers, and its calculation formula is as follows:

[0021]

[0022] Compared with existing technologies, the significant advantage of this invention lies in its use of physically meaningful test stimuli instead of random stimuli, ensuring that the verification environment meets the requirements of atomic-level computing scenarios. Simultaneously, the evaluation system combining visual analysis and quantitative error analysis guarantees the reasonableness of the computational results from this verification environment. Attached Figure Description

[0023] Figure 1 This is an operation flowchart of the present invention;

[0024] Figure 2 This is a schematic diagram of the UVM simulation verification platform in an embodiment of the present invention;

[0025] Figure 3 This is a flowchart of obtaining atomic input files in an embodiment of the present invention;

[0026] Figure 4 This is a flowchart of obtaining the initialization file in an embodiment of the present invention;

[0027] Figure 5 This is a scatter plot comparing the energy results of the design under test and the reference model in this embodiment of the invention;

[0028] Figure 6 This is a scatter plot comparing the stress results of the design under test and the reference model in this embodiment of the invention. Detailed Implementation

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] This invention relates to a UVM-based atomic-level computing chip verification method, such as... Figure 1 As shown, a UVM simulation verification platform containing all core components is first built. Then, a software program generates physically meaningful test stimuli, including information such as configuration, functionals, pseudopotentials, and orbital files. These test stimuli are then input into the built UVM simulation verification platform and the software reference model. The UVM verification platform applies the test stimuli to the design under test and outputs the calculation results. The reference model performs calculations on the same stimuli and generates a reference output. Finally, error analysis is performed between the output of the design under test and the output of the reference model to comprehensively verify the correctness of the atomic-level computing chip's functionality.

[0031] Compared to previous technologies, this invention proposes a UVM verification platform for atomic-level computing. Through physically constrained excitation generation and an effective error evaluation method, it overcomes the limitations of traditional UVM methods in scientific computing chip verification. This invention takes molecular dynamics in the field of atomic-level computing as its research object and uses a gold (chemical element: Au) system as an example to describe the implementation steps in detail.

[0032] Step S1: Use System Verilog to build a UVM simulation verification platform for atomic-level computation. For example... Figure 2 As shown, its core components include:

[0033] 1) DUT (Design Under Test): The design to be verified, i.e., the molecular dynamics calculation chip.

[0034] 2) Reference model: This model provides an ideal DUT model with the same inputs as the DUT and its output used for comparison with the DUT's output. In this embodiment, this component is implemented externally by a C++ program.

[0035] 3) Sequencer: A sequence generator used to manage and schedule test stimuli.

[0036] 4) Sequence: A sequence used to generate test stimuli. In this invention, this component is used to read the test stimulus file generated in step S2, parse the data in the file, and populate the data fields of the corresponding transaction.

[0037] 5) Monitor: Used to monitor the output of the DUT. When valid data transmission is detected, the signal-level data is reassembled into transactions and output.

[0038] 6) Driver: The driver converts the excitation into a signal recognizable by the DUT. In this embodiment, this component converts the molecular configuration and potential function model read from the sequence into a specific signal recognizable by the DUT.

[0039] 7) Agent: A proxy used to encapsulate various components.

[0040] 8) Scoreboard: The scoreboard compares the output of the DUT with the output of the reference model to verify the correctness of the function. In this embodiment, Matlab scripts are used for the comparison and analysis of the calculation results.

[0041] Step S2: Generate physically realistic test stimuli. Specifically, such as... Figure 3 As shown, a C++ program is used to read the initial configuration file of the Au example to obtain atomic information. The program encodes atomic coordinates, atomic types, and information about adjacent atoms according to a preset communication protocol and saves them in a specific binary format. For example... Figure 4 As shown, the C++ program reads the machine learning potential function model of the Au example. This model is trained based on high-precision quantum mechanical calculations and can accurately describe the energy and forces of the system within the training range, ensuring physical realism. The program obtains parameters such as network weights and biases by analyzing the potential function model and saves them as an initialization file.

[0042] Step S3: Simulate and debug the UVM verification platform using Synopsys VCS / Verdi. Start the simulation process using VCS, specifying test cases during compilation and instantiating the verification environment, the design under test (DUT), and each component. After simulation begins, the Sequence reads data from a pre-prepared stimulus file, the Driver converts the data into timing signals conforming to a preset bus protocol, and drives them to the DUT's input interface. The DUT executes its internal hardware computation logic under the drive of the input stimulus. The Monitor detects the DUT's output interface, captures the output data, and writes it to a specified file. While running the simulation, use Verdi to start the waveform debugging function, recording the signal waveforms of the DUT interface and key internal modules, providing visual evidence for functional verification and fault diagnosis.

[0043] Step S4: Build a software model using C++ to generate reference data. To improve simulation verification efficiency and verify the reliability of the ASIC chip algorithm model, a software reference model for the ASIC was constructed using C++. This reference model implements an equivalent mapping of ASIC functions and ensures the correct functionality of the reference model. The model reads test stimuli consistent with those input to the DUT and outputs the corresponding atomic energies, forces, and virial results as reference data. It can also output intermediate variable results for comparison.

[0044] Step S5: Use Matlab scripts to perform data analysis on the calculation results of the DUT and the reference model. Import the DUT output data file captured by the Monitor and the reference result file generated by the reference model into Matlab to perform error calculation and analysis. Evaluation indicators include visualization-assisted analysis and quantitative error analysis. Visual analysis compares the consistency of the two results by plotting a scatter plot with the reference model output on the horizontal axis and the DUT result on the vertical axis. Quantitative error analysis includes calculating the root mean square error (RMSE) and the maximum absolute error (MAE). RMSE measures the overall deviation of output values ​​such as energy and force. Let the test sample size be n, and the DUT calculation results be {y1, y2, ..., y...}. n The calculation results of the reference model are as follows: The formula for calculating RMSE is:

[0045]

[0046] MAE is used to capture local outliers, and its calculation formula is as follows:

[0047]

[0048] Taking the Au atom system as an example, the energy and force calculation results of the DUT (E dut F dut ) and the calculation results of the reference model (E) ref F ref The comparative scatter plots are shown below. Figure 5 and Figure 6 As shown, the calculated RMSE and MAE values ​​are also written in the lower right corner of the figure. The results show that the DUT's calculations are in high agreement with the reference model's calculations, with the RMSE for atomic energies being 6.56 × 10⁻⁶. -3 meV / atom, the RMSE of the stress is

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Referring to the description of these embodiments, those skilled in the art should be able to understand and make relevant modifications or substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A method for verifying atomic-level computing chips based on UVM, characterized in that, Includes the following steps: Step S1: Build a UVM simulation verification platform for atomic-level computing; Step S2: Generate physically meaningful test stimuli; in step S2, an external program is used to generate physically meaningful test stimuli, including configuration, functional, pseudopotential, orbital file, whether +U is applied, whether an electric field is applied, and whether spin is considered. Step S3: Run the verification platform from step S1 using Synopsys VCS / Verdi tools. In step S3, Synopsys VCS is used as the simulation tool and Verdi is used as the waveform debugging tool. During the simulation, the Sequence and Driver inside the platform work together to convert physical data into timing signals to drive the design under test to perform calculations. The output of the design under test is captured by the Monitor. Step S4: Build a software reference model using C++; Step S5: Use a script to compare the calculation results of the design under test with the reference model.

2. The method for verifying an atomic-level computing chip based on UVM as described in claim 1, characterized in that: In step S1, the core components of the UVM simulation verification platform include: 1) DUT (Design Under Test): The design to be verified; 2) Reference model: The reference model is used to provide an ideal DUT model. Its input is the same as the DUT, and its output is used to compare with the output of the DUT. 3) Sequencer: A sequence generator used to manage and schedule test stimuli; 4) Sequence: A sequence used to generate test stimuli; 5) Monitor: A monitor used to monitor the output of the DUT; 6) Driver: The driver converts the stimulus sent by the sequencer into a signal that the DUT can recognize; 7) Agent: A proxy used to encapsulate various components; 8) Scoreboard: The scoreboard compares the output of the DUT with the output of the reference model to verify the correctness of the function.

3. The method for verifying an atomic-level computing chip based on UVM as described in claim 1, characterized in that: In step S4, a software reference model is used to read test stimuli that are consistent with those input to the design under test, and the corresponding calculation results are output as reference data.

4. The method for verifying an atomic-level computing chip based on UVM as described in claim 1, characterized in that: In step S5, the comparative analysis of the calculation results between the design under test and the reference model includes visualization-assisted analysis and quantitative error analysis. The visualization analysis compares the consistency of the two results by plotting a scatter plot with the reference model output on the horizontal axis and the design under test output on the vertical axis. The quantitative error analysis includes calculating the root mean square error (RMSE) and the maximum absolute error (MAE). Assuming the test sample size is n, the calculation result of the design under test is... The calculation results of the reference model are Then the formulas for calculating RMSE and MAE are: ； RMSE is used to measure the overall deviation of energy, force, system virial, and charge density; MAE is used to capture local outliers.

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