Chip structure and method of forming the same, chip package structure and method thereof

Abstract

Embodiments of the present disclosure provide a chip structure and a forming method thereof, a chip packaging structure and a method thereof. A first dielectric layer and a second dielectric layer are sequentially stacked on a functional surface of a chip. The second dielectric layer is patterned to form a dielectric layer bump corresponding to a solder resist layer window of a packaging substrate. The solder resist layer window is provided with a pad. The dielectric layer bump and the first dielectric layer are simultaneously patterned to form an opening. A conductive bump is formed in the opening. By forming the dielectric layer bump corresponding to the solder resist layer window on the first dielectric layer, and forming the conductive bump corresponding to the pad on the dielectric layer bump and the first dielectric layer, the non-conductive adhesive layer formed on the surface of the first dielectric layer and the dielectric layer bump is also in a bump shape when the chip is mounted. Therefore, in the process of thermal compression welding, the non-conductive adhesive layer in a bump shape is preferentially filled in the solder resist layer window, the gas therein is discharged, the formation of voids is avoided, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip structure and its formation method, and a chip packaging structure and its method. Background Technology

[0002] Currently, the stacking and soldering of memory chips mainly adopts thermocompression welding, which involves in-situ soldering under the simultaneous action of pressure and temperature. The mainstream stacking process combines thermocompression welding with a non-conductive adhesive film. The non-conductive adhesive film is pre-attached to the wafer surface, covering the bumps. During the soldering process, the non-conductive adhesive film flows and fills the space between the chip and the substrate, buffering the stress on the chip while protecting the bumps.

[0003] like Figure 1 As shown, for memory chip 2, there is a solder resist window 4 on the substrate corresponding to the bump area 3 in the middle of chip 2 to expose the solder pads 5. In the process of combining the hot-press soldering process with the non-conductive adhesive film 6, when the non-conductive adhesive film 6 of chip 2 with the non-conductive adhesive film 6 comes into contact with the substrate under pressure, the air in the solder resist window 4 is trapped inside and difficult to expel. Although in terms of process, the molten non-conductive adhesive film can be made to flow and the air squeezed out by continuing to apply pressure, this requires high process requirements and is prone to porosity caused by residual air, which affects the reliability of the chip.

[0004] To address the aforementioned issues, it is necessary to propose a reasonably designed chip structure and its fabrication method, as well as a chip packaging structure and its method, that effectively solve these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a chip structure and a method for forming the same, and a chip packaging structure and a method thereof.

[0006] One aspect of this disclosure provides a method for forming a chip structure, the method comprising:

[0007] Provide chips;

[0008] A first dielectric layer and a second dielectric layer are sequentially stacked on the functional surface of the chip.

[0009] The second dielectric layer is patterned to form dielectric layer bumps, wherein the dielectric layer bumps are used to correspond to the solder mask openings of the packaging substrate, and the solder mask openings are provided with pads.

[0010] The dielectric layer bumps and the first dielectric layer are simultaneously patterned to form openings on the dielectric layer bumps and the first dielectric layer corresponding to the pads.

[0011] Conductive protrusions are formed within the opening.

[0012] Optionally, the step of patterning the second dielectric layer to form dielectric layer bumps includes:

[0013] A first photoresist layer is formed on the second dielectric layer;

[0014] The first photoresist layer is exposed and developed sequentially to form a plurality of first openings on the first photoresist layer;

[0015] The second dielectric layer is etched along the first opening to form the dielectric layer bumps corresponding to the solder mask openings of the packaging substrate;

[0016] Remove the remaining first photoresist layer.

[0017] Optionally, the height of the dielectric layer bump is the same as the depth of the solder mask window; or, the height of the dielectric layer bump is slightly greater than the depth of the solder mask window.

[0018] Optionally, simultaneously patterning the dielectric layer bumps and the first dielectric layer to form openings on the dielectric layer bumps and the first dielectric layer corresponding to the pads includes:

[0019] A second photoresist layer is formed on the dielectric layer bumps;

[0020] The second photoresist layer is sequentially exposed and developed to form a plurality of second openings corresponding to the pads on the second photoresist layer;

[0021] The dielectric layer bump and the first dielectric layer are etched sequentially along the second opening to form the opening on the dielectric layer bump and the first dielectric layer corresponding to the pad.

[0022] Remove any remaining second photoresist layer.

[0023] Optionally, forming a conductive protrusion within the opening includes:

[0024] A first conductive protrusion is formed by filling the opening;

[0025] A second conductive bump is deposited on the first conductive bump to form a second conductive bump.

[0026] Optionally, the first conductive protrusion is flush with the opening, and the second conductive protrusion protrudes from the opening.

[0027] Another aspect of this disclosure provides a chip structure, fabricated using the chip structure formation method described above; wherein, the chip structure includes:

[0028] a chip;

[0029] a first dielectric layer disposed on a functional surface of the chip;

[0030] a dielectric layer bump disposed on the first dielectric layer and corresponding to the solder resist layer window of the packaging substrate; wherein,

[0031] the dielectric layer bump and the first dielectric layer are provided with an opening at a position corresponding to the pad;

[0032] a conductive bump filled in the opening;

[0033] Optionally, the height of the dielectric layer bump is the same as the depth of the solder resist layer window; or, the height of the dielectric layer bump is slightly higher than the depth of the solder resist layer window.

[0034] Another aspect of the embodiments of the present disclosure provides a chip packaging method, the method comprising:

[0035] providing a packaging substrate, a surface of the packaging substrate is provided with a solder resist layer, the solder resist layer has a solder resist layer window, and a pad is disposed in the solder resist layer window;

[0036] providing a chip structure, wherein the chip structure is prepared by using the chip structure forming method described above; or, the chip structure is prepared by using the chip structure forming method described above;

[0037] forming a non-conductive adhesive film layer on the side of the dielectric layer bump and the first dielectric layer facing the packaging substrate;

[0038] attaching the chip structure to the packaging substrate by using a thermal compression bonding process, the dielectric layer bump fills the solder resist layer window corresponding thereto to discharge the gas in the solder resist layer window, and the conductive bump is electrically connected to the pad.

[0039] Another aspect of the embodiments of the present disclosure provides a chip packaging structure, which is packaged by using the chip packaging method described above.

[0040] The chip structure and its forming method, and the chip packaging structure and its method, in the chip structure forming method, first, the first dielectric layer and the second dielectric layer are stacked in sequence on the functional surface of the chip; the second dielectric layer is patterned to form a dielectric layer bump, wherein the dielectric layer bump is used to correspond to the solder resist layer window of the packaging substrate, and the solder pad is arranged in the solder resist layer window; the dielectric layer bump and the first dielectric layer are patterned at the same time to form an opening corresponding to the solder pad on the dielectric layer bump and the first dielectric layer; and a conductive bump is formed in the opening. By forming the dielectric layer bump corresponding to the solder resist layer window of the packaging substrate on the first dielectric layer, and forming the conductive bump corresponding to the solder pad of the packaging substrate on the dielectric layer bump and the first dielectric layer, the non-conductive glue layer formed on the surface of the first dielectric layer and the dielectric layer bump is also in a protruding shape when the chip is mounted, so that the non-conductive glue layer in a protruding shape is preferentially filled in the solder resist layer window during the hot-press welding process, the gas in the non-conductive glue layer is discharged, the formation of the cavity is avoided, and the reliability of the chip packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 It is a structural schematic diagram of the chip packaging structure in the prior art;

[0042] Figure 2 It is a flowchart of a chip structure forming method of one embodiment in the embodiment of the present disclosure;

[0043] Figures 3 to 11 It is a process schematic diagram of a chip structure forming method of another embodiment in the embodiment of the present disclosure;

[0044] Figure 12 It is a structural schematic diagram of a chip structure of another embodiment in the embodiment of the present disclosure;

[0045] Figure 13 It is a flowchart of a chip packaging method of another embodiment in the embodiment of the present disclosure;

[0046] Figures 14 to 17 It is a process schematic diagram of a chip packaging method of another embodiment in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in combination with the drawings and specific embodiments.

[0048] As Figure 2 shown, an aspect of the embodiment of the present disclosure provides a chip structure forming method S100, the S100 method comprising:

[0049] S110, providing a chip.

[0050] As shown in Figure 3 , a chip 110 is provided,

[0051] S120, a first dielectric layer and a second dielectric layer are sequentially stacked on the functional surface of the chip.

[0052] As shown in Figure 3 , the first dielectric layer 120 is first applied on the functional surface of the chip 110. The first dielectric layer 120 can be a PI layer, that is, the material of the first dielectric layer 120 is polyimide. Of course, the first dielectric layer 120 can also be made of other materials, which is not specifically limited in the embodiment and can be selected according to actual needs.

[0053] As shown in Figure 4 , after the first dielectric layer 120 is applied on the functional surface of the chip 110, the second dielectric layer 130 is applied on the first dielectric layer 120. The material of the second dielectric layer 130 can be the same as that of the first dielectric layer 120, that is, polyimide. Of course, the material of the second dielectric layer 130 can also be different from that of the first dielectric layer 120, which can be selected according to actual needs.

[0054] S130, the second dielectric layer is patterned to form a dielectric layer bump, wherein the dielectric layer bump is used to correspond to a solder mask opening window of a packaging substrate, and a pad is arranged in the solder mask opening window.

[0055] As shown in Figure 14 , the surface of the packaging substrate 210 is provided with a solder mask opening window 220, and the solder mask opening window 220 is provided with a pad 230. The specific process of forming the dielectric layer bump 140 in step S130 can be as follows:

[0056] First, as shown in Figure 5 , a first photoresist layer 150 is applied on the second dielectric layer 130. The first photoresist layer 150 can be a positive photoresist or a negative photoresist, which can be selected according to actual needs, and the embodiment is not specifically limited.

[0057] Second, as shown in Figure 5 , the first photoresist layer 150 is sequentially exposed and developed to form a plurality of first openings 151 on the first photoresist layer 150; in the embodiment, the first photoresist layer 150 remaining after development is used to correspond to the solder mask opening window 220 of the packaging substrate 210.

[0058] Third, as shown in Figure 6As shown, the second dielectric layer 130 is etched along the first opening 151 to form the dielectric layer bump 140 corresponding to the solder resist window 220 of the packaging substrate 210.

[0059] The height of the dielectric layer bump 140 is the same as the depth of the solder resist window 220, or the height of the dielectric layer bump 140 is slightly higher than the depth of the solder resist window 220. However, the planar size of the dielectric layer bump 140 is slightly smaller than the planar size of the solder resist window 220.

[0060] In this embodiment, due to the presence of the dielectric layer bump 140, the non-conductive adhesive layer formed on the dielectric layer bump 140 and the first dielectric layer 130 is also convex in shape during chip mounting. During the process of thermal compression bonding, the non-conductive adhesive layer in convex shape can be filled in the solder resist window 220 first, thereby discharging the gas in the solder resist window 220 and avoiding the formation of voids.

[0061] Finally, the residual first photoresist layer 150 is removed by etching and other processes.

[0062] S140, simultaneously patterning the dielectric layer bump and the first dielectric layer to form openings on the dielectric layer bump and the first dielectric layer corresponding to the pads.

[0063] The specific process of step S140 can be as follows:

[0064] First, as shown in the figure, a second photoresist layer 160 is applied on the dielectric layer bump 140. The first photoresist layer 150 can use positive photoresist or negative photoresist, which can be selected according to actual needs, and the embodiment is not limited in particular. Figure 7 Second, as shown in the figure, the second photoresist layer 160 is sequentially exposed and developed to form a plurality of second openings 161 on the second photoresist layer 160 corresponding to the pads 230 of the packaging substrate 210.

[0065] Figure 8 Then, as shown in the figure, the dielectric layer bump 140 and the first dielectric layer 120 are etched along the second openings 161 by etching process to form the openings 170 on the dielectric layer bump 140 and the first dielectric layer 120 corresponding to the pads 230.

[0066] Finally, the residual second photoresist layer 160 is removed by etching and other processes. Figure 9 Finally, the residual second photoresist layer 160 is removed by etching and other processes.

[0067] S150, forming a conductive bump in the opening.

[0068] S150, forming a conductive bump in the opening.​

[0069] The specific process of forming the conductive bump 180 in step S150 can be as follows:

[0070] First, as shown in FIG. 1A, a first conductive bump 181 is formed by filling the opening 170 using an electroplating process. In this embodiment, the first conductive bump 181 can be a copper bump, that is, a copper bump can be formed by electroplating in the opening 170 using an electroplating process. Figure 10 In this embodiment, the first conductive bump 181 is flush with the opening 170, that is, the first conductive bump 181 completely fills the opening 170.

[0071] Second, as shown in FIG. 1B, a second conductive bump 182 can be formed on the first conductive bump 181 by deposition using a sputtering process or the like. In this embodiment, the second conductive bump 182 can be a tin bump, that is, a tin bump can be formed on the copper bump using a sputtering process or the like. The second conductive bump 182 protrudes from the opening 170.

[0072] Figure 11 In this embodiment, the first conductive bump and the second conductive bump together constitute a conductive bump of a functional surface of a chip, the position of the conductive bump corresponds to the position of a pad on a packaging substrate, and the conductive bump is used to electrically connect with the pad of the packaging substrate.

[0073] The chip structure forming method of the embodiments of the present disclosure first stacks a first dielectric layer and a second dielectric layer on a functional surface of a chip in sequence; the second dielectric layer is patterned to form a dielectric layer bump, wherein the dielectric layer bump corresponds to a solder mask opening window of a packaging substrate, and the solder mask opening window is provided with a pad; the dielectric layer bump and the first dielectric layer are simultaneously patterned to form an opening on the dielectric layer bump and the first dielectric layer corresponding to the pad; and a conductive bump is formed in the opening. By forming a dielectric layer bump corresponding to the solder mask opening window of the packaging substrate on the first dielectric layer, and forming a conductive bump corresponding to the pad of the packaging substrate on the dielectric layer bump and the first dielectric layer, a non-conductive adhesive layer formed on the surface of the first dielectric layer and the dielectric layer bump is also in a protruding shape when the chip is mounted, so that in the process of thermal compression welding, the non-conductive adhesive layer in a protruding shape is preferentially filled in the solder mask opening window, the gas therein is discharged, the formation of a cavity is avoided, and the reliability of the chip packaging structure is improved.

[0074] As shown in FIG. 1C, another aspect of the embodiments of the present disclosure provides a chip structure 100 prepared by using the chip structure forming method S100 described above. The specific process of the chip structure forming method S100 has been described in detail above, and will not be described again here.

[0075] As shown in FIG. 1C, another aspect of the embodiments of the present disclosure provides a chip structure 100 prepared by using the chip structure forming method S100 described above. The specific process of the chip structure forming method S100 has been described in detail above, and will not be described again here. Figure 12

[0076] ​​In the embodiment, the chip structure 100 includes a chip 110, a first dielectric layer 120, a dielectric layer bump 140, and a conductive bump 180.

[0077] The first dielectric layer 120 is arranged on a functional surface of the chip 110.

[0078] The dielectric layer bump 140 is arranged on the first dielectric layer 120 and corresponds to the solder mask opening 220 of the packaging substrate 210.

[0079] The dielectric layer bump 140 and the first dielectric layer 120 are provided with an opening 170 corresponding to the pad 230.

[0080] The conductive bump 180 fills the opening 170.

[0081] For example, the height of the dielectric layer bump 140 is the same as the depth of the solder mask opening 220, or the height of the dielectric layer bump 140 is slightly higher than the depth of the solder mask opening 220.

[0082] The chip structure of the embodiment of the present disclosure, by arranging the dielectric layer bump corresponding to the solder mask opening of the packaging substrate on the first dielectric layer, and arranging the conductive bump corresponding to the pad of the packaging substrate on the dielectric layer bump and the first dielectric layer, the non-conductive adhesive layer arranged on the surface of the first dielectric layer and the dielectric layer bump is also in a protruding shape when the chip is mounted, so that the non-conductive adhesive layer in a protruding shape is filled in the solder mask opening during the hot-press welding process, the gas in the solder mask opening is discharged, the formation of the cavity is avoided, and the reliability of the chip packaging structure is improved.

[0083] As shown in Figure 13 Another aspect of the embodiment of the present disclosure provides a chip packaging method S200, the method S200 includes:

[0084] S210, providing a packaging substrate, the surface of the packaging substrate is provided with a solder mask, the solder mask has a solder mask opening, and the pad is arranged in the solder mask opening.

[0085] As shown in Figure 15 A packaging substrate 210 is provided, wherein the surface of the packaging substrate is provided with a solder mask, the solder mask has a solder mask opening 220, and the pad 230 is arranged in the solder mask opening 220.

[0086] S220, providing a chip structure, wherein the chip structure is prepared by the chip structure forming method described above; or the chip structure is prepared by the chip structure described above.

[0087] As shown in Figure 14As shown, a chip structure 100 is provided, wherein the chip structure is prepared by the chip structure forming method S100 described above, or the chip structure 100 is prepared by the chip structure 100 described above.

[0088] S230, a non-conductive adhesive film layer is formed on the dielectric layer bump and the first dielectric layer towards the side of the packaging substrate.

[0089] As shown, a non-conductive adhesive film layer 240 is formed on the dielectric layer bump 140 and the first dielectric layer 120 towards the side of the packaging substrate 210. Due to the presence of the dielectric layer bump 140, the formed non-conductive adhesive film layer 240 is also called a protrusion shape. Figure 16

[0090] S240, the chip structure is attached to the packaging substrate by a thermal compression bonding process, the dielectric layer bump fills the solder mask opening corresponding to it to discharge the gas in the solder mask opening, and the conductive bump is electrically connected to the pad.

[0091] As shown, the chip structure 100 is attached to the packaging substrate 210 by a thermal compression bonding process, wherein during the attachment process, the dielectric layer bump 140 fills the solder mask opening 220 of the packaging substrate 210 corresponding to it in priority to discharge the gas in the solder mask opening 220 and avoid the formation of voids. By the thermal compression bonding process, the conductive bump 180 of the chip structure 100 is electrically connected to the pad 230 of the packaging substrate 210. Figure 17 The chip packaging method of the embodiment of the present disclosure provides a chip structure prepared by the chip structure forming method described above, or the chip structure is prepared by the chip structure described above. The dielectric layer bump corresponding to the solder mask opening of the packaging substrate is arranged on the first dielectric layer of the functional surface of the chip structure, and the conductive bump corresponding to the pad of the packaging substrate is arranged on the dielectric layer bump and the first dielectric layer. In the process of attaching the chip structure to the packaging substrate by the thermal compression bonding process, the non-conductive adhesive layer formed on the surface of the first dielectric layer and the dielectric layer bump is also in a protrusion shape, so that the non-conductive adhesive layer in a protrusion shape fills the solder mask opening in priority to discharge the gas therein and avoid the formation of voids, thereby improving the reliability of the chip packaging structure.

[0092] Another aspect of the embodiment of the present disclosure provides a chip packaging structure prepared by the chip packaging method S200 described above. The specific process of the chip packaging method S200 has been described in detail above, and will not be described here.

[0093]

[0094] ​​In the chip packaging structure of the embodiment, the dielectric layer bump corresponding to the opening window of the solder resist layer of the packaging substrate is arranged on the first dielectric layer of the functional surface of the chip structure, and the non-conductive adhesive layer arranged on the surface of the first dielectric layer and the dielectric layer bump is also in a protruding shape, so that the non-conductive adhesive layer in a protruding shape can be filled in the opening window of the solder resist layer in the process of hot-press welding, the gas in the opening window is discharged, the formation of the cavity is avoided, and the reliability of the chip packaging structure is improved.

[0095] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered as the protection scope of the embodiments of the present disclosure.

Claims

1. A method of forming a chip structure, characterized by, The method comprises: providing a chip; stacking a first dielectric layer and a second dielectric layer on a functional surface of the chip in sequence; performing patterning on the second dielectric layer to form a dielectric layer bump corresponding to a solder resist layer window of a packaging substrate, wherein a pad is arranged in the solder resist layer window; wherein a non-conductive adhesive film layer is formed on the surface of the first dielectric layer and the dielectric layer bump when the chip is attached, and the non-conductive adhesive film layer is also protruding, so that the protruding non-conductive adhesive film layer can be filled in the solder resist layer window during the process of thermal compression bonding; performing patterning on the dielectric layer bump and the first dielectric layer simultaneously to form an opening on the dielectric layer bump and the first dielectric layer corresponding to the pad; forming a conductive bump in the opening.

2. The method of claim 1, wherein, The patterning on the second dielectric layer to form a dielectric layer bump comprises: forming a first photoresist layer on the second dielectric layer; performing exposure and development on the first photoresist layer in sequence to form a plurality of first openings on the first photoresist layer; etching the second dielectric layer along the first openings to form the dielectric layer bump corresponding to the solder resist layer window of the packaging substrate; removing the residual first photoresist layer.

3. The method of claim 1, wherein, The height of the dielectric layer bump is the same as the depth of the solder resist layer window, or the height of the dielectric layer bump is slightly higher than the depth of the solder resist layer window.

4. The method according to any one of claims 1 to 3, characterized in that, The patterning on the dielectric layer bump and the first dielectric layer simultaneously to form an opening on the dielectric layer bump and the first dielectric layer corresponding to the pad comprises: forming a second photoresist layer on the dielectric layer bump; performing exposure and development on the second photoresist layer in sequence to form a plurality of second openings corresponding to the pad on the second photoresist layer; etching the dielectric layer bump and the first dielectric layer along the second openings in sequence to form the opening on the dielectric layer bump and the first dielectric layer corresponding to the pad; removing the residual second photoresist layer.

5. The method according to any one of claims 1 to 3, characterized in that, The forming of a conductive bump in the opening comprises: filling a first conductive bump in the opening; depositing a second conductive bump on the first conductive bump.

6. The method of claim 5, wherein, The first conductive bump is flush with the opening, and the second conductive bump protrudes from the opening.

7. A chip structure, characterized by The chip structure is formed by the method of any one of claims 1 to 6, wherein the chip structure comprises: a chip; a first dielectric layer arranged on a functional surface of the chip; a dielectric layer bump arranged on the first dielectric layer and corresponding to a solder resist layer window of a packaging substrate; wherein an opening is arranged on the dielectric layer bump and the first dielectric layer corresponding to the pad; a conductive bump is filled in the opening.

8. The chip structure of claim 7, wherein, The height of the dielectric layer bump is the same as the depth of the solder resist layer window, or the height of the dielectric layer bump is slightly higher than the depth of the solder resist layer window.

9. A chip packaging method, characterized by, The method comprises: providing a packaging substrate, wherein a surface of the packaging substrate is provided with a solder resist layer, the solder resist layer has a solder resist layer window, and a pad is arranged in the solder resist layer window; A chip structure is provided, wherein the chip structure is prepared by the chip structure forming method according to any one of claims 1 to 6; or the chip structure is according to claim 7. A non-conductive adhesive film layer is formed on the side of the dielectric layer bump and the first dielectric layer facing the packaging substrate; The chip structure is attached to the packaging substrate by a thermal compression bonding process, the dielectric layer bump fills the corresponding solder resist opening, the gas in the solder resist opening is discharged, and the conductive bump is electrically connected to the pad.

10. A chip package structure, comprising: The chip packaging method according to claim 9 is used for packaging.

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