Electrical model and detection circuit for indium column connection defect in stacked packaging chip

Abstract

The invention provides an electrical model and a detection circuit for indium bump connection defects in a stacked package chip. The electrical model comprises equivalent capacitance from the indium column to the substrate of the readout circuit; a first equivalent resistor connected in parallel with the equivalent capacitor from the indium stud to the substrate of the readout circuit; the second equivalent resistor is arranged from the center of the indium column to the top end of the indium column; a first end of the first equivalent resistor connected in parallel with the equivalent capacitor is connected with one end of the second equivalent resistor; one end of the third equivalent resistor is respectively connected with one end of the second equivalent resistor and the first end; one end of the fourth equivalent resistor is connected with the other end of the second equivalent resistor; and a fifth equivalent resistor of the bonding pad, wherein one end of the fifth equivalent resistor is connected with the other end of the third equivalent resistor. The short circuit and the open circuit of the indium column connection in each pixel array can be detected by using the electrical model, so that the reliability of the indium column connection in each pixel can be detected, and the type and the position of the defect can be determined.

Description

Technical Field

[0001] This application relates to the field of stacked packaging technology, and more specifically, to an electrical model and detection circuit for indium pillar connection defects in stacked packaged chips. Background Technology

[0002] Stacked packaging technology, with its high integration, compact structure, and multi-dimensional performance optimization, has become a key supporting means in the field of electronic information technology. In X-ray detectors using stacked packaging technology, the upper layer is a sensor containing photosensitive material, and the lower layer is a readout chip. They are interconnected through flip-chip bonding to form a matrix of signals, together constituting the detector module. The pixel units of the sensor and the pixel units of the readout chip are the same size and correspond one-to-one. Typically, electrodes and pads are fabricated separately within each pixel, and the connection between them is ensured by metal interconnect materials, such as indium pillars.

[0003] Figure 1 A cross-sectional view of an X-ray detector using indium pillar connections according to the prior art is shown. Figure 1 As shown, the X-ray detector employing stacked packaging technology includes a sensor photosensitive material layer 101 on top, a readout circuit 104 below the sensor photosensitive material layer 101, a protective layer 102 disposed between the sensor photosensitive material layer 101 and the readout circuit 104, a layer 105 formed by electrodes and pads, an indium pillar 106 below the layer 105, and an underfill adhesive 103 filling the area around the indium pillar 106. The photosensitive material layer 101 and the readout circuit 104 are connected by the protective layer 102, the layer 105 formed by electrodes and pads, the indium pillar 106, and the underfill adhesive 103. The layer formed by electrodes and pads provides electrical connection with the indium pillar, while the underfill adhesive and the protective layer surrounding the electrodes provide mechanical connection and protection.

[0004] Indium, as an interconnect material, has several advantages: it is soft and ductile, allowing for stress relief in a short time and to withstand the tensile stress caused by thermal shock to a certain extent; it has a low melting point, enabling welding processes to be completed at lower temperatures; and it has good electrical conductivity, providing ideal electrical connections. Therefore, indium pillar interconnects have become an important component of stacked packaging technology.

[0005] After flip-chip bonding, indium pillar connections may exhibit varying degrees of defects due to chip warpage, inconsistent thermal expansion coefficients of different materials, mechanical stress, and metal oxidation over time. The most significant defects can be categorized as short circuits and open circuits. Current detection methods primarily rely on height measurement and thermal resistance imaging. However, these methods only indirectly measure indium pillar defects through characteristics such as height and thermal resistance, and cannot accurately test the electrical characteristics of the indium pillar connections. Furthermore, these approaches require individual observation and measurement of each indium pillar connection point, making them unsuitable for large-scale pixel arrays.

[0006] Therefore, existing indium pillar testing methods cannot accurately measure the electrical characteristics such as resistance and capacitance of the indium pillar connections; at the same time, the testing system cannot automatically save the test results for each pixel, making it unsuitable for situations with a large pixel scale. Summary of the Invention

[0007] To address the shortcomings of existing indium pillar testing schemes, such as the inability to accurately measure the electrical characteristics of indium pillar connections (resistance, capacitance, etc.) and the inability of testing systems to automatically save test results for each pixel, making them unsuitable for large pixel sizes, this application provides an electrical model and detection circuit for indium pillar defects in stacked packaged chips. This circuit not only detects short-circuit and open-circuit defects in indium pillar connections within each pixel array, significantly improving testing speed, but also automatically saves the detection results to a register within the pixel and reads them out to the external chip via a reading operation.

[0008] According to one aspect of this application, an electrical model is provided for an indium pillar connection defect in a stacked package chip, wherein the stacked package chip includes a sensor with a photosensitive layer, a readout circuit with a substrate interconnected with the sensor signal, an indium pillar, an electrode, and a pad disposed between the sensor and the readout circuit, the sensor and the readout circuit being connected through the indium pillar, the electrode, and the pad, and the electrical model includes: an equivalent capacitance from the indium pillar to the substrate of the readout circuit; a first equivalent resistance from the indium pillar to the substrate of the readout circuit, the first equivalent resistance being related to the indium pillar's capacitance to the substrate of the readout circuit. The equivalent capacitances are connected in parallel; the second equivalent resistance from the center of the indium pillar to its top, the first end of which is connected in parallel with the equivalent capacitance is connected to one end of the second equivalent resistance; the third equivalent resistance from the center of the indium pillar to its bottom, one end of which is connected to one end of the second equivalent resistance and the first end respectively; the fourth equivalent resistance of the electrode, one end of which is connected to the other end of the second equivalent resistance; and the fifth equivalent resistance of the pad, one end of which is connected to the other end of the third equivalent resistance.

[0009] Furthermore, the second end of the first equivalent resistor and the equivalent capacitor connected in parallel is connected to the substrate of the readout circuit, the other end of the fourth equivalent resistor is connected to the pixel of the sensor, and the other end of the fifth equivalent resistor is connected to the pixel of the readout circuit.

[0010] According to a second aspect of this application, a detection circuit for detecting indium pillar defects in stacked packaged chips is provided, including an electrical model of the aforementioned indium pillars.

[0011] Furthermore, the detection circuit further includes: an adjustable current source that generates an adjustable reference current and is connected to the other end of the fifth equivalent resistance of the electrical model via a first switch; a second switch that connects the other end of the fourth equivalent resistance of the electrical model to a pixel of the sensor, and the pixel of the sensor is connected to the second switch; a comparator whose first input terminal is connected to the other end of the fifth equivalent resistance of the electrical model via a third switch, and whose second input terminal receives a reference voltage, and whose comparator compares the voltage passing through the electrical model with the reference voltage at the second input terminal to obtain a comparison result; and a sampling latch circuit connected to the output terminal of the comparator for sampling and judging the comparison result of the comparator and providing a judgment result.

[0012] Furthermore, the adjustable current source, the first switch, the third switch, the comparator, and the sampling latch circuit are integrated into the pixel of the readout circuit.

[0013] Furthermore, the detection circuit also includes a register disposed inside the pixel of the readout circuit for storing the judgment result output from the sampling latch circuit.

[0014] Furthermore, the reference voltage includes a first reference voltage and a second reference voltage, wherein the first reference voltage is set based on a short circuit between the indium pillar and the substrate, and the second reference voltage is set based on a disconnection between the indium pillar and its top or bottom end.

[0015] According to a third aspect of this application, a method is provided for detecting indium pillar defects in a stacked packaged chip using the aforementioned detection circuit. The method includes: in a first mode, resetting the voltage at the top of the indium pillar to ground, turning off the second switch, and turning on the first switch; charging the equivalent capacitance of the electrical model through the adjustable current source and inputting the charge to the first input terminal of the comparator; the comparator comparing the first voltage obtained at the first input terminal with a reference voltage at the second input terminal and outputting the comparison result to the sampling latch circuit; and the sampling latch circuit sampling and judging the comparison result and providing a judgment result; or in a second mode, turning on the first switch, the second switch, and the third switch; the reference current of the adjustable current source generating a second voltage across the indium pillar and inputting the second voltage to the first input terminal of the comparator; the comparator comparing the second voltage obtained at the first input terminal with the reference voltage at the second input terminal and outputting the comparison result to the sampling latch circuit; and the sampling latch circuit sampling and judging the comparison result and providing a judgment result.

[0016] Furthermore, the method also includes latching the judgment result into a register located inside the pixel of the readout circuit.

[0017] According to a fourth aspect of this application, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program executable on the processor, wherein the processor executes the computer program to implement the steps of the method for detecting indium pillar defects in a stacked packaged chip described above.

[0018] According to a fifth aspect of this application, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, it implements the steps of the method for detecting indium pillar defects in a stacked packaged chip described above.

[0019] According to this application, not only can an electrical model of indium pillars be established for short-circuit and open-circuit defects in indium pillar connections, but a detection circuit for detecting indium pillar defects in stacked packaged chips is also designed. By using the electrical model in the detection circuit, short-circuit and open-circuit defects in indium pillar connections within each pixel array can be detected, thereby enabling the reliability of indium pillar connections within each pixel to be detected and the type and location of defects to be determined.

[0020] Furthermore, by integrating the detection circuitry into the chip pixels and performing tests using a unified testing timing sequence, the testing speed can be significantly improved. Moreover, by automatically saving the detection results to registers within the pixels and reading them out onto the chip via readout operations, a defect distribution model of the indium pillar connections across the entire pixel array can be established, which is beneficial for improving the imaging quality of the X-ray detector. Attached Figure Description

[0021] Figure 1 A cross-sectional view of an X-ray detector using indium pillar connections according to the prior art is shown;

[0022] Figure 2 A schematic diagram of an indium pillar electrical model established according to an embodiment of this application for indium pillar connection defects in stacked packaged chips is shown.

[0023] Figure 3 The use according to an embodiment of this application is illustrated. Figure 2 The diagram shows a detection circuit for detecting defects in the indium pillar connection using the indium pillar electrical model shown; and...

[0024] Figure 4 The adoption of embodiments according to this application is illustrated. Figure 3 The timing diagram of the detection circuit shown is shown. Detailed Implementation

[0025] According to the technical solution of this application, not only can an electrical model of indium pillars be established for short-circuit and open-circuit defects of indium pillar connections, but also a detection circuit for detecting indium pillar defects in stacked packaged chips is designed. It can detect the reliability of indium pillar connections in each pixel, thereby determining the type and location of the defects. Furthermore, an indium pillar detection method based on an impedance voltage divider network is provided.

[0026] Furthermore, according to one embodiment of this application, the detection circuit is integrated into the chip pixel. By using a unified test timing sequence, short-circuit and open-circuit defects in the indium pillar connections within each pixel array are detected, significantly improving the test speed. Simultaneously, the detection results can be automatically saved to a register within the pixel and read out to the external chip via a reading operation. This allows for the establishment of a defect distribution model for the indium pillar connections across the entire pixel array, which is beneficial for improving the imaging quality of the X-ray detector.

[0027] Below, we will use Figure 1 The electrical model of the indium pillar according to an embodiment of this application is described in detail using the X-ray detector shown as an example.

[0028] An indium pillar can be abstracted as a cylindrical model. Its own conductor resistance, as well as the resistance of the electrodes and pads connected to it, can all be calculated using a cylindrical conductor model.

[0029] like Figure 2 As shown, the electrical model according to an embodiment of this application uses an RC T-connection, and the electrical model includes the equivalent capacitance C from the indium pillar to the readout chip substrate. InThe first equivalent resistance R1 from the indium pillar to the substrate of the readout circuit, the second equivalent resistance R2 from the center of the indium pillar to its top, the third equivalent resistance from the center of the indium pillar to its bottom, the fourth equivalent resistance R4 of the electrode, and the fifth equivalent resistance R5 of the pad.

[0030] The resistance value of the first equivalent resistance R1 from the indium pillar to the substrate of the readout circuit is R. ox The equivalent resistance of the entire indium pillar is R. IN The resistance value of the second equivalent resistance R2 from the center of the indium pillar to its top is 0.5 R. IN The resistance of the third equivalent resistance R3 from the center of the indium pillar to its bottom is 0.5 R. IN The resistance values ​​of the fourth equivalent resistance R4 of the electrode and the fifth equivalent resistance R5 of the pad are respectively R bump .

[0031] The first equivalent resistance R1 and the equivalent capacitance C In Connected in parallel. The first equivalent resistance R1 and the equivalent capacitance C In The first terminal of the parallel connection is connected to one end of the second equivalent resistor R2. One end of the second equivalent resistor R2 is connected to one end of the third equivalent resistor R3, and the first equivalent resistor R1 is connected to the equivalent capacitance C. In The first end of the parallel connection is also connected to the same end of the third equivalent resistor R3. The other end of the second equivalent resistor R2 is connected to one end of the fourth equivalent resistor R4. The other end of the third equivalent resistor R3 is connected to one end of the fifth equivalent resistor R5.

[0032] The other end of the fourth equivalent resistor R4 is connected to the sensor pixel, and the other end of the fifth equivalent resistor R5 is connected to the readout circuit pixel. The first equivalent resistor R1 and the equivalent capacitance C... In The second terminal after parallel connection is connected to the substrate of the readout circuit.

[0033] Typically, the length of an indium pillar is around 10 μm, corresponding to a defect-free R... In +2*R bump At around 100Ω, C In ≈40fF, R ox ≈10MΩ. In the short-circuit defect model, a short circuit occurs between the indium pillar and the substrate, reducing the original RΩ value to the order of MΩ. ox It will decrease to around 1kΩ. In the open-circuit defect model, the connection from the indium pillar to the top / bottom is broken, corresponding to R in the model. bump Increase to over 150Ω.

[0034] The detection circuit for detecting defects in indium pillars using an electrical model of an indium pillar according to an embodiment of this application will be described in detail below.

[0035] like Figure 3As shown, it illustrates a detection circuit schematic for detecting defects in indium pillar connections according to an embodiment of this application.

[0036] As shown in the figure, the detection circuit includes an electrical model with an indium pillar. The top of this electrical model, i.e., one end of the fourth equivalent resistor, is connected to the bottom of the pixel in the photosensitive material layer of the sensor. At the same time, a test port is set in the photosensitive material layer. The test port can be grounded or left floating to achieve the effect of closing / opening the switch S2.

[0037] The detection circuit is equipped with an adjustable current source, which can generate an adjustable reference current I. ref And it is connected to the bottom of the electrical model, i.e., one end of the fifth equivalent resistor, via the first switch S1. Reference current I ref The size can be controlled by the voltage V of its internal operational amplifier OP. ref The adjustment range can cover 0.1mA to 10mA. ref The reference voltage V is generated through the indium pillar model. in .

[0038] The first input terminal of comparator CMP is connected to one end of the fifth equivalent resistor in the electrical model via the third switch S3, and the reference voltage V. IN The input is to the first input terminal of comparator CMP. The second input terminal of the comparator is to the first reference voltage V. refl Or the second reference voltage V ref2 The first reference voltage is set based on a short circuit between the indium pillar and the substrate. In the short-circuit defect model, a short circuit occurs between the indium pillar and the substrate, reducing the RΩ value, which is originally on the order of MΩ. ox It will decrease to around 1kΩ. Therefore, V refl =I ref *1kΩ. Second reference voltage V ref2 This is based on the scenario where the connection from the indium pillar to its top or bottom is broken. In the open-circuit defect model, a broken connection from the indium pillar to its top / bottom corresponds to R in the model. bump Increased to over 150Ω. Therefore, V refl =I ref *150Ω.

[0039] The comparator responds to the voltage V entering the first input terminal. in The first reference voltage V at the second input terminal refl Or the second reference voltage V ref2 Compare and obtain comparison result V CMP .

[0040] The output of the comparator CMP is connected to the sampling latch circuit. The comparison result obtained from the comparator enters the sampling latch circuit. The sampling latch circuit samples and judges the comparison result and gives the judgment results test_c and test_r, which serve as the basis for judging whether there is a defect in the indium pillar connection.

[0041] According to another embodiment of this application, other circuit components besides the indium pillar model, such as the adjustable current source, the first switch, the third switch, the comparator CMP, and the sampling latch circuit, are integrated into the pixel of the readout circuit connected below the indium pillar.

[0042] According to an embodiment of this application, the detection circuit further includes a register disposed inside the pixel of the readout circuit for storing the judgment result output from the sampling latch circuit.

[0043] According to this application, the test circuit is integrated into the pixel of the readout circuit chip. Through a unified test logic across the entire chip, open-circuit and short-circuit defects are tested for the indium pillar connections at each pixel, and the test results are stored in a register within the pixel. After the test is completed, the defect distribution of the indium pillar connections across the entire chip can be obtained through shift output operations on the register chain.

[0044] The following will be based on Figure 4 The timing diagram is used to illustrate the use of... Figure 3 The detection circuit shown is a method for detecting defects in indium pillars.

[0045] The detection method according to this application includes: in a first mode, resetting the voltage at the top of the indium pillar to ground level, turning off the second switch, and turning on the first switch, charging the equivalent capacitance of the electrical model through an adjustable current source and inputting the charge to the first input terminal of the comparator; the comparator compares the first voltage obtained at the first input terminal with the reference voltage at the second input terminal and outputs the comparison result to the sampling latch circuit; and the sampling latch circuit samples and judges the comparison result and provides a judgment result; or in a second mode, turning on the first switch, the second switch, and the third switch, the reference current of the adjustable current source generates a second voltage across the indium pillar, and inputting the second voltage to the first input terminal of the comparator; the comparator compares the second voltage obtained at the first input terminal with the reference voltage at the second input terminal and outputs the comparison result to the sampling latch circuit; and the sampling latch circuit samples and judges the comparison result and provides a judgment result.

[0046] Specifically, such as Figure 4 As shown, at the start of TEST_C mode, the second switch S2 is turned on to reset the voltage at the top of the indium pillar to ground. Subsequently, the second switch S2 is turned off and the first switch S1 is turned on, at which point the adjustable current source generates an adjustable reference current I. ref The equivalent capacitor C in the indium pillar modelIn A charging process lasting CLK cycles is performed. According to the law of conservation of charge, C is injected... In The amount of charge can be expressed as Q. In =I ref ×T clk (T) clk (for CLK period), V in The voltage at the terminal can be determined by V. in =Q In / C In The calculation yielded the result.

[0047] Next, in step Cmp1, the third switch S3 is turned on and V is converted by comparator CMP. in Voltage and reference voltage V ref1 Perform a comparison, using the comparator's output V at this point. CMP This serves as the basis for determining whether a short circuit has occurred.

[0048] Under normal circumstances, as mentioned above, by properly setting V ref1 Make V in >V ref1 At this time, V CMP When the level is low, the data latched at the test_c terminal is logic "0". However, when a short circuit fault occurs in the indium pillar, R... ox When the resistance is reduced to below 1kΩ, a discharge path for the charging current is created, leading to V in <V ref1 At this time, V CMP When the signal is high, the data latched at the test_c terminal is logic "1".

[0049] This timing design achieves the detection of indium pillar short-circuit faults through a coordinated mechanism of capacitor charging and discharging characteristics and comparator threshold judgment.

[0050] After TEST_R mode is activated, switches S1, S2, and S3 are turned on. Reference current I... ref Flowing through R In A voltage V is generated across the indium pillar. in =I ref ×(R In +2*R bump Subsequently, in step Cmp2, the comparator CMP converts the voltage to be measured V... in With reference voltage V ref2 Compare them. Normally, R... In +2*R bump The resistance value is less than 150Ω, making V in <V ref2 Then V CMPThe signal is high, and the data latched at the test_r terminal is logic "0". However, when an open-circuit defect occurs in the indium pillar connection, R... In +2*R bump If the resistance value is higher than 150Ω, then V CMP The signal level is low, and the data latched at the test_r terminal is logic "1". The 150Ω resistance threshold used as a failure criterion takes into account the impact of parasitic resistance under worst-case conditions, such as contact between the electrode, wire, and probe pad. Its value can be adjusted according to the actual application requirements.

[0051] After the detection mode ends, the detection results are latched into the registers corresponding to the test_c and test_r signals within each pixel. Reading the data from these registers yields the indium pillar detection results for each pixel, thus providing a distribution map of indium pillar defects across the entire readout circuit chip. The obtained detection results can be used to correct the system imaging of the X-ray detector.

[0052] According to this application, the detection circuit is integrated into the pixel of the readout circuit chip. By using a unified test timing sequence, short-circuit and open-circuit defects in the indium pillar connections within each pixel array are detected, significantly improving the test speed. Simultaneously, the detection results can be automatically saved to a register within the pixel and read out externally via a reading operation. This allows for the establishment of a defect distribution model for the indium pillar connections across the entire pixel array, which is beneficial for improving the imaging quality of the X-ray detector.

[0053] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electrical model for indium pillar interconnect defects in stacked packaged chips, wherein, The stacked packaged chip includes a sensor with a photosensitive layer, a readout circuit with a substrate interconnected with the sensor signal, an indium pillar, an electrode, and a pad disposed between the sensor and the readout circuit. The sensor and the readout circuit are connected through the indium pillar, the electrode, and the pad. The electrical model includes: The equivalent capacitance from the indium pillar to the substrate of the readout circuit; The first equivalent resistance from the indium pillar to the substrate of the readout circuit is connected in parallel with the equivalent capacitance. The second equivalent resistance from the center to the top of the indium pillar, wherein the first end of the first equivalent resistance and the equivalent capacitance connected in parallel are connected to one end of the second equivalent resistance. The third equivalent resistance from the center of the indium pillar to its bottom end, one end of the third equivalent resistance is connected to the one end of the second equivalent resistance and the first end respectively; The fourth equivalent resistance of the electrode, one end of which is connected to the other end of the second equivalent resistance; and The fifth equivalent resistance of the pad, one end of which is connected to the other end of the third equivalent resistance.

2. The electrical model according to claim 1, wherein, The second end of the first equivalent resistor and the equivalent capacitor connected in parallel is connected to the substrate of the readout circuit. The other end of the fourth equivalent resistor is connected to the pixel of the sensor. The other end of the fifth equivalent resistor is connected to the pixel of the readout circuit.

3. A detection circuit for detecting indium pillar defects in stacked packaged chips, wherein, The detection circuit includes the electrical model according to claim 1.

4. The detection circuit according to claim 3, wherein, The detection circuit further includes: An adjustable current source generates an adjustable reference current and is connected to the other end of the fifth equivalent resistance of the electrical model via a first switch. The second switch, the other end of the fourth equivalent resistor of the electrical model is connected to the pixel of the sensor, and the pixel of the sensor is connected to the second switch; A comparator, wherein the first input terminal of the comparator is connected to the other end of the fifth equivalent resistor of the electrical model via a third switch, and the second input terminal of the comparator receives a reference voltage. The comparator compares the voltage passing through the electrical model with the reference voltage at the second input terminal to obtain a comparison result; and A sampling latch circuit is connected to the output of the comparator and is used to sample and judge the comparison result of the comparator and give the judgment result.

5. The detection circuit according to claim 4, wherein, The adjustable current source, the first switch, the third switch, the comparator, and the sampling latch circuit are integrated into the pixel of the readout circuit.

6. The detection circuit according to claim 5, wherein, The detection circuit also includes a register disposed inside the pixel of the readout circuit for storing the judgment result output from the sampling latch circuit.

7. The detection circuit according to any one of claims 3 to 5, wherein, The reference voltage includes a first reference voltage and a second reference voltage. The first reference voltage is set based on a short circuit from the indium pillar to the substrate, and the second reference voltage is set based on a disconnection from the connection between the indium pillar and its top or bottom end.

8. A method for detecting indium pillar defects in a stacked packaged chip using a detection circuit according to any one of claims 3 to 7, the method comprising: In the first mode, the voltage at the top of the indium pillar is reset to ground level, the second switch is turned off, and the first switch is turned on. The equivalent capacitance of the electrical model is charged through the adjustable current source and input to the first input terminal of the comparator. The comparator compares the first voltage obtained at the first input terminal with the reference voltage at the second input terminal and outputs the comparison result to the sampling latch circuit. as well as The sampling latch circuit samples and judges the comparison result and gives the judgment result; or In the second mode, the first switch, the second switch, and the third switch are turned on, and the reference current of the adjustable current source generates a second voltage across the indium pillar, and the second voltage is input to the first input terminal of the comparator; The comparator compares the second voltage obtained at the first input terminal with the reference voltage at the second input terminal and outputs the comparison result to the sampling latch circuit. as well as The sampling latch circuit samples and judges the comparison result and gives the judgment result.

9. The method according to claim 8, wherein, The method further includes locking the judgment result in a register located inside the pixel of the readout circuit.

10. A computer device, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 8 or 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 8 or 9.

Images