Switched capacitor amplifying circuit based on ring amplifier
By using a switched capacitor amplifier circuit based on a ring amplifier, and utilizing a bias-enhanced ring amplifier and a common-mode feedback unit, the problems of insufficient voltage margin and unstable common-mode operating point under low power supply voltage are solved, thereby achieving stability and accuracy of signal amplification.
Patent Information
- Application Number
- CN202511030229.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-25
- Publication Date
- 2025-11-28
AI Technical Summary
At low power supply voltages, traditional switched capacitor amplifier circuits suffer from insufficient voltage margin and unstable common-mode operating point, leading to increased design difficulty and progressively larger errors in signal amplifiers, which in turn affects the normal operation of pipelined analog-to-digital converters.
A switched-capacitor amplifier circuit based on a ring amplifier is adopted, which combines a bias-enhanced ring amplifier, a common-mode feedback unit, and a lower plate sampling network. The near full-swing characteristic of the ring amplifier and the common-mode feedback module are used to stabilize the common-mode operating point and reduce the impact of charge injection.
It effectively solves the problem of insufficient voltage margin under low power supply voltage and reduces the common-mode offset from 8mV to 0.5mV, ensuring the normal operation of the pipelined analog-to-digital converter.
Smart Images
Figure CN121036714A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and in particular to a switched capacitor amplifier circuit based on a ring amplifier. Background Technology
[0002] With the continuous development of semiconductor technology, integrated circuits have become an important pillar of the information industry. Digital information is easy to store and transmit, while information in the real physical world, such as sound, light, heat, electricity, and force, is analog information. In order to connect these two different worlds and realize the mutual conversion between analog and digital information, data converters have been proposed. Pipeline analog-to-digital converters are the main type of high-speed converters. The switched-capacitor amplifier circuit for front-end sampling is an important component of high-performance data converters, and its performance has a significant impact on the performance of the entire circuit.
[0003] Switched-capacitor amplifier circuits typically fall into two categories: those based on charge redistribution structures and those based on charge reversal structures. Charge redistribution-based circuits determine the gain coefficient through capacitor ratios to meet interstage signal amplification requirements, but their gain coefficient is highly susceptible to capacitor mismatch, often requiring calibration. Charge reversal-based circuits, on the other hand, achieve interstage signal amplification by directly reversing the polarity of the voltage across the capacitors. The capacitors are reused in both the sampling and amplification stages, reducing capacitor mismatch and minimizing capacitor area. In switched-capacitor amplifiers, a closed-loop structure is generally used to reduce nonlinearity errors. However, the limited gain and bandwidth of existing amplifiers affect the settling speed and gain accuracy. Furthermore, with shrinking process dimensions, high-speed data converters require amplifiers to operate at low supply voltages, limiting the input and output signal swing and significantly increasing the design complexity. Compared to traditional gain bootstrap sleeve amplifier circuits, ring amplifiers offer advantages such as simple structure, low power consumption, high gain, and near full swing. Switched capacitor amplifier circuits based on ring amplifiers can effectively solve the problems of insufficient voltage margin and speed limitation under low power supply voltages.
[0004] Another problem in switched capacitor amplifier circuits based on charge-flipping structures is that during the switching process between the sampling phase and the amplification phase, the closing of the switch will cause the common-mode operating point of the circuit to shift due to charge injection and clock feedthrough. The resulting error increases step by step in the pipelined analog-to-digital converter, making the subsequent stages unable to work properly. Summary of the Invention
[0005] To address the aforementioned problems, this invention proposes a switched-capacitor amplifier circuit based on a ring amplifier, which solves the issues of insufficient voltage margin and unstable common-mode operating point in traditional switched-capacitor amplifier circuits under low power supply voltage conditions.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] A switched-capacitor amplifier circuit based on a ring amplifier includes:
[0008] The ring amplifier unit is a bias-enhanced ring amplifier, consisting of three inverters and two resistors. The first resistor enhances the bias voltage of the second stage at the output of the first inverter through cross-coupling, and the second resistor provides the dead-time voltage at the output of the second inverter.
[0009] The common-mode feedback unit, consisting of four capacitors and five switches, detects the output voltage and feeds it back to the input to reduce the common-mode offset.
[0010] The sampling network unit includes two sampling capacitors and four sampling switches, and it samples the input voltage by means of sampling through the lower plate.
[0011] The ring amplifier includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, and a second resistor. The gate of the first transistor is connected to the gate of the second transistor as the input terminal of the ring amplifier unit. The drain of the first transistor is connected to the first resistor and the gate of the fourth transistor. The drain of the second transistor is connected to the first resistor and the gate of the third transistor. The drain of the third transistor is connected to the second resistor and the gate of the fifth transistor. The drain of the fourth transistor is connected to the second resistor and the gate of the sixth transistor. The drain of the fifth transistor is connected to the drain of the sixth transistor as the output terminal of the ring amplifier. The sources of the first transistor, the third transistor, and the fifth transistor are connected to a reference voltage. The sources of the second transistor, the fourth transistor, and the sixth transistor are grounded.
[0012] The common-mode feedback unit includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switch, a second switch, a third switch, a fourth switch, and a fifth switch. The upper plate of the first capacitor serves as the first output terminal, the upper plate of the second capacitor serves as the second output terminal, the lower plate of the first capacitor is connected to the lower plate of the second capacitor, the lower plates of the first and second capacitors are connected to the common-mode level through the first switch, the lower plates of the first and second capacitors are connected to the lower plates of the third and fourth capacitors through the second switch, the upper plate of the third capacitor serves as the first input terminal, the upper plate of the fourth capacitor serves as the second input terminal, the upper plate of the third capacitor is connected to the common-mode level through the third switch, the lower plates of the third and fourth capacitors are connected to the common-mode level through the fourth switch, and the lower plate of the fourth capacitor is connected to the common-mode level through the fifth switch.
[0013] The sampling network unit includes: a fifth capacitor, a sixth capacitor, a sixth switch, a seventh switch, an eighth switch, and a ninth switch. The lower plate of the fifth capacitor is connected to the first input signal for sampling through the sixth switch. The lower plate of the sixth capacitor is connected to the second input signal for sampling through the seventh switch. The upper plate of the fifth capacitor is connected to the common-mode level through the eighth switch. The upper plate of the sixth capacitor is connected to the common-mode level through the ninth switch.
[0014] The first, third, and fifth transistors are PMOS transistors, while the second, fourth, and sixth transistors are NMOS transistors.
[0015] The first switch, second switch, third switch, fourth switch, and fifth switch are all single NMOS switches.
[0016] The sixth and seventh switches are gate voltage bootstrapping switches, and the eighth and ninth switches are single NMOS switches.
[0017] The beneficial effects of this invention are as follows: by using a pseudo-differential structure of a ring amplifier instead of a traditional fully differential amplifier, the ring amplifier, with its near-full-swing input and output, effectively solves the problem of insufficient voltage margin under low power supply voltage. Furthermore, the common-mode feedback module detects the output signal of the pseudo-differential amplifier, thereby stabilizing the common-mode operating point. Simultaneously, the use of lower plate sampling in the sampling network reduces the impact of charge injection, thus mitigating the instability of the common-mode operating point. Simulation results from the embodiments show that, compared to ordinary switched-capacitor amplifier circuits, the common-mode offset of the ring amplifier-based switched-capacitor amplifier circuit of this invention can be reduced from 8mV to 0.5mV, effectively stabilizing the common-mode operating point. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the switched capacitor amplifier circuit based on a ring amplifier proposed in this application.
[0019] Figure 2 This is a schematic diagram of the sampling phase circuit of the ring amplifier proposed in this application;
[0020] Figure 3 This is a schematic diagram of the lower plate sampling circuit of the ring amplifier proposed in this application;
[0021] Figure 4 This is a circuit diagram showing the phase-holding structure of the ring amplifier proposed in this application;
[0022] Figure 5 This is a circuit diagram of the ring amplifier proposed in this application;
[0023] Figure 6This is the timing control diagram for the switched capacitor amplifier circuit based on a ring amplifier proposed in this application;
[0024] Figure 7 This is a structural diagram of a common pseudo-differential switched capacitor amplifier circuit;
[0025] Figure 8 This is a transient simulation diagram of a typical pseudo-differential switched capacitor amplifier circuit.
[0026] Figure 9 This is a transient simulation diagram of the switched capacitor amplifier circuit based on a ring amplifier proposed in this application. Detailed Implementation
[0027] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0028] In this embodiment, a switched-capacitor amplifier circuit based on a ring amplifier is used in a pipelined analog-to-digital converter to amplify interstage signals. It uses a closed-loop ring amplifier as the interstage amplifier, and the overall workflow is divided into a sampling phase and a holding phase. The overall timing control logic is as follows: Figure 3 As shown, sampling switches S11 and S12 are connected to the CLK clock, switches S1 and S4 are connected to the CLK2 clock, and switches S2 and S3 are connected to the CLK clock. When the CLK clock is high and the CLK2 clock is low, the circuit enters the sampling phase. Sampling capacitors C1 and C2 sample the input signal, and the amount of charge they store is (VIN-VCM)*C. Switches S5 and S6 are connected to the CLK1 clock. Because sampling is performed using the lower plate, they are disconnected before sampling switches S11 and S12 are disconnected, thus eliminating the nonlinear error introduced by charge leakage from the sampling switches. When the CLK clock is low and the CLK2 clock is high, the circuit... When the signal enters the holding phase, sampling capacitors C1 and C2 are multiplexed and connected across the two ends of the ring amplifier. The charge stored in them remains unchanged. The ring amplifier charges the output terminal to eventually make the output voltage VIN, thus completing the sampling and holding of the signal. For common-mode feedback capacitors C5 and C6, they detect the output signal. Switches S8, S9, and S10 are connected to the clock signal CLK. During the sampling phase, capacitors C5 and C6 are charged. Switch S7 is connected to the clock CLK2. During the holding phase, the values detected by capacitors C5 and C6 are fed back to the input terminal of the ring amplifier through capacitors C3 and C4, thereby stabilizing the common-mode voltage.
[0029] Figure 1The switched-capacitor amplifier circuit based on a ring amplifier proposed in this application includes a ring amplifier unit, a common-mode feedback unit, and a sampling network unit. The sampling network unit adopts a lower plate sampling method to reduce the influence of charge injection from the sampling switch. The ring amplifier unit, as an interstage amplifier, has a near full-swing input and output signal swing because it is composed of three inverters, which can effectively solve the problem of insufficient voltage margin in ordinary switched-capacitor amplifier circuits. The common-mode feedback unit uses a switched capacitor to detect the output signal and feed it back to the input of the pseudo-differential ring amplifier to stabilize the output common-mode signal.
[0030] Figure 2 This is a circuit diagram of the sampling phase of the ring amplifier proposed in this application. When CLK clock is high and CLK2 clock is low, the circuit is in the sampling phase. At this time, capacitors C5 and C6 are charged to VCM, and capacitors C3 and C4 are also charged to VCM. When CLK clock is low and CLK2 clock is high, the circuit enters the holding phase. The output voltage is detected across capacitors C5 and C6. The output voltage at node A can be obtained according to charge conservation, and its error-free value is:
[0031] V out =(V outn +V outp ) / 2 = (VIN + VIP) / 2 = VCM
[0032] Figure 3 The diagram shows the lower plate sampling circuit structure of the ring amplifier proposed in this application. The CLK1 clock is pulled low before the CLK clock. While the lower plate sampling avoids the nonlinear error introduced by charge leakage from the sampling switch, it introduces a fixed linear error through charge leakage when switches S5 and S6 are open, causing the charge on the sampling capacitor to become:
[0033] Q = (VIN - VCM) * C + ΔQ
[0034] ΔQ≈WLC ox (V dd -V CM -V TH )
[0035] The introduced ΔQ error will cause the output signal to become:
[0036] V outn =VIN + ΔQ / C
[0037] V outp =VIP+ΔQ / C
[0038] Where C is the sampling capacitor, the introduced error will cause the output common-mode signal to increase by ΔQ / C, causing the common-mode signal to shift.
[0039] Figure 4 The circuit diagram for the ring amplifier proposed in this application shows the phase-holding structure. During phase holding, for the offset caused by the common-mode signal, the common-mode feedback module detects the output signal through the terminals of capacitors C5 and C6, causing the output voltage at node A to become:
[0040] V out ′=(V outn ′+V outp ′) / 2=(VIN+VIP) / 2+ΔQ / C
[0041] A change in the output common-mode signal is detected and fed back to the input of the ring amplifier through capacitors C3 and C4, increasing the voltage at its input by ΔQ / C, thereby causing the output signal to decrease by A. v *ΔQ / C, A v To increase the gain of the ring amplifier, negative feedback is used to stabilize the output voltage at node A of capacitors C5 and C6 back to VCM. At this point, the output signal is:
[0042] V outn "≈VIN
[0043] V outp "≈VIP"
[0044] The common-mode feedback module reduces the common-mode signal offset problem and prevents the pipelined ADC from malfunctioning due to the common-mode signal offset.
[0045] Figure 5 The ring amplifier proposed in this application is a bias-enhanced ring amplifier. The output of the first stage is connected to the second stage through cross-coupling, which increases the bias voltage of the second stage, thereby increasing the transconductance of the second stage and thus increasing the stability of the circuit. The resistor at the output of the second stage provides the dead zone voltage, which keeps the transistor of the third stage in the cutoff region, and the circuit reaches a stable state.
[0046] The bias-enhanced ring amplifier includes: PMOS transistor M1, NMOS transistor M2, PMOS transistor M3, NMOS transistor M4, PMOS transistor M5, NMOS transistor M6, resistor R1, and resistor R2. The gate of PMOS transistor M1 is connected to the gate of NMOS transistor M2 as the input terminal of the ring amplifier. The drain of PMOS transistor M1 is connected to resistor R1 and the gate of NMOS transistor M4. The drain of NMOS transistor M2 is connected to resistor R1 and the gate of PMOS transistor M3. The drain of PMOS transistor M3 is connected to resistor R2 and the gate of PMOS transistor M5. The drain of NMOS transistor M4 is connected to resistor R2 and the gate of NMOS transistor M6. The drain of PMOS transistor M5 is connected to the drain of NMOS transistor M6 as the output terminal.
[0047] Furthermore, the bias-enhanced ring amplifier adopts a pseudo-differential structure, with its input transistors being a pair of inverters. Compared to a fully differential structure, it has no other additional current sources, and its input swing is almost full swing. The output terminal uses a pair of inverters, which are in the cutoff region when stable, and the output swing is also almost full swing.
[0048] Figure 6 This is the timing control diagram of the switched capacitor amplifier circuit based on a ring amplifier proposed in this application. The first clock curve in the diagram is clock CLK, the second curve is clock CLK1, and the third curve is clock CLK2. Clock signal CLK1 turns off before CLK flips. When CLK clock is high and CLK2 clock is low, the circuit is in the sampling phase; when CLK clock is low and CLK2 clock is high, the circuit enters the holding phase.
[0049] Figure 7 This is a typical pseudo-differential switched capacitor amplifier circuit structure.
[0050] Figure 8 This is a transient simulation diagram of a common pseudo-differential switched capacitor amplifier circuit. It does not use a common-mode feedback module. As a comparative example, it can be seen that when the input signal is a common-mode signal, due to the use of a ring amplifier, the output signal stabilizes after experiencing dynamic oscillation. After the sampling is completed and stabilized, the common-mode signal has an offset of about 8mV. If the number of stages of the pipelined ADC is too large, this error will be amplified stage by stage, making the subsequent stages unable to work properly.
[0051] Figure 9 This is a transient simulation diagram of the switched capacitor amplifier circuit based on a ring amplifier proposed in this application. When the input signal is a common-mode signal, due to the ring amplifier used, the output signal stabilizes after experiencing dynamic oscillation. After the sampling is completed and stabilized, the common-mode signal has an offset of about 0.5mV. The presence of the common-mode feedback unit effectively reduces the offset of the common-mode signal and prevents the subsequent stage from failing to work properly due to the severe offset of the common-mode signal.
[0052] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A switched-capacitor amplifier circuit based on a ring amplifier, characterized in that, include: The ring amplifier unit is a bias-enhanced ring amplifier, consisting of three inverters and two resistors. The first resistor enhances the bias voltage of the second stage at the output of the first inverter through cross-coupling, and the second resistor provides the dead-time voltage at the output of the second inverter. The common-mode feedback unit, consisting of four capacitors and five switches, detects the output voltage and feeds it back to the input to reduce the common-mode offset. The sampling network unit includes two sampling capacitors and four sampling switches, and it samples the input voltage by means of sampling through the lower plate.
2. The switched-capacitor amplifier circuit based on a ring amplifier according to claim 1, characterized in that, The ring amplifier, acting as an interstage amplifier, amplifies the signal sampled by the sampling network.
3. The switched-capacitor amplifier circuit based on a ring amplifier according to claim 2, characterized in that, The common-mode feedback unit includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switch, a second switch, a third switch, a fourth switch, and a fifth switch. The upper plate of the first capacitor serves as the first output terminal, the upper plate of the second capacitor serves as the second output terminal, the lower plate of the first capacitor is connected to the lower plate of the second capacitor, the lower plates of the first and second capacitors are connected to the common-mode level through the first switch, the lower plates of the first and second capacitors are connected to the lower plates of the third and fourth capacitors through the second switch, the upper plate of the third capacitor serves as the first input terminal, the upper plate of the fourth capacitor serves as the second input terminal, the upper plate of the third capacitor is connected to the common-mode level through the third switch, the lower plates of the third and fourth capacitors are connected to the common-mode level through the fourth switch, and the lower plate of the fourth capacitor is connected to the common-mode level through the fifth switch.
4. The switched-capacitor amplifier circuit based on a ring amplifier according to claim 3, characterized in that, The sampling network unit includes: a fifth capacitor, a sixth capacitor, a sixth switch, a seventh switch, an eighth switch, and a ninth switch. The lower plate of the fifth capacitor is connected to the first input signal for sampling through the sixth switch. The lower plate of the sixth capacitor is connected to the second input signal for sampling through the seventh switch. The upper plate of the fifth capacitor is connected to the common-mode level through the eighth switch. The upper plate of the sixth capacitor is connected to the common-mode level through the ninth switch.
5. A switched-capacitor amplifier circuit based on a ring amplifier according to claim 3, characterized in that, The first switch, second switch, third switch, fourth switch, and fifth switch are all single NMOS switches.
6. A switched-capacitor amplifier circuit based on a ring amplifier according to claim 4, characterized in that, The sixth and seventh switches are gate voltage bootstrapping switches, and the eighth and ninth switches are single NMOS switches.