Single-channel mixed gain piled SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)
By introducing a single-channel hybrid gain structure and a split structure into the piperined SAR ADC, the problems of low speed and accuracy, and high power consumption are solved, achieving high speed, high accuracy, and low power consumption.
Patent Information
- Application Number
- CN202511135584.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2025-11-28
AI Technical Summary
Existing piperind SAR ADCs have low speed, low accuracy, and high power consumption, and the interstage gain is achieved through active amplification, which increases power consumption.
A single-channel hybrid gain piperind SAR ADC structure is adopted, which includes a first SAR ADC module, a first sampling transfer capacitor module, a margin amplifier module, a second sampling transfer capacitor module, and a second SAR ADC module connected in sequence. Through the split structure and passive amplification technology, the gain of the hybrid pipeline of active and passive functions is realized, and the power consumption of the margin amplifier is reduced.
It achieves high speed, high precision, and low power consumption, with a simple circuit structure and low cost.
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Figure CN121036765A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and more specifically, to a single-channel hybrid gain piperind SAR ADC. Background Technology
[0002] An analog-to-digital converter (ADC) is a key component that converts analog signals into digital signals.
[0003] Pipelined Successive Approximation Register (Pipelined SAR) ADCs are a hybrid structure combining the advantages of Pipelined ADCs and SAR ADCs. They inherit the high speed of Pipelined ADCs and the low power consumption of SAR ADCs, offering high speed, high accuracy, and low power consumption, making them one of the main ADC structures. With current integrated circuit technology, their sampling rates can exceed 1 GHz, and their resolutions can exceed 10 bits, while their power consumption is significantly lower than that of traditional Pipelined ADCs, leading to a wide range of applications.
[0004] The typical structure and timing of existing piperind SAR ADCs are as follows: Figure 1 As shown, the CDAC (Capacitor Digital to Analog Converter) of the first-stage SAR is also the input capacitor of the RA (Residue Amplifier), so the first-stage CDAC is always occupied during the RA amplification process; and the load capacitor of the RA is the second-stage CDAC, so the second-stage CDAC must always be connected to the RA throughout the entire amplification process. This sequential relationship between the preceding and following stages in the prior art limits the operating speed of the ADC.
[0005] Improvements to existing technologies to accelerate performance, such as Figure 2As shown, sampling transfer capacitors are added to the input and output of the RA, so that the RA amplification is not bound to input CDAC1, and the load capacitor is not bound to CDAC2. However, since it is only a single capacitor structure, the common-mode voltage of the sampling transfer capacitor can only be set to a single value during the reset period, which cannot simultaneously meet the common-mode requirements of the P-input transistor and the N-input transistor in the RA. This limits the input range and speed of the RA in low-voltage applications.
[0006] Currently, the only way to improve the accuracy of piped SAR ADCs at a given speed is by increasing the number of stages. For example... Figure 1 The timing diagram shown is limited by the single-stage conversion time, resulting in a limited number of comparisons that can be performed in a single stage, thus preventing the achievement of high resolution in a single stage. Furthermore, increasing the number of stages inevitably leads to increased power consumption.
[0007] In existing piperinded SAR ADCs, the interstage gain is achieved through a resonant amplifier (RA), such as... Figure 1 As shown, each stage of the SAR ADC does not provide gain. The margin voltage amplification between stages is achieved through RA active amplification, which comes at the cost of relatively high power consumption. Summary of the Invention
[0008] This application aims to provide a single-channel hybrid gain piperind SAR ADC, which addresses the problems of low speed, low accuracy, and high power consumption in existing single-channel technologies.
[0009] This application provides a single-channel hybrid gain piperind SAR ADC, comprising a first SAR ADC module, a first sampling transfer capacitor module, a margin amplifier module, a second sampling transfer capacitor module, and a second SAR ADC module connected in sequence.
[0010] The first SAR ADC module is used to quantize the input signal and obtain the margin voltage corresponding to the input signal based on the quantization result;
[0011] The first sampling transfer capacitor module is used to transmit the residual voltage corresponding to the input signal to the residual amplifier module using a split structure;
[0012] The margin amplifier module is used to amplify the margin voltage transmitted by the first sampling transfer capacitor module to obtain the amplified margin voltage.
[0013] The second sampling transfer capacitor module is used to save the amplified residual voltage output by the residual amplifier module;
[0014] The second SAR ADC module is used to sample, pre-quantize, passively amplify, and normally quantize the amplified residual voltage stored in the second sampling transfer capacitor module.
[0015] In one possible implementation, the first SAR ADC module includes a first CDAC submodule and a second CDAC submodule;
[0016] The first CDAC submodule is used to quantize the input signal and transmit the quantized result to the second CDAC submodule through a decoder;
[0017] The second CDAC submodule is used to obtain the margin voltage corresponding to the input signal based on the quantization result transmitted by the first CDAC submodule and the input signal.
[0018] In one possible implementation, the first sampling transfer capacitor module includes two split capacitors; one end of each of the two split capacitors is connected to the first SAR ADC module, and the other end of each of the two split capacitors is connected to the margin amplifier module.
[0019] In one possible implementation, the first sampling transfer capacitor module further includes a first switch, a second switch, and two third switches;
[0020] The first switch is located between the first SAR ADC module and the two split capacitors, the second switch is located between the two split capacitors and ground, and the third switch is located between the split capacitors and the preset voltage input terminal, with each of the third switches corresponding to one of the split capacitors.
[0021] In one possible implementation, the margin amplifier module includes a margin amplifier;
[0022] The two inverting inputs of the margin amplifier are connected to the two split capacitors respectively, the two non-inverting inputs of the margin amplifier are grounded, and the output of the margin amplifier is connected to the second sampling transfer capacitor module.
[0023] In one possible implementation, the second sampling transfer capacitor module includes a storage capacitor;
[0024] One end of the storage capacitor is connected to the margin amplifier module and the second SAR ADC module, respectively, and the other end of the storage capacitor is grounded.
[0025] In one possible implementation, the second sampling transfer capacitor module further includes a fourth switch, a fifth switch, and a sixth switch;
[0026] The fourth switch is located between one end of the storage capacitor and the margin amplifier module, the fifth switch is located between one end of the storage capacitor and the second SAR ADC module, and the sixth switch is located between one end of the storage capacitor and ground.
[0027] The second SAR ADC module includes a CDAC structure, a comparator, and digital logic connected in sequence;
[0028] The CDAC structure includes a sampling capacitor, a bridging capacitor, and a SAR array capacitor. Both ends of the sampling capacitor are connected in series with a SAR array capacitor through the bridging capacitor. The sampling capacitor includes two sub-capacitors connected in series. Two adjacent sampling sub-capacitors are connected in series through a shorting switch. The sampling sub-capacitors at the beginning and end have no shorting switch and are directly connected to the bridging capacitor. Each sampling sub-capacitor has two plates connected to a sampling switch for sampling the input signal.
[0029] In one possible implementation, the second SAR ADC module has an MSB pre-quantization function, that is, the comparator quantizes the MSB during SAR sampling and performs normal quantization of other bits besides the MSB after sampling is completed.
[0030] The prequantization and normal quantization use the same comparator.
[0031] Beneficial effects:
[0032] This application provides a single-channel hybrid gain piperind SAR ADC, which quantizes the input signal and obtains the corresponding margin voltage based on the quantization result. Then, a split structure is used to attenuate the margin voltage corresponding to the input signal and pass it to the margin amplifier for amplification to obtain the amplified margin voltage. Finally, the amplified margin voltage is subjected to sampling prequantization, passive amplification, and normal quantization. Through single-channel, active and passive hybrid pipeline, active and passive hybrid gain technology, sampling prequantization and other technologies, high speed, high precision, and low power consumption are achieved, and the circuit structure is simple and the implementation cost is low. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This document describes the working principle and timing diagram of existing piperind SAR ADC technology.
[0035] Figure 2 This document describes the working principle and timing diagram of the sampling transfer capacitor in the existing piperind SAR ADC technology.
[0036] Figure 3 This is a schematic diagram of the structure of a single-channel hybrid gain piperind SAR ADC proposed in this invention;
[0037] Figure 4 This is a circuit schematic diagram of the first SAR ADC module used in this invention;
[0038] Figure 5 This is the timing diagram of the single-channel hybrid gain piperind SAR ADC proposed in this invention;
[0039] Figure 6 This is the timing diagram of the second-stage SAR ADC proposed in this invention;
[0040] Figure 7 This is a circuit schematic diagram of the second SAR ADC module proposed in this invention. Detailed Implementation
[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0042] like Figure 3 As shown, a single-channel hybrid gain piperind SAR ADC includes a first SAR ADC module, a first sampling transfer capacitor module, a margin amplifier module, a second sampling transfer capacitor module, and a second SAR ADC module connected in sequence.
[0043] The first SAR ADC module is used to quantize the input signal and obtain the margin voltage corresponding to the input signal based on the quantization result;
[0044] The first sampling transfer capacitor module is used to transmit the residual voltage corresponding to the input signal to the residual amplifier module using a split structure;
[0045] The margin amplifier module is used to amplify the margin voltage transmitted by the first sampling transfer capacitor module to obtain the amplified margin voltage.
[0046] The second sampling transfer capacitor module is used to save the amplified residual voltage output by the residual amplifier module;
[0047] The second SAR ADC module is used to sample, pre-quantize, passively amplify, and normally quantize the amplified residual voltage stored in the second sampling transfer capacitor module.
[0048] The second SAR ADC module can provide passive gain, reduce the gain of the margin amplifier, and reduce the power consumption of the margin amplifier.
[0049] The second SAR ADC module has a sampling prequantization function, which can simultaneously complete the comparison of high bits during sampling to save time and improve speed.
[0050] The pre-quantization function of the second SAR ADC module uses the existing comparator, without the need to add a new comparator.
[0051] The second SAR ADC module has a high resolution to meet the overall high-precision design requirements of the ADC.
[0052] The second SAR ADC module can also perform multi-channel time interleaving to improve speed.
[0053] This application provides a single-channel hybrid gain piperind SAR ADC, which quantizes the input signal and obtains the corresponding margin voltage based on the quantization result. Then, a split structure is used to attenuate the margin voltage corresponding to the input signal and pass it to the margin amplifier for amplification to obtain the amplified margin voltage. Finally, the amplified margin voltage is subjected to sampling prequantization, passive amplification, and normal quantization. Through single-channel, active and passive hybrid pipeline, active and passive hybrid gain technology, sampling prequantization and other technologies, high speed, high precision, and low power consumption are achieved, and the circuit structure is simple and the implementation cost is low.
[0054] In one possible implementation, the first SAR ADC module includes a first CDAC submodule and a second CDAC submodule;
[0055] The first CDAC submodule is a low-precision conventional SAR ADC, containing a small-sized CDAC, comparator, and digital logic for quantizing the input signal. The quantized result is then transmitted to the second CDAC submodule via a decoder. The specific structures of the first and second CDAC submodules are shown below. Figure 3 as well as Figure 4 .
[0056] The second CDAC submodule is a larger-sized CDAC that can meet the noise constraints of the entire ADC. It is used to obtain the margin voltage corresponding to the input signal based on the quantization result transmitted by the first CDAC submodule and the input signal.
[0057] The first SAR ADC module is the first-stage SAR ADC, a 3-bit SAR ADC using two CDACs. The first SAR ADC module and its comparator perform the comparison function. The comparison result is passed to the large CDAC via a DAS (Detect-and-Skip) decoder, thus obtaining the margin voltage for the first stage. DAS technology is used to reduce the toggle rate of the large DAC; a small-sized capacitor array is used to complete the high-speed quantization process, improving speed and reducing power consumption.
[0058] In the embodiments of this application, 3-bit comparison takes 400ps and sampling takes 300ps. The remaining time is less than 300ps. In order to achieve a rate of 1GS / s, this embodiment adopts a sampling transfer capacitor scheme, which increases the RA input sampling capacitor and the load sampling capacitor, so that the RA operation is decoupled from the first-stage SAR and the second-stage SAR, thereby improving the speed of the piperind SARADC.
[0059] In one possible implementation, the first sampling transfer capacitor module includes two split capacitors; one end of each of the two split capacitors is connected to the first SAR ADC module, and the other end of each of the two split capacitors is connected to the margin amplifier module. A split capacitor is a capacitor that performs a splitting function.
[0060] In one possible implementation, the first sampling transfer capacitor module further includes a first switch, a second switch, and two third switches;
[0061] The first switch is located between the first SAR ADC module and the two split capacitors; the second switch is located between the two split capacitors and ground; and the third switch is located between the split capacitors and a preset voltage input terminal, with each third switch corresponding to one of the split capacitors. Figure 3 The two third switches shown are connected to different voltages Vb1 and Vb2, respectively.
[0062] In the embodiments of this application, the sampling transfer capacitor is split into two capacitors, such as... Figure 3As shown. The first plate of the two split capacitors is connected to the first-stage CDAC, and the second plate can be reset to different voltages Vb1 and Vb2 respectively. The split capacitors are two identical capacitors, and the sum of their capacitances is equal to the capacitance of the first-stage large CDAC, thus achieving an attenuation coefficient of 0.5. During the amplification stage, each split capacitor completes the amplification process with its respective feedback capacitor. Because the input of the ring amp is an inverter structure composed of P-type and N-type transistors, using a split structure can satisfy the optimal input common mode of each P-type and N-type transistor, thereby optimizing the speed of the ring amp.
[0063] exist Figure 3 In this context, SAMP / samp indicates sampling, TRAN indicates voltage transfer, and Amp indicates amplification. In specific implementations, different numerical suffixes are used to distinguish different positions, and detailed timing information is reflected in... Figure 5 In the timing diagram.
[0064] In one possible implementation, the margin amplifier module includes a margin amplifier;
[0065] The two inverting inputs of the margin amplifier are connected to the two split capacitors respectively, the two non-inverting inputs of the margin amplifier are grounded, and the output of the margin amplifier is connected to the second sampling transfer capacitor module.
[0066] In the embodiments of this application, the margin amplifier (RA) is a Ring closed-loop amplifier with a closed-loop gain of 8. Both the RA input and output use a charge transfer scheme with attenuation to improve speed, with an attenuation coefficient of 0.5. The equivalent gain of the entire RA stage is 2 (=0.5*8*0.5). The RA amplification time is approximately 600ps, and the RA input charge transfer time (sampling time) is approximately 130ps.
[0067] In one possible implementation, the second sampling transfer capacitor module includes a storage capacitor;
[0068] One end of the storage capacitor is connected to both the margin amplifier module and the second SAR ADC module, and the other end of the storage capacitor is grounded. The storage capacitor is a capacitor that stores the amplified margin voltage output from the margin amplifier module.
[0069] In one possible implementation, the second sampling transfer capacitor module further includes a fourth switch, a fifth switch, and a sixth switch;
[0070] The fourth switch is located between one end of the storage capacitor and the margin amplifier module, the fifth switch is located between one end of the storage capacitor and the second SAR ADC module, and the sixth switch is located between one end of the storage capacitor and ground.
[0071] In one possible implementation, the second SAR ADC module includes a CDAC structure, a comparator, and digital logic (i.e., second SAR logic) connected in sequence.
[0072] The CDAC structure includes a sampling capacitor, a bridging capacitor, and a SAR array capacitor. Both ends of the sampling capacitor are connected in series with a SAR array capacitor through the bridging capacitor. The sampling capacitor includes two sub-capacitors connected in series. Two adjacent sampling sub-capacitors are connected in series through a shorting switch. The sampling sub-capacitors at the beginning and end have no shorting switch and are directly connected to the bridging capacitor. Each sampling sub-capacitor has two plates connected to a sampling switch for sampling the input signal.
[0073] There is only one comparator.
[0074] The second SAR ADC module has MSB pre-quantization capability, which means that the comparator can quantize the MSB during SAR sampling and perform normal quantization of other bits besides the MSB after sampling is completed.
[0075] The pre-quantization and normal quantization require the same comparator.
[0076] In the embodiments of this application, the second SAR ADC module is a second-stage SAR ADC, which is a 10-bit SAR ADC. In order to realize the 10-bit comparison process of the second-stage SAR, a two-channel interleaving method is adopted, and the period of a single channel is 2ns.
[0077] In the embodiments of this application, the second-stage SAR ADC, in order to improve speed, has MSB (Most Significant Bit) pre-quantization capability. That is, the comparator can quantize the MSB during SAR sampling, and perform normal quantization of the bits other than the MSB after sampling. The specific timing diagram is as follows. Figure 6 As shown. Since the MSB is only related to the polarity of the input signal, the polarity of the sampled residual signal is determined for the second-stage SAR ADC and can be compared at the end of the sampling process.
[0078] The comparator used in the pre-quantization technique in this application is the existing comparator of the second-stage SAR ADC itself, eliminating the need for adding a new comparator. During the sampling period of the second-stage SAR ADC, the comparator MSB initiates the comparison process, stores the comparison result in the corresponding register, and sets the MSB result to the MSB capacitor of the CDAC after sampling is complete. This operation can save approximately 100ps of comparator comparison time.
[0079] In the embodiments of this application, the second-stage SAR employs a CDAC architecture with passive gain, such as... Figure 7 As shown, it mainly includes a sampling capacitor, a bridging capacitor, and a SAR array capacitor. Both ends of the sampling capacitor are connected in series with one of the SAR array capacitors through the bridging capacitor. The sampling capacitor includes at least two capacitors connected in series. A shorting switch is connected in series between two adjacent sampling capacitors. Each sampling capacitor is connected in parallel with a sampling switch for sampling the input signal.
[0080] During the ADC sampling phase, when Φ1 is high, the sampling switch is on; when Φ2 is low, the shorting switch is off; when Φ1 is low, the sampling switch is off, and when Φ2 is high, the shorting switch is on. At this time, the charge on the sampling capacitor is redistributed.
[0081] The transfer function of this SAR is:
[0082]
[0083] Where Csmp is the sampling capacitor, Cbrg is the bridging capacitor, Csar is the total capacitance of the SAR capacitor array, Ceq is the equivalent capacitance of the bridging capacitor and the SAR capacitor array in series, N is the SAR resolution, n is each weight of the SAR CDAC, and d is the comparison code value of the weight.
[0084] This structure provides gain for both the input signal and the DAC (reference).
[0085] In this embodiment, appropriate parameters are selected, with a gain of approximately 1.3 for Vin and approximately 0.65 for the reference. Therefore, for the entire SAR, this is equivalent to a gain of 1.3 / 0.65 = 2 for the preceding stage.
[0086] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0087] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, electronic devices, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0088] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0090] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.
[0091] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0092] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A single-channel hybrid-gain pipelined SAR ADC, characterized in that, The first SAR ADC module, used for quantizing an input signal and obtaining a residual voltage corresponding to the input signal according to a result obtained by quantization; The first sampling transfer capacitor module, used for attenuating and transmitting the residual voltage corresponding to the input signal to the residual amplifier module by using a split structure; The residual amplifier module, used for amplifying the residual voltage transmitted by the first sampling transfer capacitor module to obtain an amplified residual voltage; The second sampling transfer capacitor module, used for storing the amplified residual voltage output by the residual amplifier module; The second SAR ADC module, used for sampling, pre-quantizing, passively amplifying and normally quantizing the amplified residual voltage stored in the second sampling transfer capacitor module. The first SAR ADC module includes a first CDAC sub-module and a second CDAC sub-module; 2. The single-channel mixed-gain pipelined SAR ADC of claim 1, wherein, The first CDAC sub-module, used for quantizing an input signal and transmitting a result obtained by quantization to the second CDAC sub-module through a decoder; The second CDAC sub-module, used for obtaining a residual voltage corresponding to the input signal based on the result obtained by quantization transmitted by the first CDAC sub-module and the input signal. The first sampling transfer capacitor module includes two split capacitors; one end of each of the two split capacitors is connected to the first SAR ADC module, and the other end of each of the two split capacitors is connected to the residual amplifier module.
3. The single-channel mixed-gain pipelined SAR ADC of claim 1, wherein, The first sampling transfer capacitor module further includes a first switch, a second switch and two third switches; 4. The single-channel mixed-gain pipelined SAR ADC of claim 3, wherein, The first switch is arranged between the first SAR ADC module and the two split capacitors, the second switch is arranged between the two split capacitors and the ground, the third switch is arranged between the split capacitor and a preset voltage input end, and the third switch corresponds to the split capacitor one by one. The residual amplifier module includes a residual amplifier; 5. The single-channel mixed-gain pipelined SAR ADC of claim 3, wherein, Two non-inverting input terminals of the residual amplifier are connected to the two split capacitors one by one, two same-phase input terminals of the residual amplifier are grounded, and an output terminal of the residual amplifier is connected to the second sampling transfer capacitor module. The second sampling transfer capacitor module includes a storage capacitor; 6. The single-channel mixed-gain pipelined SAR ADC of claim 1, wherein, One end of the storage capacitor is connected to the residual amplifier module and the second SAR ADC module, respectively, and the other end of the storage capacitor is grounded. The second sampling transfer capacitor module further includes a fourth switch, a fifth switch and a sixth switch; 7. The single-channel mixed-gain pipelined SAR ADC of claim 6, wherein, The fourth switch is arranged between one end of the storage capacitor and the residual amplifier module, the fifth switch is arranged between one end of the storage capacitor and the second SAR ADC module, and the sixth switch is arranged between one end of the storage capacitor and the ground. The second SAR ADC module includes a CDAC structure, a comparator and a digital logic connected in sequence.
8. The single-channel mixed-gain pipelined SAR ADC of claim 1, wherein, The CDAC structure comprises a sampling capacitor, a bridge capacitor and a SAR array capacitor, both ends of the sampling capacitor are connected in series with one SAR array capacitor through the bridge capacitor, wherein the sampling capacitor comprises two series-connected sub-capacitors, two adjacent sampling sub-capacitors are connected in series through a short-circuit switch, the sampling sub-capacitors at the head and tail are directly connected to the bridge capacitor without the short-circuit switch; two poles of each sampling sub-capacitor are connected to a sampling switch for sampling an input signal; the number of comparators is 1.
9. The single-channel mixed-gain pipelined SAR ADC of claim 8, wherein, The second SAR ADC module has an MSB pre-quantization function, that is, the comparator performs quantization of MSB during SAR sampling, and performs normal quantization of other bits except MSB after the sampling is completed. The pre-quantization and normal quantization use the same comparator.